Transistor and memory device

Abstract

The invention provides a memory device capable of realizing miniaturization or high integration. The transistor includes a first conductor having a columnar region, a first insulator having a cylindrical first region, a second conductor having an opening through which the first conductor passes, a first semiconductor located on the second conductor and having a cylindrical second region, and a third conductor on the first semiconductor. A first region of the first insulator surrounds a columnar region of the first conductor, the first conductor has a third region located above an opening of the second conductor, and the first conductor is surrounded by a second region of the first semiconductor in the third region across the first region of the first insulator.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a storage device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are also a form of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. sometimes include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. One embodiment of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product, or composition of matter. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU, memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) formed by processing a semiconductor wafer into a chip and having electrodes as connection terminals.

[0005] Chips (IC chips) equipped with integrated circuits (ICs) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.

[0006] In addition, a technology for forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply described as display devices). As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known, and oxide semiconductors have attracted attention as other materials.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In addition, in recent years, as electronic devices have become smaller and lighter, there has been an increased demand for further high density of integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are arranged in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit.

[0009] Furthermore, if a vertical transistor can be realized, the density of integrated circuits can be increased. For example, Patent Document 4 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered by a gate electrode via a gate insulator. [Prior technical literature] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 [Non-patent literature]

[0011] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the invention Technical problem to be solved by the invention

[0012] One of the purposes of one embodiment of the present invention is to provide a transistor that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with a high operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with less uneven electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with a large on-state current.

[0013] In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device with high operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device with low power consumption.

[0014] Another object of one embodiment of the present invention is to provide a novel transistor, semiconductor device, or memory device. Another object of one embodiment of the present invention is to provide a novel method for manufacturing a transistor, semiconductor device, or memory device.

[0015] Note that the description of these purposes does not prevent the existence of other purposes. Note that one embodiment of the present invention does not necessarily achieve all of the above purposes. Note that purposes other than the above can be known and extracted from the description of the specification, drawings, claims, etc. Solutions to technical problems

[0016] One embodiment of the present invention is a transistor, which includes a first conductor having a columnar region, a first insulator having a tubular first region, a second conductor having an opening through which the first conductor passes, a first semiconductor located on the second conductor and having a tubular second region, and a third conductor on the first semiconductor, wherein the first region of the first insulator surrounds the columnar region of the first conductor, the first conductor has a third region located above the opening of the second conductor, and the first conductor is surrounded by the second region of the first semiconductor via the first region of the first insulator in the third region.

[0017] Furthermore, in the above structure, the third conductor preferably overlaps with the first conductor.

[0018] In the above structure, it is preferred that a second insulator is included, the second insulator has a second opening, the first conductor has a region located in the second opening, and the second conductor has a region in contact with a top surface of the second insulator.

[0019] In addition, one embodiment of the present invention is a transistor, which includes a first conductor having a columnar region, a first insulator having a tubular first region, a second conductor having an opening through which the first conductor passes, a first semiconductor located on the second conductor and having a tubular second region, a second insulator on the first conductor, and a third conductor on the second insulator, wherein the first region of the first insulator surrounds the columnar region of the first conductor, the first conductor has a third region located above the opening of the second conductor, the first conductor is surrounded by the second region of the first semiconductor in the third region via the first region of the first insulator, and the third conductor overlaps with the first conductor via the second insulator.

[0020] Furthermore, in the above structure, the third conductor preferably overlaps with the first conductor.

[0021] Furthermore, in the above structure, it is preferable that the first semiconductor is located on the second insulator and has a region located between the second insulator and the third conductor.

[0022] In the above structure, it is preferred that the first insulator includes at least one of silicon oxide and silicon oxynitride, and the second insulator includes at least one of silicon nitride and silicon nitride oxide.

[0023] In the above structure, preferably, a third insulator is included, the third insulator has a second opening, the first conductor has a region located in the second opening, and the second conductor has a region in contact with a top surface of the second insulator.

[0024] Furthermore, in the above structure, the third conductor is preferably in contact with the top surface of the first semiconductor.

[0025] In the above structure, the first semiconductor preferably has a region in contact with a side surface of the third conductor.

[0026] Furthermore, in the above structure, the first semiconductor is preferably a metal oxide containing indium or zinc.

[0027] In addition, one embodiment of the present invention is a storage device, which includes a transistor and a capacitor on the transistor, the transistor including a first conductor having a columnar region, a first insulator having a tubular first region, a second conductor having an opening through which the first conductor passes, a first semiconductor located on the second conductor and having a tubular second region, and a third conductor on the first semiconductor, the capacitor including a fourth conductor having a columnar region, a second insulator arranged in a manner covering a side surface of the fourth conductor, and a fifth conductor on the second insulator, the first region of the first insulator being configured to surround the columnar region of the first conductor, the first conductor having a third region located at an upper portion of the opening of the second conductor, the first conductor being surrounded by the second region of the first semiconductor in the third region via the first region of the first insulator, and the fourth conductor being located on the third conductor.

[0028] Furthermore, in the above structure, the third conductor preferably overlaps with the first conductor.

[0029] In the above structure, the first conductor preferably overlaps with the fourth conductor when viewed from a planar perspective.

[0030] In addition, in the above structure, it is preferred that it includes a third insulator having a second opening, and the fourth conductor has a fourth region located in the second opening and whose side contacts the third insulator, and a fifth region located on the fourth region and whose side contacts the second insulator. Effects of the Invention

[0031] According to one embodiment of the present invention, a transistor capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a transistor with high operating speed can be provided. In addition, according to one embodiment of the present invention, a transistor with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a transistor with less uneven electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a transistor with high reliability can be provided. In addition, according to one embodiment of the present invention, a transistor with large on-state current can be provided.

[0032] In addition, according to one embodiment of the present invention, a semiconductor device or storage device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or storage device with high operating speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or storage device with high reliability can be provided. In addition, according to one embodiment of the present invention, a storage device with less uneven electrical characteristics of transistors can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or storage device with low power consumption can be provided.

[0033] In addition, according to one embodiment of the present invention, a novel transistor, semiconductor device, or memory device can be provided. In addition, according to one embodiment of the present invention, a novel method for manufacturing a transistor, semiconductor device, or memory device can be provided.

[0034] Note that in this specification, etc., oxynitride refers to a substance containing more oxygen than nitrogen in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. In addition, oxynitride refers to a substance containing more nitrogen than oxygen in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1A and Figure 1B is a plan view showing an example of a transistor. Figure 1C to Figure 1F is a cross-sectional view showing an example of a transistor. Figure 2A and Figure 2B is a cross-sectional view showing an example of a transistor. Figure 3A is a plan view showing an example of a storage device. Figure 3B is a circuit diagram illustrating an example of the structure of a storage device. Figure 3C and Figure 3D is a cross-sectional view showing an example of a storage device. Figure 4A and Figure 4B is a cross-sectional view showing an example of a storage device. FIG. 5A to FIG. 5F is a cross-sectional view showing an example of a method for manufacturing a storage device. 6A to 6F is a cross-sectional view showing an example of a method for manufacturing a storage device. 7A to 7E is a cross-sectional view showing an example of a method for manufacturing a storage device. FIG. 8A to FIG. 8E is a cross-sectional view showing an example of a method for manufacturing a storage device. 9A to 9F is a cross-sectional view showing an example of a method for manufacturing a storage device. FIG. 10A to FIG. 10C is a cross-sectional view showing an example of a method for manufacturing a storage device. FIG. 11A to FIG. 11C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig. 12A and Fig. 12B is a cross-sectional view showing an example of a method for manufacturing a storage device. FIG. 13A to FIG. 13Cis a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.14A and Fig. 14B is a cross-sectional view showing an example of a method for manufacturing a storage device. FIG. 15A to FIG. 15D is a cross-sectional view showing an example of a memory transistor. Fig.16A and Fig. 16B is a cross-sectional view showing an example of a storage device. FIG. 17A to FIG. 17E It is a cross-sectional view explaining a method for depositing a metal oxide according to one embodiment of the present invention. 18A to 18D This is a cross-sectional view of a metal oxide according to one embodiment of the present invention. FIG. 19A to FIG. 19D It is a cross-sectional view explaining a method for depositing a metal oxide according to one embodiment of the present invention. FIG. 20A to FIG. 20C It is a cross-sectional view explaining a method for depositing a metal oxide according to one embodiment of the present invention. Fig.21A is a plan view showing an example of a storage device. Fig. 21B is a cross-sectional view showing an example of a storage device. Fig. 22 is a block diagram illustrating a structural example of a storage device. Fig.23A is a schematic diagram illustrating a configuration example of a storage device. Fig. 23B is a circuit diagram illustrating a structural example of a storage device. Fig.24A and Fig. 24B is a schematic diagram illustrating a configuration example of a storage device. Fig.25 is a circuit diagram illustrating a structural example of a storage device. Fig.26 is a cross-sectional view showing an example of a storage device. Fig.27A and Fig.27B FIG. 1 is a schematic diagram of a semiconductor device according to one embodiment of the present invention. Fig.28A and Fig.28B This is a diagram for explaining an example of an electronic component. FIG. 29A to FIG. 29E is a schematic diagram of a storage device according to one embodiment of the present invention. FIG. 30A to FIG. 30H FIG. 1 is a diagram showing an electronic device according to one embodiment of the present invention. Fig.31 is a diagram showing an example of space equipment. Modes for Carrying Out the Invention

[0036] The bottom surface of the embodiment is described with reference to the accompanying drawings. It is noted that a person skilled in the art can easily understand that the embodiment can be implemented in a plurality of different forms, and its mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiment shown on the bottom surface.

[0037] In addition, in the drawings, the size, thickness of the layer or the area are sometimes exaggerated for obvious reasons. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore the shapes or numerical values ​​shown in the drawings are not limited. For example, in the actual manufacturing process, layers or resist masks are sometimes unintentionally thinned due to treatments such as etching, but this is sometimes not reflected in the drawings for ease of understanding. In addition, in the drawings, the same symbols are sometimes used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0038] In addition, in particular, in a plan view (also referred to as a “top view”) or a perspective view, some components may be omitted to facilitate understanding of the invention. In addition, some hidden lines may be omitted.

[0039] In addition, in this specification, for the sake of convenience, ordinal numbers such as first and second are added, but they do not indicate the order of processes or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for description. In addition, the ordinal numbers recorded in this specification and the like are sometimes inconsistent with the ordinal numbers used to specify one embodiment of the present invention.

[0040] In addition, in this specification, for the sake of convenience, words and phrases indicating configuration such as "upper" and "lower" are used to explain the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in the specification are not limited, and the words and phrases can be appropriately changed according to the situation.

[0041] For example, in this specification, etc., X and Y are connected, which means that X and Y are electrically connected. Here, X and Y are electrically connected, which means that an electric signal can be transmitted between X and Y when an object (element such as a switch, transistor element or diode, or a circuit including the element and wiring, etc.) exists between X and Y. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected. Here, X and Y are directly connected, which means that X and Y can transmit an electric signal between X and Y through wiring (or electrodes) without passing through the above-mentioned object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when expressed using an equivalent circuit.

[0042] In addition, in this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. Furthermore, a transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between a drain (drain terminal, a drain region, or a drain electrode) and a source (source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification, etc., a channel formation region refers to a region where current mainly flows.

[0043] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0044] Note that the impurities of a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be said to be an impurity. When impurities are contained, for example, the defect state density of the semiconductor may increase, the crystallinity may decrease, etc. may occur. When the semiconductor is an oxide semiconductor, the impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water sometimes acts as an impurity. In addition, for example, sometimes the mixing of impurities leads to oxygen vacancies (also called V O : The formation of oxygenvacancy).

[0045] Note that in this specification, etc., oxynitride refers to a substance containing more oxygen than nitrogen in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. In addition, oxynitride refers to a substance containing more nitrogen than oxygen in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride.

[0046] In this specification, the term "insulator" may be referred to as an insulating film or insulating layer, the term "conductor" may be referred to as a conductive film or conductive layer, and the term "semiconductor" may be referred to as a semiconductor film or semiconductor layer.

[0047] In addition, in this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10 degrees and less than 10 degrees. Therefore, a state where the angle is greater than -5 degrees and less than 5 degrees is also included. In addition, "approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30 degrees and less than 30 degrees. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80 degrees and less than 100 degrees. Therefore, a state where the angle is greater than 85 degrees and less than 95 degrees is also included. In addition, "approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60 degrees and less than 120 degrees.

[0048] In addition, in this specification, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (ground potential), "voltage" can also be referred to as "potential". Note that the ground potential does not necessarily mean 0V. In addition, potential is relative, and the potential supplied to the wiring, the potential applied to the circuit, the potential output from the circuit, etc., etc., also changes according to the change of the reference potential.

[0049] In this specification and the like, when the same symbol is used for a plurality of components and it is necessary to distinguish them, a symbol for identification such as “_1”, “[n]”, or “[m, n]” may be added to the symbol.

[0050] Note that in this specification, etc., "high consistency" refers to a structure in which the height from the reference surface (for example, a flat surface such as a substrate surface) in a cross section is equal. For example, in the manufacturing process of a storage device, a flattening process (typically a CMP process) is sometimes performed to expose the surface of a single layer or multiple layers. In this case, the height of the processed surface by the CMP process is equal to the height of the reference surface. Note that depending on the processing device, processing method or material of the processed surface during the CMP process, the heights of multiple layers are sometimes different. In this specification, etc., "high consistency" also includes the above situation. For example, in the case of a layer having two heights relative to the reference surface (referred to as the first layer and the second layer here), when the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is less than 20nm, it is also referred to as "high consistency".

[0051] Note that in this specification, etc., "ends are consistent" means that at least a portion of the outline of each layer in the stack overlaps when viewed from a plane (sometimes referred to as a top view). For example, this includes the case where the upper layer and the lower layer are processed by using the same mask pattern or a portion of them is processed by using the same mask pattern. However, strictly speaking, sometimes the outlines do not overlap and the outline of the upper layer is located inside the outline of the lower layer or the outline of the upper layer is located outside the outline of the lower layer, and these cases can also be said to be "ends consistent".

[0052] Note that, in general, it is difficult to clearly distinguish between “completely consistent” and “substantially consistent.” Therefore, in this specification and the like, “consistent” includes both completely consistent and substantially consistent.

[0053] Note that in this specification, etc., the normally-on characteristic refers to a state in which a channel exists and current flows through a transistor even when no voltage is applied to the gate. Also, the normally-off characteristic refers to a state in which current does not flow through a transistor when no voltage is applied to the gate or when a ground potential is supplied to the gate.

[0054] In addition, in this specification, off-state current may be referred to as leakage current. In addition, in this specification, off-state current may refer to current flowing between a source and a drain when a transistor is in an off state, for example.

[0055] (Implementation Method 1) In this embodiment, an example of a memory device, an example of a transistor, an example of a capacitor, and methods for manufacturing these which are one embodiment of the present invention are described.

[0056] A memory device according to one embodiment of the present invention includes a transistor and a capacitor. Figures 1A to 1F An example of a structure of a transistor including one embodiment of the present invention is shown. Figure 2A and Figure 2B enlarge Figure 1E It is shown as a part of the diagram. Figures 1A to 1F Details of transistor 200 are shown in FIG.

[0057] Figure 3A , Figure 3C and Figure 3D Shown including Figure 1D and Figure 1E Examples of the structures of the transistor 200 and the capacitor according to one embodiment of the present invention are shown in FIG.

[0058] <Configuration Example of Storage Device> Reference FIG. 3A to FIG. 3DThe structure of a memory device including a transistor and a capacitor is described. A memory device according to one embodiment of the present invention includes a memory cell. The memory device according to one embodiment of the present invention preferably includes a plurality of memory cells arranged in a matrix.

[0059] Figure 3A is a plan view of a memory device including a transistor 200 and a capacitor 100. Figure 3C It is along Figure 3A A cross-sectional view of the portion along the dashed line A1-A2 in FIG. Figure 3D It is along Figure 3A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. Figure 3A Among the components included in the transistor 200 in the plan view of FIG. 1 , only the conductor 240, the conductor 242, the conductor 260, and the conductor 262 are shown, and other components are omitted. Figure 3A Some components (eg, insulator, etc.) are omitted from the capacitor 100.

[0060] Note that arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings of this specification. Note that in this specification, "X direction" refers to the direction along the X axis, and sometimes the forward and reverse directions are not distinguished unless explicitly stated. The same applies to "Y direction" and "Z direction". In addition, the X direction, Y direction, and Z direction are directions that intersect each other. For example, the X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification, one of the X direction, Y direction, and Z direction is sometimes referred to as the "first direction". In addition, the remaining one of the above directions is sometimes referred to as the "third direction".

[0061] Figure 3A , Figure 3C and Figure 3D The memory device shown includes an insulator 140 on a substrate (not shown), a transistor 200 on the insulator 140, and a capacitor 100 on the transistor 200. By combining the capacitor 100 and the transistor 200, a memory cell 150 can be formed.

[0062] like Figure 3A , Figure 3C and Figure 3DAs shown, the transistor 200 is arranged in a manner overlapping with the capacitor 100. In addition, at least a part of the components of the transistor 200 has an area overlapping with at least a part of the components of the capacitor 100. For example, the conductor 120 preferably has an area overlapping with the conductor 260. By adopting this structure, the transistor 200 and the capacitor 100 can be arranged in a manner that does not greatly increase the occupied area when viewed from a plane. As a result, the occupied area of ​​the memory cell 150 can be reduced, so the memory cell 150 can be arranged at a high density to increase the storage capacity of the storage device. In other words, a high integration of the storage device can be achieved.

[0063] By reducing the area of ​​the conductor 120 and the conductor 260 when viewed from the plane, the memory cell 150 can be arranged at a high density to increase the capacity of the memory device. The degree to which the area of ​​the conductor 120 and the conductor 260 can be reduced depends on the limiting resolution of the exposure device used in the manufacture of the memory device, the processing conditions, the deposition conditions, etc. For example, by setting the area of ​​the conductor 120 when viewed from the plane to the minimum area that can be achieved in the manufacture of the memory device, the occupied area of ​​the capacitor 100 when viewed from the plane becomes smaller. Therefore, sometimes the memory cell 150 can be arranged at an extremely high density. In addition, for example, by setting the area of ​​the conductor 260 when viewed from the plane to the minimum area that can be achieved in the manufacture of the memory device, the occupied area of ​​the transistor 200 when viewed from the plane becomes smaller. Therefore, sometimes the memory cell 150 can be arranged at an extremely high density.

[0064] In one embodiment of the present invention, the conductor 120 and the conductor 260 have, for example, a columnar (pillar)-shaped region (also referred to as a region having a column or having a columnar shape). Figure 3A , Figure 3C and Figure 3D , an example is shown in which both the conductor 120 and the conductor 260 have a columnar shape. Figure 3A , Figure 3C and Figure 3D In the figure, the axes of the conductor 120 and the conductor 260 are both along the Z direction. For example, the axes of the conductor 120 and the conductor 260 are preferably columns along the Z direction. Or, for example, the axis preferably has a columnar region along the Z direction. In addition, in a column whose axis is along the Z direction, for example, the top surface and the bottom surface of the column are perpendicular to the Z direction. Here, in a column along the Z direction, the axis of the column is, for example, a line passing through the center of gravity of the top surface shape of the column and along the Z direction. In the case of a cylinder along the Z direction, for example, the center of gravity of the column is a straight line passing through the center of the circle of the top surface and along the Z direction. In addition, the axis of the column can be roughly along the Z direction, and may also have a curve, etc. Figure 3A The example in which the conductor 120 and the conductor 260 are cylindrical is shown. Figure 3AAlthough the top surface shapes of the conductor 120 and the conductor 260 are both circular and have substantially the same diameter, the diameters of the conductor 120 and the conductor 260 may be different. Figure 3A An example is shown in which the top surface shapes of the conductor 120 and the conductor 260 are both circular, and the center positions of the circles are roughly the same, but the center positions of the conductor 120 and the conductor 260 may be different. In addition, the top surface shapes of the conductor 120 and the conductor 260 are not limited to circles. The top surface shape can have various shapes such as an ellipse, a polygon, and a figure composed of curves and straight lines. For example, when the conductor is a polygonal prism, the top surface shape is a polygon. Note that the polygonal prism also includes a triangular prism and a quadrangular prism. In the conductor 120 and the conductor 260, it is preferred that when the width of the column is 1, for example, the height of the column is greater than 1. Note that the width of the column can be, for example, the diameter of a circle corresponding to the area calculated by converting the area of ​​the top surface. Or, for example, in the cross section of the column, the width of the column at the position where the width of the cross section is the largest can be measured.

[0065] Alternatively, in one embodiment of the present invention, the conductor 120 and the conductor 260 may have, for example, a cone-shaped region (also referred to as a region having a cone or a cone shape). The conductor 120 and the conductor 260 in one embodiment of the present invention may have, for example, a cone-shaped region or a cone-shaped region.

[0066] Here, in this specification, etc., the top surface shape of a certain component refers to the outline shape of the component when viewed from a plane. In addition, viewed from a plane refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of the support body (such as a substrate) on which the component is formed.

[0067] Figure 3B 1 shows a circuit diagram of a memory device according to this embodiment. The memory cell 150 includes a transistor Tr and a capacitor C. Here, the transistor Tr corresponds to Figure 3A , Figure 3B and Figure 3D The transistor 200 shown in FIG. 1 and the capacitor C correspond to Figure 3A , Figure 3B and Figure 3D The capacitor 100 shown in FIG. 1 is a capacitor 100 shown in FIG. 1 . Figure 3A , Figure 3C and Figure 3D The components shown are used as storage units of a storage device.

[0068] One of the source and drain of the transistor Tr is connected to one of the pair of electrodes of the capacitor C. The other of the source and drain of the transistor Tr is connected to the wiring BL. The gate of the transistor Tr is connected to the wiring WL. The other of the pair of electrodes of the capacitor C is connected to the wiring PL.

[0069] Here, the wiring BL corresponds to the conductor 242, the wiring WL corresponds to the conductor 262, and the wiring PL corresponds to the conductor 110. Figure 3A , Figure 3C and Figure 3D As shown in FIG. 1 , it is preferable that the conductor 262 is provided to extend in the Y direction, and the conductor 242 is provided to extend in the X direction. By adopting this structure, the wiring BL and the wiring WL intersect each other. Figure 3A The wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited thereto. For example, the wiring PL may be parallel to the wiring WL (conductor 260) or the wiring BL (conductor 240).

[0070] [Transistor 200] Figure 1A is a plan view of transistor 200, Figure 1B It is shown Figure 1A An enlarged view of a portion of the structure shown. Figure 1C It is along Figure 1A A cross-sectional view of the portion along the dashed line A1-A2 in FIG. Figure 1D It is along Figure 1A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. Figure 1A Among the components included in the transistor 200 in the plan view of FIG. 1 , only the conductor 240 , the conductor 242 , the conductor 260 , and the conductor 262 are shown, and the other components are omitted.

[0071] like Figures 1A to 1D As shown, transistor 200 includes a conductor 260, an oxide semiconductor 230, a conductor 242, a conductor 240, and an insulator 250. Conductor 260 is used as a gate electrode of transistor 200. Oxide semiconductor 230 is used as a channel formation region of transistor 200. Conductor 240 is used as one of a source electrode and a drain electrode of transistor 200, and conductor 242 is used as the other of the source electrode and the drain electrode of transistor 200. Insulator 250 is used as a gate insulator of transistor 200.

[0072] The conductor 260 has, for example, a columnar region. Figures 1A to 1D In the structure shown, an example is shown in which the conductor 260 has a cylindrical shape. The oxide semiconductor 230 has a region arranged so as to face the side surface of the conductor 260. The insulator 250 preferably has a region in contact with the side surface of the conductor 260, and the region is sandwiched between the conductor 260 and the oxide semiconductor 230, for example. The oxide semiconductor 230 is arranged so as to surround the conductor 260 via the insulator 250. Figures 1A to 1DIn the structure shown, the insulator 250 has a cylindrical region that surrounds the conductor 260. For example, the insulator 250 may be arranged to surround the outside of the columnar region in the conductor 260. Here, when viewed from a plane, the insulator 250 is arranged, for example, on the outside of the conductor 260. Figures 1A to 1D In the structure shown, the oxide semiconductor 230 has a cylindrical region, which surrounds the conductor 260. For example, the oxide semiconductor 230 can be shown to be arranged in a manner surrounding the outer side of the columnar region in the conductor 260. Figure 1A In the top view shown, the oxide semiconductor 230 is arranged, for example, outside the conductor 260. Figure 1A In the plan view shown in FIG. 1 , the conductor 260 is surrounded by the oxide semiconductor 230. Figures 1A to 1D In the figure, the oxide semiconductor 230 can be represented as having a hollow cylindrical shape. Here, the hollow cylinder refers to a structure in which a first cylinder is hollowed out by a second cylinder, the centers of the first cylinder and the second cylinder are the same, and the diameter of the second cylinder is smaller than the diameter of the first cylinder. It can also be represented as a hollow portion in which the conductor 260 is arranged in the hollow cylindrical shape area of ​​the oxide semiconductor 230. Here, the tubular structure refers to, for example, a structure in which a first cylinder is hollowed out by a second cylinder. In addition, the axes of the first column and the second column can be the same or different.

[0073] Here, it is preferred that the shape of the pillar viewed from the top surface is substantially the same even if the heights of the upper part, the middle part, the lower part, etc. are different. However, depending on the height of the pillar, the shape of the top surface (e.g., the cross section viewed from the Z direction) may be different. For example, the pillar may have a bulging shape in which the area viewed from the top surface increases as it approaches the middle part and decreases as it approaches the upper bottom. In addition, the side surface of the pillar may have concavities and convexities.

[0074] An insulator 140 is disposed on a substrate (not shown), and an insulator 141 and a conductor 262 are disposed on the insulator 140. The conductor 262 is provided, for example, in a manner embedded in an opening of the insulator 141. A conductor 260 is disposed on the conductor 262. The conductor 260 is preferably provided in a manner in contact with the top surface of the conductor 262. As the insulator 140, a single layer or a stack of insulators described in [Insulator] to be described later can be used.

[0075] The insulator 142 is arranged on the conductor 262 and the insulator 141, and the conductor 242 and the insulator 143 are arranged on the insulator 142. The conductor 242 is provided, for example, in a manner of being embedded in the opening 142p of the insulator 143. The conductor 260 has a region arranged in the opening 142p of the insulator 142, a region arranged in the opening 242p of the conductor 242, and a region surrounded by the oxide semiconductor 230. The conductor 260 can be expressed as penetrating the opening 242p of the conductor 242.

[0076] The insulator 250 has a region sandwiched between the conductor 260 and the conductor 242. The conductor 260 and the conductor 242 are preferably electrically insulated from each other via the insulator 250.

[0077] Alternatively, the insulator 142 may be a continuous layer made of the same material as the insulator 250 .

[0078] A single layer or a stack of insulators described in [Insulator] described later can be used as the insulator 250. For example, silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are thermally stable and therefore are preferred.

[0079] In addition, a material having a high relative dielectric constant, that is, a so-called high-k material described in [Insulator] described later, may be used as the insulator 250. For example, hafnium oxide or aluminum oxide may be used.

[0080] The thickness of the insulator 250 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. At least a portion of the insulator 250 may be a region having the above thickness.

[0081] The concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0082] A single layer or a stack of conductors described in [Conductor] described later can be used as the conductor 260. For example, a highly conductive material such as tungsten can be used as the conductor 260.

[0083] In addition, as the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. As the conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride) and a conductive material containing oxygen (for example, ruthenium oxide) can be cited. Thus, the decrease in the conductivity of the conductor 260 can be suppressed.

[0084] In addition, since the conductor 242 has a region in contact with the oxide semiconductor 230, it is preferably a conductive material containing oxygen described in [Conductor] described later. By using a conductive material containing oxygen as the conductor 242, conductivity can be maintained even if the conductor 242 absorbs oxygen from the oxide semiconductor 230. As the conductor 242, for example, a single layer or a stacked layer of indium tin oxide (also called ITO), indium tin oxide added with silicon (also called ITSO), indium zinc oxide (also called IZO (registered trademark)), etc. can be used.

[0085] In addition, when the oxide semiconductor 230 is in contact with the conductor 242, a metal compound or oxygen vacancies are formed, and the resistance of the region in contact with the conductor 242 and the region near the oxide semiconductor layer 230 is reduced. When the resistance of the oxide semiconductor 230 in contact with the conductor 242 is reduced, the contact resistance between the oxide semiconductor 230 and the conductor 242 can be reduced.

[0086] Figures 1A to 1D Although an example in which the conductor 260 has a cylindrical shape is shown, the conductor 260 may have various columnar shapes such as an elliptical column and a polygonal column.

[0087] In addition, the shape of the region of the conductor 260 is not limited to a column. For example, the conductor 260 may have a cone-shaped region (sometimes referred to as a cone region or a cone region) such as a circular cone, an elliptical cone, or a polygonal cone. In addition, the conductor 260 may have a column shape or a cone shape having a bottom surface with curved corners of a polygon such as a quadrangle.

[0088] In addition, in the conical shape, for example, the area of ​​the shape of the bottom surface (here, the surface close to the top surface of the conductor 262) when viewed from the top surface is large, and the area gradually decreases as it approaches the top. In addition, the side surface of the cone may also have bumps. In addition, the conductor 260 may also have a needle-like shape. Here, the needle-like shape refers to a shape that becomes thinner as it approaches the top. In addition, the top of the needle may be an acute angle, or it may have a curved surface shape that bulges downward. In addition, the shape in which the top of the needle is an acute angle may also be called a V-shape.

[0089] The oxide semiconductor 230 is disposed on the conductor 242. The conductor 240 is disposed on the oxide semiconductor 230. The oxide semiconductor 230 preferably has a region in contact with the top surface of the conductor 242. The conductor 240 preferably has a region in contact with the top surface of the oxide semiconductor 230.

[0090] Figure 1AThe example in which the shape of the conductor 240 when viewed from the top is circular is shown. Note that the shape of the conductor 240 when viewed from the top is not limited to a circle, and may be an ellipse, a polygon, etc. In addition, the conductor 240 may extend in the X direction or the Y direction, for example.

[0091] As the conductor 240, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 240, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. In addition, for example, a structure in which tantalum nitride is stacked on titanium nitride can also be provided. In this case, titanium nitride contacts a constituent element disposed on the upper layer of the transistor 200 (for example, the conductor 120 and the insulator 144 to be described later) and tantalum nitride contacts the oxide semiconductor 230. By adopting such a structure, excessive oxidation of the conductor 120 due to the oxide semiconductor 230 can be suppressed. In addition, in the case where an oxide insulator is used for the insulator 144 disposed on the upper layer of the transistor 200, excessive oxidation of the conductor 240 due to the insulator 144 can be suppressed. Alternatively, as the conductor 240, for example, a structure in which tungsten is stacked on titanium nitride can be provided.

[0092] In addition, since the conductor 240 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in [Conductor] described later. By using a conductive material containing oxygen as the conductor 240, conductivity can be maintained even if the conductor 240 absorbs oxygen. As the conductor 240, for example, a single layer or a stacked layer of indium tin oxide (also called ITO), indium tin oxide added with silicon (also called ITSO), indium zinc oxide (also called IZO (registered trademark)), etc. can be used.

[0093] In addition, when the oxide semiconductor 230 is in contact with the conductor 240, a metal compound or oxygen vacancies are formed, and the resistance of the region in contact with the conductor 240 and the region near the oxide semiconductor 230 is reduced. When the oxide semiconductor 230 in contact with the conductor 240 is reduced in resistance, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.

[0094] As the conductor 262 , a single layer or a stacked layer of conductors described in [Conductor] to be described later can be used.

[0095] In the transistor 200, an insulator 251 is disposed between the conductor 260 and the conductor 240. By providing the insulator 251, for example, a bias region can be provided in the oxide semiconductor 230. Here, the bias region refers to a region in the oxide semiconductor 230 to which a gate electric field is not easily applied. Figure 1C and Figure 1D In the oxide semiconductor 230, a region higher than the conductor 260 may become an offset region. Alternatively, in the region having a hollow cylindrical shape of the oxide semiconductor 230, a region higher than the conductor 260 may become an offset region.

[0096] The insulator 251 has a function of suppressing electric leakage between the conductor 240 and the conductor 260. In addition, the insulator 251 may be used as a protective layer for suppressing etching of the conductor 260 during a formation process of the oxide semiconductor 230, the conductor 240, and the like.

[0097] As the insulator 251, an insulator described in [Insulator] described later can be used. In particular, silicon nitride or silicon nitride oxide can be used appropriately as the insulator 251. In addition, as the insulator 251, hafnium oxide, aluminum oxide, zirconium oxide, magnesium oxide, etc. can also be used.

[0098] An insulator 252 is disposed outside the oxide semiconductor 230. The insulator 252 is preferably provided so as to be in contact with the side surface outside the oxide semiconductor 230.

[0099] Figure 1C and Figure 1D The insulator 252 is shown as an example of a stacked structure having an insulator 252a and an insulator 252b. As the insulator 252b, for example, the same material as the insulator 250 can be used. In addition, as the insulator 252a, for example, a material with a low relative dielectric constant described in [Insulator] described later can be used.

[0100] Alternatively, the insulator 252 may have a single-layer structure instead of a stacked-layer structure. For example, in the transistor 200, the insulator 252a or the insulator 252b may not be provided.

[0101] exist Figure 1C and Figure 1D In the embodiment, the oxide semiconductor 230 has a region covering the side surface of the conductor 240. The oxide semiconductor 230 preferably has a region in contact with the side surface of the conductor 240. In addition, the insulator 252b has a region covering the side surface of the conductor 240 via the oxide semiconductor 230. By having the oxide semiconductor 230 have a region in contact with the side surface of the conductor 240, for example, the contact area between the oxide semiconductor 230 and the conductor 240 can be increased to reduce the contact resistance. Note that the oxide semiconductor 230 may not cover the side surface of the conductor 240, in which case, for example, the insulator 252b or the insulator 252a may be in contact with the side surface of the conductor 240.

[0102] In addition, the oxide semiconductor 230 has, for example, a cylindrical first region and a cylindrical second region. The first region surrounds the conductor 260 , and the second region surrounds the conductor 240 .

[0103] In addition, as an insulator disposed near the channel formation region, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is preferably used. By heat treating the insulator containing excess oxygen, oxygen can be supplied from the insulator to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and V O H. Thus, the electrical characteristics of the transistor 200 can be stabilized and the reliability can be improved.

[0104] Figure 1E and Figure 1F The structure shown is Figure 1C and Figure 1D The structures shown differ in that: Figure 1E and Figure 1F The structures shown all include a metal oxide 231 between an oxide semiconductor 230 and a conductor 242 .

[0105] In addition, as Figure 1E and Figure 1F As an example of the structure shown, the conductor 262 has a laminated structure of the conductor 262a and the conductor 262b, the conductor 242 has a laminated structure of the conductor 242a and the conductor 242b, and the conductor 240 has a laminated structure of the conductor 240a and the conductor 240b. Figure 1C and Figure 1D In other structural examples, the conductor 262 , the conductor 242 , and the conductor 240 may have a stacked structure.

[0106] Regarding materials that can be used as the conductor 262a, the conductor 262b, the conductor 242a, the conductor 242b, the conductor 240a, and the conductor 240b, refer to the description in [Conductor] which will be described later.

[0107] The metal oxide 231 preferably has a lower resistance than the oxide semiconductor 230 . The metal oxide 231 has a higher resistance than the conductor 242 , for example.

[0108] The metal oxide 231 has a lower resistance than the oxide semiconductor 230. For example, the metal oxide 231 does not become a channel formation region. Figure 1C and Figure 1D Compared to the transistor 200 shown, for example, Figure 1E and Figure 1F The transistor 200 is shown to have a short effective channel length.

[0109] When the transistor 200 is an n-channel transistor and the conductor 242 serves as a drain electrode, the inclusion of the metal oxide 231 makes it difficult for a high electric field to be generated near the drain region, and generation of hot carriers can be suppressed, thereby suppressing transistor degradation.

[0110] The metal oxide 231 is preferably a material that can make ohmic contact with the conductor 242. This can reduce the contact resistance between the metal oxide 231 and the conductor 242, and can increase the on-state current of the transistor 200 compared to a structure in which the oxide semiconductor 230 and the conductor 242 are in contact.

[0111] Figure 1E and Figure 1F The transistor 200 shown includes a conductor 260, an oxide semiconductor 230, a metal oxide 231, a conductor 242, a conductor 240, and an insulator 250. The oxide semiconductor 230 has a region arranged in a manner opposite to the side surface of the conductor 260 via the insulator 250. The metal oxide 231 has a region arranged in a manner opposite to the side surface of the conductor 260 via the insulator 250. The insulator 250 has a region sandwiched between the conductor 260 and the oxide semiconductor 230 and a region sandwiched between the conductor 260 and the metal oxide 231. The metal oxide 231 is arranged between the oxide semiconductor 230 and the conductor 242. The metal oxide 231 is preferably in contact with the top surface of the conductor 242. In addition, the metal oxide 231 is preferably in contact with the oxide semiconductor 230. Note that the metal oxide 231 and the oxide semiconductor 230 are sometimes observed as a continuous film.

[0112] The metal oxide 231 and the oxide semiconductor 230 preferably contain the same metal element. As the metal oxide 231, for example, one or more of the materials listed as the oxide semiconductor 230 can be used in combination. As the metal oxide 231, for example, reference can be made to the description in [Metal Oxide] to be described later. In particular, indium tin oxide, indium tin oxide containing silicon, zinc oxide, tin oxide, titanium oxide, zinc oxide containing gallium, zinc oxide containing aluminum, etc. can be appropriately used. Here, in indium tin oxide containing silicon, for example, when the number of indium atoms is 100, the number of silicon atoms is preferably greater than 2 and less than 25.

[0113] In addition, the material that can be used as the metal oxide 231 is not limited to metal oxides. For example, graphene, graphene compounds, etc. can also be used. In addition, graphene, graphene compounds, etc. can be used in combination with metal oxides.

[0114] The metal oxide 231 is arranged so as to surround the conductor 260 via the insulator 250 .

[0115] Note that the metal oxide 231 can be formed by an ALD method or a sputtering method as appropriate. The details of the method for forming the metal oxide 231 will be described later.

[0116] The channel length of the transistor 200 depends on the distance between the source region and the drain region. The channel length of the transistor 200 is, for example, the length of a region where a channel is formed in the oxide semiconductor 230. In the oxide semiconductor 230, the region where a channel is formed is, for example, a region of the oxide semiconductor 230 that faces the conductor 260.

[0117] In addition, in the oxide semiconductor 230 , for example, an offset region is not included in the channel formation region.

[0118] Figure 2A Show enlarged Figure 1C In addition, Figure 2A An example of a region 230 n of a low resistance region and a region 230 i of an i-type region of the oxide semiconductor 230 is shown.

[0119] The channel length of the transistor 200 may be, for example, a region where the gate electrode in the oxide semiconductor 230 is located between the conductor 242 and the conductor 240, that is, a region overlapping the conductor 260. Figure 2A As shown, the channel length Lg of the transistor 200 can be represented by, for example, the length of a region overlapping with the conductor 260 in the oxide semiconductor 230 .

[0120] In addition, in the oxide semiconductor 230 , the length of the region 230 i in the region overlapping with the conductor 260 is referred to as a length Li. For example, the length Li can be regarded as an effective channel length of the transistor 200 .

[0121] In addition, Figure 2A In the figure, the region Off can be represented, for example, as a region in the region 230i that does not overlap with the conductor 260. The region Off can be represented as an offset region. In addition, the size of the region Off varies depending on the amount of oxygen or hydrogen diffused from the insulator to the oxide semiconductor 230. For example, when the amount of hydrogen diffused from the insulator 251 is large, the region Off sometimes becomes narrower.

[0122] Figure 2B Show enlarged Figure 1E Part of the diagram.

[0123] exist Figure 2B In the embodiment, the channel length of the transistor 200 may be, for example, the region where the gate electrode in the oxide semiconductor 230 and the metal oxide 231 is located between the conductor 242 and the conductor 240, that is, the region overlapping with the conductor 260. Figure 2B As shown, the channel length Lg of the transistor 200 can be expressed as, for example, the sum of the length Li of the region overlapping the conductor 260 in the oxide semiconductor 230 and the length Lov of the region overlapping the conductor 260 in the metal oxide 231 .

[0124] In addition, the metal oxide 231 preferably has a lower resistance than the oxide semiconductor 230. When the metal oxide 231 has a lower resistance than the oxide semiconductor 230, the channel formation region may not include the metal oxide 231. In this case, for example, the length of the region overlapping with the conductor 260 in the oxide semiconductor 230, that is, the length Li, may be considered to be the effective channel length of the transistor 200.

[0125] Notice, Figure 2A and Figure 2B The region 230n and the region 230i shown are examples, and each region changes according to the diffusion amount of hydrogen released from the insulator and the conductor near the oxide semiconductor 230, the diffusion amount of oxygen released from the insulator, etc. In addition, when the diffusion amount of hydrogen released from the insulator 251 is large, the oxide semiconductor 230 near the insulator 251 tends to become a low resistance region, and when the diffusion amount of hydrogen is small or the diffusion amount of oxygen is large, for example, the oxide semiconductor 230 near the insulator 251 sometimes becomes an i-type region.

[0126] In addition, the channel length of the transistor 200 varies depending on, for example, the distance between the conductor 242 and the conductor 240. The distance between the conductor 242 and the conductor 240 varies depending on, for example, the height of the insulator 252 located between the two conductors.

[0127] In the existing transistor, the channel length is set according to the exposure limit of the photolithography method, but in the present invention, for example, the channel length can be set according to the height of the conductor 240, the height of the insulator 252, and the distance between the top surface of the conductor 242 and the bottom surface of the conductor 240. Therefore, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of the photolithography method (for example, below 60nm, below 50nm, below 40nm, below 30nm, below 20nm, or below 10nm and above 1nm or above 5nm). Therefore, the on-state current of the transistor 200 becomes larger, so that the frequency characteristics can be improved. As a result, the read speed and write speed of the memory cell 150 can be improved, so a memory device with a high operating speed can be provided.

[0128] In addition, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in a concentric circle. Therefore, the side surface of the conductor 260 arranged in the center is opposite to the side surface of the oxide semiconductor 230 via the insulator 250. In other words, the circle of the oxide semiconductor 230 as a whole becomes a channel formation region when viewed from a plane. At this time, for example, the channel width of the transistor 200 is determined by the length of the outer circumference of the oxide semiconductor 230. That is, it can be said that the channel width W of the transistor 200 is determined by the size of the maximum diameter D of the conductor 260 (the maximum diameter when the conductor 260 is circular when viewed from a plane) and the thickness of the insulator 250. For example, by increasing the size of the maximum diameter D of the conductor 260, the channel width per unit area can be increased to increase the on-state current.

[0129] When the conductor 260 is formed by photolithography, the maximum diameter D of the conductor 260 is set according to the exposure limit of the photolithography. The maximum diameter D of the conductor 260 is preferably, for example, 0.5 nm or more, 3 nm or more, or 10 nm or more and 45 nm or less, 20 nm or less, 10 nm or less, 5 nm or less, or 3 nm or less. Note that when the conductor 260 is circular when viewed from a plane, the maximum diameter D of the conductor 260 is equivalent to the diameter of the conductor 260, and the channel width W can be calculated as "D×π".

[0130] In addition, the conductor 260 is formed to have a circular shape when viewed from a plane, so that the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in concentric circles. As a result, the distance between the conductor 260 and the oxide semiconductor 230 is substantially uniform, so that the gate electric field can be applied to the oxide semiconductor 230 substantially uniformly.

[0131] In the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer, it is preferred that the number of oxygen vacancies is small or the concentration of impurities such as hydrogen, nitrogen, and metal elements is low compared to the source region and the drain region. In addition, hydrogen near an oxygen vacancy sometimes forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V O H) and generate electrons that become carriers, so in the channel formation region V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0132] In addition, the source region and the drain region of a transistor using an oxide semiconductor for a semiconductor layer are regions where there are more oxygen vacancies than in a channel formation region, and V OThe resistance is reduced by increasing the carrier concentration when there is more H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of the transistor are n-type regions with higher carrier concentration and lower resistance than the channel formation region.

[0133] When the conductor 260 has a columnar region, its sidewall is preferably perpendicular to the top surface of the substrate provided with the memory cell 150. By including a vertical sidewall, the area occupied by the conductor 260 can be reduced, thereby achieving high integration of a circuit using the transistor 200.

[0134] Alternatively, the side wall of the conductor 260 may also have a tapered shape. In the case where the conductor 260 has a tapered region, the side wall of the conductor 260 has, for example, a tapered shape. When the side wall of the conductor 260 has a tapered shape, for example, the coverage of the conductor 260 by the insulator 250 and the coverage of the insulator 250 by the oxide semiconductor 230 can be improved. By improving the coverage, the thickness uniformity of the formed layer is improved. In addition, defects such as voids in the formed layer can be reduced.

[0135] For example, when the conductor 260 has a columnar region, the angle An formed by the side surface of the conductor 260 and the top surface of the conductor 262 or the top surface of the insulator 142 is preferably 90 degrees or thereabouts. For example, the angle An is preferably 90 degrees, preferably 85 degrees or more and 95 degrees or less. Alternatively, the angle An is, for example, 70 degrees or more and less than 85 degrees.

[0136] When the angle An is greater than 90 degrees, the shape of the conductor 260 is sometimes referred to as a tapered shape, and when the angle An is less than 90 degrees, the shape of the conductor 260 is sometimes referred to as a reverse tapered shape.

[0137] The band gap of the metal oxide used as the oxide semiconductor 230 is preferably, for example, greater than 2 eV. In particular, in the oxide semiconductor used as the channel formation region, the band gap is preferably greater than 2 eV, and more preferably greater than 2.5 eV. By using a metal oxide with a large band gap as the oxide semiconductor 230, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for a memory cell, the storage content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced. In addition, the frequency of the refresh operation required for a general DRAM is about 1 time / 60 msec, and the frequency of the refresh operation of a memory device of one embodiment of the present invention can be about 1 time / 10 sec, that is, more than 10 times or more than 100 times the frequency of the refresh line operation can be achieved. In addition, by using a memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to more than 1 time / 1 sec and less than 1 time / 100 sec, preferably more than 1 time / 5 sec and less than 1 time / 50 sec.

[0138] Note that as the oxide semiconductor 230 , a single layer or a stacked layer of a metal oxide described in [Metal Oxide] to be described later can be used.

[0139] As the oxide semiconductor 230, specifically, a metal oxide having the following composition can be used: In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0140] In addition, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0141] As an analysis of the composition of the metal oxide used for the oxide semiconductor 230, for example, energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectrometry), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. Alternatively, a combination of multiple of the above methods can be used for analysis. Note that elements with low contents are sometimes affected by the accuracy of analysis, and the actual contents are different from the contents obtained by analysis. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0142] The metal oxide can be formed by sputtering or atomic layer deposition (ALD) as appropriate. Note that when the metal oxide is formed by sputtering, the composition of the metal oxide after formation is sometimes different from the composition of the sputtering target. In particular, the zinc content in the metal oxide after formation is sometimes reduced to about 50% of the zinc content in the sputtering target.

[0143] The oxide semiconductor 230 preferably has crystallinity. Examples of crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductors, and single crystal oxide semiconductors. CAAC-OS or nc-OS is preferably used as the oxide semiconductor 230, and CAAC-OS is particularly preferably used.

[0144] The CAAC-OS preferably has a plurality of layered crystal regions and its c-axis is oriented in the normal direction of the formed surface. For example, the oxide semiconductor 230 preferably has layered crystals that are roughly parallel to the side walls of the insulator 250. By adopting this structure, the layered crystals of the oxide semiconductor 230 are roughly parallel to the channel length direction of the transistor 200, so the on-state current of the transistor can be increased.

[0145] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by heat treating the metal oxide at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of the CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0146] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0147] In addition, when a crystalline oxide such as CAAC-OS is used as the oxide semiconductor 230, oxygen can be suppressed from being extracted from the oxide semiconductor 230 by the source electrode or the drain electrode. Therefore, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, so that the transistor 200 is stable to high temperatures (so-called thermal budget) in the manufacturing process.

[0148] The crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of a plurality of the above methods.

[0149] Note that Figure 1C and Figure 1D 2 shows that the oxide semiconductor 230 is a single-layer structure, but the present invention is not limited to this. The oxide semiconductor 230 may also have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types selected from the above-mentioned metal oxides are appropriately stacked may also be adopted. In addition, the metal oxide 231 may also have a stacked structure in the same manner.

[0150] Note that the composition of the metal oxide used as the oxide semiconductor 230, the metal oxide 231, and the like may be continuously changed. For example, when the metal oxide is formed by the ALD method, the composition may be changed according to the number of times a layer containing a metal element is formed, the formation time, and the like. Therefore, for example, the composition may be changed so that the band gap decreases as it approaches the source electrode or the drain electrode.

[0151] In addition, the electrical conductivity of the material used for the metal oxide 231 is preferably different from the electrical conductivity of the material used for the oxide semiconductor 230 .

[0152] For example, the metal oxide 231 may use a material having higher conductivity than the oxide semiconductor 230. By using a material having higher conductivity for the metal oxide 231 in contact with the conductor 242 serving as a source electrode or a drain electrode, the contact resistance between the oxide semiconductor 231 and the conductor 242 can be reduced, thereby realizing a transistor having a large on-state current.

[0153] In addition, the carrier concentration of the metal oxide 231 is preferably higher than the carrier concentration of the oxide semiconductor 230. By increasing the carrier concentration of the metal oxide 231, the conductivity becomes higher, and the contact resistance between the metal oxide 231 and the conductor 242 can be reduced, thereby realizing a transistor with a large on-state current. In addition, by reducing the carrier concentration of the oxide semiconductor 230, the conductivity becomes lower, thereby realizing a normally-off transistor.

[0154] The band gap of the first metal oxide used for the metal oxide 231 is preferably different from the band gap of the second metal oxide used for the oxide semiconductor 230. For example, the difference between the band gaps of the first metal oxide and the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and further preferably 0.3 eV or more.

[0155] The band gap of the first metal oxide used for the metal oxide 231 can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230. Thus, the contact resistance between the metal oxide 231 and the conductor 242 can be reduced, thereby realizing a transistor with a large on-state current. In addition, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, thereby realizing a normally-off transistor.

[0156] Here, although an example in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide is shown, one embodiment of the present invention is not limited thereto. The band gap of the first metal oxide may be larger than the band gap of the second metal oxide.

[0157] As described above, the band gap of the first metal oxide may be smaller than the band gap of the second metal oxide. The composition of the first metal oxide is preferably different from the composition of the second metal oxide. The band gap can be controlled by making the composition of the first metal oxide different from the composition of the second metal oxide. For example, the content of element M of the first metal oxide is preferably lower than the content of element M of the second metal oxide. Specifically, in the case where the first metal oxide and the second metal oxide are In-M-Zn oxides, the composition of the first metal oxide can be set to In:M:Zn=1:1:1 [atomic number ratio] or thereabouts, and the composition of the second metal oxide can be set to In:M:Zn=1:3:2 [atomic number ratio] or thereabouts. As element M, it is particularly preferred to use one or more of gallium, aluminum and tin.

[0158] The first metal oxide may not contain the element M. For example, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-Ga-Zn oxide. More specifically, the composition of the first metal oxide may be set to In:Zn=1:1 [atomic ratio] or thereabouts or In:Zn=4:1 [atomic ratio] or thereabouts, and the composition of the second metal oxide may be set to In:Ga:Zn=1:1:1 [atomic ratio] or thereabouts.

[0159] Here, although an example is shown in which the content of the element M of the first metal oxide is lower than the content of the element M of the second metal oxide, one embodiment of the present invention is not limited thereto. Sometimes the content of the element M of the first metal oxide is higher than the content of the element M of the second metal oxide. In addition, as long as the compositions of the first metal oxide and the second metal oxide are different, the contents of elements other than the element M of the first metal oxide and the second metal oxide may also be different.

[0160] The thickness of each of the oxide semiconductor 230 and the metal oxide 231 is preferably 0.5 nm or more, 1 nm or more, or 3 nm or more and 20 nm or less, 10 nm or less, 8 nm or less, or 5 nm or less. Here, the thickness of the oxide semiconductor 230 and the metal oxide 231 refers to the thickness when the side surface of the insulator 250 is formed, for example.

[0161] At least one of the insulator 252a and the insulator 252b may include an insulator containing oxygen. By increasing the oxygen content of at least one of the insulator 252a and the insulator 252b, an i-type region is easily formed in a region of the oxide semiconductor 230 that is in contact with the insulator 252 and in the vicinity thereof.

[0162] In addition, as at least one of the insulator 252a and the insulator 252b, a film that releases oxygen by heating is preferably used. Since the insulator 252a or the insulator 252b releases oxygen due to heat applied in the manufacturing process of the transistor 200, oxygen can be supplied to the oxide semiconductor 230. By supplying oxygen from the insulator 252 to the oxide semiconductor 230, especially to the channel formation region of the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 and V O H, a transistor with good electrical characteristics and high reliability can be realized.

[0163] For example, oxygen can be supplied to the insulator 252a or the insulator 252b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by depositing an oxide film on the top surface of the insulator 252a or the insulator 252b by sputtering in an oxygen atmosphere. Then, the oxide film can also be removed.

[0164] The insulator 252a and the insulator 252b are preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method. In particular, when the sputtering method is used, a deposition method that does not use hydrogen gas as a deposition gas is used for deposition, thereby achieving a film with a very low hydrogen content. Therefore, the semiconductor 230 can be suppressed from being supplied with hydrogen and the electrical characteristics of the transistor 200 can be stabilized.

[0165] When the channel length of the transistor 200 is small, oxygen vacancies in the channel formation region and V O By supplying oxygen from the insulator 252a or the insulator 252b to the oxide semiconductor 230, oxygen vacancies and V can be suppressed at least in a region of the oxide semiconductor 230 that is in contact with the insulator 252a or the insulator 252b or in a region near the insulator 252a or the insulator 252b. O H increases. Therefore, a transistor with a small channel length having good electrical characteristics and high reliability can be realized.

[0166] In addition, as at least one of the insulator 252a and the insulator 252b, an insulator having a function of capturing or fixing hydrogen described in [Insulator] described later may be used. By adopting such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed to reduce the hydrogen concentration of the oxide semiconductor 230. As an insulator having a function of capturing or fixing hydrogen, magnesium oxide, aluminum oxide, or the like can be used.

[0167] In addition, the insulator 252a may have a stacked structure. For example, a stacked structure may be provided with an insulator that releases oxygen and an insulator that has oxygen blocking properties. For example, an insulator that has oxygen blocking properties may be arranged outside the insulator that releases oxygen. Thus, the outward diffusion of oxygen in the insulator that releases oxygen may be suppressed. Thus, oxygen may be effectively supplied to the oxide semiconductor 230.

[0168] In addition, the insulator 252a may have a stacked structure. For example, a stacked structure may have an insulator that releases oxygen and an insulator that has hydrogen barrier properties. For example, an insulator that has hydrogen barrier properties may be arranged outside the insulator that releases oxygen. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through the insulator 252 to the oxide semiconductor 230. Since both the silicon nitride film and the silicon oxynitride film have the characteristics of releasing few impurities (for example, water and hydrogen) from themselves and oxygen and hydrogen are not easily permeable, they can be used appropriately.

[0169] In addition, the insulator 252a may have a stacked structure. For example, a stacked structure may have an insulator that releases oxygen and an insulator that has the function of capturing or fixing hydrogen. For example, an insulator that has the function of capturing or fixing hydrogen may be arranged on the outside of the insulator that releases oxygen. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the insulator 252 to the oxide semiconductor 230, and it is possible to capture or fix hydrogen in the oxide semiconductor 230, thereby reducing the hydrogen concentration of the oxide semiconductor 230. As an insulator that has the function of capturing or fixing hydrogen, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. In addition, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may also be used.

[0170] [Capacitor 100] Figure 3A , Figure 3C and Figure 3D The capacitor 100 shown includes a conductor 120, an insulator 130, and a conductor 110. The conductor 120 is used as one of a pair of electrodes (sometimes referred to as a lower electrode), the conductor 110 is used as the other of the pair of electrodes (sometimes referred to as an upper electrode), and the insulator 130 is used as a dielectric. That is, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0171] The conductor 120 is disposed on the conductor 240. The conductor 120 preferably has a region in contact with the top surface of the conductor 240. The conductor 120 and the conductor 240 are electrically connected.

[0172] The conductor 120 may have a columnar region such as a cylinder, an elliptical cylinder, or a polygonal column. The conductor 120 may also have a cone region such as a cone, an ellipse, or a polygonal cone. The conductor 120 may also have a columnar or cone shape having a bottom surface with curved corners of a polygon such as a quadrangle.

[0173] In the case of a trench capacitor, for example, a conductor is formed so as to cover the inner wall of an opening provided in an insulator or the like, and a dielectric is formed so as to cover the inside thereof. In this case, when the opening diameter of the opening provided in the insulator or the like becomes smaller, the coverage of the bottom of the opening or the region from the bottom to the side wall or the like may be reduced. By adopting a columnar or conical shape as the shape of the conductor 120 and covering the outside of the conductor 120 with a dielectric, miniaturization can be coped with.

[0174] Notice, Figure 3A , Figure 3B and Figure 3D Capacitor 100 shown in FIG. 1 is sometimes referred to as a pillar-type capacitor.

[0175] In addition, when the conductor 120 has a columnar region, its side wall is preferably perpendicular to the top surface of the substrate provided with the memory cell 150. By including a vertical side wall, the area occupied by the conductor 120 can be reduced, thereby achieving high integration of the memory cell. In the case where the conductor 120 has a columnar region, the angle formed by the side surface of the conductor 120 and the top surface of the conductor 240 or the top surface of the insulator 252a is greater than 60 degrees, preferably greater than 70 degrees, and more preferably greater than 80 degrees and less than 90 degrees.

[0176] Alternatively, the side wall of the conductor 120 may also have a tapered shape. When the conductor 120 has a tapered region, the side wall of the conductor 120 has, for example, a tapered shape. When the side wall of the conductor 120 has a tapered shape, for example, the coverage of the conductor 120 by the insulator 130 and the coverage of the insulator 130 by the conductor 110 can be improved.

[0177] The higher the height of the conductor 120 is, the larger the electrostatic capacitance of the capacitor 100 can be. Thus, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the read operation of the memory device can be stabilized. In addition, the miniaturization or high integration of the memory device can be promoted.

[0178] A single layer or a stack of conductors described in [Conductor] described later can be used as the conductor 120. For example, a highly conductive material such as tungsten can be used as the conductor 120.

[0179] In addition, as the conductor 120, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. As the conductive material, conductive materials containing nitrogen (for example, titanium nitride or tantalum nitride) and conductive materials containing oxygen (for example, ruthenium oxide) can be cited. Thus, the decrease in the conductivity of the conductor 260 can be suppressed.

[0180] The insulator 130 is provided on the conductor 120. The insulator 130 is provided so as to cover the top surface and the side surface of the conductor 120. In addition, the insulator 130 is preferably provided so as to be in contact with the side surface of the conductor 120. Thus, the conductor 110 and the conductor 120 can be prevented from being short-circuited.

[0181] The structure, material, etc. that can be used as the insulator 130 will be described later.

[0182] exist Figure 3C and Figure 3D In the structure shown, an insulator 121 is provided on the conductor 120. The insulator 121 is located between the conductor 120 and the conductor 110. In addition, the insulator 121 is preferably provided in a manner of contacting the top surface of the conductor 120. In addition, the structure of the combination of the insulator 121 and the conductor 120 preferably has a columnar region, for example. Alternatively, the structure of the combination of the insulator 121 and the conductor 120 may have a conical region, for example.

[0183] At the top of the columnar shape or the top of the cone shape, for example, electric field concentration may easily occur between the conductor 120 and the conductor 110. In addition, depending on the formation conditions and thickness of the insulator 130, for example, the coverage of the insulator 130 on the top of the columnar shape or the top of the cone shape may be insufficient. In the capacitor 100, by providing the insulator 121 between the conductor 120 and the conductor 110, current leakage of the conductor 120 and the conductor 110 due to electric field concentration and insufficient coverage can be suppressed, thereby improving the reliability of the capacitor 100.

[0184] In addition, the insulator 121 may be used as a protective layer for preventing the conductor 120 from being etched during a step of forming the insulator 144 and the like.

[0185] As the insulator 121 , for example, a material that can be used as the insulator 251 can be appropriately used.

[0186] Alternatively, a structure may be adopted in which the side end of the insulator 130 is aligned with the side end of the conductor 110. With such a structure, the insulator 130 and the conductor 110 can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

[0187] The conductor 110 is provided on the insulator 130. The conductor 110 is used as the wiring PL. The conductor 110 may also be provided together in a plurality of memory cells 150 electrically connected to the wiring PL. As the conductor 110, a single layer or a stack of conductors described in [Conductor] to be described later may be used. As the conductor 110, for example, a highly conductive conductive material such as tungsten may be used. By using a highly conductive conductive material in this way, the conductivity of the conductor 110 may be improved so that the conductor 110 can fully function as the wiring PL.

[0188] In addition, as the conductor 110, it is preferred to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion in a single layer or a stacked layer. For example, titanium nitride or indium tin oxide with silicon added may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which a first titanium nitride, tungsten, and a second titanium nitride are stacked in sequence may be used. By adopting such a structure, when an oxide insulator is used for the insulator 130, oxidation of the conductor 110 due to the insulator 130 may be suppressed.

[0189] exist Figure 3C and Figure 3D In the structure shown, the insulator 130 and the conductor 110 have a region provided in the opening portion provided in the insulator 144. The insulator 130 is provided so as to cover the side and top surfaces of the conductor 120 and the bottom and side surfaces of the opening provided in the insulator 144. In addition, the insulator 130 is provided so as to cover the top surface of the insulator 144.

[0190] The conductor 110 is provided so as to cover the side surface and the top surface of the conductor 120. In addition, the conductor 110 is provided so as to cover the bottom surface and the side surface of the opening provided in the insulator 144. In addition, the conductor 110 is provided so as to cover the top surface of the insulator 144.

[0191] The insulator 130 has a region provided between the conductor 110 and the insulator 144. The conductor 110 covers the side surface of the conductor 120, for example, via the insulator 130. In addition, the conductor 110 covers the top surface of the conductor 120, for example, via the insulator 121 and the insulator 130. In addition, the conductor 110 covers the bottom surface and side surfaces of the opening provided in the insulator 144, for example, via the insulator 130.

[0192] It is preferable to use a material having a high relative dielectric constant, i.e., a so-called high-k material, as described in [Insulator] described later as the insulator 130. By using the high-k material as the insulator 130, the thickness of the insulator 130 can be increased to a level that can suppress leakage current and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0193] In addition, as the insulator 130, it is preferred to stack an insulating layer composed of a high-k material, and it is preferred to use a stacked structure of a material with a high relative dielectric constant (high-k) and a material with a dielectric strength greater than that of the high-k material. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator with a relatively large dielectric strength such as aluminum oxide, the dielectric strength can be increased and the electrostatic destruction of the capacitor 100 can be suppressed.

[0194] In addition, a material having ferroelectricity may be used as the insulator 130. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which an element J1 (herein, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. Here, the ratio of the number of hafnium atoms to the number of atoms of the element J1 can be appropriately set. For example, the ratio of the number of hafnium atoms to the number of atoms of the element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material in which an element J2 (herein, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited. In addition, the ratio of the number of zirconium atoms to the number of atoms of the element J2 can be appropriately set. For example, the ratio of the number of zirconium atoms to the number of atoms of the element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0195] In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2 and nitrogen can be cited. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic number ratio of the element M1 to the element M2 can be appropriately set. In addition, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material in which the element M3 is added to the above-mentioned metal nitride can be cited. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the atomic number ratio of the element M1, the element M2 and the element M3 can be appropriately set.

[0196] In addition, as materials that can have ferroelectricity, there can be mentioned perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina.

[0197] Note that although the above description shows examples of metal oxides and metal nitrides, the present invention is not limited thereto and, for example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitride oxides obtained by adding oxygen to the above metal nitrides may also be used.

[0198] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. In addition, the insulator 130 can have a stacked structure composed of a plurality of materials selected from the above materials. Note that the crystal structure (properties) of the materials listed above may change not only depending on the deposition conditions but also depending on various processes, and thus in this specification, etc., a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0199] Metal oxides containing one or both of hafnium and zirconium are preferred because they can have ferroelectricity even if they are processed into a thin film of a few nm. Here, the thickness of the insulator 130 can be less than 100 nm, preferably less than 50 nm, more preferably less than 20 nm, and further preferably less than 10 nm (typically, more than 2 nm and less than 9 nm). For example, the thickness is preferably more than 8 nm and less than 12 nm. By using a ferroelectric layer that can be thin-filmed, the capacitor 100 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. Note that in this specification, etc., a material that can have ferroelectricity and is formed in a layered state is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification, etc., a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0200] In addition, metal oxides containing one or both of hafnium and zirconium are preferred because they can have ferroelectricity even when the area is small. For example, even if the area (occupied area) of the ferroelectric layer is 100 μm when viewed from a plane, 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following may also have ferroelectric properties. In addition, sometimes the area (occupied area) of the ferroelectric layer when viewed from a plane is 10000nm 2 Below or 1000nm 2 The area occupied by the capacitor 100 can be reduced by reducing the area of ​​the ferroelectric layer.

[0201] Ferroelectrics are insulators that are polarized internally when exposed to an external electric field and that maintain polarization even when the electric field is zero. Therefore, a nonvolatile memory element can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses the material as a dielectric. Nonvolatile memory elements using ferroelectric capacitors are sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memories, and the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to a terminal of the ferroelectric capacitor. Thus, in the case where a ferroelectric capacitor is used as the capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0202] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen of the crystal contained in the ferroelectric layer is displaced by the action of an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the crystal structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain crystals. In particular, the insulator 130 preferably contains crystals having an orthorhombic crystal structure, thereby exhibiting ferroelectricity. In addition, the crystal structure of the crystal contained in the insulator 130 is any one or more selected from the group consisting of cubic system, tetragonal system, orthorhombic system, monoclinic system and hexagonal system. In addition, the insulator 130 may also have an amorphous structure. At this time, the insulator 130 may also have a composite structure of an amorphous structure and a crystal structure.

[0203] Since the insulator 144 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 144, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used. Silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 144 contains at least silicon and oxygen.

[0204] Note that an insulator having an oxygen barrier property described in [Insulator] to be described later can be used as the insulator 144. Thus, desorption of oxygen from the oxide semiconductor 230 can be suppressed.

[0205] In addition, as the insulator 144, an insulator having hydrogen barrier properties described in [Insulator] described later is preferably used. Thus, diffusion of hydrogen from the insulator 130 and the conductor 110 to the oxide semiconductor 230 can be suppressed. Since silicon nitride and silicon oxynitride each have the characteristics of a small amount of impurities (e.g., water and hydrogen) released from themselves and oxygen and hydrogen are not easily permeable, they can be applied to the insulator 144. In this case, the insulator 144 contains at least silicon and nitrogen.

[0206] In addition, as the insulator 144, it is preferable to use an insulator having a function of capturing or fixing hydrogen as described in [Insulator] to be described later. By adopting such a structure, hydrogen of the insulator 130 can be captured or fixed to reduce the hydrogen concentration of the insulator 130. For example, magnesium oxide, aluminum oxide, or hafnium oxide can be used as appropriate for the insulator 144. In addition, as the insulator 144, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide can be used.

[0207] In addition, the insulator 144 may also have a stacked structure of two or more layers. For example, as a layer located on the oxide semiconductor 240 side in the stack, an insulator having oxygen barrier properties, an insulator having oxygen barrier properties, and an insulator having a function of capturing or fixing hydrogen may be used, and as a layer located on the insulator 130 side, a material with a low relative dielectric constant may be used.

[0208] Figure 4A The following is a structural example of a memory device in which two transistors 200 are arranged and share a conductor 242. One capacitor 100 is provided on each transistor 200, and the two capacitors 100 share a conductor 110.

[0209] in addition, Figure 4B The example of the structure in which the insulator 144 is not disposed between the regions of the conductor 110 covering the side surfaces of the conductors 120 included in the two capacitors 100 is shown.

[0210] <Constituent Materials of Storage Device> Next, constituent materials that can be used for the storage device are described.

[0211] [Substrate] As a substrate for forming the transistor 200 and the capacitor 100, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can also be cited. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can also be cited. Alternatively, a substrate provided with an element on these substrates can also be used. As the element provided on the substrate, there can be cited capacitors, resistors, switching elements, light-emitting elements, storage elements, etc. In addition, a substrate on which a circuit including a transistor is provided can be used. In addition, a substrate on which a circuit such as a drive circuit is provided can be used.

[0212] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0213] For example, when miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin filmization of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferred to select the material according to the function of the insulator. In addition, a material with a low relative dielectric constant is also a material with a large dielectric strength.

[0214] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0215] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, silicon oxide with holes can be cited. In addition, these silicon oxides can also contain nitrogen.

[0216] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used. Specifically, as an insulator having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0217] In addition, an insulator such as a gate insulator that contacts the semiconductor layer or an insulator that is disposed near the semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, when an insulator having a region containing excess oxygen contacts the semiconductor layer, or when an insulator having a region containing excess oxygen is disposed near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide having holes.

[0218] In addition, as an insulator having oxygen barrier properties, there can be mentioned an oxide containing one or both of aluminum and hafnium, an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, etc. In addition, as an oxide containing one or both of aluminum and hafnium, there can be mentioned aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0219] In addition, examples of insulators having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0220] An insulator having oxygen barrier properties and an insulator having hydrogen barrier properties can be said to be an insulator having barrier properties to one or both of oxygen and hydrogen.

[0221] In addition, as an insulator having the function of capturing or fixing hydrogen, an oxide containing magnesium or an oxide containing one or both of aluminum and hafnium can be cited. In addition, these oxides more preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following properties: oxygen atoms have dangling bonds and hydrogen is captured or fixed by the dangling bonds. In addition, these metal oxides preferably have an amorphous structure, but a portion thereof may also be formed with a crystalline region.

[0222] Note that in this specification, etc., a blocking insulating film refers to an insulating film having a barrier property. In addition, the barrier property refers to the property that the corresponding substance is not easily diffused (also referred to as the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing (also referred to as impurity absorption) the corresponding substance can be replaced by the term barrier property. In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise stated, the impurities recorded as corresponding substances refer to impurities in the channel formation region or in the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is not easily diffused.

[0223] [Conductor] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, the nitride of the alloy or the oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0224] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxide or lanthanum and nickel oxide, and materials containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials that have the function of inhibiting oxygen diffusion, or materials that absorb oxygen and maintain conductivity, so they are preferred. As conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide added with silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide can be cited. In this specification, etc., a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0225] Furthermore, a conductive material mainly composed of tungsten, copper, or aluminum is preferred because of its high conductivity.

[0226] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0227] In addition, when a metal oxide is used in the channel formation region of the transistor, the conductor used as the gate electrode preferably adopts a stacked structure of a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably arranged on the side of the channel formation region. By arranging the conductive material containing oxygen on the side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0228] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide in which a channel is formed can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0229] In addition, the conductor used as the source electrode or drain electrode has, for example, an area in contact with the semiconductor. In the case of using an oxide semiconductor as a semiconductor, there is the following concern: when a metal that is easily oxidized (for example, aluminum) is used as a source electrode or a drain electrode, an insulating oxide (for example, aluminum oxide) is formed between the source electrode or the drain electrode and the semiconductor, and the insulating oxide hinders their conduction. Therefore, as the source electrode and the drain electrode, it is preferred to use a conductive material that is not easily oxidized or a conductive material that maintains low resistance even if oxidized. For example, it is preferred to use one or more of titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Since these materials are conductive materials that are not easily oxidized or conductive materials that maintain low resistance even if oxidized, they are preferred. In addition, for example, the above-mentioned conductive material containing oxygen can be used as a source electrode or a drain electrode. Specifically, one or more of indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide added with gallium can be used.

[0230] In addition, the above-mentioned conductive material containing nitrogen can be used as the conductor 262a, the conductor 110a, the conductor 240a, the conductor 242a, etc., and the above-mentioned conductive material containing a metal element as a main component can be used as the conductor 262b, the conductor 110b, the conductor 240b, the conductor 242b, etc. The conductive material containing nitrogen sometimes has water and hydrogen barrier properties, and can improve reliability in a storage device using an oxide semiconductor whose electrical properties are changed by water and hydrogen. In addition, the conductive material containing a metal element as a main component sometimes has high conductivity, and can appropriately reduce the resistance of wiring and plugs, thereby improving the characteristics of the storage device.

[0231] Note that the conductor 240 a can use any of the materials described above that can be used as a source electrode and a drain electrode as appropriate.

[0232] Note that the conductor 242 b can use any of the materials described above that can be used as a source electrode and a drain electrode as appropriate.

[0233] Alternatively, the conductor 242 may have a three-layer stacked structure of the conductor 242a, the conductor 242b, and a third conductor. In this case, for example, the third conductor can use any of the materials that can be used as the source electrode and the drain electrode as appropriate.

[0234] [Metal oxides] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and foreign atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of lattice defects include differences in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities.

[0235] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to generation or capture of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferred that the semiconductor layer of the transistor, especially the metal oxide used for the channel formation region, has fewer lattice defects.

[0236] In a transistor using a metal oxide, in particular, if oxygen vacancies (V O ) and impurities, the electrical properties are easily changed, sometimes reducing reliability. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (V O H) and may generate electrons that become carriers. Thus, when the channel formation region in the metal oxide contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Thus, in the channel formation region of the metal oxide, it is preferred to minimize oxygen vacancies and impurities. In other words, it is preferred that the carrier concentration in the channel formation region of the metal oxide is reduced and is i-typed (intrinsic) or substantially i-typed.

[0237] On the other hand, for example, a low resistance region such as an n-type region of a metal oxide has more Vo and VoH than a channel formation region and has a higher impurity concentration of hydrogen, nitrogen, metal elements, and the like.

[0238] The type of lattice defects that are likely to exist in the metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0239] The structure of metal oxides is divided into single crystal structure and other structures (non-single crystal structure). As non-single crystal structures, there are CAAC structure, polycrystalline structure, nc structure, amorphous-like (a-like) structure and amorphous structure. The a-like structure has a structure between the nc structure and the amorphous structure. Note that the classification of crystal structures will be described later.

[0240] In addition, there are voids or low-density areas in metal oxides having an a-like structure and metal oxides having an amorphous structure. In other words, the crystallinity of metal oxides having an a-like structure and metal oxides having an amorphous structure is lower than that of metal oxides having a nc structure and metal oxides having a CAAC structure. In addition, the hydrogen concentration in the metal oxide of the metal oxide having an a-like structure is higher than that of the metal oxide having a nc structure and the metal oxide having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0241] Therefore, it is preferred to use a metal oxide with high crystallinity for the semiconductor layer of the transistor. For example, it is preferred to use a metal oxide with a CAAC structure or a metal oxide with a single crystal structure. By using this metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0242] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is sufficient to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region where carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0243] As a metal oxide of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Note that element M is a metal element or semi-metal element with high bonding energy with oxygen, for example, a metal element or semi-metal element with higher bonding energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In the case where the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains any one or more selected from indium, gallium and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0244] As a metal oxide semiconductor of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide) and the like containing silicon may be mentioned.

[0245] Here, the above oxides can be used as metal oxides that can be used in the low resistance region. In addition, elements, compounds, etc. used as dopants can be added to the above oxides for use. Examples of elements added to the oxides include one or more selected from aluminum, scandium, titanium, vanadium, gallium, yttrium, zirconium, niobium, molybdenum, indium, tin, antimony, tellurium, hafnium, tantalum, tungsten, germanium, silicon, arsenic, boron, fluorine, etc.

[0246] In particular, as the metal oxide that can be used in the low resistance region, indium tin oxide, indium tin oxide containing silicon, zinc oxide, tin oxide, titanium oxide, zinc oxide containing gallium, zinc oxide containing aluminum, and the like can be suitably used.

[0247] By increasing the atomic number ratio of indium relative to the total atomic number of all metal elements in the metal oxide, the field effect mobility of the transistor can be increased.

[0248] Note that the metal oxide may also contain one or more metal elements with a large period number instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large period number in addition to indium. There is a tendency that the greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0249] In addition, the metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field effect mobility of the transistor. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0250] The metal oxide according to one embodiment of the present invention can be suitably formed by the ALD method.

[0251] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0252] The ALD method can deposit atoms layer by layer, which has the following effects: it can deposit very thin films; it can deposit structures with high aspect ratios; it can deposit with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperatures, etc. In addition, in the PEALD method, deposition can be performed at lower temperatures by using plasma, so it is sometimes preferred. In addition, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods. In addition, the quantification of the above elements can be performed using XPS or SIMS. Note that the deposition method of the metal oxide as one embodiment of the present invention uses the ALD method, but due to the use of one or both of the conditions of high substrate temperature during deposition and impurity removal treatment, the amount of carbon and chlorine contained in the film is sometimes less than when the ALD method is used without the above conditions.

[0253] The ALD method is different from a deposition method in which particles released from a target material are deposited, and is a deposition method in which a shape is deposited due to a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as sputtering or CVD methods with fast deposition rates. For example, a method in which a first metal oxide is deposited by sputtering and a second metal oxide is deposited on the first metal oxide by the ALD method can be cited. For example, in the case where the first metal oxide has a crystalline portion, the second metal oxide sometimes grows crystals with the crystalline portion as a core.

[0254] The ALD method can control the composition of the obtained film according to the amount of source gas introduced. For example, when the ALD method is used, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition changes continuously can be deposited by changing the source gas while performing deposition. When deposition is performed while changing the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0255] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystalline, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, by using this metal oxide in the channel formation region, the variation of the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0256] In addition, by increasing the atomic number ratio of the element M relative to the sum of the atomic numbers of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, by using this metal oxide in the channel formation region, the carrier generation caused by the oxygen vacancy is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0257] In addition, in a channel formation region or the like, by increasing the atomic number ratio of In relative to the total atomic number of all metal elements in the metal oxide, the transistor can obtain a large on-state current and high frequency characteristics.

[0258] Here, the metal oxide included in the transistor of one embodiment of the present invention may also have high crystallinity. In particular, the metal oxide having a channel formation region preferably adopts a metal oxide with high crystallinity. Furthermore, the crystal preferably has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal, a layered structure). At this time, the c-axis direction of the crystal is the direction in which a plurality of layers are stacked. Metal oxides having the crystal include, for example, single crystal oxide semiconductors, CAAC-OS, and the like.

[0259] In addition, the c-axis of the crystal is preferably oriented in the normal direction of the formed surface or film surface of the metal oxide. Thus, the multiple layers are arranged in parallel or approximately parallel to the formed surface or film surface of the metal oxide. That is, the multiple layers extend in the channel length direction.

[0260] For example, the three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron in which the metal contained in the first layer exists at the center. In addition, the second layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the second layer exists at the center. In addition, the third layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the third layer exists at the center.

[0261] Examples of the crystal structure of the above-mentioned crystal include a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and deformation structures thereof.

[0262] Furthermore, it is preferred that the first to third layers are all composed of one metal element or a plurality of metal elements having the same valence and oxygen. Note that it is preferred that the valence of the one or more metal elements constituting the first layer is the same as the valence of the one or more metal elements constituting the second layer. In addition, the first layer and the second layer may also contain the same metal element. In addition, it is preferred that the valence of the one or more metal elements constituting the first layer is different from the valence of the one or more metal elements constituting the third layer.

[0263] By adopting the above structure, the crystallinity of the metal oxide can be improved and the mobility of the metal oxide can be improved. Therefore, by using the metal oxide in the channel formation region of the transistor, the on-state current of the transistor is increased and the electrical characteristics of the transistor can be improved.

[0264] [Transistor including metal oxide] Next, a case where a metal oxide (oxide semiconductor) is used for a transistor is described. In the following, a transistor using an oxide semiconductor in a semiconductor layer is sometimes referred to as an OS transistor, and a transistor using silicon in a semiconductor layer is sometimes referred to as a Si transistor.

[0265] By using a metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of more than 2nm and less than 30nm can be manufactured.

[0266] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor can be 1×10 18 cm -3 Below, preferably 1×10 17 cm- 3 Below, more preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 Above. Note that, when the purpose is to reduce the carrier concentration of the oxide semiconductor film, it is sufficient to reduce the impurity concentration in the oxide semiconductor film to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0267] Since the defect state density of a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is low, the trap state density may also be low.

[0268] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0269] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity.

[0270] In addition, the band gap of the oxide semiconductor used in the channel formation region is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor whose band gap is larger than that of silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0271] In addition, in Si transistors, short channel effect (Short Channel Effect: also called SCE) appears as the miniaturization of transistors develops. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, OS transistors use oxide semiconductors as semiconductor materials with large band gaps, which can suppress the short channel effect. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0272] In addition, the short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in the subthreshold swing width value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0273] In addition, as an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0274] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region of OS transistors and the characteristic length between the drain region and the channel formation region are smaller. Therefore, compared with Si transistors, OS transistors have a higher ability to resist short channel effects. That is to say, in the case of manufacturing transistors with short channel lengths, OS transistors are more preferred than Si transistors.

[0275] When the carrier concentration of the oxide semiconductor is reduced until the channel formation region becomes i-type or substantially i-type, in a short channel transistor, the lower end of the conduction band of the channel formation region decreases due to the conduction-band-lowering (CBL) effect, and thus the energy difference between the lower end of the conduction band of the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Therefore, the OS transistor can also be regarded as a channel formation region becoming n-type. -type region and the source region and drain region become n + n + / n - / n + Accumulation type junction-less transistor structure or n + / n - / n + Accumulation-type non-junction transistor structure.

[0276] By having the above structure, the OS transistor can have good electrical characteristics even if the storage device is miniaturized or highly integrated. For example, even if the channel length or gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, a short channel effect occurs in Si transistors, so it is sometimes difficult to set the gate length to less than 20nm or less than 15nm. Therefore, compared with Si transistors, OS transistors can be suitable for transistors with short channel lengths. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region when the transistor is operating.

[0277] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz at room temperature.

[0278] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a short channel length.

[0279] [Impurities in metal oxides] Here, the influence of each impurity in the metal oxide (oxide semiconductor) is described.

[0280] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0281] In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are generated, which increases the carrier concentration and is easily converted to n-type. As a result, transistors using oxide semiconductors containing nitrogen as semiconductors tend to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0282] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, thereby sometimes forming oxygen vacancies. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0283] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0284] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0285] [Other semiconductor materials] The oxide semiconductor 230 may be referred to as a semiconductor layer having a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. As the semiconductor layer, a semiconductor material having a band gap (a semiconductor material that is not a zero band gap semiconductor) may also be used. For example, a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) is preferably used for the semiconductor material.

[0286] Here, in this specification, etc., a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds and ionic bonds. A layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0287] As single element semiconductors that can be used as semiconductor materials, silicon and germanium can be cited. As silicon that can be used for the semiconductor layer, single crystal silicon, polycrystalline silicon, microcrystalline silicon and amorphous silicon can be cited. As polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited.

[0288] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals having a cubic crystal structure.

[0289] As layered materials, there are graphene, silicene, boron carbonitride, chalcogenides, etc. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0290] As the semiconductor layer, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As the transition metal chalcogenide that can be used as a semiconductor layer, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above-mentioned transition metal chalcogenides for the semiconductor layer, a storage device with a large on-state current can be provided.

[0291] Next, a method for manufacturing a storage device according to one embodiment of the present invention will be described.

[0292] <Example of a method for manufacturing a transistor> First, a method for manufacturing the transistor 200 will be described.

[0293] Hereinafter, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be appropriately deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0294] In addition, as a sputtering method, there can be RF sputtering method using a high frequency power supply for a sputtering power supply, DC sputtering method using a direct current power supply, and pulse DC sputtering method changing the voltage applied to the electrode in a pulsed manner. RF sputtering method is mainly used when depositing insulating films, and DC sputtering method is mainly used when depositing metal conductive films. In addition, pulse DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0295] Note that the CVD method can be divided into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0296] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used in the thermal CVD method, plasma damage to the object being processed can be reduced. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the storage device sometimes receive charges from plasma and generate charge accumulation (charge up). At this time, the wiring, electrodes, components, etc. included in the storage device are sometimes damaged by the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur when the thermal CVD method that does not use plasma is used, the yield of the storage device can be improved. In addition, when the thermal CVD method is used, plasma damage during deposition does not occur, so a film with fewer defects can be obtained.

[0297] As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method using a reactant excited by plasma, or the like can be used.

[0298] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material or the like are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio, etc. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to use it in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0299] In addition, when the CVD method is used, a film of any composition can be deposited according to the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while performing deposition. When deposition is performed while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0300] In addition, when the ALD method is used, a film of any composition can be deposited by introducing different precursors at the same time. Alternatively, when introducing different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0301] First, a substrate (not shown) is prepared, and an insulator 140 is formed on the substrate. As the insulator 140, the above-mentioned insulating materials can be used as appropriate.

[0302] Next, an insulator 141 having an opening is formed on the insulator 140, and a conductor 262 is formed so as to fit into the opening (see Figure 5A ). The above-mentioned conductive materials can be used appropriately as the conductor 262. For example, as the conductor 262, a laminated film of the conductor 262a and the conductor 262b deposited in sequence can be used, and tungsten can be formed as the conductor 262a and titanium nitride can be formed as the conductor 262b by the CVD method. For example, the conductor 262 can be formed by forming a conductor to become the conductor 262 in the opening of the insulator 141 and on the insulator 141, and removing the conductor on the insulator 141 by CMP or the like.

[0303] Next, an insulator 142f_1 having an opening 91 is formed on the insulator 141 and the conductor 262 (see Figure 5B ). The insulator 142f_1 can refer to a material that can be used as the insulator 142. The width of the opening 91 is recorded as width S1. The opening of the insulator 142f_1 can be processed by, for example, photolithography. The above-mentioned processing can be dry etching or wet etching. Processing by dry etching is suitable for micro-processing.

[0304] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, the conductor, semiconductor, or insulator is processed into a desired shape through the resist mask. For example, a resist can be exposed to light such as KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. to form a resist mask. In addition, when forming an opening, double imaging techniques such as LELE (Litho-Etch-Litho-Etch) and SADP (Self-Aligned Double Patterning), quadruple imaging techniques such as SAQP (Self-Aligned Quadruple Patterning), and multiple imaging techniques such as octuplet imaging techniques can be used. By using multiple imaging techniques, fine recesses or fine openings can be formed.

[0305] As multiple imaging, a hard mask may be used to repeatedly perform multiple patterning or patterning and etching to form a fine pattern. In addition, self-aligned multiple imaging may be used, in which an ALD film is deposited on a resist pattern, a side wall is formed on the side of the resist by anisotropic etching, the resist is removed, and the ALD film is used as a mask.

[0306] In addition, a liquid immersion technique in which exposure is performed in a state where a liquid (e.g., water) is filled between the substrate and the projection lens may be used. In addition, an electron beam or an ion beam may be used instead of the above light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask may be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0307] In addition, as a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device or the like can be used.

[0308] Note that, when viewed from a plane, the opening formed in the insulator 142f_1 has a region overlapping with the conductor 262. In addition, the conductor 262 is preferably configured in a manner including the opening formed in the insulator 142f_1. Specifically, for example, when viewed from a plane, the opening is preferably located on the inner side of the conductor 262. Alternatively, when viewed from a plane, a portion of the opening may be located on the outer side of the conductor 262. Alternatively, the opening formed in the insulator 142f_1 may be formed in a manner including the conductor 262.

[0309] Next, the insulator 142f_2 is deposited so as to cover the sidewalls of the opening 91 formed in the insulator 142f_1, the top surface of the insulator 142f_1, and the top surface of the 262 exposed in the bottom of the opening 91 of the insulator 142f_1 (see Figure 5C Here, the thickness of the insulator 142f_2 formed on the side wall of the opening 91 is referred to as thickness T1. The insulator 142f_2 can refer to a material that can be used as the insulator 142. In addition, as the insulator 142f_2, it is preferable to use the same material as the insulator 142f_1. Note that Figure 5C In the figure, the insulator 142f_1 and the insulator 142f_2 are collectively referred to as the insulator 142f.

[0310] Next, the insulator 142f is processed to form the insulator 142g. Specifically, in the insulator 142f_2, at least a portion of the region covering the top surface of the conductor 262 is removed by anisotropic etching to expose the surface of the conductor 262. Thus, for example, the insulator 142g having the opening 92 can be formed (see Figure 5D). The width of the opening 92 is recorded as width S2. The width S2 of the opening 92 can be expressed as S2=S1-(2×T1) using the width S1 of the opening 91 and the thickness T1 of the insulator 142f_2 formed on the side wall of the opening 91. Here, in the case where the conductor 260 has a cylindrical region, for example, the width S2 is the diameter of the circle of the top surface shape of the cylinder.

[0311] When the width S1 is set to the minimum value of the opening size by photolithography, the width S2 can be set to a value smaller than the minimum size. Thus, in the formation of the conductor 260 to be described later, the width of the conductor 260 can be reduced, thereby miniaturizing the transistor 200. Note that the method of reducing the opening size by forming the insulator 142f_2 is shown here, but the opening size can also be reduced by attaching the reaction product or the like to the side wall of the opening during the etching of the opening 91.

[0312] The angle of the side surface of the conductor 260 is determined by the angle of the side surface of the opening 92. The angle of the side surface of the opening 92 is preferably substantially vertical.

[0313] Next, a conductor 260f is formed in the opening 92 of the insulator 142g and on the insulator 142g (see Figure 5E The conductor 260f is preferably formed in such a manner as to be embedded in the opening 92, and is preferably formed in such a manner as to be in contact with the top surface of the conductor 262. The conductor 260f can refer to a material that can be used as the conductor 260.

[0314] Next, a portion of the conductor 260f is removed by etching to form the conductor 260. Preferably, by this etching, the region covering the top surface of the insulator 142g in the conductor 260f is removed to form the columnar conductor 260. Also, preferably, by this etching, the columnar conductor 260 is formed in such a manner that the top surface of the column is lower than the top surface of the insulator 142g.

[0315] The etching of the conductor 260f can be performed, for example, by dry etching. The height of the conductor 260 is determined by the etching, so it is preferred that the etching distribution in the substrate surface is good. Note that in the etching of the conductor 260f, only the upper area is removed, and a portion thereof remains. In this way, the process of leaving a portion by etching is sometimes called a half-etching process.

[0316] Next, an insulator 251f is formed on the top surface of the insulator 142g, the top surface of the conductor 260, and the opening 92 of the insulator 142g in the region where the conductor 260f is removed (see FIG. 14). Fig. 5F). The insulator 251f is formed, for example, in contact with the top surface of the conductor 260. Here, the deposition of the insulator 142g can be performed by, for example, the ALD method. The insulator 142g can refer to a material that can be used as the insulator 142.

[0317] The ALD method is one of the methods for appropriately obtaining a film with high coverage and high density. The deposition of the insulator 142g can appropriately embed the area on the conductor 260 in the opening 92 with the insulator 142g, for example, by making the thickness of the insulator 142g greater than half the width S2 of the opening 92 (S2×0.5).

[0318] Next, a portion of the insulator 251f is removed by etching to form the insulator 251 (see Fig. 6A ). Preferably, by this etching, the region located on the top surface of the insulator 142g is removed from the insulator 251f, thereby forming a columnar insulator 251. In addition, preferably, by this etching, the insulator 251 is formed in such a manner that the top surface of the column is lower than the top surface of the insulator 142g. Note that the insulator 251f can be removed by performing a planarization process using CMP.

[0319] The insulator 251f can be etched by dry etching, for example. Note that the etching process of the insulator 251f is sometimes referred to as half etching process.

[0320] Note that, in etching of the insulator 251f, by adopting a condition in which the etching amount of the insulator 142g is small, that is, by adopting a condition in which the selection of the insulator 142g is relatively large, the height of the insulator 251 formed can be appropriately made lower than the height of the insulator 142g. For example, the insulator 251 can be appropriately formed by using silicon nitride or silicon nitride oxide as the insulator 251 and using silicon oxide or silicon oxynitride as the insulator 142g. Alternatively, for example, silicon oxide or silicon oxynitride can be used as the insulator 142g, and hafnium oxide, aluminum oxide, zirconium oxide, magnesium oxide, or the like can be used as the insulator 251.

[0321] Next, an insulator 277f is formed on the insulator 251, in the opening of the insulator 142g, and on the insulator 142g (see Figure 6B Here, the insulator 277f can be made of the same material as the insulator 142g, for example.

[0322] Next, the insulator 142g and the insulator 277f are processed to form an insulator covering the top surface of the conductor 260 and an insulator covering the side surface of the conductor 260 (see Figure 6C). Specifically, for example, after the top surface of the insulator 142g is exposed by a planarization process such as CMP or etch back, the insulator 142 is processed using a mask to form the insulator 142k. Here, since the thickness of the insulator covering the side surface of the conductor 260 corresponds to the thickness of the insulator 250 which will be used as the gate insulator of the transistor 200 later, the thickness of the side surface of the conductor 260 is preferably substantially uniform.

[0323] Figure 6C The structure in which the insulator 277 formed by processing the insulator 277f covers the top surface of the conductor 260 and the insulator 142k formed by processing the insulator 142g covers the side surface of the conductor 260 is shown, but the insulator 277 may also have a region covering the side surface of the conductor 260. In addition, when the insulator 277f is made of the same material as the insulator 142g, it is sometimes difficult to distinguish the boundary between the insulator 277 and the insulator 142k when observing the transistor 200, and they are observed as a continuous film. For example, a mask is formed by photolithography and dry etching is performed using the mask, thereby processing the insulator 277f and the insulator 142g.

[0324] Here, the transistor 200 can be observed by, for example, exposing a cross section through processing, using a transmission electron microscope (TEM), a scanning transmission electron microscope (TEM), or the like.

[0325] Next, a conductor 242f is formed on the insulator 142k and the insulator 277 (see Fig.6D ). The conductor 242f can refer to a material that can be used as the conductor 242.

[0326] Next, a portion of the conductor 242f is removed by etching to form the conductor 242 (see Fig. 6E ). The conductor 242f can be processed, for example, by etching the top surface of the conductor 242f approximately uniformly. This etching process is sometimes referred to as an etch-back process. When the top surface of the conductor 242f has unevenness, the surface of the conductor 242 can also be flattened before etching. As a flattening process, a CMP (Chemical Mechanical Polishing) process can be used.

[0327] Next, a metal oxide 231f is formed so as to cover the conductor 242, the insulator 142k, and the insulator 277 (see Fig. 6F). The metal oxide 231f can refer to a material that can be used as the metal oxide 231. The metal oxide 231f has a region overlapping with the conductor 260 via the insulator 142k.

[0328] Next, in the metal oxide 231f, the region covering the top surface of the conductor 242 and the top surface of the insulator 277 is removed by etching, thereby forming a metal oxide 231g (see Fig. 7A ) The metal oxide 231g has a region overlapping with the conductor 260 via the insulator 142k.

[0329] Next, insulators 252a-f are formed so as to cover the conductor 242, the metal oxide 231g, the insulator 277, the insulator 142k, etc. (see Figure 7B ). The insulator 252a-f may refer to a material that can be used as the insulator 252a.

[0330] Next, the top surface of the insulator 252a-f is planarized and a portion thereof is removed to form the insulator 252a-g (see Figure 7C ). Although Figure 7B Although not shown in the figure, the surface of the insulator 252a-f may have unevenness due to the unevenness of the formed surface. In this case, by performing planarization, the surface can be made substantially flat or the unevenness of the surface can be reduced. As the planarization, CMP processing can be used.

[0331] Due to the planarization of the insulator 252a_f, for example, the thickness of the conductor 240f to be formed later can be made uniform, and the dimensional unevenness during the processing of the conductor 240 can be reduced, thereby facilitating manufacturing.

[0332] Next, a portion of the insulator 252a_g is removed to form an insulator 252a_h (see Fig.7D ). For example, the insulator 252a-h is formed in a manner to separate the regions that become the transistor 200. The region removed in the insulator 252a-g includes the region overlapping with the conductor 260 and the region overlapping with the metal oxide 231g. In addition, part of the region removed in the insulator 252a-g is a region where the insulator 252b will be formed later. For example, in the insulator 252a-g, the region located between the conductor 260 and the metal oxide 231g is removed, and this region is a region where the insulator 250 will be formed later.

[0333] Insulator 250f is formed on the region where insulator 252a_g is removed to form a gap and on insulator 252a_h (see Fig. 7E). The insulator 250f can refer to a material that can be used as the insulator 250. The region where the insulator 250f is formed includes a gap 93 formed in the region between the conductor 260 and the metal oxide 231g. The width WA of the gap 93 is equivalent to the thickness of the gate insulator of the transistor 200. In such a narrow width region, it is preferable to use a deposition method with high coverage. From the above viewpoint, the formation of the insulator 250f can appropriately use the ALD method.

[0334] Note that by making the thickness of the insulator 250 f larger than half the width WA (WA×0.5), the gap 93 can be embedded with the insulator 250 f.

[0335] Next, a portion of the insulator 250f is removed by etching to form the insulator 250 and the insulator 252b_g (see Fig. 8A ). By this etching, at least the region on the metal oxide 231g is preferably removed from the insulator 250f. In addition, the region removed by this etching includes, for example, the region covering the top surface of the insulator 252a-h. In addition, the etching process of the insulator 250f is sometimes referred to as a half-etching process.

[0336] Next, a portion of the metal oxide 231g is removed by etching to form the metal oxide 231 (see Figure 8B ). By this etching, a gap 94 is formed in the region between the insulator 250 and the insulator 252b_g. The height of the region where the oxide semiconductor 230 and the conductor 260 overlap varies due to the height of the metal oxide 231. In the transistor 200, the height of the metal oxide 231 may be determined according to the required characteristics and reliability. In addition, the etching process of the metal oxide 231g is sometimes referred to as a half etching process.

[0337] Next, an oxide semiconductor 230f is formed in a region including a gap formed by removing the metal oxide 231g (see Figure 8C ). The oxide semiconductor 230f can refer to the material that can be used as the oxide semiconductor 230. The oxide semiconductor 230f is formed in a manner that covers the metal oxide 231, the insulator 250, the insulator 251, the insulator 252b_g and the insulator 252a_h. The width WB of the gap 94 is equivalent to the thickness of the oxide semiconductor 230. In such a narrow width region, it is preferred to use a deposition method with high coverage. From the above viewpoint, the formation of the oxide semiconductor 230f can appropriately use the ALD method.

[0338] Note that by making the thickness of the oxide semiconductor 230 f larger than half the width WB (WB×0.5), the gap 94 can be embedded with the oxide semiconductor 230 f.

[0339] Next, a conductor 240f is formed on the oxide semiconductor 230f (see Fig.8D ). The conductor 240f may refer to a material that can be used as the conductor 240.

[0340] Next, the conductor 240f, the oxide semiconductor 230f, the insulators 252a-h, and the insulators 252b-g are partially removed for planarization, and the conductor 240, the oxide semiconductor 230, the insulator 252a, and the insulator 252b are formed so that the top surfaces thereof are substantially uniform in height (see Fig. 8E ). By this planarization, the conductors 240 included in the adjacent transistors 200 can be made into a structure separated by the insulator 252a. As the planarization, CMP treatment can be used.

[0341] Through the above steps, a transistor according to one embodiment of the present invention can be manufactured.

[0342] <Transistor Manufacturing Method Example 2> Note that Fig.9F As shown, in Fig. 8E In the transistor 200 shown in FIG. 1 , the insulator 121 may be replaced by a stacked structure of an insulator 149 and an insulator 148 on the insulator 149. 9A to 9E illustrate Fig.9F The manufacturing method of the structure shown.

[0343] First, an insulator 149f is formed on the insulator 141 and the conductor 262, and an insulator 147f_1 having an opening is formed on the insulator 149f. Furthermore, an insulator 147f_2 is formed on the insulator 147f_1 (see Fig.9A ). Here, the insulator 147f_2 is formed, thereby reducing the width of the opening of the insulator 147f_1. Fig.9A In the figure, the insulator 147f_1 and the insulator 147f_2 are collectively referred to as the insulator 147f.

[0344] Next, the insulator 147f is processed to form the insulator 147g. Specifically, in the insulator 147f_2, at least a portion of the region in contact with the top surface of the insulator 149f is removed to form the insulator 147g. Furthermore, using the insulator 147g as a mask, an opening is provided in the insulator 149f to form the insulator 149g (see Fig. 9B ).

[0345] Next, the conductor 260 is formed in each opening of the insulator 147g and the insulator 149g. Next, the insulator 251 is formed in the opening of the insulator 147g (see Fig. 9C ).

[0346] Next, the insulator 147g is removed to expose the surface of the insulator 149g (see Fig.9D ). Here, in the etching of the insulator 147g, it is preferred that the insulator 149g remain. Therefore, the insulator 149g preferably uses a film with a relatively large etching selectivity for the insulator 147g. For example, silicon nitride or silicon nitride oxide can be used as the insulator 149g, and silicon oxide or silicon oxynitride can be used as the insulator 147g. By providing the insulator 149g, the insulator provided between the conductor 262 and the conductor 242 can be formed without using a half-etching process. Thus, the unevenness of the insulator caused by the uneven etching amount within the substrate surface during the etching process can be suppressed.

[0347] Next, the insulator 148f is formed so as to cover the insulator 149g, the conductor 260, and the insulator 251 (see Fig.9E ). Then, refer to FIG. 6D to FIG. 8E Manufacturing process Fig.9F The structure shown.

[0348] <Example of Method for Manufacturing Storage Device> An example of a method for manufacturing a storage device according to one embodiment of the present invention will be described below.

[0349] First, use FIG. 5A to FIG. 8E The illustrated method forms an insulator 140 on a substrate (not shown), and forms a transistor 200 on the insulator 140 .

[0350] Next, an insulator to be the insulator 144f_1 is formed on the transistor 200. Then, an opening is provided in a region of the insulator that overlaps with the conductor 240, and the insulator 144f_1 is formed (see Fig. 10A ). The insulator 144f may refer to a material that can be used as the insulator 144.

[0351] Next, the insulator 144f_2 is deposited so as to cover the sidewalls of the opening formed in the insulator 144f_1, the top surface of the insulator 144f_1, and the top surface of the conductor 240 exposed in the bottom of the opening of the insulator 144f_1 (see Fig. 10B ). The insulator 144f_2 is preferably formed using the same material as the insulator 144f_1. Fig. 10B In the figure, the insulator 144f_1 and the insulator 144f_2 are collectively referred to as the insulator 144f.

[0352] Next, the insulator 144f is processed to form the insulator 144g. Specifically, in the insulator 144f_2, at least a portion of the region covering the top surface of the conductor 240 is removed. Thus, for example, the insulator 144g having the opening 96 can be formed (see Fig. 10C). By providing the insulator 144f_2, the insulator 144g having an opening with a width smaller than the minimum value of the opening size when using the photolithography method can be formed. In addition, the above-mentioned multi-image technique can be appropriately used to form the opening.

[0353] The angle of the side surface of the conductor 120 is determined by the angle of the side surface of the opening 96. The angle of the side surface of the opening 96 is preferably substantially vertical.

[0354] Next, a conductor to be the conductor 120 is formed so as to be embedded in the opening provided in the insulator 144g, and the conductor is processed so that the height of the top surface is lower than the height of the top surface of the insulator 144g to obtain a columnar conductor 120 (see Fig.11A ). For example, the conductor 120 can be formed by the ALD method. Here, for example, titanium nitride is formed by the ALD method as the conductor to be the conductor 120.

[0355] Next, an insulator 121f is formed on the top surface of the insulator 144g, the top surface of the conductor 120, and the opening 96 of the insulator 144g in a region where the conductor 120 is not embedded (see Fig. 11B ). The insulator 121f may refer to a material that can be used as the insulator 121.

[0356] Here, the insulator 121 f can be deposited by, for example, the ALD method. In addition, the thickness of the insulator 121 f may be larger than, for example, half the width of the opening 96 .

[0357] Next, a portion of the insulator 121f is removed by etching to form the insulator 121 (see Fig. 11C ). Preferably, by this etching, the region located on the top surface of the insulator 144g is removed in the insulator 251f, thereby forming a columnar insulator 121. In addition, preferably, by this etching, the insulator 121 is formed in such a way that the top surface of the column is lower than the top surface of the insulator 144g.

[0358] The insulator 121f can be etched using, for example, a dry etching method.

[0359] Note that, in etching of the insulator 121f, by adopting a condition that is relatively selective for the insulator 144g, the height of the insulator 121 formed can be appropriately lower than the height of the insulator 144g. For example, by using silicon nitride or silicon nitride oxide as the insulator 121 and using silicon oxide or silicon oxynitride as the insulator 144g, the insulator 121 can be appropriately formed.

[0360] Next, a portion of the insulator 144g is removed by etching to form the insulator 144 having the opening 97 (see Fig. 12A). By this etching, the area surrounding the conductor 120 is removed in the insulator 144g, and the side surface of the conductor 120 is exposed. The opening 97 is provided in the area surrounding the conductor 120 and the insulator 144 remains at the bottom. Thus, after the opening 97 is provided, the top surface of the conductor 240 is not exposed.

[0361] For example, a resist mask may be used to cover the region other than the region where the opening is to be provided on the insulator 144g, and the opening 97 may be formed by dry etching or the like. In this case, the insulator 144g in the region not covered by the resist mask is not etched entirely, but the etching is stopped halfway and a portion thereof is left. The etching process of the insulator 144g is sometimes referred to as a half-etching process.

[0362] in addition, Fig. 12A The structure in which the bottom of the opening 97 does not reach the top surface of the conductor 240 is shown. Thus, since the insulator 144 is arranged between the conductor 110 and the conductor 240 to be formed in the subsequent process in addition to the insulator 130, the distance between the conductor 110 and the layer forming the transistor 200 can be increased. Thus, in the case where a thin insulator 130 is formed in the bottom of the opening 97, etc., the leakage of the conductor 240 and the conductor 110 can be suppressed. In addition, since the capacitance value of the capacitor 100 depends on the depth of the opening 97, the depth can be controlled to control the capacitance value of the capacitor 100 and the capacitance unevenness between elements.

[0363] In addition, it is preferable that the insulator 121 remains by this etching, the insulator 144g in the region surrounding the insulator 121 is removed, and the side surface of the insulator 121 is exposed. Therefore, it is preferable that the insulator 121 use a film with a relatively large etching selectivity to the insulator 144g. For example, silicon nitride or silicon nitride oxide can be used as the insulator 121, and silicon oxide or silicon oxynitride can be used as the insulator 144g. Note that in the etching of the insulator 144g, when the etching selectivity with the conductor 120 can be made sufficiently large, the capacitor 100 may also adopt a structure in which the insulator 121 is not provided.

[0364] Next, the insulator 130 is formed to cover the exposed side surfaces of the conductor 120. The insulator 130 covers, for example, the bottom of the opening 97 of the insulator 144g, the side surfaces of the opening 97, and the top surface of the insulator 144g in addition to the side surfaces of the conductor 120.

[0365] As the insulator 130, for example, a stacked film of zirconium oxide, aluminum oxide, and zirconium oxide deposited in sequence may be formed by the ALD method. Here, the thickness of the insulator 130 corresponds to the electrostatic capacitance of the capacitor 100. The thickness of the insulator 130 can be appropriately set according to the design value of the electrostatic capacitance of the capacitor 100. In addition, as the insulator 130 becomes thinner, leakage current may be generated between the conductor 120 and the conductor 110. In the operation of the storage device, the thickness of the insulator 130, the height of the conductor 120, etc. may be appropriately controlled in such a way that the capacitance value is a value that can fully suppress the influence of such leakage current.

[0366] Next, the conductor 110 is formed on the insulator 130 (see Fig. 12B ) Note that it is preferable to perform a process to planarize the surface of the conductor 110. For example, a CMP method or the like can be used for the planarization.

[0367] When used as the conductor 110 Figure 3C and Figure 3D In the case of a stacked structure of the conductor 110a and the conductor 110b shown in FIG. 1 , for example, titanium nitride and tungsten may be used as the conductor 110a and the conductor 110b, respectively. For example, the conductor 110 may be formed by a CVD method.

[0368] Through the above process, Figure 4A Likewise, a storage device according to one embodiment of the present invention can be manufactured.

[0369] <Storage Device Manufacturing Method Example 2> Note that Fig. 14B As shown, in Fig. 12B In the storage device shown in FIG. 1 , the insulator 144 may be replaced by a stacked structure of an insulator 144a and an insulator 144b on the insulator 144a. FIG. 13A to FIG. 14B illustrate Fig. 14B The manufacturing method of the structure shown.

[0370] First, an insulator 144a_f is formed on the transistor 200, and an insulator 144b_f1 having an opening is formed on the insulator 144a_f. Furthermore, an insulator 144b_f2 is formed on the insulator 144b_f1 (see Fig.13A ). Here, by forming the insulator 144b_f2, the width of the opening of the insulator 144b_f1 can be reduced. Fig.13A In the figure, the insulator 144b_f1 and the insulator 144b_f2 are collectively referred to as the insulator 144b_f.

[0371] Next, the insulator 144b_f is processed to form the insulator 144b_g. Specifically, in the insulator 144b_f2, at least a portion of the region in contact with the top surface of the insulator 144a_f is removed to form the insulator 144b_g. Furthermore, using the insulator 144b_g as a mask, an opening is provided in the insulator 144a_f to form the insulator 144a (see Fig. 13B ).

[0372] Next, the conductor 120 is formed in each opening of the insulator 144a and the insulator 144b_g. Next, the insulator 121 is formed in the opening of the insulator 144b_g (see Fig. 13C ).

[0373] Next, a portion of the insulator 144b_g is removed to form an insulator 144b having an opening (see Fig.14A ). Here, in the etching of the insulator 144b_g, it is preferred that the insulator 144a remain. Therefore, the insulator 144a preferably uses a film with a relatively large etching selectivity for the insulator 144b_g. For example, silicon nitride or silicon nitride oxide can be used as the insulator 144a. By providing the insulator 144a, an opening for embedding the insulator 130 and the conductor 110 can be formed without using a half-etching process. Thus, it is possible to suppress unevenness in the depth of the opening caused by uneven etching amount within the substrate surface during the etching process.

[0374] Next, the insulator 130 is formed to cover the exposed side surfaces of the conductor 120. The insulator 130 covers, in addition to the side surfaces of the conductor 120, for example, the top surface of the insulator 144a, the side surfaces of the opening of the insulator 144b, and the top surface of the insulator 144b.

[0375] Next, the conductor 110 is formed on the insulator 130, and a storage device according to one embodiment of the present invention can be manufactured (see Fig. 14B ).

[0376] In the memory device of one embodiment of the present invention, an insulator containing excess oxygen can be formed by depositing the insulator by sputtering in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator can be reduced.

[0377] Alternatively, heat treatment may be performed after forming an insulator containing oxygen. By performing heat treatment, oxygen in the insulator can be appropriately diffused into the oxide semiconductor 230 .

[0378] [Modification Example 1 of Transistor 200] Fig.15A and Fig. 15B The structure shown is Figure 1Cand Figure 1D The structure shown is different in that the oxide semiconductor 230 does not cover the side surfaces of the conductor 240 .

[0379] [Variation Example 2 of Transistor 200] Fig. 15C and Fig.15D The structure shown is Figure 1C and Figure 1D The structure shown is different in the shape of the insulator 250, the shape of the oxide semiconductor 230, and the like.

[0380] exist Fig. 15C and Fig.15D In the embodiment, the insulator 250 includes a region covering the side surface of the conductor 260, a region covering the side surface and the top surface of the insulator 251, a region sandwiched between the insulator 142 and the conductor 242, and the like. In addition, the oxide semiconductor 230 includes a region covering the top surface of the conductor 242, a region covering the side surface and the top surface of the insulator 250, and the like. The conductor 240 includes a region covering the top surface of the oxide semiconductor 230, a region covering the top surface of the insulator 252, and the like. The insulator 252 is provided so as to surround the oxide semiconductor 230, and the conductor 240 and the conductor 242 are insulated by the insulator 252 and the like.

[0381] Note that the conductor 240 may cover part of the side surface in addition to the top surface of the oxide semiconductor 230 .

[0382] [Variation Example 1 of Storage Device] Fig.16A The memory device shown includes a transistor 200 and a capacitor 100 on the transistor 200 . Fig.16A The structure of the capacitor 100 is shown in FIG. Figure 3C The structures of the capacitors shown are different.

[0383] Fig.16A The capacitor 100 shown includes a conductor 120 on a conductor 240 , an insulator 130 on the conductor 120 , and a conductor 110 on the insulator 130 .

[0384] The insulator 144 is provided with an opening that reaches the conductor 240, and at least a portion of the conductor 120 is disposed in the opening. In addition, the conductor 120 has a region in contact with the top surface of the conductor 240 and a region in contact with the side surface of the insulator 144 in the opening. In addition, the conductor 120 has a region in contact with the top surface of the insulator 144.

[0385] The insulator 130 is provided so as to cover the top and side surfaces of the conductor 120 and the top surface of the insulator 144. In addition, in the opening of the insulator 144, the insulator 130 is provided so as to cover the side surfaces of the conductor 120, and the conductor 120 has a region sandwiched between the insulator 144 and the insulator 130. The conductor 110 is provided so as to be embedded in the recess of the insulator 144 via the insulator 130.

[0386] Fig.16A The capacitor 100 shown can be manufactured, for example, by the following simple steps: an opening is provided in the insulator 144, a film to become the conductor 120 is formed on the insulator 144 and then the conductor 120 is formed by processing, the insulator 130 is formed in a manner covering the conductor 120, and the conductor 110 is formed in a recessed portion of the insulator 144 through the insulator 130.

[0387] [Variation Example 2 of Storage Device] Fig. 16B The memory device shown includes a transistor 200 and a capacitor 100 on the transistor 200 . Fig. 16B The capacitor 100 shown is Fig.16A The difference between the capacitor ground shown in FIG. 1 and FIG. 2 is that the conductor 110 has a region located on the side of the outer side of the conductor 120 through the insulator 130. Fig. 16B In the figure, the conductor 120 has regions where both the outer side surface and the inner side surface are covered by the insulator 130 .

[0388] and Fig.16A Compared with the structure shown, due to Fig. 16B The structure shown can also form a capacitor on the side surface of the outer side of the conductor 120, so the capacitance value can be increased.

[0389] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments described in this specification as appropriate.

[0390] (Implementation Method 2) In this embodiment, a metal oxide (hereinafter, sometimes referred to as an oxide semiconductor or an oxide) and a deposition method thereof which can be used for a semiconductor layer of a transistor of the memory device described in the above embodiment are described with reference to FIGS. 17 to 20 .

[0391] In a storage device of one embodiment of the present invention, a metal oxide with high crystallinity is preferably used as a metal oxide having a channel formation region. Furthermore, the crystal preferably has a crystal structure in which a plurality of layers (e.g., a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). At this time, the c-axis direction of the crystal is the direction in which a plurality of layers are stacked.

[0392] In order to form the metal oxide having a layered crystal structure, it is preferable to deposit atoms layer by layer. For example, ALD (Atomic Layer Deposition) can be used as a method for forming the metal oxide.

[0393] The ALD method can deposit atoms layer by layer, so it has the effects of being able to deposit extremely thin layers, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with good coverage, and being able to deposit at low temperatures. In addition, the ALD (thermal ALD) method also includes a thermal ALD method that uses heat as a deposition method and a plasma ALD (PEALD: Plasma Enhanced ALD) method that uses plasma as a deposition method. By using plasma, deposition can be performed at a lower temperature, so it is sometimes preferred. In addition, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods. Note that the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

[0394] The ALD method is different from a deposition method in which particles released from a target material are deposited. It is a deposition method in which a film is formed by a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the mold deposited by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for the case where the surface of an opening with a high aspect ratio is to be covered.

[0395] <Method of Depositing Metal Oxide by ALD Method> Here, a method for depositing a metal oxide using the ALD method which can be used in one embodiment of the present invention is described.

[0396] use FIG. 17A to FIG. 17E An example of a method for depositing metal oxide using the ALD method is described. First, a precursor 611a is introduced into a chamber so that the precursor 611a is adsorbed onto the surface of a substrate 610 (see Fig.17A Hereinafter, this process is sometimes referred to as the first step. Fig.17AAs shown, since the precursor 611a is adsorbed onto the surface of the substrate 610, the self-stop mechanism of the surface chemical reaction takes effect and the precursor 611a is no longer adsorbed on the layer of the precursor 611a on the substrate 610. Note that the appropriate range of substrate temperature for the self-stop mechanism of the surface chemical reaction to take effect is also referred to as the ALD window. The ALD window is determined based on the temperature adsorption rate of the precursor, the decomposition temperature, etc., and is sometimes set to be above 100°C and below 600°C, preferably above 200°C and below 400°C.

[0397] Next, an inert gas (argon, helium, nitrogen, etc.) is introduced into the chamber to exhaust the remaining precursor 611a and the reaction products from the chamber (hereinafter, this process is sometimes referred to as the second step). Alternatively, the remaining precursor and the reaction products may be exhausted from the chamber by vacuum exhaust instead of introducing the inert gas into the chamber. The second step is also called purging.

[0398] Next, a reactant 612a (e.g., an oxidant (ozone (O3), oxygen (O2), water (H2O) and their plasma, free radicals, ions, etc.)) is introduced into the chamber to react with the precursor 611a adsorbed on the surface of the substrate 610, so that a part of the components in the precursor 611a is detached while the constituent molecules of the precursor 611a are adsorbed on the substrate 610 (see Fig. 17B (This process may be referred to as a third step hereinafter.) As a result, a layer of an oxide 613 a formed by oxidation of a portion of the precursor 611 a is formed on the surface of the substrate 610 .

[0399] Next, the remaining reactant 612a and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust (hereinafter, this process may be referred to as a fourth step).

[0400] Next, a precursor 611b containing a metal element different from the precursor 611a is introduced, and the same process as the first step is performed to make the precursor 611b adsorbed on the surface of the oxide 613a layer (see Fig. 17C ). Here, if Fig. 17C As shown, since the precursor 611 b is adsorbed onto the layer of the oxide 613 a , the self-stopping mechanism of the surface chemical reaction takes effect and the precursor 611 b is no longer adsorbed onto the layer of the precursor 611 b on the substrate 610 .

[0401] Next, similarly to the second step, the remaining precursor 611 b and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0402] Next, as in the third step, a reactant 612b is introduced into the chamber. Here, the reactant 612b may be the same as or different from the reactant 612a (see Fig.17D ). As a result, a layer of oxide 613b formed by oxidation of a portion of the precursor 611b is formed on the layer of oxide 613a.

[0403] Next, similarly to the fourth step, the remaining reactant 612b and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0404] Furthermore, by performing the first to fourth steps in the same manner, a layer of oxide 613c can be formed on the layer of oxide 613b. In this way, by repeatedly performing the steps of forming oxides 613a to 613c, a metal oxide having a layered crystal structure in which the stacked structure of oxides 613a to 613c is repeated can be formed (see Fig.17E ).

[0405] The thickness of the layered metal oxide may be greater than or equal to 1 nm and less than 100 nm, and preferably greater than or equal to 3 nm and less than 20 nm.

[0406] In addition, when forming a metal oxide having a layered crystal structure, it is preferred to perform the process shown in FIG. 17 while heating the substrate. For example, the substrate temperature is set to be above 200° C. and below 600° C., preferably above 300° C. and below the decomposition temperature of the precursor. Note that when using multiple precursors of different types and performing deposition using the ALD method, it is preferred to set the substrate temperature to be below the decomposition temperature of the lowest precursor among the multiple precursors. Thus, in deposition using the ALD method, the multiple precursors used can be adsorbed onto an object (e.g., a substrate, etc.) without being decomposed.

[0407] By performing the above deposition while heating the substrate within the above temperature range, impurities such as hydrogen or carbon contained in the precursor and reactant can be removed from the metal oxide in each process from step 1 to step 4. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. In addition, metal atoms and oxygen atoms are rearranged while removing the above impurities, so that the layers of each oxide can be arranged with high order. Thus, a metal oxide with a layered crystal structure with high crystallinity can be formed.

[0408] In order to perform deposition while heating the substrate within the above-mentioned temperature range, the decomposition temperature of the precursor used for the above-mentioned deposition is preferably high. For example, the decomposition temperature of the precursor is preferably above 200°C and below 700°C, more preferably above 300°C and below 600°C. As such a precursor with a high decomposition temperature, a precursor formed by an inorganic substance (hereinafter referred to as an inorganic precursor) is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than precursors formed by organic substances (hereinafter referred to as organic precursors), and sometimes their ALD windows are located within the above-mentioned temperature range. In addition, because inorganic precursors do not contain impurities such as hydrogen or carbon, the concentration of impurities such as hydrogen or carbon in the deposited metal oxide can be prevented from increasing.

[0409] Furthermore, it is preferred to perform a heat treatment after the deposition of the above-mentioned metal oxide. In particular, it is preferred to perform a heat treatment continuously without exposing to the outside air after the deposition using the above-mentioned ALD method. The heat treatment is performed at a temperature of 100°C or more and 1200°C or less, preferably 200°C or more and 1000°C or less, more preferably 250°C or more and 650°C or less, further preferably 300°C or more and 600°C or less, further preferably 400°C or more and 550°C or less, and further preferably 420°C or more and 480°C or less. In addition, the heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. In addition, the heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more to compensate for the oxygen that has been separated.

[0410] By performing heat treatment in this way, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. In addition, metal atoms and oxygen atoms are rearranged while removing the above impurities, so that crystallinity can be improved. Thus, a metal oxide with a layered crystal structure with high crystallinity can be formed.

[0411] In addition, it is preferred that microwave treatment is performed in an oxygen-containing atmosphere after the deposition of the metal oxide to reduce the concentration of impurities in the metal oxide. As impurities, hydrogen and carbon can be mentioned in particular. Here, microwave treatment refers to treatment using a device including a power supply that generates high-density plasma using microwaves, for example.

[0412] By performing microwave treatment in an oxygen-containing atmosphere, high frequencies such as microwaves or RF can be used to plasmatize the oxygen gas and allow the oxygen plasma to act. In addition, as oxygen acting on the metal oxide, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions and oxygen free radicals (atoms, molecules or ions with unpaired electrons also referred to as O free radicals). In addition, the oxygen acting on the metal oxide can be any one or more of the above forms, and is particularly preferably an oxygen free radical.

[0413] In addition, when the microwave treatment is performed in the oxygen-containing atmosphere, heating the substrate can further reduce the impurity concentration in the metal oxide, which is preferred. The heating of the substrate can be performed at 100°C or higher and 650°C or lower, preferably 200°C or higher and 600°C or lower, and more preferably 300°C or higher and 450°C or lower.

[0414] When the substrate is heated during microwave treatment in the above oxygen-containing atmosphere, the carbon concentration in the metal oxide measured by SIMS can be reduced to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0415] Note that the above shows a structural example in which a metal oxide is subjected to microwave treatment in an oxygen-containing atmosphere, but the present invention is not limited thereto. For example, an insulating film located near the metal oxide, specifically a silicon oxide film, may also be subjected to microwave treatment in an oxygen-containing atmosphere. For example, microwave treatment may also be performed after the insulator 250 is deposited. By subjecting the silicon oxide film to microwave treatment in an oxygen-containing atmosphere, hydrogen contained in the silicon oxide film may be released to the outside as H2O. By releasing hydrogen from the silicon oxide film located near the metal oxide, a highly reliable storage device may be provided.

[0416] Note that although a structure in which a stacked structure of oxides 613a to 613c is repeated is described in FIG17 , the present invention is not limited to this. For example, a metal oxide in which one, two, or four or more oxides are repeatedly formed may be used.

[0417] In addition, in the description of this specification, when ozone, oxygen, or water is used as a reactant or oxidant, unless otherwise specified, these include plasma states, radical states, and ion states and are not limited to gaseous states or molecular states. When deposition is performed using an oxidant in a plasma state, radical state, or ion state, a radical ALD apparatus or a plasma ALD apparatus described below may be used.

[0418] In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferred to allow the precursor to fully react with the oxidant. For example, a longer pulse time for introducing the oxidant can be set. Alternatively, the oxidant can be introduced multiple times. When the oxidant is introduced multiple times, the same type of oxidant can be introduced, and different types of oxidants can be introduced. For example, water can be introduced into the chamber as the first oxidant and then vacuum evacuated, and ozone or oxygen that does not contain hydrogen can be introduced into the chamber as the second oxidant and vacuum evacuated.

[0419] In this way, by repeatedly introducing the oxidant and the inert gas (or vacuum exhaust) in the chamber for a short period of time, the remaining hydrogen atoms, carbon atoms, chlorine atoms, etc. can be removed from the precursor adsorbed on the substrate surface and discharged outside the chamber. In addition, by introducing two oxidants, more remaining hydrogen atoms, etc. can be removed from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being introduced into the film during deposition, water, hydrogen, etc. contained in the formed film can be reduced.

[0420] The ALD method is a deposition method that uses thermal energy to react precursors and reactants. The temperature required for the reaction of the precursors and reactants is determined according to their temperature characteristics, vapor pressure, decomposition temperature, etc., and is set to be above 100°C and below 600°C, preferably above 200°C and below 600°C, and more preferably above 300°C and below 600°C.

[0421] Furthermore, an ALD method in which the above-mentioned precursor and reactant react and a reactant excited by plasma is introduced into a chamber as a third source gas for processing is sometimes referred to as a plasma ALD method. In this case, a plasma generating device is provided in the introduction portion of the third source gas. When generating plasma, inductively coupled plasma can be used. On the other hand, an ALD method in which a precursor and a reactant react using thermal energy is sometimes referred to as a thermal ALD method.

[0422] In the plasma ALD method, the reactant excited by the plasma in the third step is introduced for deposition. Alternatively, deposition is performed by repeatedly performing the first step to the fourth step while introducing the reactant excited by the plasma (the second reactant). In this case, the reactant introduced in the third step is referred to as the first reactant. In the plasma ALD method, the second reactant used for the third source gas can use the same material as the above-mentioned oxidant. That is, ozone, oxygen and water excited by the plasma can be used as the second reactant. In addition, as the second reactant, a nitriding agent can also be used in addition to the oxidant. Nitrogen (N2) or ammonia (NH3) can be used as the nitriding agent. In addition, a mixed gas of nitrogen (N2) and hydrogen (H2) can be used as a nitriding agent. For example, a mixed gas of 5% nitrogen (N2) and 95% hydrogen (H2) can be used as a nitriding agent. By depositing while introducing nitrogen or ammonia excited by plasma, a nitride film such as a metal nitride film can be formed.

[0423] In addition, argon (Ar), helium (He) or nitrogen (N2) may be used as a carrier gas for the second reactant. By using a carrier gas such as argon, helium or nitrogen, it is easy to discharge plasma and generate a second reactant excited by the plasma, so it is preferred. Note that when an oxide film such as a metal oxide film is formed by a plasma ALD method and nitrogen is used as a carrier gas, nitrogen may be mixed into the film and the desired film quality may not be obtained. In this case, it is preferred to use argon or helium as a carrier gas.

[0424] By using the ALD method, a very thin film can be deposited with a uniform thickness, and a high coverage rate can be achieved on a surface having irregularities.

[0425] Here, refer to 18A to 18D This is an explanation of the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide. Fig.18B and Fig.18D In the diagram, atoms are represented by spheres (circles), and the bonds between metal atoms and oxygen atoms are represented by lines. Fig.18B and Fig.18D In the figure, the c-axis direction in the crystal structure of In-M-Zn oxide is indicated by the arrow in the figure. In addition, the ab plane direction in the crystal structure of In-M-Zn oxide is the same as that in Fig.18B and Fig.18D The direction is perpendicular to the c-axis direction indicated by the arrow.

[0426] Fig.18A6 is a diagram showing an oxide 660 including an In-M-Zn oxide formed on a structure 650. Here, a structure refers to a constituent element constituting a semiconductor device such as a transistor. The structure 650 includes a substrate; a conductor such as a gate electrode, a source electrode, and a drain electrode; an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film; and a semiconductor such as a metal oxide and silicon. Fig.18A The case where the deposition surface of the structure 650 is arranged in parallel with the substrate (or base, not shown) is shown.

[0427] Fig.18B It is shown Fig.18A This is an enlarged view of the atomic arrangement in the crystal of a portion of region 653 of oxide 660. Fig.18A and Fig.18B The composition of the oxide 660 shown is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is a YbFe2O4 type structure. In addition, the element M is a +3 valent metal element.

[0428] like Fig.18B As shown, the crystals included in the oxide 660 are repeatedly stacked in sequence, including a layer 621 containing indium (In) and oxygen, a layer 631 containing element M and oxygen, and a layer 641 containing zinc (Zn) and oxygen. The layers 621, 631, and 641 are arranged in a manner substantially parallel to the deposited surface of the structure 650. In other words, the ab plane of the oxide 660 is substantially parallel to the deposited surface of the structure 650, and the c-axis of the oxide 660 is substantially parallel to the normal direction of the deposited surface of the structure 650.

[0429] like Fig.18B As shown, the layer 621, the layer 631, and the layer 641 of the crystal are all composed of a metal element and oxygen, and can be arranged with high crystallinity to improve the mobility of the metal oxide.

[0430] Note that the structure of the In-M-Zn oxide with In:M:Zn=1:1:1 [atomic ratio] is not limited to Fig.18B The structure shown in FIG. 6 is a structure of ...

[0431] In the above, an example of forming an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] is shown, but its composition formula is In (1+α) M (1-α) O3(ZnO)m (where α is a real number greater than 0 and less than 1, and m is a positive number) The crystalline In-M-Zn oxide can also have a layered crystal structure. As an example, refer to Fig.18C and Fig.18D which shows an In-M-Zn oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio].

[0432] Fig.18C FIG. shows an oxide 662 containing In-M-Zn oxide formed on a structure 650. Fig.18D It shows Fig.18C An enlarged view of the atomic arrangement in the crystal of a region 654 which is a part of the oxide 662 shown.

[0433] As Fig.18D shown, the crystal included in the oxide 662 has a layer 622 containing indium (In), element M and oxygen, a layer 641 containing zinc (Zn) and oxygen, and a layer 631 containing element M and oxygen. In the oxide 662, as multiple layers, the layer 622, the layer 641, the layer 631, and the layer 641 are repeatedly stacked in sequence. The layer 622, the layer 631, and the layer 641 are arranged substantially parallel to the deposition surface of the structure 650. In other words, the a-b plane of the oxide 662 is substantially parallel to the deposition surface of the structure 650, and the c-axis of the oxide 662 is substantially parallel to the normal direction of the deposition surface of the structure 650.

[0434] Note that the structure of the In-M-Zn oxide with In:M:Zn = 1:3:4 [atomic ratio] is not limited to the Fig.18D structure shown, and the structure can also be changed within the range of maintaining In:M:Zn = 1:3:4 [atomic ratio]. For example, the stacking order of the layer 622, the layer 631, and the layer 641 can also be changed. In addition, a part of the element M in the layer 631 can be replaced with zinc, and a part of the zinc in the layer 641 can be replaced with the element M. In addition, a layer 621 or a layer 631 can be formed instead of the layer 622.

[0435] <In-M-Zn oxide> Next, refer to FIG. 19A to FIG. 20C which shows Fig.18A and Fig.18B the detailed formation method of the oxide 660 containing In-M-Zn oxide shown.

[0436] First, a source gas including a precursor containing indium is introduced into the chamber to adsorb the precursor onto the surface of the structure 650 (refer to Fig.19AHere, the source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. As a precursor containing indium, trimethylindium, triethylindium, tri(2,2,6,6-tetramethyl-3,5-heptanedione)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0437] In addition, as a precursor containing indium, an inorganic precursor that does not contain hydrocarbons can also be used. As an inorganic precursor containing indium, a halogen indium compound such as indium trichloride, indium tribromide, or indium triiodide can be used. The decomposition temperature of indium trichloride is about 500°C or more and about 700°C or less. Therefore, by using indium trichloride, the substrate can be heated at about 400°C or more and about 600°C or less, for example, at 500°C, while deposition is performed using the ALD method.

[0438] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0439] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than indium are desorbed while indium is adsorbed on the substrate, thereby forming a layer 621 formed by bonding indium and oxygen (see Fig.19B As the oxidant, ozone, oxygen, water, etc. can be used. Next, the introduction of the oxidant is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0440] Next, a source gas including a precursor containing element M is introduced into the chamber so that the precursor is adsorbed onto layer 621 (see Fig.19C ). The source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. When gallium is used as the element M, as a precursor containing gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III)acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedione)gallium, dimethyl gallium chloride, diethyl gallium chloride, dimethyl gallium isopropoxide, etc. can be used.

[0441] In addition, as a precursor containing gallium, an inorganic precursor that does not contain hydrocarbons may also be used. As an inorganic precursor containing gallium, a halogen gallium compound such as gallium trichloride, gallium tribromide, or gallium triiodide may be used. The decomposition temperature of gallium trichloride is about 550°C to about 700°C. Therefore, by using gallium trichloride, the substrate may be heated at about 450°C to about 650°C, for example, at 550°C, while deposition is performed using the ALD method.

[0442] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0443] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than the element M are desorbed while the element M is adsorbed on the substrate, thereby forming a layer 631 formed by bonding the element M and oxygen (see Fig.19D At this time, a part of the oxygen constituting the layer 641 may be adsorbed on the layer 631. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0444] Next, a source gas including a zinc precursor is introduced into the chamber so that the precursor is adsorbed onto the layer 631 (see Fig. 20A ). At this time, a portion of the layer 641 formed by bonding zinc and oxygen is sometimes formed. The source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. As a precursor containing zinc, dimethyl zinc, diethyl zinc, bis (2,2,6,6-tetramethyl-3,5-heptanedione) zinc, zinc acetate, etc. can be used.

[0445] In addition, as a precursor containing zinc, an inorganic precursor that does not contain hydrocarbons may also be used. As an inorganic precursor containing zinc, a halogen-based zinc compound such as zinc dichloride, zinc dibromide, or zinc diiodide may be used. The decomposition temperature of zinc dichloride is about 450° C. to about 700° C. Therefore, by using zinc dichloride, the substrate may be heated at about 350° C. to about 550° C., for example, at 450° C., while deposition is performed using the ALD method.

[0446] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0447] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed on the substrate, thereby forming a layer 641 formed by bonding zinc and oxygen (see Fig. 20B ). Next, the introduction of the oxidant is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0448] Next, layer 621 is formed again on layer 641 by the above method (see Fig. 20C ). By repeatedly performing the above method, an oxide 660 can be formed on the substrate or the structure.

[0449] Note that the above-mentioned precursor may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. In addition, a film formed using a precursor containing halogen such as chlorine may contain halogen such as chlorine.

[0450] As described above, by forming the oxide 660 using the ALD method, a metal oxide having a c-axis oriented substantially parallel to the normal direction of the deposited surface can be formed. Figure 1B and Figure 1C In the oxide semiconductor 230 shown, layered crystals can be formed substantially parallel to the sidewalls of the insulator 250. With this structure, the layered crystals of the oxide semiconductor 230 are substantially parallel to the channel length direction of the transistor 200, so the on-state current of the transistor can be increased.

[0451] Preferably, the substrate is heated while FIG. 19A to FIG. 20C For example, the substrate temperature may be set to be 200° C. or higher and 600° C. or lower, preferably 300° C. or higher and lower than the decomposition temperature of the precursor.

[0452] In order to perform deposition while heating the substrate within the above temperature range, the decomposition temperature of the precursor used for the above deposition is preferably high. For example, the decomposition temperature of the precursor is preferably above 200°C and below 700°C, more preferably above 300°C and below 600°C. As such a precursor with a high decomposition temperature, an inorganic precursor is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even if deposition is performed while heating the substrate as described above, the precursor is not easily decomposed.

[0453] As inorganic precursors, for example, the above-mentioned indium trichloride, gallium trichloride, and zinc dichloride can be used. As mentioned above, the decomposition temperature of these precursors is above 350°C and below 700°C, which is much higher than the decomposition temperature of general organic precursors. However, as mentioned above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from each other. When using multiple precursors of such different types and depositing using the ALD method, it is preferred to set the substrate temperature to be below the lowest decomposition temperature among the decomposition temperatures of the multiple precursors. In the above example, the substrate temperature can be set within a range where zinc dichloride, which has the lowest decomposition temperature of the precursor, will not decompose. As a result, in a state where other indium trichlorides and gallium trichlorides do not decompose, they can be adsorbed onto an object (for example, a substrate, etc.).

[0454] Notice, FIG. 19A to FIG. 20C Although an example is shown in which layer 621 is formed as a layer containing indium, layer 631 is formed as a layer containing element M thereon, and layer 641 is formed as a layer containing zinc thereon, this embodiment is not limited thereto. Alternatively, one of layer 631 and layer 641 may be formed, layer 621 may be formed thereon, and the other of layer 631 and layer 641 may be formed thereon. Alternatively, one of layer 631 and layer 641 may be formed, the other of layer 631 and layer 641 may be formed thereon, and layer 621 may be formed thereon.

[0455] When forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 [atomic ratio], the above-mentioned layers 621, 631, and 641 may be formed appropriately according to the atomic ratio. Fig. 20A The formation of the layer 641 may be repeated multiple times before and after the formation of the layer 631 shown, so that a stack of the layer 631 and the layer 641 having a desired number of atoms, number of layers, and thickness may be formed between the two layers 621 .

[0456] <Oxide containing In and Sn> Next, a method for forming an oxide containing indium and tin will be described.

[0457] First, a source gas including a precursor containing indium is introduced into a chamber, and the precursor is adsorbed on the surface of the surface to be formed. Here, the source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor.

[0458] As the precursor containing indium, trimethylindium, triethylindium, tri(2,2,6,6-tetramethyl-3,5-heptanedione)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, or the like can be used.

[0459] In addition, as a precursor containing indium, an inorganic precursor that does not contain hydrocarbons can also be used. As an inorganic precursor containing indium, a halogen indium compound such as indium trichloride, indium tribromide, or indium triiodide can be used. The decomposition temperature of indium trichloride is about 500°C or more and about 700°C or less. Therefore, by using indium trichloride, the substrate can be heated at about 400°C or more and about 600°C or less, for example, at 500°C, while deposition is performed using the ALD method.

[0460] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0461] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than indium are separated while indium is adsorbed on the substrate, thereby forming a layer formed by bonding indium and oxygen. As the oxidant, ozone, oxygen, water, etc. can be used. Next, the introduction of the above-mentioned oxidant is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0462] Next, a source gas including a precursor containing tin is introduced into the chamber so that the precursor is adsorbed on the layer formed by bonding indium and oxygen. The source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor.

[0463] As a precursor containing tin, tetrakis(dimethylamide)tin, tin(II) acetylacetone, tin tetrachloride, or the like can be used.

[0464] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0465] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than tin are separated while tin is adsorbed on the substrate, thereby forming a layer formed by bonding tin and oxygen. At this time, sometimes part of the oxygen constituting the formed layer is adsorbed on the previously formed layer formed by bonding indium and oxygen. Next, the introduction of the above-mentioned oxidant is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0466] By repeatedly forming a layer in which indium and oxygen are bonded and a layer in which tin and oxygen are bonded, an oxide containing indium and tin can be formed on a substrate or a structure.

[0467] In addition, it is not necessary to alternately and repeatedly form a layer formed by bonding indium and oxygen and a layer formed by bonding in tin and oxygen, and one layer may be formed repeatedly multiple times before the other layer is formed repeatedly once or multiple times. For example, when forming a metal oxide having an atomic ratio different from In:Sn=1:1 [atomic ratio], a layer formed by bonding indium and oxygen and a layer formed by bonding in tin and oxygen may be appropriately formed according to the atomic ratio.

[0468] In addition, the formed metal oxide may contain other elements in addition to indium and tin. Hereinafter, a metal oxide containing indium, tin, and silicon will be described.

[0469] <Oxide containing In, Sn and Si> As a precursor containing silicon, an aminosilane precursor can be used. Examples of the aminosilane precursor include BTBAS (bis-tert-butylaminosilane), BDMAS (bis-dimethylaminosilane), BDEAS (bis-diethylaminosilane), DMAS (dimethylaminosilane), DEAS (diethylaminosilane), DPAS (dipropylaminosilane), BAS (butylaminosilane), DIPAS (diisopropylaminosilane), BEMAS (bis-ethylmethylaminosilane), and TDMAS (trisdimethylaminosilane).

[0470] In addition, examples of the precursor containing silicon include ethoxysilane-based precursors such as TEOS (tetraethoxysilane).

[0471] In addition, as a precursor containing silicon, for example, there can be mentioned a precursor having "CH 3n -Si-(NCO) 4-n(n is greater than 0 and less than 3)", "H-Si-(NCO)3" and other isocyanate-based silicon compounds. In addition, as precursors, gases containing silicon and not containing hydrocarbons (also called inorganic precursors) such as SiH4, Si2H6, SiF4, SiCl4, SiBr4, SiH2Cl2, and SiH2I2 can also be used.

[0472] By using a precursor containing silicon to adsorb silicon onto the surface to be formed and then using an oxidizing agent, a layer formed by bonding silicon and oxygen can be formed. Therefore, a layer formed by bonding indium and oxygen, a layer formed by bonding tin and oxygen, and a layer formed by bonding silicon and oxygen are repeatedly formed, thereby forming a metal oxide containing indium, tin, and silicon.

[0473] <Silicon Oxide> By using the above-mentioned precursor containing silicon to adsorb silicon onto the formation surface and then using an oxidizing agent, a silicon oxide layer can be formed by the ALD method.

[0474] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments described in this specification as appropriate.

[0475] (Implementation method 3) In this embodiment, a configuration example of a storage device which is one embodiment of the present invention is described.

[0476] [Structural example of memory cell array] By arranging the memory cells 150 in a three-dimensional manner and in a matrix, a memory cell array can be formed. As an example of a memory cell array, Fig.21A and Fig. 21B An example of a storage device is shown in which four×two×two storage cells 150 are arranged in the X direction, the Y direction, and the Z direction. Fig.21A is a plan view of the storage device. Fig. 21B It is along Fig.21A Note that for clarity, Fig.21A Some components are omitted in the plan view.

[0477] Each memory cell 150 is provided with a conductor 260 serving as a wiring WL. In addition, a conductor 242 serving as a part of the wiring BL is provided in such a manner as to be commonly used in the memory cells 150 adjacent in the X direction. That is, the conductor 242 is in contact with each oxide semiconductor 230 in two adjacent memory cells 150. By using the conductor 242 in common in the adjacent memory cells 150, integration of the memory device can be achieved.

[0478] The conductor 242 of the memory cell 150 is electrically connected to a conductor 245 serving as a plug (which may also be referred to as a connection electrode). The conductor 245 is disposed in an opening formed in the insulators 252, 144, 130, 283, and 287, and the insulators 141 and 142 of the memory cell disposed above, and is in contact with the top surface of the conductor 242. In addition, the conductor 245 may use a conductive material that can be used for the conductor 240.

[0479] The insulator 283 preferably has an oxygen barrier property. In addition, the insulator 283 preferably has a hydrogen barrier property. As the insulator 283, a single layer or a stacked layer of an insulator having an oxygen barrier property, an insulator having a hydrogen barrier property, or the like described in the above-mentioned [Insulator] can be used appropriately.

[0480] Since the insulator 287 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 287, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in the above-mentioned [Insulator] can be used.

[0481] In addition, the concentration of impurities such as water and hydrogen in the insulator 287 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0482] The conductor 245 is used as a plug or wiring for electrically connecting circuit elements, wiring, electrodes or terminals such as switches, transistors, capacitors, inductors, resistors and diodes to the memory cell 150. For example, the conductor 245 can be electrically connected to a sense amplifier (not shown) under the memory device.

[0483] In addition, the conductor 245 is electrically connected to the memory cell stacked in the upper layer, and the conductor 245 can be used as a part of the wiring BL.

[0484] Furthermore, two adjacent memory cells 150 sandwiching the conductor 245 have an axisymmetric structure with the perpendicular bisector of the dashed line A1 - A2 as the axis of symmetry. Thus, the transistors 200 included in each memory cell 150 are also arranged axisymmetrically with the conductor 245 sandwiched therebetween.

[0485] Note that the conductor 110 used as the wiring PL may be provided in each memory cell 150 or may be provided in common in a plurality of memory cells 150. However, the conductor 110 is provided separately from the conductor 245 to prevent the conductor 110 and the conductor 245 from being short-circuited.

[0486] As shown in FIG. 21, by stacking a plurality of memory cells, the cells can be configured in an integrated manner without increasing the occupied area of ​​the memory cell array. That is, a 3D memory cell array can be constructed. Note that FIG. 21 shows an example of a structure in which a layer including two memory cells is stacked into four layers, but the present invention is not limited to this. In the memory device, one layer including at least one memory cell 150 can be included, and two or more of the above layers can be stacked.

[0487] FIG. 21 shows a structure in which a conductor 245 serving as a plug is arranged between adjacent memory cells 150. Note that the present invention is not limited to this. In FIG. 21, a conductor 245 serving as a plug that penetrates insulator 252, insulator 144, insulator 130, insulator 283, insulator 287, insulator 141 and insulator 142 forming an upper memory cell is shown, but a plurality of plugs may be used to connect the conductors 242 in the upper and lower memory cells. For example, a plug may be provided in each insulator, or a plurality of plugs that penetrate two or more insulators may be used to connect the conductors 242 in the upper and lower memory cells.

[0488] [Configuration Example of Storage Device] Fig. 22 : is a block diagram showing a configuration example of a storage device 300 according to one embodiment of the present invention. Fig. 22 The memory device 300 shown includes a driving circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.

[0489] Fig. 22 The memory array 20 is shown as an example including a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2). In addition, as an example, a functional circuit 51 is provided for each wiring BL used as a bit line. Fig. 22 An example is shown in which a plurality of functional circuits 51 are provided corresponding to n wirings BL.

[0490] exist Fig. 22, the 1st row and 1st column storage cell 10 is represented as storage cell 10[1, 1], and the mth row and nth column storage cell 10 is represented as storage cell 10[m, n]. In addition, in the present embodiment, etc., sometimes "row i" is written to represent an arbitrary row. In addition, sometimes "column j" is written to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage cell 10 is represented as storage cell 10[i, j]. In the present embodiment, etc., when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0491] In addition, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the i-th (i-th row) wiring WL is represented as wiring WL[i]. In addition, the first (first row) wiring WL is represented as wiring WL[1], the second (second row) wiring WL is represented as wiring WL[2], and the m-th (m-th row) wiring WL is represented as wiring WL[m]. Similarly, the i-th (i-th row) wiring PL is represented as wiring PL[i]. In addition, the first (first row) wiring PL is represented as wiring PL[1], the second (second row) wiring PL is represented as wiring PL[2], and the m-th (m-th row) wiring PL is represented as wiring PL[m]. Similarly, the j-th (j-th row) wiring BL is represented as wiring BL[j]. In addition, the first (first row) wiring BL set can be expressed as wiring BL[1], the second (second row) wiring BL set can be expressed as wiring BL[2], and the nth (nth row) wiring BL set can be expressed as wiring BL[n].

[0492] The plurality of memory cells 10 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i], not shown) and the i-th row wiring PL (wiring PL[i], not shown). The plurality of memory cells 10 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0493] The memory array 20 can use DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM including 1T (transistor) 1C (capacitor) type memory cells, which refers to a memory in which the access transistor is a transistor containing an oxide semiconductor in the channel formation region (hereinafter, also referred to as an "OS transistor"). The current flowing between the source and the drain of the OS transistor in the off state, that is, the leakage current is extremely small. In DOSRAM, by turning off the access transistor (making it non-conducting), the charge according to the data held in the capacitor can be maintained for a long time. Therefore, compared with a DRAM composed of a transistor containing silicon in the channel formation region (hereinafter, also referred to as a "Si transistor"), the refresh operation frequency of DOSRAM can be lower. As a result, low power consumption can be achieved.

[0494] The memory cell 10 can be stacked by stacking OS transistors as described in Embodiment Mode 1 and the like. Fig. 22 In the memory array 20 shown, a plurality of memory arrays 20[1] to 20[m] may be stacked. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the memory density of the memory cell 10 can be increased. In addition, the memory array 20 can be manufactured repeatedly using the same manufacturing process in the vertical direction. The memory device 300 can reduce the manufacturing cost of the memory array 20.

[0495] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the on or off (conductive state or non-conductive state) of an access transistor used as a switch. Wiring PL is used as a constant potential line connected to a capacitor.

[0496] The memory cells 10 included in the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the driving circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, the power consumption and signal delay can be reduced. In addition, the operation can be performed even if the capacitance of the capacitor included in the memory cell 10 is reduced.

[0497] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 through the wiring GBL (not shown) described later. By adopting this structure, a small potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, similarly to the wiring BL. By arranging the wiring BL and the wiring GBL extending from the memory cell 10 included in the memory array 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be greatly reduced, power consumption and signal delay can be reduced.

[0498] The wiring BL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that is used as a source or a drain. Alternatively, the wiring BL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that is used as a source or a drain. That is, the wiring BL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0499] The memory array 20 can be overlapped on the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal transmission distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 300 can be miniaturized.

[0500] By forming the functional circuit 51 with OS transistors similarly to the transistors included in the memory cell 10 of the DOSRAM, the functional circuit 51 can be freely arranged on a circuit using Si transistors similarly to the memory arrays 20[1] to 20[m], thereby making it easy to integrate. By adopting a structure in which the functional circuit 51 amplifies the signal, the circuits such as the sense amplifier 46 of the subsequent circuit can be miniaturized, thereby miniaturizing the memory device 300.

[0501] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23 and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32 (control circuit) and a voltage generation circuit 33.

[0502] In the storage device 300, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0503] In addition, the signal BW, the signal CE and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. In addition, the signals PON1 and PON2 can also be generated in the control circuit 32.

[0504] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0505] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0506] The peripheral circuit 41 is a circuit for writing and reading data to the memory cell 10. In addition, the peripheral circuit 41 is a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42 (RowDecoder), a column decoder 44 (Column Decoder), a row driver 43 (Row Driver), a column driver 45 (ColumnDriver), an input circuit 47 (Input Cir.), an output circuit 48 (Output Cir.), and a sense amplifier 46 (SenseAmplifier).

[0507] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data into the memory cell 10; a function of reading data from the memory cell 10; a function of holding the read data, etc.

[0508] The input circuit 47 has a function of holding the signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is the signal RDA.

[0509] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. Fig. 22 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0510] The memory array 20 includes memory arrays 20[1] to 20[m] (m is an integer greater than or equal to 2) and a functional layer 50. A plurality of layers of memory arrays 20 may be overlapped on the drive circuit 21. By overlapping a plurality of layers of memory arrays 20, the memory density of the memory cell 10 may be increased. Fig.23A 1 is a perspective view of a storage device 300 showing a state in which five layers (m=5) of memory arrays 20 [ 1 ] to 20 [ 5 ] and a functional layer 50 are stacked on a drive circuit 21 .

[0511] exist Fig.23A , the memory array 20 set in the first layer is referred to as the memory array 20[1], the memory array 20 set in the second layer is referred to as the memory array 20[2], and the memory array 20 set in the fifth layer is referred to as the memory array 20[5]. Fig.23AThe wiring WL and wiring PL extending in the X direction and the wiring BL extending in the Z direction (a direction perpendicular to the substrate surface on which the driver circuit is provided) are shown. Note that in order to make the drawings easier to understand, a part of the wiring WL and wiring PL included in each of the memory arrays 20 is omitted. Note that Fig.23A Although the wiring PL is extended in the X direction, the present invention is not limited thereto. For example, the wiring PL may be extended in the Y direction, or may be extended in both the X and Y directions. For example, the wiring PL may be provided in a planar shape.

[0512] Fig. 23B Show instructions Fig.23A FIG. 1 is a schematic diagram of a structural example of a functional circuit 51 connected to the wiring BL and a memory cell 10 included in the memory array 20 [1] to 20 [5] connected to the wiring BL. Fig. 23B The wiring GBL provided between the functional circuit 51 and the driving circuit 21 is shown. In addition, a structure that electrically connects one wiring BL to a plurality of memory cells (memory cells 10) is also referred to as a "memory string." Note that in the drawings, the wiring GBL is sometimes shown with a thick line for improved visibility.

[0513] Fig. 23B An example of a circuit structure of a memory cell 10 connected to a wiring BL is shown. The memory cell 10 includes a transistor 11 and a capacitor 12. With respect to the transistor 11, the capacitor 12, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc.

[0514] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to the wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of the capacitor 12. The other electrode of the capacitor 12 is connected to the wiring PL. The gate of the transistor 11 is connected to the wiring WL.

[0515] For example, two memory cells 10 connected to the same wiring BL in the same layer may adopt the method according to Embodiment 1. Fig.25 The structure shown.

[0516] in addition, Fig. 23B 27 and 28 show a structure in which two memory cells 10 are connected to the same wiring BL in the same layer, but the present invention is not limited thereto. For example, a structure in which four memory cells 10 are connected to the same wiring BL in the same layer may be adopted, and a structure in which eight memory cells 10 are connected to the same wiring BL in the same layer may be adopted. For example, when four memory cells 10 are connected to the same wiring BL in the same layer, the structure shown in FIG. 27 according to Embodiment 1 may be adopted.

[0517] The wiring PL is a wiring for supplying a constant potential for maintaining the potential of the capacitor 12 .

[0518] Fig. 23B The wiring GBL shown is provided so as to electrically connect the drive circuit 21 and the functional circuit 51 . Fig.24A Schematic diagram of a memory device 300 is shown with a functional layer 50 and memory arrays 20[1] to 20[m] as a repeating unit 70. Fig.24A One wiring GBL is shown in the figure, but the wiring GBL may be appropriately provided according to the number of functional circuits 51 in the functional layer 50 .

[0519] The wiring GBL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that is used as a source or a drain. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that is used as a source or a drain. That is, the wiring GBL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the functional circuit 51 of the functional layer 50 to the drive circuit 21 in the vertical direction.

[0520] Alternatively, a structure may be provided in which a repeating unit 70 including a functional circuit 51 and memory arrays 20[1] to 20[m] is stacked. Fig. 24B The repeating units 70 [1] to 70 [p] (p is an integer greater than or equal to 2) may be included. The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be appropriately provided according to the number of the functional circuits 51.

[0521] In this embodiment, while OS transistors are stacked, wiring used as a bit line is arranged in a direction perpendicular to the substrate surface provided with the driver circuit 21. By providing wiring used as a bit line extending from the memory array 20 in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be greatly reduced.

[0522] In this embodiment, a functional layer 50 is included in the layer in which the memory array 20 is provided, and the functional layer 50 includes a functional circuit 51 having a function of amplifying the data potential held in the memory cell 10 and outputting it. By adopting this structure, a small potential difference of the wiring BL used as a bit line when reading data can be amplified to drive the sense amplifier 46 included in the driving circuit 21. Since the circuit such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, the operation can be performed even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0523] [Configuration Example of Memory Array 20 and Functional Circuit 51] Reference Fig.25 illustrate Fig. 22 The configuration examples of the functional circuit 51 and the configuration examples of the sense amplifier 46 included in the memory array 20 and the driver circuit 21 described above are described in detail in FIG. 24 . Fig.25 The driving circuit 21 is shown, and the driving circuit 21 is connected to the wiring GBL (GBL_A, GBL_B), and the wiring GBL (GBL_A, GBL_B) is connected to the functional circuit 51 (51_A, 51_B), and the functional circuit 51 (51_A, 51_B) is connected to the memory cell 10 (10_A, 10_B) connected to the different wiring BL (BL_A, BL_B). Fig.25 The driving circuit 21 shown in the figure shows a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73 in addition to the sense amplifier 46 .

[0524] Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are shown as the functional circuits 51_A and 51_B. Fig.25 The transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b shown are OS transistors like the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked like the memory arrays 20[1] to 20[m].

[0525] The wirings BL_A and BL_B are connected to the gates of the transistors 52_a and 52_b. The wirings GBL_A and GBL_B are connected to one of the source and the drain of the transistors 53_a, 53_b, 54_a, and 54_b. Similar to the wirings BL_A and BL_B, the wirings GBL_A and GBL_B are arranged in the vertical direction and connected to the transistors included in the driving circuit 21. Fig.25As shown, the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are supplied with control signals WE and RE and a selection signal MUX.

[0526] constitute Fig.25 The transistors 81_1 to 81_6 and 82_1 to 82_4 of the sense amplifier 46, the precharge circuit 71_A and the precharge circuit 71_B shown are composed of Si transistors. The switches 83_A to 83_D constituting the switch circuit 72_A and the switch circuit 72_B can also be composed of Si transistors. One of the source and drain of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistor or switch constituting the precharge circuit 71_A, the precharge circuit 71_B, the sense amplifier 46, and the switch circuit 72_A.

[0527] The precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. The precharge circuit 71_A precharges the wirings BL_A and BL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in accordance with a precharge signal supplied to the precharge line PCL1.

[0528] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6 and precharges the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in accordance with a precharge signal supplied to the precharge line PCL2.

[0529] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or the wiring VLL. The wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors constituting an inverter loop. The potential of the wiring BL_A and the wiring BL_B is precharged by selecting the memory cells 10_A and 10_B, and the potential of the wiring GBL_A and the wiring GBL_B is set to the high power supply potential VDD or the low power supply potential VSS according to the change. The potential of the wiring GBL_A and the wiring GBL_B can be output to the outside through the switch 83_C, the switch 83_D and the write-read circuit 73. The wiring BL_A and the wiring BL_B and the wiring GBL_A and the wiring GBL_B are equivalent to a bit line pair. The write-read circuit 73 is controlled to write the data signal according to the signal EN_data.

[0530] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and the wiring GBL_B. The switch circuit 72_A can be switched on or off by controlling the switching signal CSEL1. In the case where the switches 83_A and 83_B are n-channel transistors, they are turned on when the switching signal CSEL1 is at a high level, and are turned off when the switching signal CSEL1 is at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B can be switched on or off by controlling the switching signal CSEL2. The switches 83_C and 83_D can be the same as the switches 83_A and 83_B.

[0531] like Fig.25 As shown, the memory device 300 may have a structure in which the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected via the wiring BL and the wiring GBL arranged in the shortest vertical direction. By adopting the above structure, the load of the wiring BL is reduced, the writing time can be shortened, and data can be easily read.

[0532] like Fig.25 As shown, each transistor included in the functional circuit 51_A, 51_B is controlled by the control signal WE, RE and the selection signal MUX. Each transistor can output the potential of the wiring BL to the driving circuit 21 through the wiring GBL according to the control signal and the selection signal. The functional circuits 51_A, 51_B can be used as a sense amplifier composed of OS transistors. By adopting this structure, a small potential difference of the wiring BL can be amplified during reading, and the sense amplifier 46 using Si transistors can be driven.

[0533] As described above, by stacking a plurality of memory cell arrays and drive circuits, high integration of the memory device and increased storage capacity can be achieved.

[0534] Fig.26 An example of a cross-sectional structure of a memory device in which a layer including memory cells is stacked on a layer including a driver circuit including a sense amplifier.

[0535] exist Fig.26 In the embodiment, the capacitor 100 is disposed above the transistor 301 , and the transistor 200 is disposed above the transistor 301 and the capacitor 100 .

[0536] The transistor 301 is one of transistors included in the sense amplifier.

[0537] Fig.26 The structure of the illustrated memory cell 150 (transistor 200 and capacitor 100 ) is as described above.

[0538] like Fig.26 As shown in FIG. 1 , the bit line can be shortened by adopting a structure in which the sense amplifier is provided so as to overlap the memory cell 150. As a result, the bit line capacitance is reduced, and the storage capacitance of the memory cell can be reduced.

[0539] Furthermore, by placing the transistor 200 above the capacitor 100, the transistor 200 is not affected by the thermal history during the manufacture of the capacitor 100. Therefore, the degradation of the electrical characteristics of the transistor 200, such as the change in threshold voltage and the increase in parasitic resistance, and the increase in the variation in electrical characteristics caused by the degradation of the electrical characteristics can be suppressed.

[0540] exist Fig.26 In the memory device shown, for example, transistor 301 corresponds to a transistor included in sense amplifier 46. In addition, memory cell 150 corresponds to memory cell 10, transistor 200 corresponds to transistor 11, and capacitor 100 corresponds to capacitor 12.

[0541] The transistor 301 is provided on a substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 301 may be a p-channel type or an n-channel type. In addition, the conductor 316d refers to a dummy gate.

[0542] Here, in Fig.26 In the transistor 301 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, a material that adjusts the work function can also be used for the conductor 316. Because the convex portion of the semiconductor substrate is utilized, this transistor 301 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper surface of the convex portion can also be provided. In addition, although a case where a part of the semiconductor substrate is processed to form a convex portion is shown here, an SOI substrate can also be processed to form a semiconductor film having a convex portion.

[0543] Notice, Fig.26 The structure of the transistor 301 shown is only an example and is not limited to the above structure. An appropriate transistor can be used according to the circuit structure or driving method.

[0544] A wiring layer including an interlayer film, wiring, and plugs may also be provided between each structure. In addition, the wiring layer may be provided in multiple layers according to the design. Here, in a conductor having the function of a plug or wiring, the same symbol is sometimes used to represent multiple structures. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be a component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0545] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 301. Furthermore, a conductor 328 is embedded in the insulator 320 and the insulator 322, and a conductor 330 is embedded in the insulator 324 and the insulator 326. Furthermore, the conductor 328 and the conductor 330 are used as plugs or wirings.

[0546] In addition, the insulator used as the interlayer film can also be used as a planarization film that covers the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 322, planarization can also be achieved by a planarization process using a CMP method or the like.

[0547] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.26 In the embodiment, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 is used as a plug or wiring.

[0548] As the insulator 352 and the insulator 354 serving as an interlayer film, for example, an insulator that can be used in the above-described memory device can be used.

[0549] As the conductive layer used as a plug or wiring, for example, as the conductor 328, the conductor 330, and the conductor 356, the conductor described in the above [Conductor] can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum and copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0550] The conductor 240 included in the transistor 200 is electrically connected to the low resistance region 314 b functioning as a source region or a drain region of the transistor 301 through the conductor 644 , the conductor 645 , the conductor 646 , the conductor 356 , the conductor 330 , and the conductor 328 .

[0551] Conductor 644 is embedded in insulator 142. Conductor 645 is embedded in insulator 141. Conductor 645 can be manufactured using the same material and process as conductor 242. Conductor 646 is embedded in insulator 648. Transistor 301 is electrically insulated from conductor 242 of transistor 200 via insulator 648. Note that conductor 245 provided on insulator 141 and conductor 242 provided on insulator 142 may also be connected via a conductor provided on an insulator on an upper layer thereof. For example, a conductor provided on insulator 141 is electrically connected to plugs provided on insulator 142, insulator 143, insulator 252, insulator 144, etc. provided on an upper layer thereof, and plugs connected to conductor 242 provided on insulator 142 may be provided in sequence from the plug provided on the upper layer to the lower layer.

[0552] According to one embodiment of the present invention, a novel transistor, semiconductor device, and storage device can be provided. In addition, a transistor, semiconductor device, and storage device that can achieve miniaturization or high integration can be provided. In addition, a transistor, semiconductor device, and storage device with high reliability can be provided. In addition, a transistor with large on-state current, a semiconductor device and storage device including the transistor can be provided. In addition, a semiconductor device and storage device with less uneven transistor characteristics can be provided. In addition, a transistor with good electrical characteristics, a semiconductor device and storage device including the transistor can be provided. In addition, a semiconductor device and storage device with low power consumption can be provided. In addition, a storage device with good frequency characteristics can be provided. In addition, a storage device with good frequency characteristics can be provided. In addition, a storage device with high operating speed can be provided.

[0553] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0554] (Implementation 4) In this embodiment, refer to Fig.27A and Fig.27B An example of a chip 1200 on which the memory device of the present invention is mounted will be described. A plurality of circuits (systems) are mounted on the chip 1200. In this way, the technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0555] like Fig.27A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0556] Bumps (not shown) are provided on the chip 1200. Fig.27B As shown in FIG. 1 , the first surface of the package substrate 1201 is connected to the first surface of the package substrate 1201 . In addition, a plurality of bumps 1202 are provided on the back side of the first surface of the package substrate 1201 , and the bumps 1202 are connected to the motherboard 1203 .

[0557] A storage device such as a DRAM 1221 or a flash memory 1222 may be provided on the motherboard 1203. For example, the DOS RAM described in the above embodiment may be applied to the DRAM 1221. Thus, the DRAM 1221 can have low power consumption, high speed, and large capacity.

[0558] CPU1211 preferably has multiple CPU cores. In addition, GPU1212 preferably has multiple GPU cores. In addition, CPU1211 and GPU1212 may also each have a memory for temporarily storing data. Alternatively, a memory commonly used by CPU1211 and GPU1212 may be provided on chip 1200. The above-mentioned DOSRAM can be applied to the memory. In addition, GPU1212 is suitable for parallel calculation of multiple data, which can be used for image processing or product-sum operations. By providing an image processing circuit or product-sum operation circuit using the oxide semiconductor of the present invention in GPU1212, image processing and product-sum operations can be performed with low power consumption.

[0559] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0560] The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the analog operation unit 1213 may also include the above-mentioned product-sum operation circuit.

[0561] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0562] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0563] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network) and may also include a network security circuit.

[0564] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at a low cost.

[0565] A motherboard 1203 including a package substrate 1201 provided with a chip 1200 having a GPU 1212 , a DRAM 1221 , and a flash memory 1222 may be referred to as a GPU module 1204 .

[0566] The GPU module 1204 can be reduced in size because it has a chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles because of its high image processing capabilities. In addition, by using the product-sum operation circuit of the GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be performed, thereby using the chip 1200 as an AI chip, or using the GPU module 1204 as an AI system module.

[0567] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments, etc. described in this specification as appropriate.

[0568] (Implementation method 5) This embodiment mode describes an example of an electronic component and an electronic device in which the storage device described in the above embodiment mode is incorporated. By using the storage device described in the above embodiment mode for the following electronic component and electronic device, low power consumption and high speed of the electronic component and electronic device can be achieved.

[0569] <Electronic components> First, refer to Fig.28A and Fig.28B An example of an electronic component in which the storage device 720 is incorporated will be described.

[0570] Fig.28A It is a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. Fig.28A The electronic component 700 shown includes a storage device 720 within a mold 711. Fig.28A , a part of the electronic component 700 is omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 720 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of the above-mentioned electronic components and electrically connecting them on the printed circuit board 702, respectively, a mounting substrate 704 is completed.

[0571] The storage device 720 includes a driving circuit layer 721 and a storage circuit layer 722 .

[0572] Fig.28B 7 is a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731. By using the storage device described in the above embodiment as the storage device 720, low power consumption and high speed can be achieved.

[0573] As the semiconductor device 735 , an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.

[0574] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 may be a silicon interposer, a resin interposer, or the like.

[0575] The plug board 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are arranged in a single layer or in multiple layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit arranged on the plug board 731 to the electrode arranged on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "redistribution substrate" or "intermediate substrate". In addition, sometimes a through electrode is arranged in the plug board 731 and the through electrode is used to electrically connect the integrated circuit to the package substrate 732. In addition, in the case of using a silicon plug board, TSV (Through Silicon Via: silicon through hole) can also be used as a through electrode.

[0576] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring formation of the silicon interposer can be performed in a semiconductor process, so it is easy to form fine wiring that is difficult to form when using a resin interposer.

[0577] In addition, in SiP, MCM, etc. using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection between the integrated circuit disposed on the silicon interposer and the silicon interposer is not likely to occur. In particular, the silicon interposer is preferably used for 2.5D packaging (2.5 mounting), in which a plurality of integrated circuits are arranged on the interposer in a horizontal direction.

[0578] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the height of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the height of the storage device 720 and the semiconductor device 735 consistent.

[0579] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.28B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0580] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0581] As described above, the structure, method, and the like described in this embodiment mode can be used in combination with other structures, methods described in this embodiment mode, and structures, methods, and the like described in other embodiments mode as appropriate.

[0582] (Implementation 6) In this embodiment, an application example of a storage device using the storage device shown in the above embodiment is described. The storage device shown in the above embodiment can be applied to the storage device of various electronic devices (for example, information terminals, computers, smart phones, e-book readers, digital cameras (including video cameras), video playback devices, navigation systems, etc.). By using the storage device shown in the above embodiment for the storage device of the above electronic device, low power consumption and high speed of the electronic device can be achieved. Note that here, computers include tablet computers, notebook computers, desktop computers, and large computers such as server systems. Alternatively, the storage device shown in the above embodiment is applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, SSDs (solid state drives), etc. FIG. 29A to FIG. 29E Several structural examples of the removable storage device are schematically shown. For example, the storage device shown in the above embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0583] Fig.29A 11 is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The storage device shown in the above embodiment can be assembled to the memory chip 1105 and the like.

[0584] Fig.29B This is a schematic diagram of the appearance of an SD card. Fig.29C11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The storage device shown in the above embodiment can be assembled on the memory chip 1114, etc.

[0585] Fig.29D This is a schematic diagram of the appearance of SSD. Fig.29E 1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and a DOSRAM chip can be used, for example. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The storage device shown in the above embodiment can be assembled to the memory chip 1154, etc.

[0586] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments, etc. described in this specification as appropriate.

[0587] (Implementation 7) The storage device according to one embodiment of the present invention can be used in a processor or chip such as a CPU or a GPU. By using such a processor or chip such as a CPU or a GPU in an electronic device, it is possible to realize low power consumption and high speed of the electronic device. FIG. 30A to FIG. 30H A specific example of an electronic device including a processor or chip such as a CPU or a GPU using the storage device is shown.

[0588] <Electronic equipment and systems> A GPU or chip according to one embodiment of the present invention can be installed in a variety of electronic devices. Examples of electronic devices include television devices, displays for desktop or notebook information terminals, digital signage, large-scale game machines such as pinball machines, and other electronic devices with larger screens, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. In addition, by setting a GPU or chip according to one embodiment of the present invention in an electronic device, the electronic device can be provided with artificial intelligence.

[0589] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal using the antenna, an image, information, etc. can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0590] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of sensing, detecting or measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared).

[0591] An electronic device of one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc. FIG. 30A to FIG. 30H An example of an electronic device is shown.

[0592] [Information Terminal] Fig. 30A The figure shows a mobile phone (smartphone) which is one of the information terminals. The information terminal 5100 includes a housing 5101 and a display portion 5102 . The display portion 5102 is provided with a touch panel as an input interface, and buttons are provided on the housing 5101 .

[0593] The information terminal 5100 can realize low power consumption and high speed by adopting the chip of one embodiment of the present invention.

[0594] Fig. 30B 1 and 2. The notebook information terminal 5200 is shown. The notebook information terminal 5200 includes an information terminal body 5201, a display portion 5202, and a keyboard 5203.

[0595] Similar to the above-mentioned information terminal 5100 , the notebook information terminal 5200 can realize low power consumption and high speed by adopting a chip according to one embodiment of the present invention.

[0596] Note that in the above, Fig. 30A and Fig. 30B Although a smartphone and a notebook information terminal are shown as examples of electronic devices, information terminals other than smartphones and notebook information terminals may also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0597] [Game console] Fig. 30C A portable game console 5300 is shown as an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, and operation keys 5306. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided in the housing 5301 to another housing (not shown), the image output to the display unit 5304 can be output to another video display device (not shown). At this time, the housing 5302 and the housing 5303 can be used as an operation unit, respectively. Thus, multiple game players can play games at the same time. The chip shown in the above embodiment can be assembled to a chip provided on a substrate of the housing 5301, the housing 5302, and the housing 5303.

[0598] in addition, Fig.30D A stationary gaming machine 5400, which is one of the gaming machines, is shown. The stationary gaming machine 5400 is connected to a controller 5402 by wireless or wired connection.

[0599] By applying a GPU or chip of one embodiment of the present invention to a gaming machine such as the portable gaming machine 5300 and the fixed gaming machine 5400, a gaming machine with low power consumption can be realized. In addition, the heat generated by the circuit can be reduced by means of low power consumption, thereby reducing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0600] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, low power consumption and high speed can be achieved.

[0601] Although Fig. 30C and Fig.30DPortable game consoles and stationary game consoles are shown as examples of game consoles, but game consoles to which a GPU or chip according to one embodiment of the present invention is applied are not limited thereto. Game consoles to which a GPU or chip according to one embodiment of the present invention is applied include, for example, arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like.

[0602] [Mainframe computer] The GPU or chip according to one embodiment of the present invention can be applied to large computers.

[0603] Fig.30E A supercomputer 5500 is shown as an example of a large computer. Fig.30F A rack-mount computer 5502 included in the supercomputer 5500 is shown.

[0604] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that the plurality of computers 5502 are housed in the rack 5501. In addition, the computer 5502 is provided with a plurality of substrates 5504 on which the GPUs or chips described in the above embodiment can be mounted.

[0605] Supercomputer 5500 is a large computer mainly suitable for scientific computing. Scientific computing requires huge calculations at high speed, so the power consumption is large and the heat generation of the chip is high. For example, the amount of data used in a data center including multiple supercomputers 5500 is very large. Specifically, it is estimated that the amount of digital data in the world exceeds 10 24 (yota) bytes or 10 30 (quetta) bytes.

[0606] By applying a GPU or chip of one embodiment of the present invention to supercomputer 5500, a low-power supercomputer can be realized. In addition, low power consumption can reduce the heat generated by the circuit, thereby reducing the impact of heat on the circuit itself, peripheral circuits and modules. By applying a GPU or chip using a storage device of one embodiment of the present invention, a low-power supercomputer can be realized. Thus, by reducing the amount of digital data in the world, it is expected to contribute to global warming countermeasures.

[0607] exist Fig.30E and Fig.30F In the embodiment of the present invention, a supercomputer is shown as an example of a large-scale computer, but a large-scale computer to which a GPU or chip of one embodiment of the present invention is applied is not limited to this. As a large-scale computer to which a GPU or chip of one embodiment of the present invention is applied, for example, a computer (server) providing a service, a large-scale general-purpose computer (mainframe), etc. can be cited.

[0608] [Mobile body] The GPU or chip according to one embodiment of the present invention c...

Claims

1. A transistor, comprising: a first electrical conductor having a columnar region; a first insulator having a cylindrical first region; a second conductor having an opening through which the first conductor passes; A first semiconductor located on the second conductor and having a cylindrical second region; as well as a third conductor on the first semiconductor, wherein the first region surrounds the columnar region, The first conductor has a third region located above the opening, Furthermore, the first conductor is surrounded by the second region via the first region in the third region.

2. The transistor according to claim 1, The third conductor overlaps with the first conductor.

3. The transistor according to claim 1, further comprising: The second insulator, wherein the second insulator has a second opening, The first conductor has a region located within the second opening, And the second conductor has a region in contact with the top surface of the second insulator.

4. A transistor comprising: a first electrical conductor having a columnar region; a first insulator having a cylindrical first region; a second conductor having an opening through which the first conductor passes; A first semiconductor located on the second conductor and having a cylindrical second region; a second insulator on the first electrical conductor; as well as a third conductor on the second insulator, wherein the first region surrounds the columnar region, The first conductor has a third region located above the opening, The first conductor is surrounded by the second region of the first semiconductor via the first region in the third region. Furthermore, the third conductor overlaps with the first conductor via the second insulator.

5. The transistor according to claim 4, The third conductor overlaps with the first conductor.

6. The transistor according to claim 4, The first semiconductor is located on the second insulator and has a region located between the second insulator and the third conductor.

7. The transistor according to claim 4, wherein the first insulator comprises at least one of silicon oxide and silicon oxynitride, And the second insulator includes at least one of silicon nitride and silicon oxynitride.

8. The transistor according to claim 4, further comprising: The third insulator, wherein the third insulator has a second opening, The first conductor has a region located within the second opening, And the second conductor has a region in contact with the top surface of the second insulator.

9. The transistor according to claim 1 or 4, The third conductor is in contact with the top surface of the first semiconductor.

10. The transistor according to claim 1 or 4, The first semiconductor has a region in contact with a side surface of the third conductor.

11. The transistor according to claim 1 or 4, The first semiconductor is a metal oxide containing indium or zinc.

12. A storage device, comprising: transistor; as well as The capacitor across the transistor, The transistor includes a first conductor having a columnar region, a first insulator having a tubular first region, a second conductor having an opening through which the first conductor passes, a first semiconductor having a tubular second region and located on the second conductor, and a third conductor on the first semiconductor. The capacitor includes a fourth conductor having a columnar region, a second insulator provided to cover a side surface of the fourth conductor, and a fifth conductor on the second insulator. The first region of the first insulator surrounds the columnar region, The first conductor has a third region located above the opening, The first conductor is surrounded by the second region of the first semiconductor via the first region in the third region. Furthermore, the fourth conductor is located on the third conductor.

13. The storage device according to claim 12, The third conductor overlaps with the first conductor.

14. The storage device according to claim 12, When viewed from a plane, the first conductor overlaps with the fourth conductor.

15. The storage device according to claim 12, further comprising: The third insulator, wherein the third insulator has a second opening, The fourth conductor has a fourth region located in the second opening and having a side surface thereof in contact with the third insulator, and a fifth region located on the fourth region and having a side surface thereof in contact with the second insulator.

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