An optical proximity correction method, apparatus, device, and storage medium

Abstract

This application provides an optical proximity correction method, apparatus, device, and storage medium, including: constructing a three-dimensional thin-film stacking model based on the structural layout information of a target wafer; performing photolithography simulation on the three-dimensional thin-film stacking model based on photolithography parameter information to determine the simulated size data and simulated photoresist three-dimensional data; accurately simulating the actual light intensity distribution of the three-dimensional wafer during the photolithography process, and the simulation results provide a strong reference for the subsequent correction process, thereby improving the practicality of the correction process; and performing optical proximity correction based on standard size data and standard photoresist three-dimensional data. The technical solution provided by this application can fully consider the multi-layered structure of the target wafer at a three-dimensional level during the optical proximity effect correction process, effectively improving the realism and practicality of the subsequent photolithography simulation process. By considering the actual light intensity distribution in conjunction with the wafer structure, it enhances the optical proximity correction effect and the production efficiency of compliant wafers.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing, and in particular relates to an optical proximity correction method, apparatus, device, and storage medium. Background Technology

[0002] In the semiconductor manufacturing industry, optical proximity correction (OPC) is one of the important processes for manufacturing chip masks that can be used to lithographically create compliant wafers based on the chip layout.

[0003] Currently, the correction of optical proximity effect in chip masks is mainly achieved through wafer lithography simulation to determine appropriate and specific correction methods. However, most current wafer lithography simulations only simulate two-dimensional cross-sections of the wafer. Traditional two-dimensional cross-section simulations cannot accurately simulate the actual light intensity distribution on the wafer during the lithography process. For example, when special process structures such as shallow trench isolation (STI) or polysilicon gate (Poly Gate) are stacked on the wafer surface, two-dimensional cross-section lithography simulations cannot fully consider the reflection problem of these special structures, resulting in errors in the optical proximity effect correction process, which in turn affects the actual wafer lithography process. Summary of the Invention

[0004] This application provides an optical proximity correction method, apparatus, and storage medium to effectively improve the accuracy and practicality of the optical proximity effect correction process for wafers.

[0005] In a first aspect, embodiments of this application provide an optical proximity correction method, including:

[0006] Based on the structural layout information of the target wafer, construct a three-dimensional thin film stacking model corresponding to the target wafer;

[0007] Obtain the standard dimension data and standard photoresist 3D data corresponding to the target wafer;

[0008] Based on the preset photolithography parameters, a photolithography simulation is performed on the three-dimensional thin film stacking model to determine the simulation size data and simulation photoresist three-dimensional data corresponding to the three-dimensional thin film stacking model.

[0009] Based on simulated and standard size data, as well as simulated and standard 3D photoresist data, optical proximity correction is performed on the target wafer.

[0010] Secondly, embodiments of this application provide an optical proximity correction device, including:

[0011] The model building unit is used to build a three-dimensional thin film stacking model of the target wafer based on the structural layout information of the target wafer.

[0012] The acquisition unit is used to acquire standard dimension data and standard photoresist three-dimensional data corresponding to the target wafer;

[0013] The photolithography simulation unit is used to perform photolithography simulation on the three-dimensional thin film stacking model according to the preset photolithography parameter information, and to determine the simulation size data and simulation photoresist three-dimensional data corresponding to the three-dimensional thin film stacking model.

[0014] The optical proximity correction unit is used to perform optical proximity correction on the target wafer based on simulated size data and standard size data, as well as simulated photoresist 3D data and standard photoresist 3D data.

[0015] Thirdly, embodiments of this application provide an electronic device, which includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement the steps of any of the optical proximity correction methods of embodiments of this application.

[0016] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, the steps of any of the optical proximity correction methods of embodiments of this application are implemented.

[0017] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, enable the electronic device to perform the steps of any of the optical proximity correction methods of embodiments of this application.

[0018] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:

[0019] The optical proximity correction method provided in this application can construct a three-dimensional thin-film stacking model based on the structural layout information of the target wafer. This fully considers the multi-layered structure of the target wafer at a three-dimensional level, effectively improving the realism and practicality of subsequent photolithography simulation. Then, based on photolithography parameters, photolithography simulation is performed on the three-dimensional thin-film stacking model to determine the corresponding simulated size data and simulated photoresist three-dimensional data. This accurately simulates the actual light intensity distribution of the three-dimensional wafer during the photolithography process. The simulation results provide a strong reference for the subsequent correction process, thereby improving its practicality. Finally, optical proximity correction is performed based on standard size data and standard photoresist three-dimensional data. By fully considering the wafer structure and light intensity distribution at a three-dimensional level, the optical proximity correction effect and the production efficiency of compliant wafers are improved.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram illustrating photolithographic simulation of a two-dimensional cross-section of a wafer, provided as an embodiment of this application.

[0023] Figure 2 A schematic flowchart of an optical proximity correction method provided in one embodiment of this application;

[0024] Figure 3(a) is one of the schematic diagrams of a three-dimensional thin film stacking model corresponding to a target wafer with uneven structural layout provided in an embodiment of this application;

[0025] Figure 3(b) is a second schematic diagram of a three-dimensional thin film stacking model corresponding to a target wafer with uneven structural layout provided in an embodiment of this application;

[0026] Figure 4 A schematic diagram illustrating a process for photolithography simulation using an optical analysis model and a photoresist analysis model, provided as an embodiment of this application;

[0027] Figure 5(a) is one of the schematic diagrams of an optical proximity correction process for a target wafer with a shallow trench isolation structure provided in an embodiment of this application;

[0028] Figure 5(b) is a second schematic diagram of an optical proximity correction process for a target wafer with a shallow trench isolation structure provided in an embodiment of this application;

[0029] Figure 6(a) is one of the schematic diagrams of an optical proximity correction process for a target wafer having a polysilicon gate structure according to an embodiment of this application;

[0030] Figure 6(b) is a second schematic diagram of an embodiment of the present application providing an optical proximity correction process for a target wafer having a polysilicon gate structure;

[0031] Figure 7 This is a schematic diagram of the overall process of an optical proximity correction method provided in one embodiment of this application;

[0032] Figure 8 This is a schematic diagram of the structure of an optical proximity correction device provided in another embodiment of this application;

[0033] Figure 9 This is a schematic diagram of the structure of an optical proximity correction device provided in another embodiment of this application. Detailed Implementation

[0034] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0035] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0036] Currently, optical proximity correction (OPC) is one of the important steps in chip manufacturing. At present, it is mainly determined by performing wafer lithography simulation to determine the correction to be performed.

[0037] However, current optical proximity effect correction methods mostly only simulate the photolithography of two-dimensional wafer cross-sections, failing to accurately capture the actual light intensity distribution during the photolithography process. When dealing with target wafers of different stacking structures, the significant discrepancy between the light intensity distribution and reality leads to errors in the subsequent optical proximity effect correction process, thus affecting the actual photolithography process on the wafer. For a photolithography simulation process targeting two-dimensional wafer cross-sections, please refer to [reference needed]. Figure 1 As shown in the image.

[0038] Figure 1 This is a schematic diagram illustrating photolithographic simulation of a two-dimensional cross-section of a wafer, provided as an embodiment of this application.

[0039] like Figure 1As shown, the top layer is the photolithography light source and the mask corresponding to the wafer. The middle layer is a two-dimensional cross-sectional image of the wafer, consisting of multiple stacked layers, which may specifically include... Figure 1 The image shows the top anti-reflective coating (TARC), photoresist layer (PR), and substrate layer. The bottom layer shows the development result after photolithography simulation.

[0040] The specific process is as follows: Figure 1 The light source in the middle layer is partially blocked by the mask, illuminating only a portion of the middle layer. Upon exposure to the light source, some of the photoresist in the middle layer undergoes chemical decomposition and dissolves in the developer. Finally, after the photolithography simulation ends, the development result shown in the bottom layer is obtained. It can be seen that only a portion of the photoresist on the substrate was not illuminated due to the mask's obstruction.

[0041] like Figure 1 The process of photolithography simulation based on two-dimensional cross-sectional images shown is relatively simple, as the wafer itself has no special processes or structures. However, when the wafer contains special process structures such as shallow trench isolation (STI) or polysilicon gate (Poly Gate), Figure 1 The method shown can no longer perform photolithography simulation more accurately.

[0042] The reason is that different processes and structures within a wafer may cause light reflection during the actual photolithography process due to processing techniques or material properties. This reflection can decompose a portion of the photoresist layer that should not be decomposed. Consequently, the photoresist morphology on the actual wafer surface deviates significantly from the standard condition, thus affecting the performance and yield of the post-lithographic wafer. This is achieved solely through... Figure 1 The method of lithography simulation based on two-dimensional cross-sectional images shown cannot accurately simulate the light intensity distribution in the actual lithography process. Furthermore, when there are special process structures, the specific images corresponding to different cross-sections of the wafer are also different. A single two-dimensional cross-sectional image cannot accurately cover the complete internal structure of the wafer.

[0043] Based on the technical issues mentioned above, embodiments of this application provide an optical proximity correction method, apparatus, device, and storage medium that can construct a three-dimensional thin film stacking model corresponding to the structural layout information of the target wafer, so as to fully consider the multi-level structure of the target wafer from a three-dimensional perspective, thereby improving the realism and practicality of the subsequent photolithography simulation process.

[0044] Photolithographic simulations were performed on a three-dimensional thin-film stacked model to determine the simulated dimensional data and the simulated three-dimensional photoresist data. The simulation accurately simulated the actual light intensity distribution within the three-dimensional wafer, providing a strong theoretical basis for subsequent correction processes and improving their practicality. Finally, optical proximity correction was performed based on standard dimensional data and standard photoresist three-dimensional data. The technical solution of this application fully considers the wafer structure and light intensity distribution at a three-dimensional level, improving the practical effect of optical proximity correction and enhancing wafer production efficiency and yield.

[0045] The execution entity used in the embodiments of this application can be a terminal device, such as a desktop computer or laptop computer, or a remote device such as a server. In addition, the execution entity used in the embodiments of this application can also be a software entity, such as a client or software program installed on a terminal device. The execution entity used in applying the technical solutions provided in the embodiments of this application is not strictly limited and can be determined according to the actual application scenario and actual needs.

[0046] The specific application scenarios corresponding to the optical proximity correction method, apparatus, device, and storage medium provided in the embodiments of this application are not strictly limited in this application, and can be determined according to actual needs.

[0047] For example, in a scenario where optical proximity effect correction is performed on a target wafer with a shallow trench isolation structure, the execution subject (e.g., a terminal device) applying the embodiments of this application can construct a three-dimensional thin film stack model with a shallow trench isolation structure.

[0048] Then, based on the preset photolithography parameters, the three-dimensional thin film stacking model is simulated to accurately simulate the reflection of the shallow trench isolation structure by the light source during the photolithography process, thereby determining the simulated size data and simulated photoresist three-dimensional data of the target wafer with the shallow trench isolation structure.

[0049] Further optical proximity correction based on simulation data is performed to effectively overcome the negative impact of reflection from shallow trench isolation structures on the three-dimensional morphology of photoresist on wafers, thereby ensuring wafer quality and production yield.

[0050] It should be noted that the application scenarios described in the above embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems. The optical proximity correction method provided by the embodiments of this application can be applied to various scenarios requiring optical proximity correction of wafers.

[0051] Figure 2 This is a flowchart illustrating an optical proximity correction method provided in one embodiment of this application.

[0052] like Figure 2 As shown in the figure, the optical proximity correction method provided in this application embodiment includes steps S201 to S204.

[0053] S201: Based on the structural layout information of the target wafer, construct a three-dimensional thin film stacking model corresponding to the target wafer.

[0054] In step S201, the execution subject (e.g., terminal device) of the technical solution provided in the embodiments of this application can construct a three-dimensional thin film stacking model corresponding to the target wafer based on the structural layout information corresponding to the target wafer.

[0055] The structural layout information can specifically represent the structural type contained in the target wafer, such as the Shallow Trench Isolation (STI) or Polysilicon Gate (PolyGate) mentioned in the example above.

[0056] Regarding the specific construction process of the three-dimensional thin film stacking model, in one embodiment provided in this application, the three-dimensional thin film stacking model can be constructed based on the preset photolithography process data and the structural layout information corresponding to the target wafer.

[0057] Specifically, photolithography process data may include, but is not limited to, coating parameters, deposition parameters, chemical mechanical polishing (CMP) parameters, and etching parameters.

[0058] Spraying parameters specifically represent the speed, thickness, and uniformity of photoresist coating during the three-dimensional thin-film stack model. Deposition parameters represent the deposition temperature, pressure, gas flow rate, and deposition rate of the three-dimensional thin-film stack model, and can be further categorized into different deposition techniques, such as Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD). Chemical mechanical polishing parameters specifically represent data such as polishing pressure, slurry composition, rotation speed, and flatness. Etching parameters specifically represent data such as etching gas type, etching time, temperature, and plasma power.

[0059] Based on the aforementioned data and the structural layout corresponding to the target wafer, a three-dimensional thin-film stacking model of the target wafer can be accurately constructed. It should also be noted that when the structural layout is not uniformly distributed within the target wafer, the two-dimensional cross-sections at different locations in the three-dimensional thin-film stacking model will not be entirely identical.

[0060] Therefore, the technical solution provided in this application not only provides a three-dimensional thin film stacking model that can simulate the actual light intensity distribution for subsequent photolithography simulation processes, but also fully considers the impact of structural non-uniformity on photolithography simulation. Instead of performing photolithography simulation of the entire three-dimensional wafer based solely on a single two-dimensional cross-section of the target wafer, a specific example of the three-dimensional thin film stacking model is shown in Figures 3(a) and 3(b), taking the structural layout information corresponding to the target wafer, which includes two bottom anti-reflection layers, as well as the presence of etching structures and deposition processes.

[0061] Figures 3(a) and 3(b) are schematic diagrams of a three-dimensional thin film stacking model corresponding to a target wafer with a non-uniform structural layout provided in one embodiment of this application.

[0062] Figure 3(a) is a front top view of the three-dimensional thin film stack model corresponding to the target wafer with uneven structural layout. As can be seen from Figure 3(a), the etched structure and corresponding deposition distribution in the target wafer of this example are not uniform, with different sizes of etched and deposited structures in the middle left, lower middle, and upper right.

[0063] Figure 3(b) is a schematic diagram of multiple cross-sections of a three-dimensional thin-film stacked model corresponding to the non-uniform structural layout distribution of the target wafer in Figure 3(a). As shown in Figure 3(b), the structural layouts represented in the front, back, and middle cross-sections of the three-dimensional thin-film stacked model corresponding to the target wafer in this example are completely different.

[0064] The technical solution provided in this application allows for simulation of the entire three-dimensional thin-film stacked model shown in Figure 3(b) during subsequent photolithography simulation, rather than simulating a specific cross-section. This fully considers the influence of each structural layout on the light intensity distribution, as well as the impact of non-uniform layout distribution on the overall photolithography simulation process of the target wafer. This provides a strong basis for subsequent optical proximity correction, thereby ensuring the accuracy of the actual photolithography process and improving wafer production yield and quality.

[0065] S202: Obtain the standard dimension data and standard photoresist 3D data corresponding to the target wafer.

[0066] In step S202, the technical solution provided in this application embodiment can obtain the standard size data and standard photoresist three-dimensional data corresponding to the target wafer.

[0067] Specifically, standard dimension data can be used to represent the dimensional scanning data (Critical Dimension, CD) of a target wafer with standard dimensions, determined by a Critical Dimension Scanning Electron Microscope (CD-SEM). Standard photoresist 3D data can be used to represent the 3D morphology of the photoresist on the surface of a target wafer that conforms to the standard.

[0068] Regarding the specific process of determining standard size data and standard photoresist three-dimensional data, in one embodiment provided in this application, the size scan data corresponding to the target wafer under theoretical conditions can be determined based on the design layout data corresponding to the target wafer, and used as the standard size data.

[0069] Then, 3D data of multiple sample wafers corresponding to the target wafer can be obtained. Specifically, the sample wafers can be historically produced wafers corresponding to the target wafer; the corresponding dimensional scan data needs further verification to determine if they conform to standards.

[0070] Next, for each sample wafer, the corresponding dimensional scanning data can be determined based on its 3D data. Finally, the dimensional scanning data of each sample wafer is compared with the acquired standard dimensional data. Matching sample wafers are designated as standard wafers, and their corresponding 3D data can be used as standard photoresist 3D data. Specifically, the matching process involves determining whether the data error between the dimensional scanning data of each sample wafer and the standard dimensional data meets a predefined error threshold.

[0071] It should be noted that the target wafer and the corresponding multiple sample wafers mentioned above can all be partial wafers of a whole wafer. Specifically, the 3D data of the sample wafers can be 3D slice data of the same wafer portion from multiple historically produced wafers. Furthermore, if multiple sample wafers matching standard size data exist simultaneously, the 3D features corresponding to the 3D data of multiple sample wafers can be extracted to determine the average 3D data covering multiple sample wafers, which can then be used as standard photoresist 3D data.

[0072] Through the above determination process, the technical solution provided in this application embodiment can accurately determine the standard size data of the target wafer and accurately screen out sample wafers that match the standard size data, using the corresponding three-dimensional data as standard photoresist three-dimensional data. This provides a reference standard for subsequent inspection of photolithography simulation results, effectively ensuring the accuracy of inspecting photolithography simulation results and improving the effectiveness and practicality of subsequent optical proximity correction processes.

[0073] S203: Based on the preset photolithography parameters, perform photolithography simulation on the three-dimensional thin film stacking model to determine the simulation size data and simulation photoresist three-dimensional data corresponding to the three-dimensional thin film stacking model.

[0074] In step S203, the technical solution provided in this application embodiment can perform photolithographic simulation on the three-dimensional thin film stacking model constructed in the above steps based on pre-set photolithographic parameter information. Based on the photolithographic simulation results, the simulated size data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stacking model are determined.

[0075] The lithography parameter information may include, but is not limited to, the light source corresponding to the lithography process and the mask information corresponding to the target wafer, used to simulate the actual lithography simulation process. The simulated dimensional data is similar to the standard dimensional data in the above steps, specifically the dimensional scan data in the 3D thin film stack model after lithography simulation. Similarly, the simulated photoresist 3D data is similar to the standard photoresist 3D data in the above steps, specifically used to represent the 3D morphology of the photoresist corresponding to the 3D thin film stack model after lithography simulation.

[0076] Regarding the specific processing of photolithography simulation, in one embodiment provided in this application, the technical solution provided in this application can input a three-dimensional thin film stacking model and photolithography parameter information into a preset photolithography simulation model, so that the photolithography simulation model can perform photolithography simulation on the three-dimensional thin film stacking model based on the photolithography parameter information, thereby accurately determining the simulation size data and simulation photoresist three-dimensional data corresponding to the three-dimensional thin film stacking model after photolithography simulation.

[0077] In one embodiment provided in this application, the photolithography simulation model may specifically include, but is not limited to, an optical analysis model and a photoresist analysis model. The optical analysis model can be used to analyze the light path and intensity distribution of the light source on multiple stacked layers of the three-dimensional thin film stack model during the photolithography simulation. The photoresist analysis model can be used to analyze the three-dimensional morphology of the undecomposed portion of the photoresist in the photoresist layer of the three-dimensional thin film stack model after the photolithography simulation.

[0078] In this embodiment, the specific process of photolithography simulation using optical analysis models and photoresist analysis models can be found in [reference needed]. Figure 4 As shown in the image.

[0079] Figure 4 This is a schematic flowchart of a photolithography simulation using an optical analysis model and a photoresist analysis model, provided as an embodiment of this application, specifically including steps S401 to S403.

[0080] S401: Determine the light intensity distribution data of the three-dimensional thin film stacking model during the photolithography simulation process using the optical analysis model and photolithography parameter information.

[0081] Through step S401, the photolithography analysis model can analyze and determine the distribution of light intensity in each stacked layer of the three-dimensional thin film stack model when it is irradiated by a light source, based on the light source information and mask information in the photolithography parameters. For example, it can fully and accurately determine the reflection of each material or structure from the irradiated light. The determined light intensity distribution data can be used for subsequent photolithography simulation processes.

[0082] This application does not limit the specific type of optical analysis model. It could be, for example, a rigorous coupled-wave analysis (RCWA) model. This involves first calculating the incident light intensity at the top of the three-dimensional thin-film stack model, then solving Maxwell's equations corresponding to the three-dimensional thin-film stack model using rigorous coupled-wave analysis to accurately calculate the propagation path, scattering, and reflection of the incident light in each stacked layer. Finally, the data is integrated to determine the light intensity distribution. Alternatively, it could be other models or algorithms with optical analysis capabilities, which can be flexibly defined according to the actual application scenario and specific needs.

[0083] S402: Based on the light intensity distribution data, perform photolithography simulation on the three-dimensional thin film stacking model to determine the simulation size data corresponding to the three-dimensional thin film stacking model.

[0084] In step S402, based on the light intensity distribution data determined by the optical analysis model, a photolithographic simulation conforming to the actual light intensity distribution is performed on the three-dimensional thin film stacking model to obtain the photolithographically simulated three-dimensional thin film stacking model. Based on the photolithographically simulated three-dimensional thin film stacking model, the corresponding simulated size data can be determined.

[0085] It should be noted that, in another embodiment provided in this application, before performing photolithography simulation based on light intensity distribution data, it is also possible to pre-determine whether there may be potential abnormal problems in the subsequent photolithography simulation process based on the light intensity distribution data, so as to adjust the model structure of the three-dimensional thin film stacking model in time before photolithography simulation and avoid the execution of photolithography simulation process that is invalid or has abnormal problems.

[0086] The specific method for determining whether there are potential anomalies in the photolithography simulation process based on light intensity distribution data is not strictly limited in the embodiments provided in this application. It can be that relevant personnel, based on historical experience, determine the light intensity distribution data through an optical analysis model and then proactively predict the subsequent photolithography simulation process based on the light intensity distribution data before conducting the photolithography simulation, thereby promptly identifying simulation anomalies that may be caused by the current light intensity distribution data.

[0087] For example, it can identify special cases where areas that should have strong light intensity distribution actually have abnormally low light intensity distribution. Besides manual observation, it can also be done by predicting potential anomalies in the photolithography simulation process based on pre-set detection rules and light intensity distribution data. Specific implementation methods and approaches can be determined according to the actual application scenario and specific needs.

[0088] After identifying a problem in the light intensity distribution data that could cause anomalies in subsequent photolithography simulations, the model structure corresponding to the 3D thin film stacking model can be adjusted in advance based on this anomaly. Then, the light intensity distribution data corresponding to the adjusted 3D thin film stacking model is determined using the optical analysis model described in the previous steps. Finally, based on the adjusted light intensity distribution data, photolithography simulations are performed on the adjusted 3D thin film stacking model to determine the simulation dimensions.

[0089] Based on the above process, potential anomalies that may exist during the photolithography simulation can be accurately detected before the simulation begins, allowing for timely adjustments to the 3D thin film stacking model. This effectively ensures the realism and practicality of the photolithography simulation process, avoids ineffective simulations, and improves simulation efficiency. Furthermore, an accurate photolithography simulation process also enhances the accuracy and practicality of subsequent optical proximity correction processes.

[0090] S403: By using the photoresist analysis model, analyze the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stacking model simulated by photolithography, and obtain the simulated three-dimensional data of the photoresist.

[0091] In step S403, the photoresist analysis model can accurately determine the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stack model after photolithography simulation, thereby obtaining the corresponding simulated three-dimensional photoresist data. The specific model type and structure of the photoresist analysis model are not strictly limited in this embodiment. Specifically, it can be a computational model with three-dimensional model image analysis capabilities, such as Convolutional Neural Networks (CNNs), and can be selected according to the actual application scenario and actual needs.

[0092] Through the steps S401 to S403 described above, a photolithography simulation that closely approximates the real-world situation can be performed on the three-dimensional thin-film stacked model, accurately determining the simulated dimensional data and simulated photoresist 3D data corresponding to the simulated three-dimensional thin-film stacked model. This provides a strong basis for the subsequent optical proximity correction process, improving the practicality and accuracy of the correction process, and further enhancing the final wafer production efficiency and yield.

[0093] S204: Based on simulated size data and standard size data, as well as simulated photoresist 3D data and standard photoresist 3D data, perform optical proximity correction on the target wafer.

[0094] In step S204, the technical solution provided in this application embodiment can determine whether the optical simulation process of the target wafer conforms to the standard based on the simulated size data and simulated photoresist three-dimensional data determined after photolithographic simulation of the three-dimensional thin film stacking model through the above steps, as well as the standard size data and standard photoresist three-dimensional data obtained in the previous steps. For target wafers that do not conform to the standard, optical proximity correction can be performed.

[0095] Specifically, in one embodiment provided in this application, the simulation error corresponding to the three-dimensional thin film stacking model during photolithography simulation can be determined first based on the simulated size data and standard size data. The simulation error can specifically be the root mean square (RMS) of the simulated size data and the standard size data. Then, it is determined whether the simulation error is less than a preset standard error threshold.

[0096] Simultaneously, it can also determine whether simulated photoresist 3D data matches standard photoresist 3D data. Specifically, it can determine the similarity between simulated and standard photoresist 3D data, and judge whether they match based on a preset similarity threshold.

[0097] When the simulation error is determined to be less than the preset standard error threshold through the above process, or when the simulated photoresist 3D data does not match the standard photoresist 3D data, it can be determined that the photolithography simulation corresponding to the target wafer does not meet the standard, and optical proximity correction processing can be performed on the target wafer. Only when the simulation error is not less than the preset standard error threshold, and the simulated photoresist 3D data matches the standard photoresist 3D data, can it be determined that the photolithography simulation corresponding to the target wafer fully meets the standard.

[0098] Based on the above verification process, it is possible to accurately determine whether the photolithography simulation process of the target wafer meets the standards, and to accurately determine whether optical proximity correction is needed based on simulation results that closely resemble real-world simulation conditions. This effectively ensures the production quality and yield of subsequent wafers, and to some extent also improves the production efficiency of standard wafers.

[0099] The specific process for optical proximity correction of target wafers that do not meet the standards in photolithography simulation can involve adjusting the mask pattern of the target wafer in the photolithography parameter information, adjusting the model structure of the 3D thin film stacking model, or adjusting other parameters in the simulation process. The specific approach depends on the actual application scenario and specific requirements.

[0100] To provide a concrete understanding of the optical proximity correction process for a target wafer, the optical proximity correction process of this application embodiment will be illustrated below using a target wafer with a shallow trench isolation structure and a target wafer with a polysilicon gate as examples.

[0101] Figures 5(a) and 5(b) are schematic diagrams of an embodiment of the present application providing an optical proximity correction process for a target wafer with a shallow trench isolation structure.

[0102] Figure 5(a) is a schematic diagram of the photolithography simulation process of a two-dimensional cross section of a target wafer with a shallow trench isolation structure before optical proximity correction.

[0103] As shown in Figure 5(a), when the incident light from the top light source is blocked by a mask and enters the stack with the shallow trench isolation structure, the side of the shallow trench isolation structure reflects the light back to the photoresist area that was originally not illuminated by the mask. This causes the photoresist that should not be decomposed to be decomposed by the reflected light. The simulation results obtained from the bottom of Figure 5(a) clearly show that some of the photoresist adjacent to the stack with the shallow trench isolation structure in the undecomposed portion is abnormally decomposed, resulting in a significant error between the simulated three-dimensional morphology of the photoresist and the standard three-dimensional data of the photoresist.

[0104] Figure 5(b) is a schematic diagram of the photolithography simulation process after optical proximity correction of the two-dimensional cross-section corresponding to Figure 5(a).

[0105] As shown in Figure 5(b), a light-shielding module was added to the photoresist layer in the two-dimensional cross-section of the three-dimensional thin film stacking model shown in Figure 5(a). The development results at the bottom of Figure 5(b) clearly show that the problem of the photoresist being decomposed due to the reflection of the shallow trench isolation structure in Figure 5(a) no longer occurs. Finally, the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stacking model after the simulation is completely consistent with the standard three-dimensional photoresist data.

[0106] As shown in Figures 5(a) and 5(b), in one embodiment provided in this application, when performing optical proximity correction on a target wafer that does not meet the standards in the photolithography simulation process, the internal structure of the three-dimensional thin film stacking model in the photolithography simulation process can be adjusted, thereby effectively overcoming the abnormal decomposition of photoresist caused by the reflection of light from the structure surface, as shown in Figures 5(a) and 5(b).

[0107] Ultimately, a three-dimensional thin-film stacking model with an added light-shielding module in the photoresist layer, similar to Figure 5(a), along with the unadjusted photolithography parameters, can be used as the optical proximity correction result for the target wafer. This allows the target wafer to be accurately produced according to the design specifications during the subsequent actual production process, significantly improving the production quality and yield of the target wafer.

[0108] Figures 6(a) and 6(b) are schematic diagrams of an embodiment of the present application providing an optical proximity correction process for a target wafer having a polysilicon gate structure.

[0109] Similar to Figure 5(a), Figure 6(a) is a schematic diagram of the photolithography simulation process of a two-dimensional cross-section of a target wafer with a polysilicon gate structure before optical proximity correction.

[0110] As shown in Figure 6(a), when the incident light from the top light source is blocked by the mask and enters the photoresist layer with the polysilicon gate structure, the polysilicon gate structure itself will reflect the light to the photoresist area that was originally not illuminated by the mask, causing the part of the photoresist that should not be decomposed to be decomposed by the reflected light.

[0111] As can be clearly seen from the simulation results obtained from the bottom of Figure 6(a), a portion of the photoresist that should be retained in the three-dimensional morphology of the standard photoresist is abnormally decomposed by the light emitted by the polysilicon gate structure, resulting in a significant error between the three-dimensional morphology of the photoresist in the simulation results and the three-dimensional data of the standard photoresist. This type of photolithography simulation process does not conform to the standard specifications in terms of either the simulated size data or the simulated three-dimensional data of the photoresist.

[0112] Figure 6(b) is a schematic diagram of the photolithography simulation process after optical proximity correction of the two-dimensional cross section corresponding to Figure 5(a).

[0113] As shown in Figure 6(b), a mask auxiliary pattern was added to the structure composed of the light source and mask shown at the top of Figure 6(a). Furthermore, the simulation results at the bottom of Figure 6(b) clearly show that the problem of some photoresist being decomposed due to the light problem of the polysilicon gate structure in Figure 6(a) did not reappear. Finally, the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stack model after the simulation is completely consistent with the standard three-dimensional photoresist data.

[0114] As shown in Figures 6(a) and 6(b), in one embodiment provided in this application, when performing optical proximity correction on a target wafer that does not meet the standards in the photolithography simulation process, the photolithography parameter information in the photolithography simulation process can be adapted and adjusted.

[0115] Specifically, this can be achieved by adjusting the mask image corresponding to the target wafer, as shown in Figures 6(a) and 6(b), and adding auxiliary mask images. The internal structure of the three-dimensional thin-film stacking model can be adjusted to effectively overcome the abnormal decomposition of some photoresist caused by light emitted from the structure itself, as seen in Figures 6(a) and 6(b).

[0116] Ultimately, the adjusted lithography parameters (including the mask image with added mask auxiliary image) and the unadjusted 3D thin film stacking model, similar to those in Figure 6(a), can be used together as the optical proximity correction result for the target wafer. This allows the target wafer to be accurately produced according to the design specifications during the subsequent actual production process, significantly improving the production quality and yield of the target wafer.

[0117] In addition to the examples described above, the technical solutions provided in this application can also achieve optical proximity correction by adjusting other parameters in the photolithography simulation process. For example, adjusting the light source parameters, developer concentration, and simulation temperature. The adjusted parameters can also be used as the optical proximity correction result in the subsequent actual production process of the target wafer.

[0118] Furthermore, the technical solution provided in this application embodiment can perform photolithography simulation again on the target wafer after optical proximity correction to verify whether the target wafer after optical proximity correction strictly conforms to the standard specifications. If the photolithography simulation process still fails to conform to the standard specifications after a single optical proximity correction, optical proximity correction can be performed again, and the correction method can be readjusted or changed. This process is repeated until a photolithography simulation process that conforms to the standard specifications is determined, and the corresponding relevant data is used as the optical proximity correction result.

[0119] To facilitate understanding of the above content, the optical proximity correction method provided in the embodiments of this application will be fully described below, such as... Figure 7 As shown in the image.

[0120] Figure 7 This is a schematic diagram of the overall process of an optical proximity correction method provided in one embodiment of the present application, including steps S701 to S706.

[0121] like Figure 7As shown in the illustration, the optical proximity correction method provided in this application embodiment can construct a three-dimensional thin film stacking model corresponding to the target wafer through step S701 based on photolithography process data and structural layout information. Then, standard size data can be determined through step S702 based on design layout data, and a standard wafer can be determined from multiple sample wafers, thereby determining the three-dimensional data of the standard photoresist.

[0122] Next, in step S703, the three-dimensional thin film stacking model is simulated using the optical analysis model and the photoresist analysis model based on the preset photoresist parameter information to determine the simulated size data and simulated three-dimensional photoresist data corresponding to the three-dimensional thin film stacking model.

[0123] Furthermore, in step S704, based on the standard size data and standard photoresist 3D data, it is determined whether the simulated size data and simulated photoresist 3D data conform to the standard. If they do not conform to the standard, then in step S705, optical proximity correction is performed on the target wafer. The specific correction method can be to adjust the 3D thin film stacking model constructed in S701, or it can be to adjust the photolithography parameters and other parameters used in the photolithography simulation process in step S703 accordingly.

[0124] After adjustment, steps S701 to S704 can be executed again, repeatedly correcting until a photolithography simulation process conforming to standard specifications is determined. Step S706 outputs the corresponding three-dimensional thin film stacking model and photolithography parameter information as optical proximity correction results, enabling high-efficiency and high-precision target wafer manufacturing based on the optical proximity correction results.

[0125] The above describes the specific implementation of the optical proximity correction method provided in this application embodiment. It can construct a three-dimensional thin film stacking model corresponding to the structural layout information of the target wafer, so as to fully consider the multi-level structure of the target wafer from a three-dimensional perspective, thereby improving the realism and practicality of the subsequent photolithography simulation process.

[0126] Photolithography simulations were performed on a three-dimensional thin-film stacked model to determine the simulated dimensional data and the three-dimensional data of the simulated photoresist. The simulation accurately simulated the actual light intensity distribution within the three-dimensional wafer, and the results provide a strong theoretical basis for subsequent correction processes, improving their practicality. The simulation process separately considered and analyzed the light intensity distribution and the three-dimensional morphology of the photoresist, which helps to achieve accurate and effective optical proximity correction processes.

[0127] Finally, optical proximity correction is performed based on standard size data and standard photoresist 3D data. The technical solution of this application fully considers the wafer structure and light intensity distribution at a 3D level, improving the practical effect of optical proximity correction and the wafer production efficiency and yield. Furthermore, the technical solution provided by this application can perform optical proximity correction on the target wafer from multiple angles, increasing the robustness of optical proximity correction and improving wafer production quality and yield.

[0128] Based on the optical proximity correction method provided in the above embodiments, this application also provides specific implementation methods of the optical proximity correction device, please refer to the following embodiments.

[0129] Figure 8 The diagram below shows the structure of an optical proximity correction device provided in another embodiment of this application. The optical proximity correction device 800 includes: a model building unit 801, an acquisition unit 802, a photolithography simulation unit 803, and an optical proximity correction unit 804.

[0130] Model building unit 801 is used to build a three-dimensional thin film stacking model corresponding to the target wafer based on the structural layout information corresponding to the target wafer.

[0131] The acquisition unit 802 is used to acquire the standard dimension data and standard photoresist three-dimensional data corresponding to the target wafer;

[0132] The photolithography simulation unit 803 is used to perform photolithography simulation on the three-dimensional thin film stacking model according to the preset photolithography parameter information, and to determine the simulation size data and simulation photoresist three-dimensional data corresponding to the three-dimensional thin film stacking model.

[0133] The optical proximity correction unit 804 is used to perform optical proximity correction on the target wafer based on simulated size data and standard size data, as well as simulated photoresist three-dimensional data and standard photoresist three-dimensional data.

[0134] In the embodiments provided in this application, the aforementioned apparatus can construct a three-dimensional thin-film stacking model based on the structural layout information of the target wafer. This fully considers the multi-layered structure of the target wafer at a three-dimensional level, effectively improving the realism and practicality of subsequent photolithography simulation processes. Photolithography simulation is performed on the three-dimensional thin-film stacking model based on photolithography parameter information to determine the corresponding simulated size data and simulated photoresist three-dimensional data. The actual light intensity distribution of the three-dimensional wafer during the photolithography process is accurately simulated. The simulation results provide a strong reference for subsequent correction processes, thereby improving the practicality of the correction process. Finally, optical proximity correction is performed based on standard size data and standard photoresist three-dimensional data. By fully considering the wafer structure and light intensity distribution at a three-dimensional level, the optical proximity correction effect and the production efficiency of compliant wafers are improved.

[0135] In one embodiment, the photolithography simulation unit 803 is specifically used for:

[0136] The three-dimensional thin film stacking model and photolithography parameter information are input into the preset photolithography simulation model so that the photolithography simulation model can perform photolithography simulation on the three-dimensional thin film stacking model based on the photolithography parameter information, and determine the simulation size data and the simulation photoresist three-dimensional data.

[0137] In one embodiment, the photolithography simulation model includes an optical analysis model and a photoresist analysis model;

[0138] The aforementioned photolithography simulation unit 803 is specifically used for:

[0139] The light intensity distribution data of the three-dimensional thin film stacking model during the photolithography simulation process were determined by using optical analysis models and photolithography parameter information.

[0140] Based on the light intensity distribution data, a photolithographic simulation was performed on the three-dimensional thin film stacking model to determine the simulation size data corresponding to the three-dimensional thin film stacking model.

[0141] By using a photoresist analysis model, the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stacking model simulated by photolithography is analyzed, and the three-dimensional data of the simulated photoresist are obtained.

[0142] In one embodiment, the photolithography simulation unit 803 is specifically used for:

[0143] Based on the light intensity distribution data, determine whether there are simulation anomalies in the photolithography simulation process;

[0144] If so, adjust the three-dimensional thin film stacking model according to the simulation anomaly;

[0145] The aforementioned photolithography simulation unit 803 is specifically used for:

[0146] By using optical analysis models and photolithography parameter information, the adjusted light intensity distribution data corresponding to the adjusted three-dimensional thin film stacking model is determined.

[0147] Based on the adjusted light intensity distribution data, photolithographic simulation was performed on the adjusted three-dimensional thin film stacking model to determine the simulation size data corresponding to the adjusted three-dimensional thin film stacking model.

[0148] In one embodiment, the optical proximity correction unit 804 is specifically used for:

[0149] Based on the simulated size data and standard size data, determine the simulation error corresponding to the three-dimensional thin film stacking model;

[0150] Determine whether the simulation error is less than the preset standard error threshold, and determine whether the simulated photoresist 3D data matches the standard photoresist 3D data;

[0151] If the simulation error is determined to be less than the preset standard error threshold, or if the simulated photoresist 3D data does not match the standard photoresist 3D data, optical proximity correction is performed on the target wafer.

[0152] In one embodiment, the structural layout information includes a shallow trench isolation structure, and the optical proximity correction process includes adjusting the model structure of the three-dimensional thin film stack model.

[0153] The aforementioned optical proximity correction unit 804 is specifically used for:

[0154] Based on the simulated size data and standard size data, as well as the simulated three-dimensional data and standard three-dimensional data of photoresist, a light-shielding module is added to the photoresist layer in the three-dimensional thin film stacking model with shallow trench isolation structure.

[0155] The three-dimensional thin film stacking model and lithography parameter information after the addition of the light-shielding module are used as the optical proximity correction result for the target wafer.

[0156] In one embodiment, the structural layout information includes a polysilicon gate structure, and the optical proximity correction process further includes adjusting the lithography parameter information, which includes the mask image and lithography light source information corresponding to the target wafer.

[0157] The aforementioned optical proximity correction unit 804 is specifically used for:

[0158] Based on simulated size data and standard size data, as well as simulated photoresist 3D data and standard photoresist 3D data, mask auxiliary patterns are added to the mask image corresponding to the target wafer with a polysilicon gate structure.

[0159] The three-dimensional thin film stacking model and the adjusted lithography parameters are used as the optical proximity correction result for the target wafer. The adjusted lithography parameters include a mask image with added mask auxiliary patterns.

[0160] In one embodiment, the model building unit 801 is specifically used for:

[0161] Based on the structural layout information and the preset photolithography process data, a three-dimensional thin film stacking model corresponding to the target wafer is constructed. The photolithography process data includes at least one of the following parameters: spraying parameters, deposition parameters, chemical mechanical polishing parameters, and etching parameters.

[0162] In one embodiment, the acquisition unit 802 is specifically used for:

[0163] Determine the standard dimension data based on the design layout data corresponding to the target wafer;

[0164] Obtain 3D data of multiple sample wafers corresponding to the target wafer;

[0165] Based on the three-dimensional data of multiple sample wafers, determine the corresponding dimension scanning data of multiple sample wafers;

[0166] Based on the dimensional scanning data corresponding to multiple sample wafers, at least one standard wafer is determined from the multiple sample wafers, and the dimensional scanning data corresponding to the standard wafer matches the standard dimensional data;

[0167] Based on the three-dimensional data of at least one standard wafer, determine the three-dimensional data of the standard photoresist.

[0168] Figure 9 A schematic diagram of the hardware structure of the optical proximity correction device provided in an embodiment of this application is shown.

[0169] The optical proximity correction device may include a processor 901 and a memory 902 storing computer program instructions.

[0170] Specifically, the processor 901 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0171] Memory 902 may include mass storage for data or instructions. For example, and not limitingly, memory 902 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 902 may include removable or non-removable (or fixed) media. Where appropriate, memory 902 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 902 is non-volatile solid-state memory.

[0172] In a particular embodiment, memory 902 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0173] The processor 901 implements any of the optical proximity correction methods in the above embodiments by reading and executing computer program instructions stored in the memory 902.

[0174] In one example, the optical proximity correction device may also include a communication interface 903 and a bus 910. Wherein, as Figure 9 As shown, the processor 901, memory 902, and communication interface 903 are connected through bus 910 and complete communication with each other.

[0175] The communication interface 903 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0176] Bus 910 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 910 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0177] Furthermore, in conjunction with the optical proximity correction methods described in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the optical proximity correction methods described in the above embodiments.

[0178] This application also provides a computer program product, including a computer program that, when executed, implements any of the optical proximity correction methods described in the above embodiments.

[0179] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0180] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0181] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0182] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0183] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. An optical proximity correction method, characterized in that, include: Based on the structural layout information corresponding to the target wafer and the preset photolithography process data, a three-dimensional thin film stacking model corresponding to the target wafer is constructed. The photolithography process data includes at least one of the following parameters: spraying parameters, deposition parameters, chemical mechanical polishing parameters, and etching parameters. Obtain the standard dimension data and standard photoresist three-dimensional data corresponding to the target wafer; Based on the preset photolithography parameters, the three-dimensional thin film stacking model is simulated using photolithography to determine the simulated size data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stacking model. Based on the simulated size data and the standard size data, as well as the simulated photoresist 3D data and the standard photoresist 3D data, optical proximity correction is performed on the target wafer.

2. The method according to claim 1, characterized in that, Based on preset photolithography parameters, a photolithography simulation is performed on the three-dimensional thin film stack model to determine the simulated size data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model, including: The three-dimensional thin film stacking model and the lithography parameter information are input into a preset lithography simulation model, so that the lithography simulation model performs lithography simulation on the three-dimensional thin film stacking model based on the lithography parameter information, and determines the simulation size data and the simulation photoresist three-dimensional data.

3. The method according to claim 2, characterized in that, The lithography simulation model includes an optical analysis model and a photoresist analysis model; Based on the photolithography parameter information, a photolithography simulation is performed on the three-dimensional thin film stacking model to determine the simulated size data and the simulated photoresist three-dimensional data, including: The light intensity distribution data of the three-dimensional thin film stacking model during the photolithography simulation process are determined using the optical analysis model and the photolithography parameter information. Based on the light intensity distribution data, a photolithographic simulation is performed on the three-dimensional thin film stacking model to determine the simulated size data corresponding to the three-dimensional thin film stacking model; The three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stacking model simulated by photolithography is analyzed using the photoresist analysis model to obtain the three-dimensional data of the simulated photoresist.

4. The method according to claim 3, characterized in that, Before performing photolithographic simulation on the three-dimensional thin film stacking model based on the light intensity distribution data to determine the simulation size data corresponding to the three-dimensional thin film stacking model, the method further includes: Based on the light intensity distribution data, determine whether there are any simulation anomalies in the photolithography simulation process; If so, adjust the three-dimensional thin film stacking model according to the simulation anomaly; Based on the light intensity distribution data, photolithographic simulation is performed on the three-dimensional thin film stacking model to determine the simulated size data corresponding to the three-dimensional thin film stacking model, including: Using the optical analysis model and the lithography parameter information, the adjusted light intensity distribution data corresponding to the adjusted three-dimensional thin film stacking model is determined; Based on the adjusted light intensity distribution data, photolithographic simulation is performed on the adjusted three-dimensional thin film stacking model to determine the simulation size data corresponding to the adjusted three-dimensional thin film stacking model.

5. The method according to claim 1, characterized in that, Based on the simulated size data and the standard size data, as well as the simulated photoresist 3D data and the standard photoresist 3D data, optical proximity correction is performed on the target wafer, including: Based on the simulated size data and the standard size data, determine the simulation error corresponding to the three-dimensional thin film stacking model; Determine whether the simulation error is less than a preset standard error threshold, and determine whether the simulated photoresist three-dimensional data matches the standard photoresist three-dimensional data; If the simulation error is determined to be less than a preset standard error threshold, or if the simulated photoresist 3D data does not match the standard photoresist 3D data, optical proximity correction is performed on the target wafer.

6. The method according to claim 1, characterized in that, The structural layout information includes a shallow trench isolation structure, and the optical proximity correction process includes adjusting the model structure of the three-dimensional thin film stacking model; Based on the simulated size data and the standard size data, as well as the simulated photoresist 3D data and the standard photoresist 3D data, optical proximity correction is performed on the target wafer, including: Based on the simulated size data and the standard size data, as well as the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data, a light-shielding module is added to the photoresist layer in the three-dimensional thin film stacking model with a shallow trench isolation structure. The three-dimensional thin film stacking model after the addition of the light-shielding module and the lithography parameter information are used as the optical proximity correction result corresponding to the target wafer.

7. The method according to claim 1, characterized in that, The structural layout information includes a polysilicon gate structure, and the optical proximity correction process also includes adjusting the lithography parameter information, which includes the mask image and lithography light source information corresponding to the target wafer. Based on the simulated size data and the standard size data, as well as the simulated photoresist 3D data and the standard photoresist 3D data, optical proximity correction is performed on the target wafer, including: Based on the simulated size data and the standard size data, as well as the simulated photoresist 3D data and the standard photoresist 3D data, a mask auxiliary pattern is added to the mask image corresponding to the target wafer with the polysilicon gate structure; The three-dimensional thin film stacking model and the adjusted lithography parameter information are used as the optical proximity correction result corresponding to the target wafer. The adjusted lithography parameter information includes a mask image with added mask auxiliary patterns.

8. The method according to claim 1, characterized in that, Obtaining the standard dimension data and standard photoresist three-dimensional data corresponding to the target wafer includes: The standard dimension data are determined based on the design layout data corresponding to the target wafer; Obtain three-dimensional data of multiple sample wafers corresponding to the target wafer; Based on the three-dimensional data of the multiple sample wafers, determine the corresponding size scan data of the multiple sample wafers; Based on the dimensional scanning data corresponding to the plurality of sample wafers, at least one standard wafer is determined from the plurality of sample wafers, wherein the dimensional scanning data corresponding to the standard wafer matches the standard dimensional data; The three-dimensional data of the standard photoresist are determined based on the three-dimensional data of the at least one standard wafer.

9. An electronic device, characterized in that, The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, it implements the optical proximity correction method as described in any one of claims 1-8.

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