Layout processing method for reducing parasitic RC through cascode structure

Abstract

The invention discloses a layout processing method for reducing parasitic RC through a cascode structure, and relates to the technical field of integrated circuit design. According to the method, parasitic RC is reduced through a cascode structure, the performance of a high-frequency module of a chip is improved, MOS transistor and metal wire parameters are extracted by analyzing a layout file, a report is generated by utilizing a parasitic parameter extraction tool, a distribution map is generated through mapping to identify a high parasitic area, an optimizable MOS transistor combination is identified according to the distribution map, a cascode structure diagram is designed, and the high-frequency module performance of the chip is improved. Guiding re-layout and re-wiring of MOS (Metal Oxide Semiconductor) tubes in layout software, combining a source end and a drain end, optimizing a connection path, performing layout verification and circuit simulation, comparing parasitic parameters and working frequencies before and after optimization, and generating a simulation report; the parasitic effect can be accurately quantified, the layout is optimized, parasitic parameters are reduced, the module working frequency is effectively improved, and the design requirement of a high-performance chip is met.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit design, in particular to a layout processing method for reducing parasitic RC through a cascode structure. Background Art

[0002] With the continuous development of the electronics industry, the frequency requirements for chip design are getting higher and higher. In high-speed modules, the parasitic resistance and capacitance on the devices and traces have a particularly significant impact on module performance. These parasitic parameters will increase the load, causing the module's operating frequency to decrease, thereby affecting the overall performance of the IP module. Especially in some scenarios that are sensitive to high-frequency signals, the presence of unnecessary parasitic resistance and parasitic capacitance makes it difficult for the module to reach the required operating frequency, limiting the performance improvement of the chip. Summary of the invention

[0003] The purpose of the present invention is to provide a layout processing method for reducing parasitic RC through a cascode structure, optimize the layout design through the cascode structure, reduce parasitic resistance and parasitic capacitance, and thus improve the operating frequency of the module.

[0004] The purpose of the present invention can be achieved through the following technical solutions: The present application provides a layout processing method for reducing parasitic RC through a cascode structure, comprising the following steps: Parse the original layout file, extract the parameters of the MOS tube, and store them in the layout parameter list; Use the parasitic parameter extraction tool to input the layout parameter list, calculate the parasitic resistance and capacitance of each MOS tube and metal line segment, and then generate a parasitic parameter report; According to the parasitic parameter report, the parasitic parameter values ​​are mapped onto the layout to generate a parasitic parameter distribution map, in which high parasitic areas are marked with different colors or marks; According to the parasitic parameter distribution diagram, identify the MOS tube combination optimized by the cascode structure, determine the merging method of the source end and the drain end of the MOS tube, and generate the design diagram of the cascode structure; In the layout design software, according to the cascode structure design diagram, the MOS tubes are re-arranged and wired, and the source and drain ends of the same group of devices are merged and the connection paths are optimized; Based on the optimized connection route, layout verification and circuit simulation are performed to compare the changes in parasitic parameters before and after the application of the cascode structure.

[0005] Furthermore, the original layout file is parsed, the parameters of the MOS tube are extracted, and stored in the layout parameter list, including: Read the original layout file and obtain the graphic element information in the layout, including the parameters of MOS tubes, metal wires, and polysilicon graphic elements; According to the graphic element information of the MOS tube, the type of the MOS tube is judged, and the position coordinates of the source, drain, gate and substrate of the MOS tube are determined, and the level of the metal line is judged, and the starting and ending coordinates of the metal line, as well as the width and length parameters of the metal line are determined; According to the graphic element information of polysilicon, the type of polysilicon is judged, and the position coordinates, width and length parameters of polysilicon are determined. Then, according to the position coordinates of the source, drain, gate and substrate of the MOS tube, as well as the position coordinates of the metal wire and polysilicon, the connection relationship between the MOS tube and the metal wire and polysilicon is judged, and the connection relationship parameters are stored in the layout parameter list; According to the starting and ending point coordinates of the metal line, as well as the width and length parameters of the metal line, the routing information in the layout is extracted, and the routing information parameters are stored in the layout parameter list. The extracted MOS tube layout position, connection relationship and routing information are stored in the layout parameter list according to the preset data format.

[0006] Furthermore, the parasitic parameter extraction tool is used to input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS tube and metal line segment, and then generate a parasitic parameter report, which includes: According to the input layout parameter list, obtain the geometric parameter information of each MOS tube and metal line segment; According to the geometric parameter information, the parasitic resistance and parasitic capacitance calculation model established in advance is used to calculate the parasitic resistance and parasitic capacitance value of each MOS tube; and then the parasitic resistance and parasitic capacitance value thereof are calculated using the parasitic resistance and parasitic capacitance calculation model established in advance; The parasitic resistance value and the parasitic capacitance value of each MOS tube are associated with the corresponding layout parameter information to obtain the parasitic parameter information of each MOS tube, and then the parasitic resistance value and the parasitic capacitance value of each metal line segment are associated with the corresponding layout parameter information to obtain the parasitic parameter information of each metal line segment; According to the parasitic parameter information of each MOS tube and the parasitic parameter information of each metal line segment, a data table containing the parasitic parameters of all MOS tubes and metal line segments is generated, and a final parasitic parameter report file is generated according to the preset report template and format requirements.

[0007] Furthermore, according to the parasitic parameter report, the parasitic parameter values ​​are mapped to the layout to generate a parasitic parameter distribution map. In the distribution map, high parasitic areas are marked with different colors or marks, including: Obtain a parasitic parameter report, extract the parasitic parameter values ​​and corresponding layout position information in the report, and determine different colors or marking methods according to the size of the parasitic parameter values ​​to represent different degrees of parasitic parameters in the layout; Use layout design software to load the layout file to be analyzed, superimpose parasitic parameter values ​​at the corresponding positions according to the layout position information in the parasitic parameter report, and use data visualization tools to map the parasitic parameter values ​​to different colors or marks to generate a parasitic parameter distribution map on the layout; Determine whether the parasitic parameter value exceeds a preset threshold. If it exceeds, mark the area as a high parasitic area and highlight it; All regions on the layout are traversed, and a complete parasitic parameter distribution map is generated according to the parasitic parameter values ​​to obtain a visualization result including annotations of high parasitic regions.

[0008] Furthermore, according to the parasitic parameter distribution diagram, the MOS tube combination optimized by the cascode structure is identified, the merging method of the source end and the drain end of the MOS tube is determined, and the design diagram of the cascode structure is generated, which specifically includes: Obtain a parasitic parameter distribution diagram of the MOS tube, and group the MOS tubes using a clustering algorithm according to the parasitic parameter characteristics of the MOS tubes in the distribution diagram to obtain a combination of MOS tubes with similar parasitic parameters; By analyzing the distribution characteristics of the parasitic parameters of each MOS tube combination, it is determined whether it is suitable to use the cascode structure for optimization. If it is suitable, the MOS tube combination is marked as an optimizable combination; Then, for each optimizable MOS tube combination, determine whether to merge the source end and the drain end of the MOS tube in series or in parallel according to the position relationship and parasitic parameter distribution of the MOS tubes; According to the determined MOS tube merging method, the corresponding cascode structure design diagram is generated, and the connection relationship of the merged MOS tube is clearly marked in the design diagram, including the connection between gate, source, and drain.

[0009] Furthermore, in the layout design software, according to the cascode structure design diagram, the MOS tubes are re-layouted and wired, and the source and drain ends of the same group of devices are merged and the connection paths are optimized, including: According to the given cascode circuit structure diagram, the position, direction and connection relationship layout information of the MOS tube are obtained; whether the source and drain of the same group of MOS tubes meet the merging conditions is determined, and if so, they are merged into one node; The source and drain positions of the merged MOS tube are determined by a graphic recognition algorithm, and the layout information is updated. Based on the updated layout information, a minimum spanning tree algorithm is used to optimize the wiring scheme of the metal interconnection line. Perform design rule check on the optimized wiring scheme to determine whether it meets the process requirements. If not, return to re-wiring. Based on the routing scheme that passes the DRC check, a new layout file is generated, and the device parameters and interconnection information are updated; the new layout file is imported into the layout design software, and the MOS tubes and metal interconnects are laid out and routed to complete the optimized design of the cascode circuit.

[0010] Furthermore, after merging the source terminals and drain terminals of the same group of devices, the method further includes: determining the same group of devices that need to merge the source and drain terminals according to the preset device grouping information, and then obtaining the layout position and pin information of the same group of devices to determine the position relationship between the source port and the drain port; when the source port and the drain port are adjacent in position, directly merging the two in the layout to form a shared port structure; when the source port and the drain port are not adjacent in position, introducing an additional interconnection structure in the layout; According to the signal integrity and parasitic parameter characteristics of the merged circuit, the wiring topology of the interconnect structure is optimized; the optimized wiring topology is evaluated by parasitic parameter extraction and post-simulation verification methods to ensure that it meets the design index requirements; after layout and routing, the device unit after the source and drain are merged is extracted.

[0011] Furthermore, layout verification is performed, including: According to the optimized connection route, the preset electrical rules and physical rules are obtained, and the optimized layout is checked for rules. If the check finds that there are electrical rule errors, the circuit design is corrected according to the electrical rules to obtain a corrected circuit design scheme; When physical rule errors are found during the inspection, the physical design is corrected according to the physical rules to obtain a corrected physical design solution, and the corrected circuit design solution is integrated with the physical design solution to obtain a corrected layout design solution; According to the revised layout design scheme, the connection route is optimized again by using a simulated annealing algorithm to obtain a re-optimized connection route; According to the re-optimized connection route, the revised layout design plan is verified again to determine whether there are still electrical rule errors or physical rule errors. If the re-verification passes, the final layout design plan is determined; if the re-verification fails, the rule check and correction will continue until the verification passes.

[0012] Furthermore, the parasitic parameter changes before and after the application of the cascode structure are compared, including: Obtain the original circuit diagram of the circuit to be analyzed, determine the target module therein, and perform circuit simulation analysis on the target module; In the circuit simulation environment, build the simulation circuit diagram of the original circuit, set the circuit parameters, perform simulation, and obtain the performance index data of parasitic parameters and operating frequency when the cascode structure is not applied; The cascode structure is used to optimize the circuit design of the target module of the original circuit to obtain the optimized circuit diagram; By building an optimized circuit simulation diagram, setting the same circuit parameters as the original circuit, and performing simulation, the performance index data of parasitic parameters and operating frequency after applying the cascode structure are obtained; Then, the changes of parasitic parameters before and after the application of the cascode structure are compared and analyzed, and the influence of the cascode structure on the parasitic parameters is intuitively displayed through data curves and values; the changes of operating frequency before and after the application of the cascode structure are compared and analyzed, and the influence of the cascode structure on the operating frequency is intuitively displayed through data curves and values; Based on the comparative analysis results of parasitic parameters and operating frequency, the overall impact of the cascode structure on the performance of the circuit module is determined, and a complete circuit simulation analysis report is generated.

[0013] It also includes: According to the simulation report, when it is found that the parasitic RC reduction effect cannot meet the expected performance requirements, the design and layout of the cascode structure are iteratively optimized until the performance requirements are met.

[0014] The beneficial effects of the present invention are: By parsing the original layout file and using the parasitic parameter extraction tool, this method can accurately extract the parameters of the MOS tube and metal line segment and generate a detailed parasitic parameter report, solving the problem of difficulty in accurately identifying and quantifying parasitic effects in complex layouts, enabling designers to intuitively identify high parasitic areas and providing accurate data support for subsequent optimization; by reading the layout file, extracting graphic element information, calculating parasitic parameters and generating a distribution map, the parasitic resistance and parasitic capacitance values ​​of each MOS tube and metal line segment can be clearly seen, thereby locating the area with the greatest impact on module performance; Based on the parasitic parameter distribution diagram, the layout design is optimized through the cascode structure, which significantly reduces the parasitic resistance and parasitic capacitance. Then, by identifying the MOS tube combination suitable for optimization, determining the merging method of the source end and the drain end, and generating the cascode structure design diagram, designers can accurately re-layout and route in the layout design software, solving the problem of difficult-to-control parasitic effects in traditional layout design. By merging the source end and the drain end of the same group of devices, the use of metal wires is reduced and the connection path is optimized, thereby effectively reducing the parasitic effects and improving the operating frequency and overall performance of the module. Through layout verification and circuit simulation, this method ensures that the optimized layout design not only complies with electrical and physical rules, but also actually improves the performance of the module. By comparing the changes in parasitic parameters and operating frequency before and after the application of the cascode structure, a detailed simulation report is generated, and designers can intuitively evaluate the optimization effect. When it is found that the parasitic RC reduction effect cannot meet the expected performance requirements, iterative optimization can be performed until the performance requirements are met; the problem of uncertain effects after optimized design is solved. Through repeated verification and correction, it is ensured that the final layout design solution achieves the expected performance goals, providing reliable guarantees for high-performance chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0016] Figure 1 A schematic diagram of a flow chart of a layout processing method for reducing parasitic RC through a cascode structure provided in the present application; Figure 2 A schematic diagram of a flow chart of extracting parameters of MOS tubes by a layout processing method for reducing parasitic RC through a cascode structure provided in the present application; Figure 3 A schematic flow chart of a parasitic parameter report generated by a layout processing method for reducing parasitic RC through a cascode structure provided in the present application. DETAILED DESCRIPTION

[0017] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0018] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0019] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0020] See also Figure 1-Figure 3 This embodiment provides a layout processing method for reducing parasitic RC through a cascode structure, comprising the following steps: S1. Analyze the original layout file, extract the layout position, connection relationship, routing information and other parameters of the MOS tube, and store them in the layout parameter list; Furthermore, the original layout file is parsed to extract the layout position, connection relationship, routing information and other parameters of the MOS tube and store them in the layout parameter list, including: S11. Read the original layout file to obtain the graphic element information in the layout, including the position coordinates, shape and size parameters of graphic elements such as MOS tubes, metal wires, and polysilicon.

[0021] S12, judging the type of the MOS tube (NMOS or PMOS) according to the graphic element information of the MOS tube, determining the position coordinates of the source, drain, gate and substrate of the MOS tube, judging the level of the metal line (Metal1, Metal2, etc.), and determining the starting point and end point coordinates of the metal line, as well as parameters such as the width and length of the metal line; S13, judging the type of polysilicon (N-type polysilicon or P-type polysilicon) according to the graphic element information of polysilicon, and determining the position coordinates, width, length and other parameters of the polysilicon, and then judging the connection relationship between the MOS tube and the metal wire and polysilicon according to the position coordinates of the source, drain, gate and substrate of the MOS tube, and the position coordinates of the metal wire and polysilicon, and storing the connection relationship parameters in the layout parameter list; S14. According to the starting point and end point coordinates of the metal line, as well as parameters such as the width and length of the metal line, the routing information in the layout is extracted, and the routing information parameters are stored in a layout parameter list. The extracted parameters such as the MOS tube layout position, connection relationship and routing information are stored in the layout parameter list according to a preset data format for subsequent layout analysis and optimization.

[0022] Specifically, by analyzing the original layout file in detail, extracting and storing the parameters of MOS tubes, metal wires and polysilicon and the connection relationships between them, an accurate data basis is provided for subsequent layout analysis and optimization, solving the problem of unclear component position, type and connection information during layout optimization, enabling designers to accurately identify and locate areas with higher parasitic parameters, thereby performing targeted optimization to reduce parasitic effects and improve the operating frequency and overall performance of the module.

[0023] S2. Use the parasitic parameter extraction tool to input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS tube and metal line segment, and then generate a parasitic parameter report, including the parasitic resistance and parasitic capacitance values ​​of each MOS tube and metal line segment; Among them, according to the parasitic parameter report, use layout design software or data visualization tools to map the parasitic parameter values ​​to the layout and generate a parasitic parameter distribution map. In the distribution map, the high parasitic areas are marked with different colors or marks to intuitively identify the key areas that need to be optimized. This step helps us determine the areas that have the greatest impact on the module operating frequency, thereby identifying the key areas that need to be optimized.

[0024] Furthermore, the parasitic parameter extraction tool is used to input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS tube and metal line segment, and then generate a parasitic parameter report, which includes: S21. According to the input layout parameter list, obtain the geometric parameter information of each MOS tube and metal line segment, including length, width, thickness, etc.; S22, according to its geometric parameter information, using a pre-established parasitic resistance and parasitic capacitance calculation model to calculate the parasitic resistance value and parasitic capacitance value of each MOS tube; and then using a pre-established parasitic resistance and parasitic capacitance calculation model to calculate the parasitic resistance value and parasitic capacitance value; S23, associating the parasitic resistance value and the parasitic capacitance value of each MOS tube with the corresponding layout parameter information to obtain the parasitic parameter information of each MOS tube, and then associating the parasitic resistance value and the parasitic capacitance value of each metal line segment with the corresponding layout parameter information to obtain the parasitic parameter information of each metal line segment; S24. Generate a data table containing parasitic parameters of all MOS tubes and metal segments according to the parasitic parameter information of each MOS tube and the parasitic parameter information of each metal segment, and generate a final parasitic parameter report file according to a preset report template and format requirements.

[0025] Specifically, by accurately calculating and visualizing parasitic parameters, this method enables designers to intuitively identify and locate high parasitic areas in the layout, thereby performing targeted optimization, effectively reducing parasitic effects, and significantly improving the operating frequency and performance of the module.

[0026] Furthermore, according to the parasitic parameter report, the parasitic parameter values ​​are mapped to the layout using layout design software or data visualization tools to generate a parasitic parameter distribution map. In the distribution map, high parasitic areas are marked with different colors or marks, including: Obtain a parasitic parameter report, extract the parasitic parameter values ​​and corresponding layout position information in the report, and determine different colors or marking methods according to the size of the parasitic parameter values ​​to represent different degrees of parasitic parameters in the layout; Use layout design software to load the layout file to be analyzed, superimpose parasitic parameter values ​​at the corresponding positions according to the layout position information in the parasitic parameter report, and use data visualization tools to map the parasitic parameter values ​​to different colors or marks to generate a parasitic parameter distribution map on the layout; Determine whether the parasitic parameter value exceeds a preset threshold. If so, mark the area as a high parasitic area and highlight it; All regions on the layout are traversed, and a complete parasitic parameter distribution map is generated according to the parasitic parameter values ​​to obtain a visualization result including annotations of high parasitic regions.

[0027] Specifically, by mapping the parasitic parameter values ​​to the layout and generating a parasitic parameter distribution map, the parasitic parameters in the layout are intuitively visualized, solving the problem of difficulty in intuitively identifying and locating high parasitic areas in complex layouts, allowing designers to quickly and accurately identify the areas that have the greatest impact on module performance. By highlighting with different colors or markers, designers can make targeted optimizations, thereby effectively reducing parasitic effects, improving the operating frequency and overall performance of the module, and ensuring that the chip design meets high performance requirements.

[0028] S3. According to the parasitic parameter distribution diagram, identify the MOS tube combination optimized by the cascode structure, design an algorithm to determine the merging method of the source end and the drain end of the MOS tube, generate a design diagram of the cascode structure, and clearly mark the connection relationship of the merged MOS tube. This step is the core of achieving parasitic parameter reduction. Through a reasonable cascode structure design diagram, the parasitic effect can be significantly reduced; Furthermore, according to the parasitic parameter distribution diagram, the MOS tube combination optimized by the cascode structure is identified, and an algorithm is designed to determine the merging method of the source end and the drain end of the MOS tube, and a design diagram of the cascode structure is generated, and the connection relationship of the merged MOS tube is clearly marked, including: Obtain a parasitic parameter distribution diagram of the MOS tube, and group the MOS tubes using a clustering algorithm according to the parasitic parameter characteristics of the MOS tubes in the distribution diagram to obtain a combination of MOS tubes with similar parasitic parameters; By analyzing the distribution characteristics of the parasitic parameters of each MOS tube combination, it is determined whether it is suitable to use the cascode structure for optimization. If it is suitable, the MOS tube combination is marked as an optimizable combination; Then, for each optimizable MOS tube combination, determine whether to merge the source end and the drain end of the MOS tube in series or in parallel according to the position relationship and parasitic parameter distribution of the MOS tubes; According to the determined MOS tube merging method, the corresponding cascode structure design diagram is generated, and the connection relationship of the merged MOS tube is clearly marked in the design diagram, including the connection between gate, source, and drain.

[0029] Specifically, by analyzing the parasitic parameter distribution diagram and using the clustering algorithm to identify the MOS tube combination with similar parasitic parameters, it is determined whether it is suitable for cascode structure optimization. For suitable combinations, the merging method of the source end and the drain end of the MOS tube is determined, and a detailed cascode structure design diagram is generated, which solves the problem of how to accurately select from a large number of MOS tubes that can be optimized through specific structures to reduce parasitic effects, achieving the effect of significantly reducing parasitic parameters and improving module performance. It is a key method to achieve the core step of reducing parasitic parameters.

[0030] S4. In the layout design software, according to the cascode structure design drawing, the MOS tube is re-layouted and wired, the source end and the drain end between the same group of devices are merged to reduce the use of metal wires. At the same time, the merged connection path is optimized to ensure the efficiency and reliability of signal transmission. This step converts the design drawing into an actual layout to prepare for subsequent optimization and verification.

[0031] Furthermore, in the layout design software, according to the cascode structure design drawing, the MOS tubes are re-arranged and wired, and the source and drain ends of the same group of devices are merged to reduce the use of metal wires, including: According to the given cascode circuit structure diagram, the layout information such as the position, direction and connection relationship of the MOS tube is obtained; the source and drain of the MOS tubes in the same group are judged whether they meet the merging conditions, and if so, they are merged into one node; The source and drain positions of the merged MOS tube are determined through the graphic recognition algorithm, and the layout information is updated. Based on the updated layout information, the minimum spanning tree algorithm is used to optimize the wiring scheme of the metal interconnection line to reduce the line length and crossing; Perform design rule checking (DRC) on the optimized wiring scheme to determine whether it meets the process requirements. If not, return to re-wiring; Based on the routing scheme that passes the DRC check, a new layout file is generated, and the device parameters and interconnection information are updated; the new layout file is imported into the layout design software, and the MOS tubes and metal interconnects are laid out and routed to complete the optimized design of the cascode circuit.

[0032] Specifically, by accurately re-layouting and routing the MOS tubes according to the cascode structure design diagram in the layout design software, the pattern recognition algorithm and the minimum spanning tree algorithm are used to solve the parasitic parameter problem caused by too many metal wires in the traditional layout; specifically, the use of metal wires is reduced by merging the source and drain ends between the same group of devices, and the connection path is optimized to reduce the delay and distortion of signal transmission. This process not only reduces parasitic effects, but also ensures the efficiency and reliability of signal transmission, and finally transforms the theoretical design into a practical layout, effectively improving the performance and stability of the circuit.

[0033] Furthermore, after merging the source end and the drain end between the devices in the same group, the method further includes: optimizing the merged connection path; According to the preset device grouping information, the devices in the same group that need to merge the source and drain are determined, and then the layout position and pin information of the devices in the same group are obtained to determine the position relationship between the source port and the drain port; when the source port and the drain port are adjacent, the two are directly merged in the layout to form a common port structure; when the source port and the drain port are not adjacent, an additional interconnection structure is introduced in the layout to realize the electrical connection between the two; According to the signal integrity and parasitic parameter characteristics of the merged circuit, the wiring topology of the interconnect structure is optimized; the optimized wiring topology is evaluated by parasitic parameter extraction and post-simulation verification to ensure that it meets the design index requirements; after layout and routing, the device unit after merging the source and drain is extracted for subsequent chip-level integrated design.

[0034] Specifically, by optimizing the connection path after merging, this method effectively solves the impact of the source and drain position relationship on circuit performance. When the port positions are adjacent, they are directly merged to form a common port structure, which simplifies the layout and reduces parasitic effects; when the port positions are not adjacent, additional interconnect structures are introduced to ensure the integrity of the electrical connection. Furthermore, by optimizing the wiring topology of the interconnect structure and using parasitic parameter extraction and post-simulation verification, it is ensured that the optimized wiring topology meets the design index requirements, thereby improving signal integrity and circuit performance.

[0035] S5. Perform layout verification based on the optimized connection route to check whether there are electrical rule errors or physical rule errors. Through circuit simulation, compare the changes in parasitic parameters before and after the application of the cascode structure, as well as the impact on performance indicators such as the module operating frequency; and generate a simulation report, including key indicators such as the percentage of parasitic parameter reduction and the increase in module operating frequency. This step is an important part of verifying the optimization effect and ensuring that our design has achieved the expected performance improvement.

[0036] Furthermore, according to the optimized connection route, the layout verification is performed to check whether there are any electrical rule errors or physical rule errors, including: According to the optimized connection route, the preset electrical rules and physical rules are obtained, and the optimized layout is checked for rules. If the check finds that there are electrical rule errors, the circuit design is corrected according to the electrical rules to obtain a corrected circuit design scheme; When physical rule errors are found during the inspection, the physical design is corrected according to the physical rules to obtain a corrected physical design solution, and the corrected circuit design solution is integrated with the physical design solution to obtain a corrected layout design solution; According to the revised layout design scheme, the connection route is optimized again by using a simulated annealing algorithm to obtain a re-optimized connection route; According to the re-optimized connection route, the revised layout design plan is verified again to determine whether there are still electrical rule errors or physical rule errors. If the re-verification passes, the final layout design plan is determined; if the re-verification fails, the rule check and correction will continue until the verification passes.

[0037] Specifically, through layout verification and circuit simulation, it is ensured that the optimized connection route not only complies with electrical and physical rules, but also actually improves the performance of the module; potential design errors are effectively identified and corrected, and the connection route is further optimized through the simulated annealing algorithm. Finally, a layout design scheme is determined that has no rule errors and meets the performance improvement requirements, thereby ensuring the reliability and efficiency of the chip design.

[0038] Furthermore, through circuit simulation, the changes in parasitic parameters before and after the application of the cascode structure are compared, as well as the impact on performance indicators such as the module operating frequency; and a simulation report is generated, including: Obtain the original circuit diagram of the circuit to be analyzed, determine the target module therein, and perform circuit simulation analysis on the target module; In the circuit simulation environment, build the simulation circuit diagram of the original circuit, set the circuit parameters, perform simulation, and obtain the performance index data such as parasitic parameters and operating frequency when the cascode structure is not applied; The cascode structure is used to optimize the circuit design of the target module of the original circuit to obtain the optimized circuit diagram; By building an optimized circuit simulation diagram, setting the same circuit parameters as the original circuit, and performing simulation, we can obtain the performance index data such as parasitic parameters and operating frequency after applying the cascode structure. Then, the changes of parasitic parameters before and after the application of the cascode structure are compared and analyzed, and the influence of the cascode structure on the parasitic parameters is intuitively displayed through data curves and values; the changes of operating frequency before and after the application of the cascode structure are compared and analyzed, and the influence of the cascode structure on the operating frequency is intuitively displayed through data curves and values; Based on the comparative analysis results of parasitic parameters and operating frequency, the overall impact of the cascode structure on the performance of the circuit module is determined, and a complete circuit simulation analysis report is generated.

[0039] Specifically, by comparing the circuit simulation results before and after the application of the cascode structure, this method intuitively demonstrates the changes in parasitic parameters and operating frequencies, thereby quantitatively evaluating the effect of the cascode structure on circuit performance improvement. The generated simulation report provides a strong basis for design decisions, ensuring the effectiveness and reliability of the optimized design, so that the circuit module can significantly increase the operating frequency while reducing parasitic effects, meeting the requirements of high-performance chip design.

[0040] S6. According to the simulation report, if it is found that the parasitic RC reduction effect cannot meet the expected performance requirements, the design and layout of the cascode structure are iteratively optimized until the performance requirements are met. This step ensures that our optimization process is continuous and effective until the best performance is achieved.

[0041] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A layout processing method for reducing parasitic RC through a cascode structure, characterized in that: The steps include: Parse the original layout file, extract the parameters of the MOS tube, and store them in the layout parameter list; Use the parasitic parameter extraction tool to input the layout parameter list, calculate the parasitic resistance and capacitance of each MOS tube and metal line segment, and then generate a parasitic parameter report; According to the parasitic parameter report, the parasitic parameter values ​​are mapped onto the layout to generate a parasitic parameter distribution map, in which high parasitic areas are marked with different colors or marks; According to the parasitic parameter distribution diagram, identify the MOS tube combination optimized by the cascode structure, determine the merging method of the source end and the drain end of the MOS tube, and generate the design diagram of the cascode structure; In the layout design software, according to the cascode structure design diagram, the MOS tubes are re-arranged and wired, and the source and drain ends of the same group of devices are merged and the connection paths are optimized; Based on the optimized connection route, layout verification and circuit simulation are performed to compare the changes in parasitic parameters before and after the application of the cascode structure.

2. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 1, characterized in that: Parse the original layout file, extract the parameters of the MOS tube, and store them in the layout parameter list, including: Read the original layout file and obtain the graphic element information in the layout, including the parameters of MOS tubes, metal wires, and polysilicon graphic elements; According to the graphic element information of the MOS tube, the type of the MOS tube is judged, and the position coordinates of the source, drain, gate and substrate of the MOS tube are determined, and the level of the metal line is judged, and the starting and ending coordinates of the metal line, as well as the width and length parameters of the metal line are determined; According to the graphic element information of polysilicon, the type of polysilicon is judged, and the position coordinates, width and length parameters of polysilicon are determined. Then, according to the position coordinates of the source, drain, gate and substrate of the MOS tube, as well as the position coordinates of the metal wire and polysilicon, the connection relationship between the MOS tube and the metal wire and polysilicon is judged, and the connection relationship parameters are stored in the layout parameter list; According to the starting and ending point coordinates of the metal line, as well as the width and length parameters of the metal line, the routing information in the layout is extracted, and the routing information parameters are stored in the layout parameter list. The extracted MOS tube layout position, connection relationship and routing information are stored in the layout parameter list according to the preset data format.

3. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 1, characterized in that: Use the parasitic parameter extraction tool to input the layout parameter list, calculate the parasitic resistance and capacitance of each MOS tube and metal line segment, and then generate a parasitic parameter report, including: According to the input layout parameter list, obtain the geometric parameter information of each MOS tube and metal line segment; According to the geometric parameter information, the parasitic resistance and parasitic capacitance calculation model established in advance is used to calculate the parasitic resistance and parasitic capacitance value of each MOS tube; and then the parasitic resistance and parasitic capacitance value thereof are calculated using the parasitic resistance and parasitic capacitance calculation model established in advance; The parasitic resistance value and the parasitic capacitance value of each MOS tube are associated with the corresponding layout parameter information to obtain the parasitic parameter information of each MOS tube, and then the parasitic resistance value and the parasitic capacitance value of each metal line segment are associated with the corresponding layout parameter information to obtain the parasitic parameter information of each metal line segment; According to the parasitic parameter information of each MOS tube and the parasitic parameter information of each metal line segment, a data table containing the parasitic parameters of all MOS tubes and metal line segments is generated, and a final parasitic parameter report file is generated according to the preset report template and format requirements.

4. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 1, characterized in that: According to the parasitic parameter report, the parasitic parameter values ​​are mapped to the layout to generate a parasitic parameter distribution map. In the distribution map, high parasitic areas are marked with different colors or marks, including: Obtain a parasitic parameter report, extract the parasitic parameter values ​​and corresponding layout position information in the report, and determine different colors or marking methods according to the size of the parasitic parameter values ​​to represent different degrees of parasitic parameters in the layout; Use layout design software to load the layout file to be analyzed, superimpose parasitic parameter values ​​at the corresponding positions according to the layout position information in the parasitic parameter report, and use data visualization tools to map the parasitic parameter values ​​to different colors or marks to generate a parasitic parameter distribution map on the layout; Determine whether the parasitic parameter value exceeds a preset threshold. If it exceeds, mark the area as a high parasitic area and highlight it; All regions on the layout are traversed, and a complete parasitic parameter distribution map is generated according to the parasitic parameter values ​​to obtain a visualization result including annotations of high parasitic regions.

5. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 1, characterized in that: According to the parasitic parameter distribution diagram, identify the MOS tube combination optimized by the cascode structure, determine the merging method of the source end and the drain end of the MOS tube, and generate the design diagram of the cascode structure, including: Obtain a parasitic parameter distribution diagram of the MOS tube, and group the MOS tubes using a clustering algorithm according to the parasitic parameter characteristics of the MOS tubes in the distribution diagram to obtain a combination of MOS tubes with similar parasitic parameters; By analyzing the distribution characteristics of the parasitic parameters of each MOS tube combination, it is determined whether it is suitable to use the cascode structure for optimization. If it is suitable, the MOS tube combination is marked as an optimizable combination; Then, for each optimizable MOS tube combination, determine whether to merge the source end and the drain end of the MOS tube in series or in parallel according to the position relationship and parasitic parameter distribution of the MOS tubes; According to the determined MOS tube merging method, the corresponding cascode structure design diagram is generated, and the connection relationship of the merged MOS tube is clearly marked in the design diagram, including the connection between gate, source, and drain.

6. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 1, characterized in that: In the layout design software, according to the cascode structure design diagram, the MOS tubes are re-layouted and wired, and the source and drain ends of the same group of devices are merged and the connection paths are optimized, including: According to the given cascode circuit structure diagram, the position, direction and connection relationship layout information of the MOS tube are obtained; whether the source and drain of the same group of MOS tubes meet the merging conditions is determined, and if so, they are merged into one node; The source and drain positions of the merged MOS tube are determined by a graphic recognition algorithm, and the layout information is updated. Based on the updated layout information, a minimum spanning tree algorithm is used to optimize the wiring scheme of the metal interconnection line. Perform design rule check on the optimized wiring scheme to determine whether it meets the process requirements. If not, return to re-wiring. Based on the routing scheme that passes the DRC check, a new layout file is generated, and the device parameters and interconnection information are updated; the new layout file is imported into the layout design software, and the MOS tubes and metal interconnects are laid out and routed to complete the optimized design of the cascode circuit.

7. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 6, characterized in that: After merging the source and drain ends of the devices in the same group, the method further includes: determining the devices in the same group that need to merge the source and drain according to the preset device grouping information, and then obtaining the layout position and pin information of the devices in the same group to determine the position relationship between the source port and the drain port; when the source port and the drain port are adjacent in position, directly merging the two in the layout to form a shared port structure; when the source port and the drain port are not adjacent in position, introducing an additional interconnection structure in the layout; According to the signal integrity and parasitic parameter characteristics of the merged circuit, the wiring topology of the interconnect structure is optimized; the optimized wiring topology is evaluated by parasitic parameter extraction and post-simulation verification methods to ensure that it meets the design index requirements; after layout and routing, the device unit after the source and drain are merged is extracted.

8. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 1, characterized in that: Perform layout verification, including: According to the optimized connection route, the preset electrical rules and physical rules are obtained, and the optimized layout is checked for rules. If the check finds that there are electrical rule errors, the circuit design is corrected according to the electrical rules to obtain a corrected circuit design scheme; When physical rule errors are found during the inspection, the physical design is corrected according to the physical rules to obtain a corrected physical design solution, and the corrected circuit design solution is integrated with the physical design solution to obtain a corrected layout design solution; According to the revised layout design scheme, the connection route is optimized again by using a simulated annealing algorithm to obtain a re-optimized connection route; According to the re-optimized connection route, the revised layout design plan is verified again to determine whether there are still electrical rule errors or physical rule errors. If the re-verification passes, the final layout design plan is determined; if the re-verification fails, the rule check and correction will continue until the verification passes.

9. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 1, characterized in that: Compare the changes in parasitic parameters before and after the application of the cascode structure, including: Obtain the original circuit diagram of the circuit to be analyzed, determine the target module therein, and perform circuit simulation analysis on the target module; In the circuit simulation environment, build the simulation circuit diagram of the original circuit, set the circuit parameters, perform simulation, and obtain the performance index data of parasitic parameters and operating frequency when the cascode structure is not applied; The cascode structure is used to optimize the circuit design of the target module of the original circuit to obtain the optimized circuit diagram; By building an optimized circuit simulation diagram, setting the same circuit parameters as the original circuit, and performing simulation, the performance index data of parasitic parameters and operating frequency after applying the cascode structure are obtained; Then, the changes of parasitic parameters before and after the application of the cascode structure are compared and analyzed, and the influence of the cascode structure on the parasitic parameters is intuitively displayed through data curves and values; the changes of operating frequency before and after the application of the cascode structure are compared and analyzed, and the influence of the cascode structure on the operating frequency is intuitively displayed through data curves and values; Based on the comparative analysis results of parasitic parameters and operating frequency, the overall impact of the cascode structure on the performance of the circuit module is determined, and a complete circuit simulation analysis report is generated.

10. The layout processing method for reducing parasitic RC by using a cascode structure according to claim 1, characterized in that: Also includes: According to the simulation report, when it is found that the parasitic RC reduction effect cannot meet the expected performance requirements, the design and layout of the cascode structure are iteratively optimized until the performance requirements are met.

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