Packaging method and structure of embedded glass substrate chip

Abstract

The invention relates to the technical field of chip packaging, in particular to a packaging method and structure of an embedded glass substrate chip. Comprising the following steps: S1, obtaining a glass core plate; s2, grooving is carried out, and a chip is fixed in a groove; s3, laminating a resin material layer; s4, forming a first copper plating layer; s5, forming an inner layer circuit; s6, a resin material layer is laminated, and the other glass core plate is bonded; s7, sputtering a second copper plating layer; s8, forming an outer layer circuit; s9, a resin material layer is laminated; s10, TGV punching is carried out, and the bottom of the through hole falls on a bonding pad of the chip, and S11, a seed layer is formed in the through hole, chemical copper plating is carried out, a copper surface layer is formed, and the copper surface layer is electrically communicated with the chip, the inner layer circuit and the outer layer circuit. Compared with the prior art, the rigidity and the hardness of glass are utilized, so that the glass substrate is embedded in the glass, the overall three-dimensional height of the chip structure is reduced to thin the chip, one or more layers of chips can be embedded in the glass substrate, and the height of the whole glass substrate chip is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, in particular to a packaging method and structure of an embedded glass substrate chip. Background Art

[0002] Since the 1970s, the chip substrate material has evolved from the lead frame at the beginning to the ceramic substrate replacing the lead frame in the 1990s. Now the most common is the organic material substrate. However, the organic material substrate will have warping and flatness problems during the production process, which will affect the packaging performance. At the same time, due to the limited space of the substrate, the number of dies is also limited.

[0003] Since September 2023, Intel's pioneering efforts in supporting GCS have laid the foundation for adoption across the industry, and announced that it will launch products after 2025 to promote the development of Moore's Law. Glass substrates have advantages over organic substrates: (1) Ultra-low flatness. It can improve the focal depth of lithography and good dimensional stability of interconnects; (2) Good thermal and mechanical stability. It can withstand higher temperatures and is more resilient in data center applications; (3) It can achieve higher interconnect density; (4) It can reduce pattern deformation by 50%.

[0004] Glass substrate packaging technology improves CoWoS-S technology. TSMC's 2.5D packaging technology CoWoS-S connects the chip to the silicon adapter and then connects the stacked chip to the substrate, thereby realizing a three-dimensional packaging structure of chip-adapter-substrate. Glass substrate packaging technology has made improvements to it: (1) Substrate material: from FC-BGA substrate to glass core substrate; (2) Interposer: from silicon to glass substrate; (3) Key technology: from through silicon via TSV to through glass via TGV.

[0005] The current glass substrate basically adopts a symmetrical design to laminate ABF materials on both sides for building-up stacking. The disadvantage of this process is that it is difficult to make asymmetrical glass substrates. Secondly, the current glass substrate development is to replace FCBGA organic substrates, but the normal thickness of the glass substrate is slightly thicker than the organic substrate. After the current glass substrate is made, it will be used for chip packaging and chip bump connection, which will increase the thickness of the chip stack (chip + glass substrate thickness). Finally, the current glass substrate chip is mainly used for chip bumping process. The chip is bumped and connected on the glass substrate. The chip is exposed outside the substrate, which will easily increase the risk of abnormal failure of the chip during the packaging process. Summary of the invention

[0006] The present invention overcomes the deficiencies of the prior art and provides a packaging method and structure for an embedded glass substrate chip.

[0007] To achieve the above object, a packaging method for an embedded glass substrate chip is designed, comprising the following steps: S1, pre-treating the glass and thinning it to obtain a glass core board; S2, using a laser drilling process to make grooves on one side of the glass core board and fix the chip in the grooves; S3, after the chip is fixed, a layer of resin material is pressed on the surface of the chip and one side of the glass core board; S4, copper is plated on one surface of the resin material layer to form a first copper plated layer; S5, forming an inner layer circuit on the first copper plating layer; S6, laminating a layer of resin material on the surface of the inner layer circuit to wrap the inner layer circuit, and coating a layer of adhesive layer on the insulating layer of the inner layer circuit to bond another glass core board; S7, sputtering a second copper plating layer on one side surface of another glass core board; S8, forming an outer layer circuit on the second copper plating layer; S9, laminating a layer of resin material on the surface of the outer circuit layer; S10, TGV drilling is performed on the glass core board, and the bottom of the through hole falls on the pad of the chip. S11, forming a seed layer in the through hole, and performing chemical copper plating to form a copper surface layer, and the copper surface layer is electrically connected to the chip, the inner layer circuit, and the outer layer circuit.

[0008] The following steps are also included: S12, forming a photopolymerization protective layer on one surface of the glass chip; S13, irradiating the photopolymerization protective layer with ultraviolet light and developing it to form an opening, exposing the copper surface layer on the surface, and forming an anti-oxidation layer on the outer side of the copper surface layer; S14, planting balls on the copper surface layer; S15, a shielding layer is sputtered on the outside of the package body, the material of the shielding layer is a Ti layer or a stainless steel layer or a metal layer that can shield the signal, and the thickness is 30~100um. When used specifically, the shielding layer is an EMI plating layer, which is formed by a sputtering process.

[0009] The specific method of step S2 is as follows: S21, cleaning the bottom of the groove; S22, coating a layer of adhesive on the inner wall of the groove; S23, fixing the chip in the groove by bonding with a DAF film; in step S21, the groove is cleaned by high-cleaning acid or plasma cleaning.

[0010] The high-cleaning acid is an AC organic acid formed by mixing sulfuric acid or formic acid with acetic acid, and the concentration is 5%.

[0011] In the step S3, the resin material is selected from one of ABF material, PP material and PI material.

[0012] In the step S4, a thin copper layer is first plated on the surface of the resin material layer, and then thick electroplating is performed on the copper surface to form a first copper-plated layer, and the thickness of the first copper-plated layer is 20-30 um.

[0013] In the step S10, the inner wall of the through hole (8) is treated by a composite additive, wherein the composite additive is a mixture of leveling agents S1, S2, and S3, wherein the leveling agent S1 is (CH) n N m OH, mass fraction is 10%~15%; leveling agent S2 is H x (SO3) y (CH2) z 2. The mass fraction is 20%~40%; the leveling agent S3 is N x (CH3) y (CH2) z , mass fraction 30%~50%, the balance is water.

[0014] In the step S14, a hollow fixture is installed at the bottom of the chip (2) during ball implantation, and a nitrogen reflow chamber is used.

[0015] To achieve the above-mentioned purpose, a structure of an embedded glass substrate chip is designed, including a glass core board, a groove is provided on one side of the glass core board, and the chip is fixed in the groove by adhesive glue and DAF film. A resin material layer is provided on the surface of the chip and one side of the glass core board, and a first copper-plated layer, a resin material layer, another glass core board, a second copper-plated layer, and a resin material layer are sequentially provided on the outer side of the resin material layer. A through hole is provided on the outermost resin material layer, and the through hole penetrates the resin material layer, the second copper-plated layer, another glass core board, the resin material layer, the first copper-plated layer, and the resin material layer. The bottom of the hole falls on the chip pad, and the through hole is provided with a copper surface layer. The copper surface layer electrically connects the chip, the circuit on the first copper-plated layer, and the circuit on the second copper-plated layer to form a package.

[0016] The outermost copper surface layer is provided with a photopolymerization protective layer and is connected to solder balls, and a shielding layer is provided on the outside of the package body.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. Utilize the rigidity and hardness of glass to embed the glass substrate into it, reduce the overall three-dimensional height of the chip structure to thin the chip. It can be achieved that one or more layers of chips are embedded in the glass substrate to reduce the height of the overall glass substrate chip.

[0018] 2. TGV drilling technology is used to open through holes in the glass, and connect the chip pad and the glass substrate layer to achieve electrical interconnection. A multi-additive composite system is used to treat the surface inside the through hole in order to complete the filling and plating of through holes with a depth-to-diameter ratio of 20:1 or above.

[0019] 3. Utilize glass substrate lamination technology and use adhesive coating to bond glass to achieve multi-layer glass substrate production, which increases the strength of the substrate while also increasing the wiring density of the circuit.

[0020] 4. Taking advantage of the hardness of the underlying glass, the chip is embedded inside the glass to protect the chip, and at the same time the use of MD resin material is reduced to achieve the thickness of the chip.

[0021] 5. Using EMI technology to sputter a metal layer on the surface of the bottom glass can enhance the bottom hardness and shield interference signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of step S1 of the present invention.

[0023] Figure 2 It is a schematic diagram of step S2 of the present invention.

[0024] Figure 3 It is a schematic diagram of step S3 of the present invention.

[0025] Figure 4 It is a schematic diagram of step S4 of the present invention.

[0026] Figure 5 It is a schematic diagram of step S5 of the present invention.

[0027] Figure 6 It is a schematic diagram of step S6 of the present invention.

[0028] Figure 7 It is a schematic diagram of step S7 of the present invention.

[0029] Figure 8 It is a schematic diagram of step S8 of the present invention.

[0030] Fig. 9 It is a schematic diagram of step S9 of the present invention.

[0031] Fig.10 It is a schematic diagram of step S10 of the present invention.

[0032] Fig.11 It is a schematic diagram of step S11 of the present invention.

[0033] Fig.12 It is a schematic diagram of step S12 of the present invention.

[0034] Fig.13 It is a schematic diagram of step S13 of the present invention.

[0035] Fig.14 It is a schematic diagram of step S14 of the present invention.

[0036] Fig.15 It is a schematic diagram of step S15 of the present invention.

[0037] Fig.16 It is a structural schematic diagram of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be further described below with reference to the accompanying drawings.

[0039] like Figures 1 to 15 As shown, the packaging method of the embedded glass substrate chip in this embodiment includes the following steps: S1, pre-treating the glass and thinning it to obtain a glass core board 1; S2, a groove is made on one side of the glass core board 1 through a laser drilling process, and the chip 2 is fixed in the groove; S3, after the chip 2 is fixed, a layer of resin material layer 5 is pressed on the chip 2 and one side surface of the glass core board 1; S4, copper is plated on one side of the resin material layer 5 to form a first copper plated layer 6; S5, forming an inner layer circuit on the first copper plating layer 6; S6, laminating a layer of resin material 5 on the surface of the inner layer circuit to wrap the inner layer circuit, and coating a layer of adhesive layer on the insulating layer of the inner layer circuit to bond another glass core board 1; S7, sputtering a second copper plating layer 7 on one side surface of another glass core board 1; S8, forming an outer layer circuit on the second copper plating layer 7; S9, laminating a layer of resin material 5 on the surface of the outer circuit layer; S10, TGV drilling is performed on the glass core board 1, and the bottom of the through hole 8 falls on the pad 21 of the chip 2, S11, forming a seed layer in the through hole 8, and performing chemical copper plating to form a copper surface layer 9, the copper surface layer 9 is electrically connected to the chip 2, the inner layer circuit, and the outer layer circuit.

[0040] The following steps are also included: S12, forming a photopolymerization protective layer 10 on one side surface of the glass chip 2; S13, irradiating the photopolymerized protective layer 10 with ultraviolet light and developing it to form an opening, exposing the copper surface layer 9 on the surface, and forming an anti-oxidation layer on the outer side of the copper surface layer 9; S14, planting balls on the copper surface layer 9 on the surface; S15, sputtering a shielding layer 11 on the outside of the package, the shielding layer is made of Ti layer or stainless steel layer or metal layer capable of shielding signals, with a thickness of 30-100 um. When used, the shielding layer 11 is made of EMI plating layer, formed by sputtering process.

[0041] In step S1, the glass is thinned to 150-200 um by a grinder, and the flatness of the surfaces on both sides of the obtained glass core board 1 is less than 0.05 um.

[0042] The specific method of step S2 is as follows: S21, cleaning the bottom of the groove; S22, coating a layer of adhesive 3 on the inner wall of the groove; S23, bonding and fixing the chip 2 in the groove through the DAF film 4; in the step S21, the groove is cleaned by high-cleaning acid or plasma cleaning. The high-cleaning acid is an AC organic acid formed by mixing sulfuric acid or formic acid with acetic acid, and the concentration is 5%.

[0043] In step S3, the resin material is selected from one of ABF material, PP material and PI material.

[0044] In step S4, a thin copper layer is first plated on the surface of the resin material layer 5, and then thick electroplating is performed on the copper surface to form a first copper-plated layer 6, and the thickness of the first copper-plated layer 6 is 20-30um. In specific use, copper plating is performed twice. The first copper plating is copper plating, which mainly plates a thin copper layer on the surface of the resin to increase the bonding force of the electroplated copper. The second copper layer is mainly a thick copper layer electroplated, and the thick copper is used to form a circuit.

[0045] In step S5, a 20 / 20 um inner layer circuit is formed on the surface of the first copper plating layer 6 by lamination, exposure, etching, and development processes. In specific use, etching can be performed using a vacuum two-fluid solution of a sodium perchlorate system.

[0046] In step S6, the glass core board 1 is subjected to several times of thinning, grinding and polishing, and the thickness is 30-50 um.

[0047] In step S8, a 15 / 15um outer layer circuit is formed on the surface of the second copper plating layer 7 through the MSAP process of lamination, exposure, development, electroplating, etching, and development, and the thickness of the second copper plating layer 7 is 10-17um.

[0048] In step S10, the diameter of the through hole 8 is 5-20um, and the aspect ratio is less than or equal to 20:1. In step S10, the inner wall of the through hole 8 is treated by a composite additive, and the composite additive is a mixture of leveling agents S1, S2, and S3. The leveling agent S1 is (CH) n N m OH, mass fraction is 10%~15%; leveling agent S2 is H x (SO3) y(CH2) z 2. The mass fraction is 20%~40%; the leveling agent S3 is N x (CH3) y (CH2) z , mass fraction 30%~50%, the balance is water.

[0049] In step S12, the protective layer is made of solder resist material or PI material, and the thickness of the photopolymerized protective layer 10 is 15-30 um.

[0050] In step S14, a hollow fixture is installed at the bottom of the chip 2 during ball planting, and a nitrogen reflow chamber is used.

[0051] In step S13, when used, a layer of OSP or anti-rust layer is formed to prevent oxidation.

[0052] like Fig.16 As shown, the structure of the embedded glass substrate chip obtained by the above packaging method includes a glass core board, a groove is provided on one side of the glass core board 1, and the chip 2 is fixed in the groove by adhesive glue 3 and DAF film 4, a resin material layer 5 is provided on the surface of the chip 2 and one side of the glass core board 1, and the outer side of the resin material layer 5 is sequentially provided with a first copper plating layer 6, a resin material layer 5, another glass core board 1, a second copper plating layer 7, and a resin material layer 5, a through hole is provided on the outermost resin material layer 5, and the through hole 8 passes through the resin material layer 5, the second copper plating layer 7, another glass core board 1, the resin material layer 5, the first copper plating layer 6, and the resin material layer 5, and the bottom of the hole falls on the pad 21 of the chip 2, and the through hole 8 is provided with a copper surface layer 9, and the copper surface layer 9 is electrically connected to the chip 2, the circuit on the first copper plating layer 6, and the circuit on the second copper plating layer 7 to form a packaging body.

[0053] A photopolymerization protective layer 10 is provided on the outermost copper surface layer 9 and connected to solder balls 12 . A shielding layer 11 is provided on the outer side of the package body.

[0054] The CTE of the glass core is smaller than that of existing Si and BT materials. The present invention takes advantage of the small CTE of the glass core. The glass core has good flatness and can reduce the gap between the chip and the glass substrate, ultimately reducing the warping of the substrate and the warping of the packaged chip.

[0055] In the existing glass substrate stacking process, some of them first complete the stacking and pressing, and then groove to bury the chip. The present invention first buries the core and then performs substrate stacking and pressing to increase the layer. In order to reduce CTE, a second glass core board pressing is also added.

[0056] In the present invention, the chip is buried in the glass core board 1 of the first layer. The glass core board 1 is used to bury the chip first and then the substrate is laminated and pressed to make the circuit. In this way, the board-level or wafer-level core embedding process can be realized to increase the alignment. Because the core is buried first and then the circuit and substrate are aligned based on the chip, the alignment can be more accurate and the error between layers can be reduced. In addition, the chip is placed on the first layer of chips, close to the outer layer, which is easy to dissipate heat during the operation of the chip. Furthermore, the present invention directly coats a layer of EMI metal layer on the outside of the first layer of glass core board 1, which makes heat conduction faster.

Claims

1. A method for packaging an embedded glass substrate chip, characterized in that: The steps include: S1, pre-treating the glass and thinning it to obtain a glass core board (1); S2, using a laser drilling process to make a groove on one side of the surface of the glass core board (1), and fixing the chip (2) in the groove; S3, after the chip (2) is fixed, a layer of resin material (5) is pressed onto the chip (2) and the surface of one side of the glass core board (1); S4, copper is plated on one surface of the resin material layer (5) to form a first copper plated layer (6); S5, forming an inner layer circuit on the first copper plating layer (6); S6, laminating a layer of resin material (5) on the surface of the inner layer circuit to wrap the inner layer circuit, and coating a layer of adhesive layer on the insulating layer of the inner layer circuit to bond another glass core board (1); S7, sputtering a second copper plating layer (7) on one side surface of another glass core board (1); S8, forming an outer layer circuit on the second copper plating layer (7); S9, laminating a layer of resin material (5) on the surface of the outer circuit layer; S10, TGV drilling is performed on the glass core board (1), and the bottom of the through hole (8) falls on the pad (21) of the chip (2). S11, forming a seed layer in the through hole (8), and performing chemical copper plating to form a copper surface layer (9), wherein the copper surface layer (9) is electrically connected to the chip (2), the inner layer circuit, and the outer layer circuit.

2. The method for packaging a buried glass substrate chip according to claim 1, characterized in that: The following steps are also included: S12, forming a photopolymerization protective layer (10) on one surface of the glass chip (2); S13, irradiating the photopolymerized protective layer (10) with ultraviolet light and developing it to form an opening, exposing the copper surface layer (9) on the surface, and forming an anti-oxidation layer on the outside of the copper surface layer (9); S14, planting a ball on the copper surface layer (9); S15, sputtering a shielding layer (11) on the outer side of the package body, wherein the shielding layer is made of a Ti layer or a stainless steel layer or a metal layer capable of shielding signals, and has a thickness of 30 to 100 μm. When used specifically, the shielding layer (11) is an EMI coating layer, formed by a sputtering process.

3. The packaging method of a buried glass substrate chip according to claim 1, characterized in that: The specific method of step S2 is as follows: S21, cleaning the bottom of the groove; S22, coating a layer of adhesive (3) on the inner wall of the groove; S23, bonding and fixing the chip (2) in the groove through a DAF film (4); in step S21, the groove is cleaned by high-cleaning acid or plasma cleaning.

4. The method for packaging a buried glass substrate chip according to claim 1, characterized in that: The high-cleaning acid is an AC organic acid formed by mixing sulfuric acid or formic acid with acetic acid, and the concentration is 5%.

5. The method for packaging a buried glass substrate chip according to claim 1, characterized in that: In the step S3, the resin material is selected from one of ABF material, PP material and PI material.

6. The method for packaging a buried glass substrate chip according to claim 1, characterized in that: In the step S4, a thin copper layer is first plated on the surface of the resin material layer (5), and then thick electroplating is performed on the copper surface to form a first copper-plated layer (6). The thickness of the first copper-plated layer (6) is 20-30 um.

7. The packaging method of a buried glass substrate chip according to claim 1, characterized in that: In the step S10, the inner wall of the through hole (8) is treated by a composite additive, wherein the composite additive is a mixture of leveling agents S1, S2, and S3, wherein the leveling agent S1 is (CH) n N m OH, mass fraction is 10%~15%; leveling agent S2 is H x (SO3) y (CH2) z 2. The mass fraction is 20%~40%; the leveling agent S3 is N x (CH3) y (CH2) z , mass fraction 30%~50%, the balance is water.

8. The method for packaging an embedded glass substrate chip according to claim 1, characterized in that: In the step S14, a hollow fixture is installed at the bottom of the chip (2) during ball implantation, and a nitrogen reflow chamber is used.

9. A structure of an embedded glass substrate chip, comprising a glass core board, characterized in that: The glass core board (1) is provided with a groove on one side, and the chip (2) is fixed in the groove by adhesive glue (3) and DAF film (4). The surface of the chip (2) and one side of the glass core board (1) is provided with a resin material layer (5). The outer side of the resin material layer (5) is provided with a first copper plating layer (6), a resin material layer (5), another glass core board (1), a second copper plating layer (7), and a resin material layer (5) in sequence. A through hole is provided on the outermost resin material layer (5). The through hole (8) penetrates the resin material layer (5), the second copper plating layer (7), another glass core board (1), the resin material layer (5), the first copper plating layer (6), and the resin material layer (5). The bottom of the hole falls on the pad (21) of the chip (2). The through hole (8) is provided with a copper surface layer (9). The copper surface layer (9) is electrically connected to the chip (2), the circuit on the first copper plating layer (6), and the circuit on the second copper plating layer (7), so as to form a package.

10. The structure of an embedded glass substrate chip according to claim 9, characterized in that: A photopolymerization protective layer (10) is provided on the surface of the outermost copper surface layer (9) and is connected to a solder ball (12); a shielding layer (11) is provided on the outside of the package body.

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