Auxiliary tube parameter loose type low-end ideal diode

Abstract

The invention relates to the technical field of diodes, in particular to an auxiliary tube parameter loose type low-end ideal diode, which utilizes the natural difference of the conduction threshold voltage of a diode and an NMOS (N-channel Metal Oxide Semiconductor) tube and the characteristic that the forward voltage of the diode is not enough to conduct an NMOS auxiliary tube, adopts the diode or an NPN tube to replace the NMOS tube, designs three combined auxiliary tubes, and does not need the requirement of consistent parameters. In the aspects of price, performance and the like, the high-matching-degree pair transistors are achieved, the requirements for parameters of the high-matching-degree pair transistors and the auxiliary transistors are low, the circuit is simple, the cost is low, and the practicability is very high.

Description

Technical Field

[0001] The invention relates to the technical field of power diodes, and in particular to a low-end ideal diode with loose auxiliary tube parameters. Background Art

[0002] In electronic products, diodes are increasingly used because of their unidirectional conduction characteristics and the ability to prevent backflow. Diodes are one of the indispensable devices. However, the conduction voltage drop (VF) of a diode is about 0.6V. Although the conduction voltage drop (VF) of a Schottky diode is about 0.2-0.3V, it has a smaller voltage drop and is welcomed by many designers. Although Schottky diodes can meet some circuit design requirements, for circuits that require extremely low conduction voltage drops, the voltage drop of Schottky diodes is still greater than that of MOS tubes, making it difficult to meet the needs of such circuits. For some voltage-sensitive circuits, MOS tubes with low impedance characteristics are more likely to be used to improve product reliability. Therefore, it is necessary to develop unidirectional conduction devices (ideal diodes) with extremely low conduction voltage drops to reduce circuit power loss and improve power efficiency. Therefore, low-loss ideal diodes are needed to further reduce voltage drops, and have anti-backflow and protection functions for the front stage to minimize losses and extend battery operating time.

[0003] According to the polarity of the controlled power supply, it is divided into High Side (high-end, high-side, high-side) load switch and Low Side (low-end, low-side, low-side) load switch, which are similar to controlling the live wire and neutral wire of the 220V AC power supply. High-end load switch: It connects or disconnects the power supply (battery or adapter) to a specific load through the control of an external enable signal. Compared with the low-end load switch, the high-end load switch "flows" current to the load, while the low-end load switch connects or disconnects the load to the negative pole, so it "draws" current from the load. The low-end ideal diode is installed between the load and the negative pole of the power supply as a low-end drive switch to control the conduction or disconnection of the negative pole of the power supply, so it "draws" current from the load.

[0004] The combination forms of low-end ideal diodes mainly include: NMOS main tube + NPN auxiliary tube, NMOS main tube + NMOS auxiliary tube, etc. In addition, the technical implementation scheme of low-end ideal diodes that is most similar to the present invention is as follows.

[0005] The technical solution of NMOS main tube + NPN auxiliary tube (patent number of unidirectional conduction device: TW200537799A) is a low-end ideal diode with unidirectional conductivity. The circuit uses a dual NPN auxiliary tube combination logic control circuit to control the power NMOS main tube, and uses two NPN tubes from the same manufacturer and the same batch, so that the parameters of the two NPN tubes can be basically equal, or preferably two NPN pairs of tubes packaged together, the parameters of the two are almost equal, so as to ensure proper switching and anti-backflow functions, and its insertion conduction voltage drop is low, which is suitable for ultra-low loss applications, and can be used as a low-loss low-end ideal power diode. The disadvantage is that the parameters of the NPN auxiliary tube are required to be consistent, the bias resistance of the NPN tube is in the kilo-ohm level, and the static working current loss is in the milliampere level. The current loss is large, and the loss is large, such as Figure 1 As shown in the figure: when the drain-source channel of the V1 tube is forward biased, that is, A>B, the NPN tube V3 is turned on and the NPN tube V2 is turned off; when the drain-source channel of the V1 tube is reverse biased, that is, B>A, the NPN tube V3 is turned off and the NPN tube V2 is turned off. In summary: when the V1 tube is turned on, the V3 tube is turned on, and when the V1 tube is turned off, the V3 tube is also turned off. Therefore, the turn-on and turn-off of the V3 tube have the same directional characteristics as the V1 tube.

[0006] The NMOS main tube + NMOS auxiliary tube technical solution (an ultra-low loss low-end ideal diode, patent number: CN202020206261.X) is improved on the basis of the above patent, using dual NMOS auxiliary tubes to replace dual NPN auxiliary tubes, and simplifying the circuit. It is a low-end ideal diode with unidirectional conductivity. It is required to use two NMOS tubes from the same batch of the same manufacturer, so that the parameters of the two NMOS tubes can be basically equal, or preferably two NMOS pairs packaged together, the parameters of the two are almost equal. The circuit uses a dual NMOS auxiliary tube combination logic control circuit to control the power NMOS main tube. The bias resistance of the NMOS tube is in the megohm level, and the static operating current loss is in the microampere level. The current loss is small and the loss is small, such as Figure 2 As shown: When the NMOS tube V1 is forward biased: NMOS tube V3 is turned on, NMOS tube V2 is weakly turned on, and V1 is turned on; when the tube V1 is reverse biased: NMOS tube V3 is turned off, NMOS tube V2 is turned off or turned on (VCC2-V F -VCC1 ≥ V TN , because a closed loop cannot be formed, short-circuit current cannot be generated, the simulation current is at the nanoampere level and can be ignored, and conduction is equivalent to cutoff), and V1 is cutoff. In summary: when V1 is turned on, NMOS V3 is turned on, and when V1 is cut off, NMOS V3 is cut off. Therefore, the conduction and cutoff of NMOS V3 have the same directional characteristics as V1.

[0007] Matched Pairs Transistor, referred to as Matched Pairs Transistor, is a pair of transistors of the same type (NPN, PNP, NMOS or PMOS) with very similar parameters made on the same substrate and packaged in a single chip. The temperatures of the two transistors will affect each other, and the ambient temperature will have the same effect on the two transistors. The noise coefficient, characteristic curve, amplification factor, etc. of the two transistors are required to be as consistent as possible, and the consistency can be within 10%, or even 1%. In this case, by forming a circuit through a specific wiring method, the noise of the transistor itself, the zero drift caused by temperature, and the influence of the common mode signal on the differential mode signal can be offset to a considerable extent. Matched pair transistors can be used in current mirrors, differential amplifier circuits, balanced amplifiers, mixers, detectors and limiters, etc. NPN and PNP tubes are used in push-pull emitter followers, etc. For example, AD's monolithic dual-channel NPN pair tube MAT01GHZ, NPN pair tube SSM2212RZ; CMKT2222A integrated dual-channel NPN transistor; BSS84DW-7-F, CTLDM304P-M832DS integrated dual-channel PMOS tube, CMKT2907A integrated dual PNP tube, etc., are not listed one by one.

[0008] AD company NPN pair tube MAT01GHZ matching degree: V BE Typical value 40μV, maximum 200μV, temperature drift 0.15μV / ℃, magnification h FE The typical value is 1.0%, and the maximum is 8.0%, which achieves a very good matching degree. It can be called a high matching pair of tubes. The disadvantage is that the price is very expensive. The price of a single piece in a famous domestic electronic component mall exceeds ￥90 yuan (tax included), and the price of 100 pieces exceeds ￥75 yuan (tax included). Overseas purchasing is adopted, and the minimum order of 15 pieces is: the price of a single piece exceeds ￥180 yuan (tax included), and the price of 1,000 pieces exceeds ￥160 yuan (tax included). AD company's same series NPN pair tube MAT01AH / 883 matching degree: magnification h FE Typical value = 0.7%, maximum 3.0%, overseas purchasing, minimum order of 1 piece: single piece price exceeds ￥1000 yuan (tax included), 5 pieces price exceeds ￥940 yuan (tax included).

[0009] AD company NPN pair tube SSM2212RZ matching degree: V BEThe typical value is 10μV, the maximum is 100μV, the temperature drift is 0.03μV / ℃, and the typical value of current gain = 0.5%, which achieves a good matching degree. It can be called a high-matching pair of tubes. The disadvantage is that the price is very expensive. The unit price of a single piece in a famous domestic electronic mall exceeds ￥60 yuan (tax included), and the unit price of 100 pieces exceeds ￥50 yuan (tax included).

[0010] The dual transistors packaged together can realize a pair of devices with high matching degree. The advantage is that there is no need for costly fine-tuning. Considering factors such as price, dual transistors packaged together are generally chosen, but the matching degree is generally higher than that of single transistors, and can be used in higher precision occasions; the matching degree of high matching pairs of tubes can be within 1%, but due to the complexity of the processing technology, the price is naturally expensive, and ordinary products cannot afford it. In addition, the research and development cost of high matching pairs of tubes is high, there are few manufacturers, few models, few options, and low demand. The price is in a monopoly state and has remained high. The scope of application is greatly limited, so it is necessary to compromise between price and matching degree (performance).

[0011] The above two technical solutions require that the parameters of the NPN auxiliary tube or the NMOS auxiliary tube are consistent. If the parameters of the auxiliary tube are inconsistent, they cannot be used for some high-precision occasions. To solve the problem of inconsistent parameters of the auxiliary tube, it is necessary to design a low-end ideal diode with loose auxiliary tube parameters. By using conventional and inexpensive transistors (with inconsistent parameters of the auxiliary tube), a highly "matched" pair of tubes can be achieved, which may even exceed the highly matched pair of tubes in terms of price and performance, thereby controlling the conduction and cutoff of the NMOS main tube and enriching the implementation methods of the low-end ideal diode. Summary of the invention

[0012] The technical problem to be solved by the present invention is to overcome the above technical defects and provide a low-end ideal diode with loose auxiliary tube parameters that exceeds the high-matching pair of tubes in terms of price and performance.

[0013] In order to solve the above technical problems, the present invention provides a technical solution: a low-end ideal diode with loose auxiliary tube parameters, including a circuit, wherein the circuit includes an NMOS tube, a transistor and a voltage comparator, a resistor RL is connected between the source of the NMOS tube and the power supply VCC, and the voltage comparator is used to compare the drain and source voltage difference of the NMOS tube V1;

[0014] When the NMOS tube is forward biased, the NMOS tube is turned on, and when the NMOS tube is reverse biased, the NMOS tube is turned off.

[0015] Preferably, the transistor includes an NMOS auxiliary transistor, an NPN auxiliary transistor and a PNP transistor.

[0016] Preferably, the voltage comparator comprises an NMOS auxiliary tube V2 and an NPN auxiliary tube V3, the drain of the NMOS auxiliary tube is connected to the power supply VCC through a resistor R1, the source is connected to the source of the NMOS main tube, and the gate is connected to the base of the NPN auxiliary tube;

[0017] The resistor R1 is connected to the gate of the NMOS main tube, the drain of the NMOS main tube and the emitter of the NPN auxiliary tube are connected to the negative pole of the power supply, the resistor R2 is connected between the collector of the NPN auxiliary tube and the power supply VCC, and the resistor R2 is also connected to the gate of the NMOS auxiliary tube and the base of the NPN auxiliary tube.

[0018] Preferably, the voltage comparator includes an NMOS auxiliary tube V2 and a diode D1;

[0019] The source of the NMOS auxiliary tube is connected to the resistor RL, the drain is connected to the resistor R1, the gate is connected to the diode D1, the gate of the NMOS auxiliary tube is also connected to the resistor R4 and the base of the PNP tube is connected to the resistor R2;

[0020] The resistor R1, the resistor R2 and the emitter of the PNP tube are all connected to the power supply VCC, and the drain of the diode D1 and the NMOS tube is connected to the negative electrode of the power supply;

[0021] A resistor R3 is connected between the gate and source of the NMOS main tube, and the gate of the NMOS main tube is also connected to the collector of the PNP tube. The source of the NMOS main tube, the source of the NMOS auxiliary tube, and the resistor R3 are all connected to the resistor RL.

[0022] Preferably, the voltage comparator comprises an NMOS auxiliary tube V2 and an NPN auxiliary tube V3, the drain of the NMOS auxiliary tube is connected to the power supply VCC through a resistor R1, the source is connected to a resistor RL, the gate is connected to the base of the NPN auxiliary tube, and the resistor R1 is also connected to the gate of the NMOS auxiliary tube;

[0023] The drain of the NMOS main tube and the emitter of the NPN auxiliary tube are connected to the negative electrode of the power supply, and a resistor R2 is connected between the collector of the NPN auxiliary tube and the power supply VCC;

[0024] The emitter of the PNP tube is connected to R1, R2 and the power supply VCC, a resistor R4 is also connected between the base of the PNP tube and the resistor R2, a collector of the PNP tube is connected to the gate of the NMOS tube, and a resistor R3 is also connected between the gate of the NMOS tube and its source.

[0025] Compared with the prior art, the advantages of the present invention are as follows: the auxiliary tube used in the present circuit is NMOS+diode or NMOS+NPN tube, which are common components, cheap, with many models and manufacturers, and the parameters of the two are basically unrelated. The auxiliary tube parameter requirements are very loose, and the diode and NPN tube have natural conduction and cutoff characteristics, and only the minimum conduction threshold voltage V of the NMOS tube is required. TN(MIN) >V F This requirement is very easy to achieve.

[0026] The combined auxiliary tube composed of NMOS tube, NPN tube and diode is used in low-end ideal diode circuit. The circuit is simple, the cost is very low (the cost is less than one thousandth of that of a high-matching pair of tubes, which greatly saves costs), and it is very practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is the ideal diode schematic diagram composed of NMOS main tube + NPN auxiliary tube in the existing technology;

[0028] Figure 2 This is the ideal diode schematic diagram composed of NMOS main tube + NMOS auxiliary tube in the prior art;

[0029] Figure 3 The low-end ideal diode (I) is realized by the auxiliary tube composed of the NMOS tube + diode of the present invention;

[0030] Figure 4 The low-end ideal diode (II) is realized by the combined auxiliary tube and the NOT gate formed by the NMOS tube + diode of the present invention;

[0031] Figure 5 The low-end ideal diode (III) is realized by the combined auxiliary tube and the NOT gate formed by the NMOS tube + NPN tube of the present invention;

[0032] Figure 6 for Figure 3 Forward conduction simulation;

[0033] Figure 7 for Figure 3 Reverse cutoff simulation;

[0034] Figure 8 for Figure 4 Forward conduction simulation;

[0035] Fig. 9 for Figure 4 Reverse cutoff simulation;

[0036] Fig.10 for Figure 5 Forward conduction simulation;

[0037] Fig.11 for Figure 5Reverse cutoff simulation. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0039] Technical solution 1: NMOS tube + NPN tube constitutes an auxiliary tube to realize the low-end ideal diode (I)

[0040] The schematic diagram of the low-end ideal diode realized by the auxiliary tube composed of NMOS tube + NPN tube is as follows Figure 3 Shown: In Figure 2 On the basis of the NMOS main tube + NMOS pair tube (auxiliary tube), an NPN tube is used to replace the NMOS tube V3 to realize a low-end ideal diode with loose auxiliary tube parameters. The theoretical analysis is as follows.

[0041] like Figure 3 As shown in the schematic diagram, the minimum conduction threshold voltage of NMOS tube V2 is V TN(MIN) =1.0V>V F , VCC>V TN(MAX) , when NMOS tube V1 is forward biased, that is, A>B=0V, A≈0V, due to V TN(MIN) =1.0V>V F , the base and collector of NPN tube V3 are short-circuited, the emitter junction of NPN tube V3 is first to be turned on, and the gate voltage of NMOS tube V2 is Y=V F =0.7V, the gate-source voltage difference of NMOS tube V2 is V2 GS =YA=V F -A≈V F =0.7V<V TN(MIN) , NMOS tube V2 is naturally cut off (it is impossible to conduct anyway), the drain voltage V1G of NMOS tube V2 gradually increases, V1G≈VCC, V1 GS =V1G-A≈VCC>V TN(MAX) , the drain-source channel of NMOS V1 is turned on.

[0042] When the NMOS tube V1 is reverse biased, that is, B>A (B=VCC2, A=VCC1=VCC), the emitter junction of the NPN tube V3 is naturally reverse cutoff, the NPN tube V3 is cut off, and the gate voltage of the NMOS tube V2 is Y≈VCC; the body diode of the NMOS tube V1 is reverse cutoff, and no current flows through the body diode of the V2 tube (there is no closed loop between the load RL, the V2 tube, and R1), and the source voltage of the V2 tube V2S=A=VCC, V2 GS =YA=V F -VCC≈0V<V TN(MIN) Obviously, the NMOS tube V2 is naturally cut off (it is impossible to conduct anyway), V1G≈VCC, V1GS =V1G-A≈VCC-VCC=0V, the NMOS main V1 is cut off, the power supply VCC1 is isolated from the external power supply VCC2, and the current of the external power supply cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0043] When the NMOS tube V1 is forward biased: the NPN tube V3 is naturally turned on first, the NMOS tube V2 is naturally turned off, and the V1 tube is turned on; when the NMOS tube V1 is reverse biased: the NPN tube V3 is naturally reversely turned off, the NMOS tube V2 is naturally turned off, and the V1 tube is turned off. In summary: when the V1 tube is turned on, the NPN tube V3 is naturally turned on, and when the V1 tube is turned off, the NPN tube V3 is naturally turned off, so the turn-on and turn-off of the NPN tube V3 have the same directional characteristics as the V1 tube.

[0044] The auxiliary tube composed of NMOS tube + NPN tube realizes the function of low-end ideal diode well. It belongs to the front end of voltage comparator. NMOS auxiliary tube V2 outputs V1G signal to control the conduction and cutoff of NMOS main tube V1: when the potential A of the low end of load is greater than the negative electrode GND (B) of power supply, NMOS main tube V1 is turned on; otherwise, NMOS main tube V1 is cut off to prevent the current of negative electrode GND of power supply from flowing back to the power supply circuit through load RL, which is equivalent to low-end ideal diode.

[0045] The characteristics of this technical solution are consistent with the aforementioned "NMOS main tube + NMOS auxiliary tube technical solution". The "NMOS main tube + NMOS auxiliary tube technical solution" requires the auxiliary tube parameters to be consistent. The combined auxiliary tube of this technical solution is composed of NMOS tube + NPN tube. Both NMOS tube and NPN tube are common components, cheap, with many models and manufacturers, and the parameters of the two are basically unrelated. The auxiliary tube parameter requirements are very loose, and the NPN tube has natural conduction and cutoff characteristics, and only requires the minimum conduction threshold voltage V of the NMOS tube. TN(MIN) >V F This requirement is very easy to achieve.

[0046] Technical Solution 2: NMOS tube + diode constitutes a low-end ideal diode realized by a combined auxiliary tube and a NOT gate (Part 2)

[0047] Technical solution 1 is that the front-end NMOS auxiliary tube V2 of the voltage comparator outputs the V1G signal to control the conduction and cutoff of the NMOS main tube V1. Everything has two sides: there is a low-end ideal diode that controls the NMOS main tube by the front-end auxiliary tube, and a low-end ideal diode that controls the NMOS main tube by the back-end auxiliary tube should also be designed.

[0048] Therefore, in this embodiment, the comparator rear end auxiliary tube ( Figure 3 A back-end auxiliary tube is designed to control the low-end ideal diode of the NMOS tube V3, thereby controlling the conduction and cutoff of the NMOS tube V1.

[0049] Similarly, referring to the technical solution 1, on the basis of the NMOS tube + diode forming a combined auxiliary tube, a PNP tube is added as a NOT gate. The signal V4B output by the auxiliary tube diode D1 at the back end of the comparator controls the low-end ideal diode of the NMOS tube after passing through the NOT gate (PNP tube V4). The schematic diagram of the low-end ideal diode realized by the combined auxiliary tube and NOT gate formed by the NMOS tube + diode is as follows: Figure 4 Shown: The theoretical analysis is as follows.

[0050] Figure 4 Assume that the minimum conduction threshold voltage of NMOS tube V2 is V TN(MIN) =1.0V>V F , VCC>V TN(MAX) , when NMOS tube V1 is forward biased, that is, A>B=0V, A≈0V, due to V TN(MIN) =1.0V>V F , diode D1 takes the lead and is naturally turned on first, and the gate voltage of NMOS tube V2 is Y = V F =0.7V, the gate-source voltage difference of NMOS tube V2 is V2 GS =YA=V F -A≈V F =0.7V<V TN(MIN) , NMOS tube V2 is naturally cut off (it is impossible to conduct anyway); the base voltage of PNP tube V4 is V4B = VCC-V F , the PNP tube V4 is saturated and turned on, the collector voltage V1G of the V4 tube gradually increases, and the saturation conduction voltage drop V4 EC(sat) Very small, V1G = VCC-V4 EC(sat) ≈VCC, V1 GS =V1G-A≈VCC>V TN(MAX) , the drain-source channel of NMOS V1 is turned on.

[0051] When the NMOS tube V1 is reverse biased, that is, B>A (B=VCC2, A=VCC1=VCC), the diode D1 is naturally reverse cutoff, and the gate voltage Y of the NMOS tube V2 is ≈ VCC; the body diode of the NMOS tube V1 is reverse cutoff, and no current flows through the body diode of the V2 tube (there is no closed loop between the load RL, the body diode of the V2 tube, and R1), and the source voltage of the V2 tube V2S=A=VCC, V2 GS =YA=VCC-VCC≈0V<V TN(MIN) Obviously, the NMOS tube V2 is naturally cut off (it is impossible to conduct anyway); the base voltage V4B of the PNP tube V4 is VCC, the PNP tube V4 is cut off, and the collector voltage V1G of the V4 tube is pulled up to VCC by the resistor R3, V1G≈VCC, V1 GS=V1G-A≈0V<V TN(MIN) , the NMOS supervisor V1 is cut off, the power supply VCC1 is isolated from the external power supply VCC2, and the current of the external power supply cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0052] When the NMOS tube V1 is forward biased: the diode D1 is naturally turned on first (the PNP tube V4 is turned on), the NMOS tube V2 is naturally turned off, and the V1 tube is turned on; when the NMOS tube V1 is reverse biased: the diode D1 is naturally reversely turned off (the PNP tube V4 is turned off), the NMOS tube V2 is naturally turned off, and the V1 tube is turned off. In summary: when the V1 tube is turned on, the diode D1 is naturally turned on (the PNP tube V4 is turned on), and when the V1 tube is turned off, the diode D1 is naturally turned off (the PNP tube V4 is turned off), so the turn-on and turn-off of the diode D1 (PNP tube V4) have the same directional characteristics as the V1 tube.

[0053] The characteristics of this technical solution are consistent with the aforementioned "NMOS main tube + NMOS auxiliary tube technical solution". The "NMOS main tube + NMOS auxiliary tube technical solution" requires the auxiliary tube parameters to be consistent. The combined auxiliary tube of this technical solution is composed of NMOS tube + diode. The PNP tube V4 enhances the driving ability and improves the conduction and cutoff speed of the NMOS main tube V1. NMOS tubes, PNP tubes and diodes are all common components, which are cheap, have many models and manufacturers, and the parameters of the two are basically unrelated. The auxiliary tube parameter requirements are very loose, and the diode has natural conduction and cutoff characteristics, and only requires the minimum conduction threshold voltage V of the NMOS tube. TN(MIN) >V F This requirement is very easy to achieve. The performance is the same as that of the technical solution 1 "NMOS tube + diode constitutes an auxiliary tube to realize the low-end ideal diode".

[0054] Technical solution three: NMOS tube + NPN tube constitutes a low-end ideal diode realized by a combined auxiliary tube and a non-gate (III)

[0055] Similarly, referring to Technical Solution 1, Figure 3 On the basis of the above, a PNP tube V4 is added as a NOT gate driver. The signal V4B output by the auxiliary tube NPN tube V3 at the back end of the comparator is driven by the NOT gate (PNP tube V4) to output the signal V1G to control the low-end ideal diode of the NMOS main tube. The NMOS tube + NPN tube constitutes a combined auxiliary tube and a NOT gate to realize the low-end ideal diode schematic diagram as shown in the figure. Figure 5 shown.

[0056] Figure 5 The circuit shown in the figure assumes that the minimum conduction threshold voltage of NMOS tube V2 is V TN(MIN) =1.0V>V F , VCC>V TN(MAX), when NMOS tube V1 is forward biased, that is, A>B=0V, A≈0V, due to V TN(MIN) =1.0V>V F , the base and collector of NPN tube V3 are short-circuited, the emitter junction of NPN tube V3 is first to be turned on, and the gate voltage of NMOS tube V2 is Y=V F =0.7V, the gate and drain of NMOS tube V2 are short-circuited, and the gate and source voltage difference of NMOS tube V2 is V2 GS =YA=V F -A≈V F =0.7V<V TN(MIN) , NMOS tube V2 is naturally cut off (it is impossible to conduct anyway); NPN tube V3 saturation conduction voltage drop V CE(sat) , the collector voltage of NPN tube V3 is V CE(sat) , PNP tube V4 is saturated and turned on, and the collector voltage V1G of PNP tube V4 gradually increases, V1G≈=VCC-V4 EC(sat) =VCC, V1 GS =V1G-A≈VCC>V TN(MAX) , the drain-source channel of NMOS V1 is turned on.

[0057] When the NMOS tube V1 is reverse biased, that is, B>A (B=VCC2, A=VCC1=VCC), the emitter junction of the NPN tube V3 is naturally reverse cutoff, the NPN tube V3 is cut off, and the gate voltage of the NMOS tube V2 is Y≈VCC; the body diode of the NMOS tube V1 is reverse cutoff, and no current flows through the body diode of the V2 tube (there is no closed loop between the load RL, the body diode of the V2 tube, and R1), and the source voltage of the V2 tube V2S=A=VCC, V2 GS =YA=VCC-VCC≈0V<V TN(MIN) Obviously, the NMOS tube V2 is naturally cut off (it is impossible to conduct anyway); the NPN tube V3 is cut off, and the collector voltage of the NPN tube V3 is VCC. The PNP tube V4 is cut off, and the collector voltage V1G of the V4 tube is pulled up to VCC by the resistor R3, V1G≈VCC, V1 GS =V1G-A≈0V, the NMOS main V1 is cut off, the power supply VCC1 is isolated from the external power supply VCC2, and the current of the external power supply cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0058] When the NMOS tube V1 is forward biased: V1 is turned on, NPN tube V3 is naturally turned on first (PNP tube V4 is turned on), and NMOS tube V2 is naturally turned off; when the NMOS tube V1 is reverse biased: V1 is turned off, NPN tube V3 is naturally turned off in the reverse direction (PNP tube V4 is turned off), and NMOS tube V2 is naturally turned off. In summary: when V1 is turned on, NPN tube V3 is naturally turned on (PNP tube V4 is turned on), and when V1 is turned off, NPN tube V3 is naturally turned off (PNP tube V4 is turned off), so the turn-on and turn-off of NPN tube V3 (PNP tube V4) have the same directional characteristics as V1.

[0059] The characteristics of this technical solution are consistent with the aforementioned "NMOS main tube + NMOS auxiliary tube technical solution". The "NMOS main tube + NMOS auxiliary tube technical solution" requires the auxiliary tube parameters to be consistent. The combined auxiliary tube of this technical solution is composed of NMOS tube + NPN tube. The PNP tube V4 enhances the driving ability and improves the conduction and cutoff speed of the NMOS main tube V1. Both NMOS tubes and NPN tubes are common components, which are cheap, have many models and manufacturers, and their parameters are basically unrelated. The auxiliary tube parameter requirements are very loose, and the NPN tube has natural conduction and cutoff characteristics, and only requires the NMOS tube to have a minimum conduction threshold voltage V TN(MIN) >V F This requirement is very easy to achieve. The performance is the same as that of the second technical solution "NMOS tube + NPN tube constitutes an auxiliary tube to realize the low-end ideal diode".

[0060] according to Figure 3 to Figure 5 The circuit schematic is simulated and tested using the National Instruments simulation software Multisim (version V14.0). The NMOS tube is NXP, model BSP030, and the minimum on-threshold voltage V TN(MIN) =1V, maximum value V TN(MAX) =2.8V, typical value V is not given TN , the conduction current is up to 10A, the conduction resistance R DS(ON) =30mΩ(V GS =10V), R DS(ON) =50mΩ(V GS =4.5V), we can take the typical value of the on-threshold voltage V TN =2.8V. The diode model is 1N4001, and the NPN is 2N2222A. The specific simulation test is as follows. The load resistance RL = 10Ω, and the specific simulation test is as follows.

[0061] Implementation Method 1 Simulation

[0062] DC power supply forward bias simulation test: VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open), the gate and source voltages of V1 tube are V1 GS =V1G-A≈12.0V-0V=12.0V>V TN(MAX) , the drain-source channel of the V1 tube is turned on, and the on-current is 1.2A (test points PR3 and PR5). Figure 6 shown.

[0063] Disconnect point B from the negative pole of the power supply, and perform a reverse bias simulation test on the DC power supply: When the power supply VCC2 is reversely input, VCC2 = 25V (switches J1 and J2 are closed, and the drain of the main V1 is not connected to GND), the gate and source voltages of the V1 tube are V1 GS =V1G-A≈12.0V-12.0V=0V<V TN(MIN) , the drain-source channel of the V1 tube is cut off, the current of VCC2 from point B through the V1 tube to point A is 5.64nA (test point PR5), and the backflow current flowing into VCC1 is 4.73nA (test point PR3), which can be ignored. Figure 7 shown.

[0064] Implementation Method 2 Simulation

[0065] DC power supply forward bias simulation test: VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open), the gate and source voltages of V1 tube are V1 GS =V1G-A≈12.0V-0V=12.0V>V TN(MAX) , the drain-source channel of the V1 tube is turned on, and the on-current is 1.2A (test points PR3 and PR5). Figure 8 shown.

[0066] Disconnect point B from the negative pole of the power supply, and perform a reverse bias simulation test on the DC power supply: When the power supply VCC2 is reversely input, VCC2 = 25V (switches J1 and J2 are closed, and the drain of the main V1 is not connected to GND), the gate and source voltages of the V1 tube are V1 GS =V1G-A≈12.0V-12.0V=0V<V TN(MIN) , the drain-source channel of the V1 tube is cut off, the current of VCC2 from point B through the V1 tube to point A is 5.64nA (test point PR5), and the backflow current flowing into VCC1 is 3.89nA (test point PR3), which can be ignored. Fig. 9 shown.

[0067] Implementation Method 3 Simulation

[0068] DC power supply forward bias simulation test: VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open), the gate and source voltages of V1 tube are V1GS =V1G-A≈12.0V-0V=12.0V>V TN(MAX) , the drain-source channel of the V1 tube is turned on, and the on-current is 1.2A (test points PR3 and PR5). Fig.10 shown.

[0069] Disconnect point B from the negative pole of the power supply, and perform a reverse bias simulation test on the DC power supply: When the power supply VCC2 is reversely input, VCC2 = 25V (switches J1 and J2 are closed, and the drain of the main V1 is not connected to GND), the gate and source voltages of the V1 tube are V1 GS =V1G-A≈12.0V-12.0V=0V<V TN(MIN) , the drain-source channel of the V1 tube is cut off, the current of VCC2 from point B through the V1 tube to point A is 5.64nA (test point PR5), and the backflow current flowing into VCC1 is 4.08nA (test point PR3), which can be ignored. Fig.11 shown.

[0070] The present invention and its embodiments are described above, which is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it and do not deviate from the purpose of the invention, they can creatively design a structure and embodiment similar to the technical solution, which should fall within the protection scope of the present invention.

Claims

1. A low-end ideal diode with loose auxiliary tube parameters, including a circuit, characterized in that: The circuit includes an NMOS tube, a transistor and a voltage comparator, a resistor RL is connected between the source of the NMOS tube and the power supply VCC, and the voltage comparator is used to compare the drain and source voltage difference of the NMOS tube V1; When the NMOS tube is forward biased, the NMOS tube is turned on, and when the NMOS tube is reverse biased, the NMOS tube is turned off.

2. The auxiliary tube parameter loose type low-end ideal diode according to claim 1, characterized in that: The transistors include NMOS auxiliary transistors, NPN auxiliary transistors and PNP transistors.

3. The auxiliary tube parameter loose type low-end ideal diode according to claim 1, characterized in that: The voltage comparator includes an NMOS auxiliary tube V2 and an NPN auxiliary tube V3, wherein the drain of the NMOS auxiliary tube is connected to the power supply VCC through a resistor R1, the source is connected to the source of the NMOS main tube, and the gate is connected to the base of the NPN auxiliary tube; The resistor R1 is connected to the gate of the NMOS main tube, the drain of the NMOS main tube and the emitter of the NPN auxiliary tube are connected to the negative pole of the power supply, the resistor R2 is connected between the collector of the NPN auxiliary tube and the power supply VCC, and the resistor R2 is also connected to the gate of the NMOS auxiliary tube and the base of the NPN auxiliary tube.

4. The low-end ideal diode with loose auxiliary tube parameters according to claim 1, characterized in that: The voltage comparator includes an NMOS auxiliary tube V2 and a diode D1; The source of the NMOS auxiliary tube is connected to the resistor RL, the drain is connected to the resistor R1, the gate is connected to the diode D1, the gate of the NMOS auxiliary tube is also connected to the resistor R4 and the base of the PNP tube is connected to the resistor R2; The resistor R1, the resistor R2 and the emitter of the PNP tube are all connected to the power supply VCC, and the drain of the diode D1 and the NMOS tube is connected to the negative electrode of the power supply; A resistor R3 is connected between the gate and source of the NMOS main tube, and the gate of the NMOS main tube is also connected to the collector of the PNP tube. The source of the NMOS main tube, the source of the NMOS auxiliary tube, and the resistor R3 are all connected to the resistor RL.

5. The low-end ideal diode with loose auxiliary tube parameters according to claim 1, characterized in that: The voltage comparator includes an NMOS auxiliary tube V2 and an NPN auxiliary tube V3, wherein the drain of the NMOS auxiliary tube is connected to the power supply VCC through a resistor R1, the source is connected to the resistor RL, the gate is connected to the base of the NPN auxiliary tube, and the resistor R1 is also connected to the gate of the NMOS auxiliary tube; The drain of the NMOS main tube and the emitter of the NPN auxiliary tube are connected to the negative electrode of the power supply, and a resistor R2 is connected between the collector of the NPN auxiliary tube and the power supply VCC; The emitter of the PNP tube is connected to R1, R2 and the power supply VCC, a resistor R4 is also connected between the base of the PNP tube and the resistor R2, a collector of the PNP tube is connected to the gate of the NMOS tube, and a resistor R3 is also connected between the gate of the NMOS tube and its source.

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