Memory and method of forming the same

Abstract

A memory and a forming method thereof, the memory comprising a substrate; a floating gate structure on the substrate; a select gate structure on the substrate and spaced from the floating gate structure, the select gate structure comprising a plurality of first gates extending in a first direction and spaced in a second direction; a first drain region in the substrate on one side of the first gates; a first source region in the substrate on another side of the first gates, and a plurality of the first source regions being electrically connected; a second drain region in the substrate on one side of the floating gate structure and electrically connected to the first source region; and a second source region in the substrate on another side of the floating gate structure. The first gates and the first drain and source regions on both sides of the first gates form select transistors, and the plurality of the first source regions being electrically connected makes the plurality of the select transistors in parallel, so that the current value input to the second drain region during writing is the sum of the output current values of the select transistors, and more charges enter the floating gate structure during writing, thereby facilitating distinguishing the state of the floating gate structure during writing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a memory and a method for forming the same. Background Technology

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory, and analog circuits, with memory devices accounting for a significant proportion. With the development of semiconductor technology and the wider application of memory devices, it is necessary to integrate these memory devices with other components onto a single chip to form embedded semiconductor memory devices. For example, if the memory device is embedded within a central processing unit (CPU), it is necessary to ensure compatibility between the memory device and the embedded CPU platform while maintaining the original specifications and corresponding electrical performance of the memory device.

[0003] Generally, the storage device needs to be compatible with embedded standard logic devices. Embedded semiconductor devices are typically divided into a logic area and a storage area. The logic area usually includes logic devices, while the storage area includes storage devices. With the development of storage technology, various types of semiconductor memories have emerged, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), One-time Programmable Read Only Memory (OTPROM), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and Flash memory. Because OTPROM memory is non-volatile and can only be programmed once during use, it has high data reliability. Typically, OTPROM memory is mainly used for storing initial information and keys.

[0004] However, the performance of current memory still needs to be improved. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a memory and a method for forming the same, so as to improve the performance of the memory.

[0006] To address the aforementioned problems, embodiments of the present invention provide a memory, comprising: a substrate; a floating gate structure located on the substrate; a select gate structure disposed at intervals on the side of the floating gate structure on the substrate, the select gate structure including a plurality of first gates extending along a first direction and spaced apart along a second direction, the second direction being perpendicular to the first direction; a first drain region located in the substrate on one side of the first gate; a first source region located in the substrate on the other side of the first gate, and the plurality of first source regions being electrically connected; a second drain region located in the substrate on one side of the floating gate structure and electrically connected to the first source region; and a second source region located in the substrate on the other side of the floating gate structure.

[0007] Optionally, adjacent first gates may share the first drain region or the first source region.

[0008] Optionally, the second drain region is adjacent to the first source region closest to the floating gate structure and is an integral structure.

[0009] Optionally, the memory further includes: a source line plug located on top of the first drain region and electrically connected to the first drain region; a word line plug located on top of the select gate structure and electrically connected to the select gate structure; a bit line plug located on top of the second source region and electrically connected to the second source region; and a first source region plug located on top of the first source region and electrically connected to the first source region.

[0010] Optionally, the number of source line plugs located on the same first drain region is multiple and arranged sequentially along the first direction; the number of bit line plugs located on the same second source region is multiple and arranged sequentially along the first direction; the number of first source region plugs located on the same first source region is multiple and arranged sequentially along the first direction.

[0011] Optionally, the memory further includes: an interconnect structure located on top of the first source region plugs and connecting multiple first source region plugs, wherein the multiple first source regions are electrically connected through the interconnect structure.

[0012] Optionally, the source line plug and the first source area plug are staggered.

[0013] Optionally, the select gate structure further includes a second gate connecting each of the first gates and extending along the second direction; the memory further includes: word line plugs located on top of the second gates, the number of word line plugs being multiple and arranged sequentially along the second direction.

[0014] Optionally, the material of the first gate includes one or more of polycrystalline silicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0015] Accordingly, embodiments of the present invention also provide a method for forming a memory, comprising: providing a substrate; forming a floating gate structure and a select gate structure spaced apart on the substrate, the select gate structure including a plurality of first gates extending along a first direction and spaced apart along a second direction, the second direction being perpendicular to the first direction; forming a first drain region and a first source region in the substrate on both sides of the first gates respectively, and the plurality of first source regions being electrically connected; forming a second drain region and a second source region in the substrate on both sides of the floating gate structure respectively, the second drain region being electrically connected to the first source region.

[0016] Optionally, in the step of forming a first drain region and a first source region in the substrate on both sides of the first gate, adjacent first gates share the first drain region or the first source region.

[0017] Optionally, in the step of forming the first source region and the second drain region, the second drain region is adjacent to the first source region closest to the floating gate structure and is an integral structure.

[0018] Optionally, after forming the first source region, the first drain region, the second source region, and the second drain region, the forming method further includes: forming a source line plug on top of the first drain region, and the source line plug being electrically connected to the first drain region; forming a first source region plug on top of the first source region, and the first source region plug being electrically connected to the first source region; forming a word line plug on top of the select gate structure, and the word line plug being electrically connected to the select gate structure; and forming a bit line plug on top of the second source region, and the bit line plug being electrically connected to the second source region.

[0019] Optionally, in the step of forming the source line plug, the number of source line plugs located on the same first drain region is multiple and arranged sequentially along the first direction; in the step of forming the first source region plug, the number of first source region plugs located on the same first source region is multiple and arranged sequentially along the first direction; in the step of forming the bit line plug, the number of bit line plugs located on the same second source region is multiple and arranged sequentially along the first direction.

[0020] Optionally, in the step of forming the select gate structure, the select gate structure further includes a second gate connecting each of the first gates and extending along the second direction; after forming the first source region, the first drain region, the second source region and the second drain region, the forming method further includes: forming a word line plug on the top of the second gate, wherein the number of word line plugs is multiple and arranged sequentially along the second direction.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0022] The memory provided in this embodiment of the invention includes a select gate structure spaced on a substrate on the side of the floating gate structure. The select gate structure includes a plurality of first gates, a first drain region in the substrate on one side of the first gate, a first source region in the substrate on the other side of the first gate and the plurality of first source regions being electrically connected, a second drain region in the substrate on one side of the floating gate structure and the second drain region being electrically connected to the first source region, and a second source region in the substrate on the other side of the floating gate structure. The first gate, along with the first drain region and the first source region located on either side of it, constitute a selection transistor. Since multiple first source regions are electrically connected, multiple selection transistors are connected in parallel. By increasing the number of first gates, the total output current of the selection transistors can be increased, so that the current input to the second drain region during writing is the sum of the output current values ​​of each selection transistor. Therefore, by including multiple first gates in the selection gate structure, the current input to the second drain region during writing is increased, allowing more charge to enter the floating gate structure during writing. This makes it easier to reach the turn-on voltage during reading and also makes it easier to have a larger current value during reading. Consequently, it is easier to distinguish the state of the floating gate structure during writing, thus improving the readability of the memory and thereby improving the performance of the memory.

[0023] In the memory formation method provided by the embodiments of the present invention, a floating gate structure and a select gate structure are formed on the substrate at intervals. The select gate structure includes a plurality of first gates extending along a first direction and arranged at intervals along a second direction, the second direction being perpendicular to the first direction. A first drain region and a first source region are formed in the substrate on both sides of the first gate, and the plurality of first source regions are electrically connected. A second drain region and a second source region electrically connected to the first source are formed in the substrate on both sides of the floating gate structure. The first gate, along with the first drain region and the first source region located on either side of it, constitute a selection transistor. Since multiple first source regions are electrically connected, multiple selection transistors are connected in parallel. By increasing the number of first gates, the total output current of the selection transistors can be increased, so that the current input to the second drain region during writing is the sum of the output current values ​​of each selection transistor. Therefore, by including multiple first gates in the selection gate structure, the current input to the second drain region during writing is increased, allowing more charge to enter the floating gate structure during writing. This makes it easier to reach the turn-on voltage during reading and also makes it easier to have a larger current value during reading. Consequently, it is easier to distinguish the state of the floating gate structure during writing, thus improving the readability of the memory and thereby improving the performance of the memory. Attached Figure Description

[0024] Figures 1 to 2 This is a schematic diagram of a memory structure;

[0025] Figure 3This is a top view of an embodiment of the memory of the present invention;

[0026] Figure 4 for Figure 3 Sectional view at AA1;

[0027] Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the memory of the present invention. Detailed Implementation

[0028] Currently, memory performance still needs improvement. This paper analyzes the reasons why memory performance needs further improvement, using one specific type of memory as an example.

[0029] Figures 1 to 2 This is a schematic diagram of a memory structure. Among them, Figure 1 This is a top view. Figure 2 for Figure 1 Sectional view at AA1.

[0030] refer to Figures 1 to 2 The memory includes: a substrate 10; a floating gate structure 11 located on the substrate 10; a selection gate structure 12 disposed at intervals on the substrate 10 on the side of the floating gate structure 11; a first drain region 14 located in the substrate 10 on one side of the selection gate structure 12; a first source region 15 located in the substrate 10 on the other side of the selection gate structure 12; a second drain region 16 located in the substrate 10 on one side of the floating gate structure 11 and electrically connected to the first source region 15; and a second source region 17 located in the substrate 10 on the other side of the floating gate structure 11.

[0031] Research has revealed that the aforementioned memory tends to have a smaller current input to the second drain region 16 during writing, which in turn tends to have less charge entering the floating gate structure 11 during writing. This increases the difficulty of reaching the turn-on voltage during reading, or it tends to have a smaller current during reading, which makes it difficult to distinguish the state of the floating gate structure 11 during writing. Consequently, the readability of the memory is poor, and the performance of the memory needs to be improved.

[0032] To address the aforementioned technical problems, embodiments of the present invention provide a memory, comprising: a substrate; a floating gate structure located on the substrate; a selection gate structure disposed at intervals on the side of the floating gate structure on the substrate, the selection gate structure including a plurality of first gates extending along a first direction and spaced apart along a second direction, the second direction being perpendicular to the first direction; a first drain region located in the substrate on one side of the first gate; a first source region located in the substrate on the other side of the first gate, and the plurality of first source regions being electrically connected; a second drain region located in the substrate on one side of the floating gate structure and electrically connected to the first source region; and a second source region located in the substrate on the other side of the floating gate structure.

[0033] The memory provided in this embodiment of the invention includes a select gate structure spaced on a substrate on the side of the floating gate structure. The select gate structure includes a plurality of first gates, a first drain region in the substrate on one side of the first gate, a first source region in the substrate on the other side of the first gate and the plurality of first source regions being electrically connected, a second drain region in the substrate on one side of the floating gate structure and the second drain region being electrically connected to the first source region, and a second source region in the substrate on the other side of the floating gate structure. The first gate, along with the first drain region and the first source region located on either side of it, constitute a selection transistor. Since multiple first source regions are electrically connected, multiple selection transistors are connected in parallel. By increasing the number of first gates, the total output current of the selection transistors can be increased, so that the current input to the second drain region during writing is the sum of the output current values ​​of each selection transistor. Therefore, by including multiple first gates in the selection gate structure, the current input to the second drain region during writing is increased, allowing more charge to enter the floating gate structure during writing. This makes it easier to reach the turn-on voltage during reading and also makes it easier to have a larger current value during reading. Consequently, it is easier to distinguish the state of the floating gate structure during writing, thus improving the readability of the memory and thereby improving the performance of the memory.

[0034] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figure 3 This is a top view of an embodiment of the memory of the present invention; Figure 4 for Figure 3 Sectional view at AA1.

[0036] It should be noted that, in order to clearly show the structure of the memory, Figure 3 The shallow trench isolation structure, sidewalls, and interconnection structure are omitted. Figure 4 The source line plug, first source region plug, word line plug, bit line plug, and interconnect structure have been simplified.

[0037] refer to Figures 3 to 4In this embodiment, the memory includes: a substrate 100; a floating gate structure 130 located on the substrate 100; a select gate structure 140 disposed at intervals on the substrate 100 on the side of the floating gate structure 130, the select gate structure 140 including a plurality of first gates 143 extending along a first direction y and spaced apart along a second direction x, the second direction x being perpendicular to the first direction y; a first drain region 161 located in the substrate 100 on one side of the first gate 143; a first source region 162 located in the substrate 100 on the other side of the first gate 143, and the plurality of first source regions 162 being electrically connected; a second drain region 166 located in the substrate 100 on one side of the floating gate structure 130 and electrically connected to the first source region 162; and a second source region 167 located in the substrate 100 on the other side of the floating gate structure 130.

[0038] Substrate 100 is used to provide a process platform for the formation of memory.

[0039] In this embodiment, the substrate 100 is used to form a field-effect transistor.

[0040] In this embodiment, the memory includes non-volatile memory.

[0041] Specifically, non-volatile memory includes one-time programmable memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, or flash memory. In this embodiment, one-time programmable memory is used as an example for explanation.

[0042] As an example, the memory is a planar device, and correspondingly, the substrate 100 is a planar substrate. In other embodiments, the substrate may also be a substrate with channel protrusions.

[0043] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0044] In this embodiment, a shallow trench isolation structure (STI) 110 is formed in the substrate 100.

[0045] The shallow trench isolation structure 110 is used to define the active area (AA) (not shown) and the isolation area (not shown). The area located between the shallow trench isolation structures 110 is the active area, and the remaining area is the isolation area. Specifically, the material of the shallow trench isolation structure 110 is SiO2. In other embodiments, the material of the shallow trench isolation structure may also be other dielectric materials such as SiN or SiON.

[0046] In this embodiment, a well region 120 is formed in the substrate 100, and the doping type of the well region 120 is different from the channel conductivity type of the MOS transistor. As an example, the well region 120 is doped with N-type ions. In other embodiments, the well region may also be doped with P-type ions.

[0047] The floating gate structure 130 can capture and store electrons, and the electrons stored in the floating gate structure 130 will not be lost after power failure, thus realizing information storage.

[0048] In this embodiment, the floating gate structure 130 includes a first gate dielectric layer 131 located on the substrate 100 and a floating gate (FG) layer 132 located on the first gate dielectric layer 131.

[0049] The first gate dielectric layer 131 is a tunnel oxide layer of the memory, used to achieve electrical isolation between the floating gate layer 132 and the substrate 100, thereby utilizing the tunneling effect to allow electrons to enter the floating gate layer 132 through the first gate dielectric layer 131.

[0050] The floating gate layer 132 is used to store electrons in the memory, thereby enabling the memory to perform data storage functions. Specifically, when electrons in the channel are drawn into the floating gate layer 132, a write operation is achieved.

[0051] It should be noted that the material of the floating gate layer 132 includes polysilicon. Using polysilicon as the material of the floating gate layer 132 has the advantages of high process maturity and low process cost.

[0052] It should also be noted that the material of the first gate dielectric layer 131 includes SiO2. In other embodiments, the material of the first gate dielectric layer may also include materials such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0053] The selection gate structure 140 is used to determine the memory cells to be edited and read. Specifically, the memory cells to be edited and read are determined by applying a third electrical signal to the selection gate structure 140.

[0054] As an example, the third electrical signal is a voltage signal.

[0055] In this embodiment, the select gate structure 140 includes a second gate dielectric layer 142 located on a substrate 100 spaced apart from the side of the first gate dielectric layer 131, and a select gate (SG) layer 141 located on the second gate dielectric layer 142.

[0056] The second gate dielectric layer 142 is used to isolate the gate layer 141 from the channel.

[0057] The materials of the second gate dielectric layer 142 include HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0058] The selected gate layer 141 includes a plurality of first selected gate layers (not shown) extending along a first direction y and spaced apart along a second direction x. The first selected gate layers and the second gate dielectric layer 142 located at the bottom of the first selected gate layers constitute a first gate 143.

[0059] The material of the selected gate layer 141 includes one or more of polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC). Specifically, the material of the selected gate layer 141 depends on the type of the selected gate structure 140.

[0060] In this embodiment, the gate structure 140 is a polysilicon gate structure, and therefore the material of the gate layer 141 is polysilicon. Using polysilicon as the material of the gate layer 141 has the advantages of high process maturity and low process cost.

[0061] In other embodiments, the type of gate structure selected is a metal gate structure, and correspondingly, the material of the selected gate layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0062] Correspondingly, the material of the first gate 143 also includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0063] In this embodiment, the select gate structure 140 further includes a second gate 144 that connects each of the first gates 143 and extends along the second direction x.

[0064] The selected gate structure 140 also includes a second gate 144 that connects each of the first gates 143 and extends along the second direction x, which facilitates increasing the process window during the formation of word line plugs, thereby reducing the difficulty of forming word line plugs.

[0065] In this embodiment, the memory further includes: a sidewall 150 located on the sidewall of the floating gate structure 130 and on the sidewall of the select gate structure 140.

[0066] Specifically, the sidewall 150 can be a single-layer structure or a multi-layer structure; the material of the sidewall 150 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the sidewall 150 is a single-layer structure, and the material of the sidewall 150 is silicon nitride.

[0067] The first gate 143, and the first drain region 161 and the first source region 162 located on both sides thereon constitute a selection transistor. Since the multiple first source regions 162 are electrically connected, the multiple selection transistors are connected in parallel. By increasing the number of first gates 143, the total output current of the selection transistors can be increased, so that the current input to the second drain region 166 during writing is the sum of the output current values ​​of each selection transistor. Therefore, by making the selection gate structure 140 include multiple first gates 143, the current value input to the second drain region 166 during writing is increased, so that more charge can enter the floating gate structure 130 during writing, thereby making it easier to reach the turn-on voltage during reading and making it easier to have a larger current value during reading. Correspondingly, it is easier to distinguish the state of the floating gate structure 130 during writing, that is, to improve the readability of the memory, and thus improve the performance of the memory.

[0068] The first drain region 161 is used as the drain of the selection transistor.

[0069] The first source region 162 is used as the source of the selection transistor.

[0070] It should be noted that by applying a first electrical signal to each of the first drain regions 161, multiple selection transistors are connected in parallel, enabling the memory to write or read data. As an example, the first electrical signal is a voltage signal.

[0071] Specifically, both the first drain region 161 and the first source region 162 are doped with P-type ions, including B, Ga, or In. In other embodiments, both the first drain region and the first source region may also be doped with N-type ions, including P, As, or Sb.

[0072] In this embodiment, adjacent first gates 143 share a first drain region 161 or a first source region 162. This sharing of the first drain region 161 or the first source region 162 by adjacent first gates 143 helps to save the substrate area 100 occupied by the selection transistor.

[0073] The floating gate structure 130, and the second drain region 166 and the second source region 167 located on both sides of it constitute a data storage transistor.

[0074] The second drain region 166 is used as the drain of the data storage transistor.

[0075] The second source region 167 is used as the source of the data storage transistor.

[0076] Specifically, both the second drain region 166 and the second source region 167 are doped with P-type ions. In other embodiments, both the second drain region and the second source region may also be doped with N-type ions.

[0077] It should be noted that the second electrical signal applied to the second source region 167 is controlled to determine whether the data storage transistor writes "0" or "1".

[0078] As an example, the second electrical signal is a voltage signal. For instance, when the data storage transistor needs to write "1", a voltage drop exists between the second source region 167 and the second drain region 166, allowing charge to enter the floating gate structure 130, thus causing the data storage transistor to store "1". When the data storage transistor needs to write "0", there is no voltage drop between the second source region 167 and the second drain region 166, preventing charge from entering the floating gate structure 530, thus causing the data storage transistor to store "0".

[0079] In this embodiment, the second drain region 166 is adjacent to the first source region 162 closest to the floating gate structure 130 and is an integral structure.

[0080] The second drain region 166 is adjacent to the first source region 162 closest to the floating gate structure 130 and is an integral structure, which facilitates the electrical connection between the second drain region 166 and the first source region 162 and reduces the difficulty of the electrical connection between the second drain region 166 and the first source region 162.

[0081] In this embodiment, the memory further includes: a source line plug 171, located on top of the first drain region 161 and electrically connected to the first drain region 161; a word line plug 173, located on top of the select gate structure 140 and electrically connected to the select gate structure 140; a bit line plug 174, located on top of the second source region 167 and electrically connected to the second source region 167; and a first source region plug 172, located on top of the first source region 162 and electrically connected to the first source region 162.

[0082] The first drain region 161 is electrically connected to the source line (SL) via the source line plug 171, thereby loading a first electrical signal onto the multiple first drain regions 161.

[0083] Select gate structure 140 is electrically connected to word line (WL) via word line plug 173, thereby loading a third electrical signal onto multiple select gate structures 140.

[0084] The second source region 167 is electrically connected to the bit line (BL) via the bit line plug 174, thereby loading a second electrical signal onto the second source region 167.

[0085] Multiple first source regions 162 are electrically connected through first source region plugs 172 and interconnection structures.

[0086] In this embodiment, the select gate structure 140 further includes a second gate 144 connecting each of the first gates 143 and extending along the second direction x. Correspondingly, word line plugs are located on top of the second gates, and there are multiple word line plugs arranged sequentially along the second direction.

[0087] The presence of multiple word line plugs 173 helps to reduce the current flowing through a single word line plug 173. Furthermore, the word line plugs 173 are arranged sequentially along the second direction X, which facilitates the increase of the process window for forming the word line plugs 173, thereby reducing the difficulty of forming the word line plugs 173.

[0088] In this embodiment, there are multiple source line plugs 171 located on the same first drain region 161 and arranged sequentially along the first direction y; there are multiple bit line plugs 174 located on the same second source region 167 and arranged sequentially along the first direction y; there are multiple first source region plugs 172 located on the same first source region 162 and arranged sequentially along the first direction y.

[0089] The number of source line plugs 171, first source region plugs 172, and bit line plugs 174 are all multiple, which helps to reduce the current value flowing through a single plug. Moreover, the source line plugs 171, first source region plugs 172, and bit line plugs 174 are all arranged sequentially along the first direction y, which helps to increase the process window for forming the plugs, thereby reducing the difficulty of forming the plugs.

[0090] Specifically, the source line plug 171 and the first source region plug 172 are staggered. The staggered arrangement of the source line plug 171 and the first source region plug 172 helps to increase the distance between adjacent source line plugs 171 and the first source region plug 172, thereby reducing parasitic capacitance.

[0091] In this embodiment, the source line plug 171, the first source region plug 172, the word line plug 173, and the bit line plug 174 are all made of conductive materials, such as copper and aluminum.

[0092] In this embodiment, the memory further includes an interconnect structure 180 located on top of the first source region plugs 172 and connected to a plurality of first source region plugs 172, wherein the plurality of first source regions 162 are electrically connected through the interconnect structure 180.

[0093] An interconnection structure 180 is formed on the top of the first source region plug 172 to connect multiple first source region plugs 172, so that multiple first source regions 162 can be electrically connected through the interconnection structure 180.

[0094] Specifically, in the step of forming the interconnect structure 180, the interconnect structure 180 is also located on top of the source line plug 171, the word line plug 173, and the bit line plug 174. The interconnect structure 180 located on top of the source line plug 171 is connected to the source line plug 171, the interconnect structure 180 located on top of the word line plug 173 is connected to the word line plug 173, and the interconnect structure 180 located on top of the bit line plug 174 is connected to the bit line plug 174. The interconnect structure 180 on top of the first source region plug 172, the interconnect structure 180 on top of the source line plug 171, the interconnect structure 180 on top of the word line plug 173, and the interconnect structure 180 on top of the bit line plug 174 are independent of each other.

[0095] As an example, the interconnect structure 180 is made of copper. In other embodiments, the interconnect structure may be made of other conductive materials, such as aluminum.

[0096] Accordingly, the present invention also provides a method for forming a memory. Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the memory of the present invention.

[0097] refer to Figures 5 to 6 Provides a 500 base.

[0098] in, Figure 5 This is a top view. Figure 6 for Figure 5 Sectional view at AA1.

[0099] It should be noted that, in order to clearly show the structure of the memory, Figure 5 The shallow trench isolation structure is omitted.

[0100] The substrate 500 is used to provide a process platform for subsequent process manufacturing.

[0101] In this embodiment, the substrate 500 is used to form a field-effect transistor.

[0102] In this embodiment, the memory formed by the forming method includes non-volatile memory.

[0103] Specifically, non-volatile memory includes one-time programmable memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, or flash memory. In this embodiment, a method for forming one-time programmable memory is used as an example for explanation.

[0104] As an example, the memory is a planar device, and correspondingly, the substrate 500 is a planar substrate. In other embodiments, the substrate may also be a substrate with channel protrusions.

[0105] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0106] In this embodiment, during the step of providing the substrate 500, a shallow trench isolation structure 510 is formed in the substrate 500.

[0107] The shallow trench isolation structure 510 is used to define an active region (not shown) and an isolation region (not shown). The area located between the shallow trench isolation structures 510 is the active region, and the remaining area is the isolation region. Specifically, the material of the shallow trench isolation structure 510 is SiO2. In other embodiments, the material of the shallow trench isolation structure may also be other dielectric materials such as SiN or SiON.

[0108] In this embodiment, during the step of providing the substrate 500, a well region 520 is formed in the substrate 500. The doping type of the well region 520 is different from the channel conductivity type of the MOS transistor. As an example, the well region 520 is doped with N-type ions. In other embodiments, the well region may also be doped with P-type ions.

[0109] refer to Figures 7 to 8 A floating gate structure 530 and a selection gate structure 540 are formed on a substrate 500 at intervals. The selection gate structure 540 includes a plurality of first gates 543 extending along a first direction Y and spaced apart along a second direction X. The second direction X is perpendicular to the first direction Y.

[0110] in, Figure 7 This is a top view. Figure 8 for Figure 7 Sectional view at AA1.

[0111] It should be noted that, in order to clearly show the structure of the memory, Figure 7 The shallow trench isolation structure and sidewalls are omitted.

[0112] The floating gate structure 530 can capture and store electrons, and the electrons stored in the floating gate structure 530 will not be lost after power failure, thus realizing information storage.

[0113] In this embodiment, in the step of forming the floating gate structure 530, the floating gate structure 530 includes a first gate dielectric layer 531 located on the substrate 500 and a floating gate layer 532 located on the first gate dielectric layer 531.

[0114] The first gate dielectric layer 531 is a tunneling oxide layer of the memory, used to achieve electrical isolation between the floating gate layer 532 and the substrate 500, thereby utilizing the tunneling effect to allow electrons to enter the floating gate layer 532 through the first gate dielectric layer 531.

[0115] The floating gate layer 532 is used to store electrons in the memory, thereby enabling the memory to perform data storage functions. Specifically, when electrons in the channel are drawn into the floating gate layer 532, a write operation is achieved.

[0116] It should be noted that the floating gate layer 532 is made of polysilicon. Using polysilicon as the material for the floating gate layer 532 has the advantages of high process maturity and low process cost.

[0117] It should also be noted that the material of the first gate dielectric layer 531 includes SiO2. In other embodiments, the material of the first gate dielectric layer may also include materials such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0118] The selection gate structure 540 is used to determine the memory cells to be edited and read. Specifically, the memory cells to be edited and read are determined by applying a third electrical signal to the selection gate structure 540.

[0119] As an example, the third electrical signal is a voltage signal.

[0120] In this embodiment, in the step of forming the select gate structure 540, the select gate structure 540 includes a second gate dielectric layer 542 located on a substrate 500 spaced apart from the side of the first gate dielectric layer 531, and a select gate layer 541 located on the second gate dielectric layer 542.

[0121] The second gate dielectric layer 542 is used to isolate the select gate layer 541 from the channel.

[0122] The materials of the second gate dielectric layer 542 include HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0123] The selected gate layer 541 includes a plurality of first selected gate layers (not shown) extending along a first direction Y and spaced apart along a second direction X. The first selected gate layers and the second gate dielectric layer 542 at the bottom of the first selected gate layers constitute the first gate 543.

[0124] The material of the selected gate layer 541 includes one or more of polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC). Specifically, the material of the selected gate layer 541 depends on the type of the selected gate structure 540.

[0125] In this embodiment, since the gate structure 540 is made of polysilicon, the gate layer 541 is also made of polysilicon. Using polysilicon as the material for the gate layer 541 has advantages such as high process maturity and low process cost.

[0126] In other embodiments, the type of gate structure selected is a metal gate structure, and correspondingly, the material of the selected gate layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0127] Correspondingly, the material of the first gate 543 also includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0128] In this embodiment, during the step of forming the selection gate structure 540, the selection gate structure 540 further includes a second gate 544 that connects each of the first gates 543 and extends along the second direction X.

[0129] The selected gate structure 540 also includes a second gate 544 that connects each of the first gates 543 and extends along the second direction X, which facilitates increasing the process window during the subsequent formation of word line plugs, thereby reducing the difficulty of forming word line plugs.

[0130] In this embodiment, to reduce process steps, shorten manufacturing time, and save costs, the floating gate structure 530 and the selection gate structure 540 are formed in the same process step. In other embodiments, the floating gate structure can be formed first, followed by the selection gate structure; or the selection gate structure can be formed first, followed by the floating gate structure.

[0131] In this embodiment, after forming the floating gate structure 530 and the selection gate structure 540, and before forming the first drain region, the first source region, the second drain region, and the second source region, the forming method further includes: forming sidewalls 550 on the sidewalls of both the floating gate structure 530 and the selection gate structure 540.

[0132] Sidewall 550 is used to protect the floating grid structure and the sidewall of the selective grid structure 540.

[0133] Specifically, the sidewall 550 can be a single-layer structure or a multi-layer structure; the material of the sidewall 550 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the sidewall 550 is a single-layer structure, and the material of the sidewall 550 is silicon nitride.

[0134] refer to Figures 9 to 10 A first drain region 561 and a first source region 562 are formed in the substrate 500 on both sides of the first gate 543, and the plurality of first source regions 562 are electrically connected.

[0135] in, Figure 9 This is a top view. Figure 10 for Figure 9 Sectional view at AA1.

[0136] It should be noted that, in order to clearly show the structure of the memory, Figure 9 The shallow trench isolation structure and sidewalls are omitted.

[0137] The first gate 543, and the first drain region 561 and the first source region 562 located on both sides thereon constitute a selection transistor. Since the multiple first source regions 562 are electrically connected, the multiple selection transistors are connected in parallel. By increasing the number of first gates 543, the total output current of the selection transistors can be increased, so that the current input to the subsequently formed second drain region during writing is the sum of the output current values ​​of each selection transistor. Therefore, by making the selection gate structure 540 include multiple first gates 543, the current value input to the second drain region during writing is increased, so that more charge can enter the floating gate structure 530 during writing, thereby making it easier to reach the turn-on voltage during reading and making it easier to have a larger current value during reading. Correspondingly, it is easier to distinguish the state of the floating gate structure during writing, that is, improve the readability of the memory, and thus improve the performance of the memory.

[0138] The first drain region 561 is used as the drain of the selection transistor. The first source region 562 is used as the source of the selection transistor.

[0139] It should be noted that by applying a first electrical signal to each of the first drain regions 561, multiple selection transistors are connected in parallel, enabling the memory to write or read data. As an example, the first electrical signal is a voltage signal.

[0140] Specifically, both the first drain region 561 and the first source region 562 are doped with P-type ions, including B, Ga, or In. In other embodiments, both the first drain region and the first source region may also be doped with N-type ions, including P, As, or Sb.

[0141] In this embodiment, during the step of forming the first drain region 561 and the first source region 562 in the substrate 500 on both sides of the first gate 543, adjacent first gates 543 share the first drain region 561 or the first source region 562. Adjacent first gates 543 sharing the first drain region 561 or the first source region 562 helps to save the substrate 500 area occupied by the selection transistor.

[0142] Continue to refer to Figures 9 to 10 A second drain region 566 and a second source region 567 are formed in the substrates on both sides of the floating gate structure 530, respectively, and the second drain region 566 is electrically connected to the first source region 562.

[0143] The floating gate structure 530, and the second drain region 566 and the second source region 567 located on both sides of it constitute a data storage transistor.

[0144] The second drain region 566 is used as the drain of the data storage transistor. The second source region 567 is used as the source of the data storage transistor.

[0145] Specifically, both the second drain region 566 and the second source region 567 are doped with P-type ions. In other embodiments, both the second drain region and the second source region may also be doped with N-type ions.

[0146] It should be noted that the second electrical signal applied to the second source region 567 is controlled to determine whether the data storage transistor writes "0" or "1".

[0147] As an example, the second electrical signal is a voltage signal. For instance, when the data storage transistor needs to write a "1", a voltage drop exists between the second source region 567 and the second drain region 566, allowing charge to enter the floating gate structure 530, thus causing the data storage transistor to store a "1". When the data storage transistor needs to write a "0", there is no voltage drop between the second source region 567 and the second drain region 566, preventing charge from entering the floating gate structure 530, thus causing the data storage transistor to store a "0".

[0148] In this embodiment, in the step of forming the first source region 562 and the second drain region 566, the second drain region 566 is adjacent to the first source region 562 closest to the floating gate structure 530 and is an integral structure.

[0149] The second drain region 566 is adjacent to the first source region 562 closest to the floating gate structure 530 and is an integral structure, which facilitates the electrical connection between the second drain region 566 and the first source region 562 and reduces the difficulty of the electrical connection between the second drain region 566 and the first source region 562.

[0150] In this embodiment, the first drain region 561, the first source region 562, the second drain region 566, and the second source region 567 are formed in the same step. Forming the first drain region 561, the first source region 562, the second drain region 566, and the second source region 567 in the same step helps to reduce process steps, shorten manufacturing time, and save costs.

[0151] refer to Figures 11 to 12In this embodiment, after forming the first source region 562, the first drain region 561, the second source region 567, and the second drain region 566, the forming method further includes: forming a source line plug 571 on the top of the first drain region 561, and the source line plug 571 is electrically connected to the first drain region 561; forming a first source region plug 572 on the top of the first source region 562, and the first source region plug 572 is electrically connected to the first source region 562; forming a word line plug 573 on the top of the select gate structure 540, and the word line plug 573 is electrically connected to the select gate structure 540; and forming a bit line plug 574 on the top of the second source region 567, and the bit line plug 574 is electrically connected to the second source region 567.

[0152] in, Figure 11 This is a top view. Figure 12 for Figure 11 Sectional view at AA1.

[0153] It should be noted that, in order to clearly show the structure of the memory, Figure 11 The shallow trench isolation structure, sidewalls, and interconnection structure are omitted. Figure 12 The source line plug, first source region plug, word line plug, bit line plug, and interconnect structure have been simplified.

[0154] The first drain region 561 is electrically connected to the source line (SL) via the source line plug 571, thereby loading a first electrical signal onto the multiple first drain regions 561.

[0155] Multiple first source regions 562 are electrically connected through first source region plugs 572 and the subsequent interconnection structure.

[0156] Select gate structure 540 is electrically connected to word line (WL) via word line plug 573, thereby loading a third electrical signal onto multiple select gate structures 540.

[0157] The second source region 567 is electrically connected to the bit line (BL) via the bit line plug 574, thereby loading a second electrical signal onto the second source region 567.

[0158] In this embodiment, during the step of forming the select gate structure 540, the select gate structure 540 further includes a second gate 544 that connects each of the first gates 543 and extends along the second direction X. Accordingly, a word line plug 573 is formed on the top of the second gate 544, and there are multiple word line plugs 573 arranged sequentially along the second direction X.

[0159] The presence of multiple word line plugs 573 helps reduce the current flowing through a single word line plug 573. Furthermore, the word line plugs 573 are arranged sequentially along the second direction X, which facilitates the increase of the process window for forming the word line plugs 573, thereby reducing the difficulty of forming the word line plugs 573.

[0160] In this embodiment, in the step of forming the source line plug 571, there are multiple source line plugs 571 located on the same first drain region 561 and they are arranged sequentially along the first direction Y; in the step of forming the first source region plug 572, there are multiple first source region plugs 572 located on the same first source region 562 and they are arranged sequentially along the first direction Y; in the step of forming the bit line plug 574, there are multiple bit line plugs 574 located on the same second source region 567 and they are arranged sequentially along the first direction Y.

[0161] The number of source line plugs 571, first source region plugs 572, and bit line plugs 574 are all multiple, which helps to reduce the current value flowing through a single plug. Moreover, the source line plugs 571, first source region plugs 572, and bit line plugs 574 are all arranged sequentially along the first direction Y, which helps to increase the process window for forming the plugs, thereby reducing the difficulty of forming the plugs.

[0162] Specifically, the source line plug 571 and the first source region plug 572 are staggered. The staggered arrangement of the source line plug 571 and the first source region plug 572 helps to increase the distance between adjacent source line plugs 571 and the first source region plug 572, thereby reducing parasitic capacitance.

[0163] In this embodiment, the source line plug 571, the first source region plug 572, the word line plug 573, and the bit line plug 574 are all made of conductive materials, such as copper and aluminum.

[0164] In this embodiment, the forming method further includes: forming an interconnect structure 580 on the top of the first source region plug 572, the interconnect structure 580 connecting multiple first source region plugs 572, and multiple first source regions 562 being electrically connected through the interconnect structure 580.

[0165] An interconnection structure 580 is formed on the top of the first source region plug 572 to connect multiple first source region plugs 572, so that multiple first source regions 562 can be electrically connected through the interconnection structure 580.

[0166] Specifically, in the step of forming interconnect structure 580, interconnect structure 580 is also located on top of source line plug 571, top of word line plug 573, and top of bit line plug 574. The interconnect structure 580 located on top of source line plug 571 is connected to source line plug 571, the interconnect structure 580 located on top of word line plug 573 is connected to word line plug 573, and the interconnect structure 580 located on top of bit line plug 574 is connected to bit line plug 574. The interconnect structure 580 on top of first source plug 572, the interconnect structure 580 on top of source line plug 571, the interconnect structure 580 on top of word line plug 573, and the interconnect structure 580 on top of bit line plug 574 are independent of each other.

[0167] It should be noted that the plug and interconnect structure 580 can be formed using a double damask process, or the plug and interconnect structure 580 can be formed separately using a single damask process. The interconnect structure 580 and the plug are electrically connected, for example, through physical contact.

[0168] As an example, the interconnect structure 580 is made of copper. In other embodiments, the interconnect structure may be made of other conductive materials, such as aluminum.

[0169] It should be noted that the memory can be formed using the forming method described in the foregoing embodiments, or it can be formed using other forming methods. For a detailed description of the memory in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these will not be repeated here.

[0170] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A memory, comprising: The memory comprises: a substrate; a floating gate structure on the substrate; a select gate structure on the substrate and spaced apart from the floating gate structure, the select gate structure comprising a plurality of first gates extending in a first direction and spaced apart in a second direction perpendicular to the first direction; a first drain region in the substrate on one side of the first gates; a first source region in the substrate on the other side of the first gates, and a plurality of the first source regions being electrically connected; a second drain region in the substrate on one side of the floating gate structure, and electrically connected to the first source regions; a second source region in the substrate on the other side of the floating gate structure; wherein adjacent first gates share the first drain region or the first source region.

2. The memory of claim 1, wherein, The second drain region is adjacent to and integral with the first source region closest to the floating gate structure.

3. The memory of claim 1, wherein, The memory further comprises: a source line plug on top of the first drain region and electrically connected to the first drain region; a word line plug on top of the select gate structure and electrically connected to the select gate structure; a bit line plug on top of the second source region and electrically connected to the second source region; a first source region plug on top of the first source region and electrically connected to the first source region.

4. The memory of claim 3, wherein, The number of source line plugs on the same first drain region is a plurality and arranged in the first direction in sequence. The number of bit line plugs on the same second source region is a plurality and arranged in the first direction in sequence. The number of first source region plugs on the same first source region is a plurality and arranged in the first direction in sequence.

5. The memory of claim 3, wherein, The memory further comprises an interconnection structure on top of the first source region plugs and connecting a plurality of the first source region plugs, and a plurality of the first source regions are electrically connected through the interconnection structure.

6. The memory of claim 3 or 4, wherein, The source line plug and the first source region plug are staggered.

7. The memory of claim 1, wherein, The select gate structure further comprises a second gate connecting the first gates and extending in the second direction. The memory further comprises a plurality of word line plugs on top of the second gate and arranged in the second direction in sequence.

8. The memory of claim 1, wherein, The material of the first gate comprises one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, silicon titanium nitride, and aluminum titanium carbide.

9. A method of forming a memory, comprising: The method comprises: providing a substrate; forming a floating gate structure and a select gate structure on the substrate, the select gate structure comprising a plurality of first gates extending in a first direction and spaced apart in a second direction perpendicular to the first direction; forming a first drain region and a first source region in the substrate on both sides of the first gates, and a plurality of the first source regions being electrically connected; forming a second drain region and a second source region in the substrate on both sides of the floating gate structure, and the second drain region being electrically connected to the first source regions.

10. The method of forming a memory of claim 9, wherein, In the step of forming the first drain region and the first source region in the substrate on both sides of the first gates, adjacent first gates share the first drain region or the first source region.

11. The method of forming a memory of claim 9, wherein, In the step of forming the first source region and the second drain region, the second drain region is adjacent to and integral with the first source region closest to the floating gate structure.

12. The method of forming a memory of claim 9, wherein, After forming the first source region, the first drain region, the second source region and the second drain region, the forming method further comprises: forming a source line plug on top of the first drain region, and the source line plug is electrically connected with the first drain region; forming a first source region plug on top of the first source region, and the first source region plug is electrically connected with the first source region; forming a word line plug on top of the select gate structure, and the word line plug is electrically connected with the select gate structure; forming a bit line plug on top of the second source region, and the bit line plug is electrically connected with the second source region.

13. The method of forming a memory of claim 12, wherein, In the step of forming the source line plug, the number of source line plugs on the same first drain region is multiple and arranged in sequence along the first direction; In the step of forming the first source region plug, the number of first source region plugs on the same first source region is multiple and arranged in sequence along the first direction; In the step of forming the bit line plug, the number of bit line plugs on the same second source region is multiple and arranged in sequence along the first direction.

14. The method of forming a memory of claim 9, wherein, In the step of forming the select gate structure, the select gate structure further comprises a second gate connected with each first gate and extending along the second direction; After forming the first source region, the first drain region, the second source region and the second drain region, the forming method further comprises: forming a word line plug on top of the second gate, and the number of word line plugs is multiple and arranged in sequence along the second direction.

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