Control circuit, chip and equipment

Abstract

The invention provides a control circuit, a chip and equipment, and belongs to the field of interface circuits, the control circuit comprises a first phase inverter, a second phase inverter and a second logic unit, when a signal control terminal of a controller of electronic equipment outputs a first level signal, the first logic unit is switched on, and the second logic unit is switched off; therefore, the equipment receives a communication signal; and when the signal control terminal of the controller of the electronic equipment outputs a second level signal, the second logic unit is switched on and the first logic unit is switched off, so that the equipment sends a communication signal, double-wire transmission is converted into single-wire transmission, the space structure of the equipment is simplified, the occupied space is reduced, and the communication efficiency is improved. And therefore, the equipment is lighter and smaller.

Description

Technical Field

[0001] The present application relates to the technical field of interface circuits, and in particular to a control circuit, a chip and a device. Background Art

[0002] With the continuous development of science and technology, augmented reality (AR) glasses are becoming more and more popular, and more and more requirements are being put forward for the battery life and communication functions of AR glasses. For this reason, existing AR glasses are generally equipped with charging interfaces and communication interfaces, such as using 2 type-C interfaces for charging and 2 Pogo Pins for data transmission. However, AR glasses themselves are similar to traditional glasses in appearance and structure. Such a design not only increases the weight of AR glasses, but also is not conducive to product lightweighting and miniaturization.

[0003] Therefore, how to set up the communication method of AR glasses to reduce the occupied space is a problem that needs to be solved urgently. Summary of the invention

[0004] The main purpose of this application is to provide a control circuit, chip and device, aiming to simplify the spatial structure of the device to reduce the occupied space and make the device more lightweight.

[0005] In a first aspect, the present application provides a control circuit, applied to an electronic device, the circuit comprising:

[0006] A first inverter, wherein an input end of the first inverter is connected to a signal control terminal of a controller of the electronic device;

[0007] A second inverter, wherein an input terminal of the second inverter is connected to an output terminal of the first inverter;

[0008] A first logic unit, wherein a first control end of the first logic unit is connected to an output end of the first inverter, a second control end of the first logic unit is connected to an output end of the second inverter, a first terminal of the first logic unit is connected to a signal receiving terminal of a controller of the electronic device, and a second terminal of the first logic unit is connected to an IO terminal;

[0009] a second logic unit, wherein a first control end of the second logic unit is connected to the output end of the second inverter, a second control end of the second logic unit is connected to the output end of the first inverter, a first terminal of the second logic unit is connected to a signal sending terminal of a controller of the electronic device, and a second terminal of the second logic unit is connected to an IO terminal;

[0010] When the signal control terminal of the controller of the electronic device outputs a first level signal, the first logic unit is turned on and the second logic unit is turned off; when the signal control terminal of the controller of the electronic device outputs a second level signal, the second logic unit is turned on and the first logic unit is turned off, so as to realize the conversion of two-line transmission into single-line transmission.

[0011] In a second aspect, the present application further provides a control chip, wherein the control chip comprises the control circuit of any embodiment of the present invention.

[0012] In a third aspect, the present application further provides an electronic device, the electronic device comprising:

[0013] Controller;

[0014] Storage;

[0015] The control chip, the controller, the storage and the are connected via a system bus.

[0016] The present application provides a control circuit, a chip and a device. The control circuit of the present application includes a first inverter, an input end of the first inverter is connected to a signal control terminal of a controller of an electronic device; a second inverter, an input end of the second inverter is connected to an output end of the first inverter; a first logic unit, a first control end of the first logic unit is connected to an output end of the first inverter, a second control end of the first logic unit is connected to an output end of the second inverter, a first terminal of the first logic unit is connected to a signal receiving terminal of the controller of the electronic device, and a second terminal of the first logic unit is connected to an IO terminal; a second logic unit, the first control end of the first logic unit is connected to an output end of the first inverter, a second control end of the first logic unit is connected to an output end of the second inverter, a first terminal of the first logic unit is connected to a signal receiving terminal of the controller of the electronic device, and a second terminal of the first logic unit is connected to an IO terminal; The first control end of the second logic unit is connected to the output end of the second inverter, the second control end of the second logic unit is connected to the output end of the first inverter, the first terminal of the second logic unit is connected to the signal sending terminal of the controller of the electronic device, and the second terminal of the second logic unit is connected to the IO terminal; wherein, when the signal control terminal of the controller of the electronic device outputs a first level signal, the first logic unit is turned on and the second logic unit is turned off; when the signal control terminal of the controller of the electronic device outputs a second level signal, the second logic unit is turned on and the first logic unit is turned off, so as to realize the conversion of two-wire transmission into single-wire transmission. In the present application, when the signal control terminal of the controller of the electronic device outputs a first level signal, the first logic unit is turned on and the second logic unit is turned off, so as to enable the device to receive communication signals; when the signal control terminal of the controller of the electronic device outputs a second level signal, the second logic unit is turned on and the first logic unit is turned off, so as to enable the device to send communication signals, so as to realize the conversion of two-wire transmission into single-wire transmission, simplify the spatial structure of the device, reduce the occupied space, and make the device more lightweight and miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A circuit diagram of a control circuit provided in an embodiment of the present application;

[0019] Figure 2 Another circuit diagram of a control circuit provided by an embodiment of the present application;

[0020] Figure 3 Another circuit diagram of a control circuit provided by an embodiment of the present application;

[0021] Figure 4 Another circuit diagram of a control circuit provided by an embodiment of the present application;

[0022] Figure 5 Another circuit diagram of a control circuit provided by an embodiment of the present application;

[0023] Figure 6 Another circuit diagram of a control circuit provided by an embodiment of the present application;

[0024] Figure 7 A schematic block diagram of the structure of a control chip provided in an embodiment of the present application;

[0025] Figure 8 A schematic block diagram of the structure of an electronic device provided in an embodiment of the present application.

[0026] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0029] The embodiment of the present application provides a control circuit, a chip and a device. The control circuit includes a first inverter, the input end of the first inverter is connected to the signal control terminal of the controller of the electronic device; a second inverter, the input end of the second inverter is connected to the output end of the first inverter; a first logic unit, the first control end of the first logic unit is connected to the output end of the first inverter, the second control end of the first logic unit is connected to the output end of the second inverter, the first terminal of the first logic unit is connected to the signal receiving terminal of the controller of the electronic device, and the second terminal of the first logic unit is connected to the IO terminal; a second logic unit, the first control end of the second logic unit is connected to the output end of the second inverter, the second control end of the second logic unit is connected to the output end of the first inverter, the first terminal of the second logic unit is connected to the signal sending terminal of the controller of the electronic device, and the second terminal of the second logic unit is connected to the IO terminal; wherein, when the signal control terminal of the controller of the electronic device outputs a first level signal, the first logic unit is turned on and the second logic unit is turned off; when the signal control terminal of the controller of the electronic device outputs a second level signal, the second logic unit is turned on and the first logic unit is turned off, so as to realize the conversion of two-line transmission into single-line transmission.

[0030] Among them, the control circuit can be applied to electronic devices, which can be electronic devices such as AR glasses, VR glasses, smart watches and smart bracelets.

[0031] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0032] Please refer to Figure 1 , Figure 1 A circuit diagram of a control circuit provided in an embodiment of the present application.

[0033] like Figure 1 As shown, the control circuit is applied to an electronic device, and the control circuit 100 includes a first inverter 110, a second inverter 120, a first logic unit 130, and a second logic unit 140. The input end of the first inverter 110 is connected to the signal control terminal of the controller of the electronic device 200, and the input end of the second inverter 120 is connected to the output end of the first inverter 110.

[0034] In some embodiments, the first control end of the first logic unit 130 is connected to the output end of the first inverter 110, the second control end of the first logic unit 130 is connected to the output end of the second inverter 120, the first terminal of the first logic unit 130 is connected to the signal receiving terminal of the controller of the electronic device 200, and the second terminal of the first logic unit 130 is connected to the IO terminal 150.

[0035] In some embodiments, the first control end of the second logic unit 140 is connected to the output end of the second inverter 120, the second control end of the second logic unit 140 is connected to the output end of the first inverter 110, the first terminal of the second logic unit 140 is connected to the signal sending terminal of the controller of the electronic device 200, and the second terminal of the second logic unit 140 is connected to the IO terminal 150.

[0036] It should be noted that the electronic devices include but are not limited to AR glasses, VR glasses, smart watches, smart bracelets and other electronic devices, and the external devices include but are not limited to mobile phones, tablets, laptops, desktop computers and chargers and other devices.

[0037] In some embodiments, when the signal control terminal of the controller of the electronic device 200 outputs a first level signal, the first logic unit 130 is turned on and the second logic unit 140 is turned off; when the signal control terminal of the controller of the electronic device 200 outputs a second level signal, the second logic unit 140 is turned on and the first logic unit 130 is turned off, so as to convert two-line transmission into single-line transmission.

[0038] When a first level signal is output through the signal control terminal of the controller of the electronic device, the first logic unit is turned on and the second logic unit is disconnected, so that the device receives a communication signal; when a second level signal is output through the signal control terminal of the controller of the electronic device, the second logic unit is turned on and the first logic unit is disconnected, so that the device sends a communication signal, thereby realizing that the same IO terminal can be used for sending and receiving communication signals, so as to realize the conversion of two-line signal transmission into single-line signal transmission, that is, the sending and receiving of communication signals can be completed using one communication line, which effectively reduces the equipment space required to be occupied and facilitates the overall lightweight and miniaturization of the equipment.

[0039] It should be noted that the first level signal is an electrical signal whose level voltage value is greater than the preset voltage value, and the second level signal is an electrical signal whose level voltage value is less than the preset voltage value. It can be understood that the signal control terminal of the controller outputs an electrical signal greater than the preset voltage value, that is, outputs the first level signal, and the signal control terminal of the controller outputs an electrical signal less than the preset voltage value, that is, outputs the second level signal. In the embodiment of the present application, the electrical signals whose level voltage value is greater than the preset voltage value are all first level signals, and the electrical signals whose level voltage value is less than the preset voltage value are all first level signals. Among them, the preset voltage value can be set according to actual conditions, and the embodiment of the present invention does not specifically limit this. For example, the preset voltage value can be set to 1.5v.

[0040] For example, Figure 1 As shown, when the signal control terminal of the controller of the electronic device 200 outputs a first level signal, the first inverter 110 outputs a second level signal, the second inverter 120 outputs a first level signal, the first control terminal of the first logic unit 130 inputs the second level signal, the second control terminal of the first logic unit 130 inputs the first level signal, the first logic unit 130 converts the second level signal input to the first control terminal into a first level signal, and performs AND processing on the first level signal and the first level signal input to the second control terminal to obtain a first level signal, when the electrical signal output by the first logic unit 130 is the first level signal, the first logic unit 130 is turned on; and the controller of the electronic device 200 When the signal control terminal outputs a first level signal, the first control end of the second logic unit 140 inputs a first level signal, and the second control end of the second logic unit 140 inputs a second level signal. The second logic unit 140 converts the first level signal input to the first control end into a second level signal, and processes the second level signal and the second level signal input to the second control end to obtain a second level signal. When the electrical signal output by the second logic unit 140 is a second level signal, the second logic unit 140 is disconnected, that is, the first logic unit 130 is turned on, and the second logic unit 140 is disconnected, so that the IO terminal 150 is turned on with the signal receiving terminal of the electronic device 200, so that the electronic device receives a signal.

[0041] It should be noted that when the first logic unit and / or the second logic unit outputs a first level signal, the first logic unit and / or the second logic unit is turned on, and when the first logic unit and / or the second logic unit outputs a second level signal, the first logic unit and / or the second logic unit is turned off.

[0042] For example, Figure 1As shown, when the signal control terminal of the controller of the electronic device 200 outputs the second level signal, the first inverter 110 outputs the first level signal, the second inverter 120 outputs the second level signal, the first control terminal of the first logic unit 130 inputs the first level signal, the second control terminal of the first logic unit 130 inputs the second level signal, the first logic unit 130 converts the first level signal input to the first control terminal into a second level signal, and performs AND processing on the second level signal and the second level signal input to the second control terminal to obtain the second level signal, when the electrical signal output by the first logic unit 130 is the second level signal, the first logic unit 130 is disconnected; and the controller of the electronic device 200 When the signal control terminal outputs a second level signal, the first control terminal of the second logic unit 140 inputs a second level signal, and the second control terminal of the second logic unit 140 inputs a first level signal. The second logic unit 140 converts the second level signal input from the first control terminal into a first level signal, and processes the first level signal and the first level signal input from the second control terminal to obtain a first level signal. When the electrical signal output by the second logic unit 140 is a first level signal, the second logic unit 140 is turned on, that is, the first logic unit 130 is disconnected, and the second logic unit 140 is turned on, so that the IO terminal 150 is connected to the signal sending terminal of the electronic device 200, so that the electronic device sends a signal.

[0043] It can be understood that, by outputting the first level signal or the second level signal through the signal control terminal of the controller of the electronic device 200, the IO terminal and the sending terminal of the controller of the electronic device 200 are controlled to be turned on or off, and the IO terminal and the receiving terminal of the controller of the electronic device 200 are controlled to be turned on or off, so that the same IO terminal can be used for sending and receiving communication signals, thereby realizing the transformation of two-line transmission into single-line transmission.

[0044] In some embodiments, Figure 2 As shown, the first logic unit 130 includes a first NOT gate 131 and a first AND gate 132, the input end of the first NOT gate 131 is connected to the output end of the first inverter 110, the output end of the first NOT gate 131 is connected to the first input end of the first AND gate 132, and the second input end of the first AND gate 132 is connected to the output end of the second inverter 120.

[0045] In some embodiments, Figure 2 As shown, the second logic unit 140 includes a second NOT gate 141 and a second AND gate 142, the input end of the second NOT gate 141 is connected to the output end of the second inverter 120, the output end of the second NOT gate 141 is connected to the first input end of the second AND gate 142, and the second input end of the second AND gate 142 is connected to the output end of the first inverter 110.

[0046] For example, Figure 2 As shown, when the signal control terminal of the controller of the electronic device 200 outputs a first level signal, the first inverter 110 outputs a second level signal, the second inverter 120 outputs a first level signal, the input end of the first NOT gate 131 receives the second level signal output from the output end of the first inverter 110, and the output end of the first NOT gate 131 outputs a first level signal; the first input end of the first AND gate 132 receives the first level signal output from the output end of the second inverter 120, and the second input end of the first AND gate 132 inputs the first level signal, wherein the first AND gate 132 performs AND processing on the first level signal input to the first input end and the first level signal input to the second input end, so that the first AND gate 132 outputs the first level signal, and when the first AND gate 132 outputs the first level signal, the first logic unit 130 is turned on to connect the IO terminal with the receiving terminal of the controller of the electronic device 200.

[0047] The second NOT gate 141 inputs a first level signal and outputs a second level signal, the first input terminal of the second AND gate 142 inputs a second level signal, and the second input terminal of the second AND gate 142 inputs a second level signal, wherein the second AND gate 142 performs AND processing on the second level signal input to the first input terminal and the second level signal input to the second input terminal, so that the second AND gate 142 outputs the second level signal, and when the second AND gate 142 outputs the second level signal, the second logic unit 140 is disconnected, so that the IO terminal is disconnected from the sending terminal of the controller of the electronic device 200. Then the electronic device receives data through the IO terminal.

[0048] For example, Figure 2 As shown, when the signal control terminal of the controller of the electronic device 200 outputs the second level signal, the first inverter 110 outputs the first level signal, the second inverter 120 outputs the second level signal, the first NOT gate 131 inputs the first level signal and outputs the second level signal; the first input terminal of the first AND gate 132 inputs the second level signal, and the second input terminal of the first AND gate 132 inputs the second level signal, wherein the first AND gate 132 performs AND processing on the second level signal input to the first input terminal and the second level signal input to the second input terminal, so that the first AND gate 132 outputs the second level signal, and when the first AND gate 132 outputs the second level signal, the first logic unit 130 is disconnected to disconnect the IO terminal from the receiving terminal of the controller of the electronic device 200.

[0049] The second NOT gate 141 inputs a second level signal and outputs a first level signal, the first input terminal of the second AND gate 142 inputs a first level signal, and the second input terminal of the second AND gate 142 inputs a first level signal, wherein the second AND gate 142 performs AND processing on the first level signal input to the first input terminal and the first level signal input to the second input terminal, so that the second AND gate 142 outputs the first level signal, and when the second AND gate 142 outputs the first level signal, the second logic unit 140 is turned on to connect the IO terminal with the sending terminal of the controller of the electronic device 200. Then the electronic device sends data through the IO terminal.

[0050] In some embodiments, Figure 3 As shown, the control circuit 100 also includes a level control unit 160, a first end of the level control unit 160 is connected to the IO terminal 150, and a second end of the level control unit 160 is connected to a common terminal, which is a connection point between the second terminal of the first logic unit 130 and the second terminal of the second logic unit 140.

[0051] In some embodiments, Figure 3 As shown, the level control unit 160 includes a first NMOS tube 161 and a second NMOS tube 162, the gate of the first NMOS tube 161 and the gate of the second NMOS tube 162 are both connected to the preset power supply 170, the drain of the first NMOS tube 161 is connected to the IO terminal 150, the source of the first NMOS tube 161 is connected to the source of the second NMOS 162, and the drain of the second NMOS tube 162 is connected to a common terminal, which is the connection point of the second terminal of the first logic gate 130 and the second terminal of the second logic gate 140.

[0052] In some embodiments, when the signal control terminal of the controller of the electronic device 200 outputs a first level signal, the electronic device enters a communication signal receiving mode. When a high level signal is input to the IO terminal, the voltage difference between the gate and source of the first NMOS tube 161 and the second NMOS tube 162 does not meet the conduction condition, so that the first NMOS tube 161 and the second NMOS tube 162 are in a closed state. Since the signal receiving terminal of the controller of the electronic device 200 is connected to a pull-up voltage by default, the controller of the electronic device 200 receives a high level signal.

[0053] In some embodiments, when the signal control terminal of the controller of the electronic device 200 outputs a first level signal, the electronic device enters a communication signal receiving mode, wherein the first NMOS tube 161 has a built-in first diode, the anode of the first diode is connected to the source of the first NMOS tube 161, and the cathode of the first diode is connected to the drain of the first NMOS tube 161, and the second NMOS tube 162 has a built-in second diode, the anode of the second diode is connected to the source of the second NMOS tube 162, and the cathode of the second diode is connected to the drain of the second NMOS tube 162. When the IO terminal inputs a low-level signal, the first diode is unidirectionally conducted, so that the voltage difference between the gate and source of the first NMOS tube 161 and the second NMOS tube 162 meets the conduction condition, so that the first NMOS tube 161 and the second NMOS tube 162 are turned on, and the low-level signal input by the IO terminal is transmitted to the signal receiving terminal of the controller, so that the controller of the electronic device 200 receives the low-level signal.

[0054] By controlling the on and off of the first NMOS transistor 161 and the second NMOS transistor 162 of the level control unit 160 , the controller of the electronic device 200 receives a low level signal or a high level signal.

[0055] In some embodiments, Figure 3 As shown, when the signal control terminal of the controller of the electronic device 200 outputs a second level signal, the electronic device enters a communication signal sending mode. When the signal sending terminal of the controller of the electronic device 200 outputs a high level signal, the voltage difference between the gate and source of the first NMOS tube 161 and the second NMOS tube 162 does not meet the conduction condition, so that the first NMOS tube 161 and the second NMOS tube 162 are in a closed state. Since the IO terminal is connected to the pull-up voltage by default, the IO terminal outputs a high level signal, thereby enabling the electronic device to accurately send a high level signal.

[0056] In some embodiments, Figure 3As shown, when the signal control terminal of the controller of the electronic device 200 outputs the second level signal, the electronic device enters the communication signal sending mode, wherein the first NMOS tube 161 has a built-in first diode, the anode of the first diode is connected to the source of the first NMOS tube 161, and the cathode of the first diode is connected to the drain of the first NMOS tube 161, and the second NMOS tube 162 has a built-in second diode, the anode of the second diode is connected to the source of the second NMOS tube 162, and the cathode of the second diode is connected to the drain of the second NMOS tube 162. When the signal sending terminal of the controller of the electronic device 200 outputs a low level signal, the first diode is unidirectionally conducted, so that the voltage difference between the gate and the source of the first NMOS tube 161 and the second NMOS tube 162 meets the conduction condition, so that the first NMOS tube 161 and the second NMOS tube 162 are turned on, and the signal sending terminal outputs a low level signal, which is transmitted to the IO terminal through the first NMOS tube 161 and the second NMOS tube 162, and the low level signal is sent through the IO terminal, thereby enabling the electronic device to accurately send a low level signal.

[0057] In some embodiments, Figure 4 As shown, the control circuit also includes a charging interface 180 and a charging communication switching module 190. The charging interface 180 includes a first pin 181 and a second pin 182. The charging interface 181 is used to connect an external device that can communicate and / or supply power. The charging communication switching module 190 includes a charging communication terminal, a charging terminal, and a communication terminal. The charging communication terminal is connected to the first pin 181. The charging terminal is used to supply power or charge the electronic device. The communication terminal is connected to the level control unit 160.

[0058] In some embodiments, when the voltage at the charging communication terminal is greater than or equal to the first preset voltage, the charging communication terminal and the communication terminal are controlled to be turned on so that the electronic device communicates with the external device through the first pin. When the voltage at the charging communication terminal is greater than or equal to the second preset voltage, the charging communication terminal and the charging terminal are controlled to be turned on so that the external device can power the electronic device through the first pin, and the second preset voltage is greater than the first preset voltage. Among them, the first preset voltage and the second preset voltage can be set according to actual conditions, and the embodiment of the present invention does not specifically limit this. For example, the first preset voltage can be set to 1.5v, and the preset second voltage can be set to 5v.

[0059] In some embodiments, Figure 5As shown, the charging communication switching module 190 includes a charging unit 191, and the charging unit 191 includes a first PMOS tube 1911. The gate of the first PMOS tube 1911 is connected to a preset power supply, the source of the first PMOS tube 1911 is connected to a first pin 181, and the source drain of the first PMOS tube 1911 is connected to a charging terminal. The voltage of the preset power supply is greater than the first preset voltage and less than the second preset voltage.

[0060] For example, Figure 2 As shown, when the first pin 181 is connected to the first preset voltage, the first PMOS tube 1911 is disconnected, and when the first pin 181 is connected to the second preset voltage, the first PMOS tube 1911 is turned on, so that the external device can power the electronic device 200 through the first pin 181.

[0061] In some embodiments, Figure 5 As shown, the charging communication switching module 190 includes a communication unit 192, and the communication unit 192 includes a third NMOS tube 1921 and a second PMOS tube 1922; the gate of the third NMOS tube 1921 is connected to the preset power supply 170, the source of the third NMOS tube 1921 is connected to the charging communication terminal, the drain of the third NMOS tube 1921 is connected to the gate of the second PMOS tube 1922 and is connected to the preset power supply, the source of the second PMOS tube is connected to the preset power supply, and the drain of the second PMOS tube 1922 is connected to the level control unit 160.

[0062] In some embodiments, the control circuit further includes a resistor R1 and a resistor R2, wherein one end of the resistor R1 is connected to the source of the third NMOS transistor 1921 and the other end is grounded. One end of the resistor R2 is connected to the gate of the second PMOS transistor 1922 and the other end is connected to a preset power supply.

[0063] Exemplarily, the voltage connected to the first pin 181 is less than the preset second voltage, the first PMOS tube 1911 is disconnected, that is, the charging link is disconnected; the voltage connected to the first pin 181 is divided by the resistor R1 to turn on the third NMOS tube 1921, and the resistor R2 divides the voltage input to the gate of the second PMOS tube 1922 to turn on the second PMOS tube, so that the gates of the first NMOS tube and the second NMOS tube of the level control unit 160 are connected to the preset power supply. This facilitates the transmission of high and low level signals during communication transmission.

[0064] In some embodiments, Figure 6 As shown, the control circuit further includes a protection circuit 210, and the protection circuit 210 includes a first diode; the anode of the first diode is connected to the first pin 181, and the cathode is connected to the charging communication terminal. The first diode can effectively prevent current backflow.

[0065] It should be noted that a second diode may also be provided between the source of the third NMOS tube 1921 and the charging communication terminal. The anode of the second diode is connected to the charging communication terminal, and the cathode is connected to the third NMOS tube 1921, which can effectively prevent current backflow.

[0066] The control circuit provided in the above embodiment includes a first inverter, the input end of which is connected to the signal control terminal of the controller of the electronic device; a second inverter, the input end of which is connected to the output end of the first inverter; a first logic unit, the first control end of which is connected to the output end of the first inverter, the second control end of which is connected to the output end of the second inverter, the first terminal of which is connected to the signal receiving terminal of the controller of the electronic device, and the second terminal of which is connected to the IO terminal; a second logic unit, the first control end of which is connected to the output end of the second inverter, the second control end of which is connected to the output end of the first inverter, the first terminal of which is connected to the signal sending terminal of the controller of the electronic device, and the second terminal of which is connected to the IO terminal; wherein, when the signal control terminal of the controller of the electronic device outputs a first level signal, the first logic unit is turned on and the second logic unit is turned off; when the signal control terminal of the controller of the electronic device outputs a second level signal, the second logic unit is turned on and the first logic unit is turned off, so as to realize the conversion of two-wire transmission into single-wire transmission. In the present application, when a first level signal is output through the signal control terminal of the controller of the electronic device, the first logic unit is turned on and the second logic unit is disconnected, so that the device receives communication signals; when a second level signal is output through the signal control terminal of the controller of the electronic device, the second logic unit is turned on and the first logic unit is disconnected, so that the device sends communication signals, so as to realize the conversion of two-line transmission into single-line transmission, simplify the spatial structure of the device, reduce the occupied space, and make the device more lightweight and miniaturized.

[0067] See also Figure 7 , Figure 7 A schematic block diagram of the structure of a control chip provided in an embodiment of the present application.

[0068] As shown in the figure, the control chip 300 includes a control circuit 310 of any embodiment of the present application, and the control chip is used to power or communicate with the electronic device.

[0069] It should be noted that those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-mentioned control chip can refer to the corresponding process in the aforementioned control circuit embodiment, and will not be repeated here.

[0070] See also Figure 8 , Figure 8 A schematic block diagram of the structure of an electronic device provided in an embodiment of the present application.

[0071] like Figure 8 As shown, the electronic device 400 includes:

[0072] Controller 410;

[0073] Storage 420;

[0074] The control chip 430 in any embodiment of the present application, wherein the controller 410 , the storage 420 and the control chip 430 are connected via a system bus 440 .

[0075] It should be noted that the electronic device includes but is not limited to AR glasses, VR glasses, smart watches, smart bracelets and other electronic devices.

[0076] The controller is used to provide computing and control capabilities to support the operation of the entire electronic device.

[0077] Those skilled in the art will understand that Figure 8 The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0078] It should be noted that those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-mentioned electronic device can refer to the corresponding process in the aforementioned control circuit embodiment, and will not be repeated here.

[0079] It should be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0080] It should also be understood that the term "and / or" used in the present specification refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations. It should be noted that, in this article, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "including a..." does not exclude the presence of other identical elements in the process, method, article or system including the element.

[0081] The serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments. The above description is only a specific implementation mode of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A control circuit, characterized in that: Applied to electronic equipment, the circuit comprises: A first inverter, wherein an input end of the first inverter is connected to a signal control terminal of a controller of the electronic device; A second inverter, wherein an input terminal of the second inverter is connected to an output terminal of the first inverter; A first logic unit, wherein a first control end of the first logic unit is connected to an output end of the first inverter, a second control end of the first logic unit is connected to an output end of the second inverter, a first terminal of the first logic unit is connected to a signal receiving terminal of a controller of the electronic device, and a second terminal of the first logic unit is connected to an IO terminal; a second logic unit, wherein a first control end of the second logic unit is connected to the output end of the second inverter, a second control end of the second logic unit is connected to the output end of the first inverter, a first terminal of the second logic unit is connected to a signal sending terminal of a controller of the electronic device, and a second terminal of the second logic unit is connected to an IO terminal; When the signal control terminal of the controller of the electronic device outputs a first level signal, the first logic unit is turned on and the second logic unit is turned off; when the signal control terminal of the controller of the electronic device outputs a second level signal, the second logic unit is turned on and the first logic unit is turned off, so as to realize the conversion of two-line transmission into single-line transmission.

2. The control circuit according to claim 1, characterized in that: The first logic unit includes a first NOT gate and a first AND gate, the input end of the first NOT gate is connected to the output end of the first inverter, the output end of the first NOT gate is connected to the first input end of the first AND gate, and the second input end of the first AND gate is connected to the output end of the second inverter; The second logic unit includes a second NOT gate and a second AND gate, the input end of the second NOT gate is connected to the output end of the second inverter, the output end of the second NOT gate is connected to the first input end of the second AND gate, and the second input end of the second AND gate is connected to the output end of the first inverter.

3. The control circuit according to claim 1, characterized in that: The control circuit also includes a level control unit, a first end of the level control unit is connected to the IO terminal, and a second end of the level control unit is connected to a common terminal, and the common terminal is a connection point between the second terminal of the first logic unit and the second terminal of the second logic unit.

4. The control circuit according to claim 3, characterized in that: The level control unit includes a first NMOS tube and a second NMOS tube. The gate of the first NMOS tube and the gate of the second NMOS are both connected to a preset power supply, the drain of the first NMOS tube is connected to the IO terminal, the source of the first NMOS tube is connected to the source of the second NMOS tube, and the drain of the second NMOS tube is connected to a common terminal, and the common terminal is a connection point between the second terminal of the first non-AND gate and the second terminal of the second non-AND gate.

5. The control circuit according to claim 3, characterized in that: The control circuit further includes a charging interface and a charging communication switching module, wherein the charging interface includes a first pin and a second pin, and the charging interface is used to connect an external device, and the external device can communicate and / or supply power; The charging communication switching module comprises a charging communication terminal, a charging terminal and a communication terminal, wherein the charging communication terminal is connected to the first pin, the charging terminal is used to supply power or charge the electronic device, and the communication terminal is connected to the level control unit; When the voltage at the charging communication terminal is greater than or equal to a first preset voltage, the charging communication terminal and the communication terminal are controlled to be turned on so that the electronic device communicates with an external device through the first pin. When the voltage at the charging communication terminal is greater than or equal to a second preset voltage, the charging communication terminal and the charging terminal are controlled to be turned on so that the external device supplies power to the electronic device through the first pin. The second preset voltage is greater than the first preset voltage.

6. The control circuit according to claim 5, characterized in that: The charging communication switching module includes a charging unit, and the charging unit includes a first PMOS tube, a gate of the first PMOS tube is connected to a preset power supply, a source of the first PMOS tube is connected to the first pin, a source drain of the first PMOS tube is connected to the charging terminal, and a voltage of the preset power supply is greater than the first preset voltage and less than the second preset voltage.

7. The control circuit according to claim 5, characterized in that: The charging communication switching module includes a communication unit, which includes a third NMOS tube and a second PMOS tube; the gate of the third NMOS tube is connected to a preset power supply, the source of the third NMOS tube is connected to the charging communication terminal, the drain of the third NMOS tube is connected to the gate of the second PMOS tube and connected to the preset power supply, the source of the second PMOS tube is connected to the preset power supply, and the drain of the second PMOS tube is connected to the level control unit.

8. The control circuit according to claim 5, characterized in that: The control circuit further includes a protection circuit, wherein the protection circuit includes a first diode; The anode of the first diode is connected to the first pin, and the cathode of the first diode is connected to the charging communication terminal.

9. A control chip, characterized in that: include: A control circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: include: Controller; Storage; The control chip as claimed in claim 9, wherein the controller, the memory and the are connected via a system bus.

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