Low-power-consumption MCU power management unit realized by using asynchronous circuit

Abstract

The invention relates to the field of chip design, in particular to a low-power-consumption MCU (Microprogrammed Control Unit) power management unit realized by using an asynchronous circuit. Isolation unit control, voltage-stabilized power supply control, HSI clock control and VCORE domain reset control are asynchronously realized through the trigger and a series of delay chains. Compared with a PMU realized based on a state machine, the PMU is designed in a fully asynchronous manner, a clock is not needed during working, the dynamic power consumption of the PMU is reduced, and the power consumption required for maintaining clock operation in a low-power-consumption mode is saved. Compared with a PMU which is realized by a state machine and needs to start to work after a clock is stable, the method provided by the invention starts to work after a wake-up mark is effective, so that the wake-up response time of the chip is effectively shortened.

Description

Technical Field

[0001] The invention relates to the field of chip design, and in particular to a low-power MCU power management unit implemented by using an asynchronous circuit. Background Art

[0002] With the continuous development of IoT technology, MCU plays an increasingly important role in it. Power consumption is an important indicator for measuring an MCU. Reducing MCU power consumption can not only extend the working time of the IoT system in a battery-powered environment, but also reduce the operating temperature of the MCU chip, thereby extending the service life of the chip. At present, the main low-power processing method is to divide the chip into multiple power domains, and then turn off the clock and power supply inside the MCU as much as possible when the CPU is not working. This is usually achieved through the power management unit (PMU) in conjunction with the clock, reset, isolation unit, power switch, etc. to control the low power consumption of the MCU. In the existing scheme, the PMU is usually implemented based on the state machine, and the circuit control is completed by jumping to different states. This implementation method usually has two disadvantages. First, the state machine is a timing circuit, which requires a clock when working. The PMU implemented based on the state machine will generate a lot of dynamic power consumption when working, and even in low-power mode, it is impossible to turn off all clock sources, otherwise the PMU will not be able to perform the wake-up operation. In addition, even if the clock source can be turned off in low-power mode by using an asynchronous wake-up circuit, the PMU needs to wait for the clock to recover before it can start working, thus increasing the recovery time when the chip wakes up. Summary of the invention

[0003] The purpose of this patent is to solve the problem of the shortcomings of the existing MCU power management unit implementation technology by providing a power management unit implemented by an asynchronous circuit to effectively reduce power consumption and area cost, while shortening the response time of waking up from low power mode.

[0004] The present invention provides the following technical solutions:

[0005] The present invention provides a low-power MCU power management unit implemented by asynchronous circuit, referred to as PMU, wherein the MCU includes LDO, HSI, ISO, VCORE domain, and HSION register; the output signal of the VCORE domain is output to other modules after passing through ISO;

[0006] The PMU includes an isolation control module, a power-on control module, and a delayed wake-up module;

[0007] Among them, the isolation control module outputs Iso_on to ISO as an enable signal of ISO;

[0008] The Isolation Control Module is configured as:

[0009] When Por_rstn_dly is in the power-on reset state or Iso_clamp is in the valid state, Iso_on is set to the valid state; wherein, Por_rstn_dly is Por_rstn released after delay, and Por_rstn is the power-on reset signal; Iso_clamp is the signal obtained by Standby_en after delay chain delay, and Standby_en is the low power mode switching enable signal;

[0010] When the first condition changes from an unsatisfied state to a satisfied state, after a delay in the delay chain, Iso_on is set to an invalid state, and the content of the first condition is that Por_rstn_dly is in a reset release state and Standby_rstn is in an invalid state; wherein Standby_rstn is a VCORE domain reset signal, and when Standby_rstn is valid, the VCORE domain is reset;

[0011] The power-on control module outputs Ldo_on to the LDO as an enable signal of the LDO;

[0012] The power-on control module is configured as:

[0013] When Por_rstn_dly is in the power-on reset state or the wake-up condition is met, Ldo_on is set to the valid state; wherein the wake-up condition includes the wake-up flag signal Stdby_wkup_src being in the valid state, wherein Ldo_on_dly is Ldo_on after being delayed by the delay chain;

[0014] When Iso_on_dly changes from invalid to valid, Ldo_on is set to invalid state; where Iso_on_dly is Iso_on after being delayed by the delay chain;

[0015] Among them, the delayed wake-up module outputs Standby_rstn;

[0016] The delayed wake-up module is configured as:

[0017] When Por_rstn_dly is in the power-on reset state, Standby_rstn is set to the invalid state;

[0018] When the wake-up condition changes from not satisfied to satisfied, Standby_rstn is set to a valid state. When the preset wake-up time is delayed, Standby_rstn is set to an invalid state.

[0019] The core circuit of the present invention patent only uses several delay chains to complete all timing control, does not rely on the clock, reduces the dynamic power consumption of the PMU, and has a simpler circuit structure than the PMU implemented by the state machine. Compared with the PMU implemented by the state machine, which needs to wait for the clock to stabilize before starting to work, the present invention patent starts working after the wake-up flag is valid, effectively shortening the wake-up response time of the chip.

[0020] Furthermore, when the enable signals sent by the LDO and HSION register to the HSI are both valid, the HSI is turned on, otherwise the HSI is turned off; after the output voltage of the LDO reaches the threshold and lasts for a preset time, the enable signal sent by the LDO to the HSI is valid;

[0021] The external wiring of the PMU is configured as:

[0022] When Por_rstn_dly is in the power-on reset state or Standby_rstn is in the valid state, the VCORE domain is reset, and the HSION register is reset, so that the enable signal sent by the HSION register to the HSI is set valid.

[0023] This solution indirectly controls the HSI clock source enable by controlling LDO enable and Standby_rstn, thereby achieving hardware control of HSI without affecting software control of HSI.

[0024] Furthermore, the delayed wake-up module uses the clock signal Hsi_clk generated by HSI for timing when delaying the preset wake-up time.

[0025] This solution uses the clock signal Hsi_clk for timing, thereby ensuring that the VCORE domain reset is released after the HSI clock is stable.

[0026] Furthermore, the wake-up condition also includes Ldo_on_dly being in an invalid state.

[0027] This solution shields the wake-up flag signal before the power-off process ends (Ldo_on_dly has not yet become invalid) to prevent the circuit from being woken up by mistake.

[0028] Further, the isolation control module includes a DFF trigger ISO_ON and a delay chain;

[0029] The data input terminal D of ISO_ON is always 1, and the positive output terminal Q is connected to Iso_on;

[0030] Use a delay chain to delay Standby_en to get Iso_clamp, perform a logical OR operation on Iso_clamp and the inverted Por_rstn_dly, and then connect it to the high-level active reset input of ISO_ON;

[0031] After the logical AND operation of Por_rstn_dly and Standby_rstn is performed, the operation result is delayed by the delay chain and then connected to the rising edge trigger clock input terminal of ISO_ON;

[0032] Among them, Iso_on and Standby_rstn are valid at low level, Standby_en is valid at high level, Por_rstn_dly power-on reset state is low level, reset release state is high level; Iso_on is set to 0 when ISO_ON is reset;

[0033] Further, the power-on control module includes a DFF trigger LDO_ON and a delay chain;

[0034] The data input terminal D of LDO_ON is always 1, and the inverting output terminal QN is connected to Ldo_on;

[0035] Use a delay chain to delay Iso_on and then connect it to the falling edge trigger clock input of LDO_ON;

[0036] After delaying Ldo_on using a delay chain, Ldo_on_dly is obtained. After Ldo_on_dly is inverted, a logical AND operation is performed with Stdby_wkup_src to obtain Ldo_on_set. After Ldo_on_set is inverted, a logical AND operation is performed with Por_rstn_dly, and then connected to the low-level effective reset input terminal of LDO_ON.

[0037] Among them, Ldo_on and Stdby_wkup_src are valid at high level, and Iso_on is valid at low level; Por_rstn_dly power-on reset state is low level, and reset release state is high level; Ldo_on is set to 1 when LDO_ON is reset;

[0038] Furthermore, the delayed wake-up module includes a DFF trigger LDO_HSI_ON, a counter Standby_rstn_cnt, a comparator, and a delay chain;

[0039] The data input terminal D of LDO_HSI_ON is always 1, the positive output terminal Q is connected to Ldo_hsi_on, and the inverting output terminal QN is connected to Standby_rstn; the result of the inverted Ldo_on_dly and the logical AND operation with Stdby_wkup_src is connected to the rising edge trigger input terminal of LDO_HSI_ON, where Ldo_on_dly is Ldo_on after the delay chain delay; Ldo_hsi_on is synchronized and input to the enable input terminal of Standby_rstn_cnt, and the clock signal Hsi_clk generated by HSI is connected to the rising edge trigger clock input terminal of Standby_rstn_cnt, and the count value H generated by Standby_rstn_cnt is si_cnt is connected to the input of the comparator, and the output of the comparator is connected to the Hsi_stable signal. When Hsi_cnt is equal to the set threshold n, Hsi_stable is set to 1, otherwise Hsi_stable is set to 0. Hsi_stable is delayed by a delay chain to obtain Hsi_stable_dly. Hsi_stable_dly is inverted and logically ANDed with Por_rstn_dly to obtain Ldo_hsi_on_rstn. Ldo_hsi_on_rstn is input to the low-level effective reset input of the LDO_HSI_ON trigger, and Ldo_hsi_on_rstn is input to the low-level effective reset input of Standby_rstn_cnt.

[0040] Among them, Standby_rstn is valid at a low level, Ldo_hsi_on, Ldo_on, and Stdby_wkup_src are valid at a high level; the power-on reset state of Por_rstn_dly is a low level, and the reset release state is a high level; when LDO_HSI_ON is reset, Ldo_hsi_on is set to 0 and Standby_rstn is set to 1.

[0041] Beneficial effects: The patent of the present invention asynchronously realizes isolation unit control, voltage-stabilized power supply control, HSI clock control and VCORE domain reset control through triggers and a series of delay chains. Compared with the PMU implemented based on the state machine, the patent of the present invention is a fully asynchronous design, which does not require a clock when working, reduces the dynamic power consumption of the PMU, and saves the power consumption required to maintain the clock operation in low-power mode. Compared with the PMU implemented by the state machine, which needs to wait for the clock to stabilize before starting to work, the patent of the present invention starts working after the wake-up flag is valid, effectively shortening the wake-up response time of the chip. From the perspective of circuit scale, the core circuit of the patent of the present invention only uses 3 triggers, 1 counter and several delay chains to complete all timing controls, which is simpler than the PMU circuit structure implemented by the state machine. The patent of the present invention can reset and release the VCORE domain when waking up, and automatically reset the internal counter after waking up, without software reset. The patent of the present invention indirectly controls the HSI clock source enable by controlling LDO enable and Standby_rstn, so that HSI can be controlled by hardware without affecting the control of HSI by software. Finally, the patent of the present invention can shield the wake-up flag signal before the power-off process ends to prevent the circuit from being woken up by mistake. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A structural diagram of an implementation mode of a power management unit in the present invention;

[0043] Figure 2 A structural diagram of an implementation mode of a peripheral circuit of a power management unit in the present invention;

[0044] Figure 3 is a timing control diagram of a power management unit in an embodiment of the present invention; DETAILED DESCRIPTION

[0045] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] A low-power MCU power management unit implemented using an asynchronous circuit, referred to as PMU, the MCU includes an LDO (linear regulated power supply), an HSI (high-speed internal oscillator), an ISO (isolation unit), a VCORE domain, and an HSION register; the output signal of the VCORE domain is output to other modules after passing through the ISO; when the enable signals sent by the LDO and the HSION register to the HSI are both valid, the HSI is turned on, otherwise the HSI is turned off; after the output voltage of the LDO reaches the threshold and lasts for a preset time, the enable signal sent to the HSI is valid;

[0047] The PMU includes an isolation control module, a power-on control module, and a delayed wake-up module;

[0048] Among them, the isolation control module outputs Iso_on to ISO as an enable signal of ISO;

[0049] The Isolation Control Module is configured as:

[0050] When Por_rstn_dly is in the power-on reset state or Iso_clamp is in the valid state, Iso_on is set to the valid state; wherein, Por_rstn_dly is Por_rstn released after delay, and Por_rstn is the power-on reset signal; Iso_clamp is the signal obtained by Standby_en after delay chain delay, and Standby_en is the low power mode switching enable signal;

[0051] When the first condition changes from an unsatisfied state to a satisfied state, after a delay in the delay chain, Iso_on is set to an invalid state, and the content of the first condition is that Por_rstn_dly is in a reset release state and Standby_rstn is in an invalid state; wherein Standby_rstn is a VCORE domain reset signal, and when Standby_rstn is valid, the VCORE domain is reset;

[0052] The power-on control module outputs Ldo_on to the LDO as an enable signal of the LDO;

[0053] The power-on control module is configured as:

[0054] When Por_rstn_dly is in the power-on reset state or the wake-up condition is met, Ldo_on is set to the valid state; wherein the wake-up condition includes that the wake-up flag signal Stdby_wkup_src is in the valid state and Ldo_on_dly is in the invalid state, wherein Ldo_on_dly is Ldo_on after being delayed by the delay chain;

[0055] When Iso_on_dly changes from invalid to valid, Ldo_on is set to invalid state; where Iso_on_dly is Iso_on after being delayed by the delay chain;

[0056] Among them, the delayed wake-up module outputs Standby_rstn;

[0057] The delayed wake-up module is configured as:

[0058] When Por_rstn_dly is in the power-on reset state, Standby_rstn is set to the invalid state;

[0059] When the wake-up condition changes from not satisfied to satisfied, Standby_rstn is set to the valid state. When the preset wake-up time is delayed, Standby_rstn is set to the invalid state.

[0060] The external wiring of the PMU is configured as:

[0061] When Por_rstn_dly is in the power-on reset state or Standby_rstn is in the valid state, the VCORE domain is reset, and the HSION register is reset, so that the enable signal sent by the HSION register to the HSI is set valid.

[0062] A more specific embodiment is described below:

[0063] The PMU is located in the 3.3V digital normally-on power domain of the MCU, which is powered by the chip power pin and remains powered when entering low-power mode.

[0064] The VCORE domain is located in the 1.1V digital power-down domain, which contains the MCU core, bus and various 1.1V digital peripherals, and is powered off when the chip enters a low power consumption mode.

[0065] The circuit architecture of the PMU is as follows: Figure 1 As shown, it consists of 3 DFF triggers (ISO_ON, LDO_ON, LDO_HSI_ON), ​​1 counter (Standby_rstn_cnt), 1 digital comparator (COMP), 5 groups of delay chains and several logic gates and synchronizers. The PMU completes asynchronous power-on and power-off timing control through 5 groups of delay chains without clock. The counter counts with the clock signal Hsi_clk to release the VCORE domain reset after the HSI clock is stable.

[0066] The PMU controls the ISO enable signal Iso_on and the LDO enable signal Ldo_on to be set to 0 when the chip enters the low power mode, controls Ldo_on to be set to 1 when exiting the low power mode, controls the VCORE domain reset signal Standby_rstn to be set to 0 and set to 1 after a period of time, and finally controls Iso_on to be set to 1 to release the isolation of the VCORE domain.

[0067] The Iso_on is a low-level effective ISO enable signal. When Iso_on is 0, the output signals of all VCORE domains are isolated. When Iso_on is 1, the isolation of the VCORE domain is released.

[0068] The Ldo_on is a high-level effective LDO enable signal. When Ldo_on is 1, the LDO is enabled to restore the power supply of the VCORE domain. When Ldo_on is 0, the LDO is disabled to power off the VCORE domain.

[0069] The Standby_rstn is a low-level effective VCORE domain reset signal. When Standby_rstn is 0, the VCORE domain is reset. When Standby_rstn is 1, the VCORE domain reset is released.

[0070] The circuit connection relationship of the PMU is as follows: Figure 1As shown, Por_rstn_dly and Standby_rstn are combined to obtain Iso_release_in. After a delay chain, Iso_release_in is delayed to obtain Iso_release and connected to the rising edge trigger clock input of the ISO_ON trigger. The Standby_en signal is delayed by a delay chain to obtain Iso_clamp. Iso_clamp and the inverted Por_rstn_dly are combined to obtain Iso_on_rst. Iso_on_rst is connected to the high level effective reset input of the ISO_ON trigger. The data input terminal D of the ISO_ON trigger is always 1, and the positive output terminal Q is connected to Iso_on. After a delay chain, Iso_on obtains Iso_on_dly and is input to the falling edge trigger clock input of the LDO_ON trigger. The data input terminal D of the LDO_ON is always 1, and the inverted output terminal QN is connected to Ldo_on to control the enablement of the 1.1V regulated power supply. Ldo_on passes through a set of delay chains to obtain Ldo_on_dly, which is inverted and combined with the wake-up flag signal Stdby_wkup_src to obtain Ldo_on_set. Ldo_on_set is inverted and combined with Por_rstn_dly to obtain the low-level effective reset input signal Ldo_on_rstn of the LDO_ON trigger. Ldo_on_set is also connected to the rising edge trigger clock input of the LDO_HSI_ON trigger, and the data input D of the LDO_HSI_ON trigger is always 1. The positive output Q of the LDO_HSI_ON trigger is connected to Ldo_Hsi_on, which is synchronized to the HSI clock through a two-stage synchronizer and used as the enable signal of the Standby_rstn_cnt counter; the inverted output QN of the LDO_HSI_ON is connected to the Standby_rstn signal, which resets the VCORE domain when it is 0. The rising edge of the Standby_rstn_cnt counter triggers the clock input to connect to Hsi_clk, and when the enable signal EN of the Standby_rstn_cnt counter is 1, Hsi_clk starts to count upward. The count value Hsi_cnt output by the Standby_rstn_cnt is connected to the input of the comparator, and the output of the comparator is connected to the Hsi_stable signal. When Hsi_cnt is equal to the set threshold n, Hsi_stable is set to 1, otherwise Hsi_stable is 0.Hsi_stable is delayed by a set of delay chains to obtain Hsi_stable_dly, and Hsi_stable_dly is inverted and combined with Por_rstn_dly to obtain Ldo_hsi_on_rstn. Ldo_hsi_on_rstn is input to the low-level active reset input terminal of the LDO_HSI_ON trigger, and Ldo_hsi_on_rstn is input to the low-level active reset input terminal of Standby_rstn_cnt.

[0071] The peripheral circuits of the PMU are as follows Figure 2 As shown in the figure, Por_rstn_dly and Standby_rstn are connected to the HSION register and the low-level active reset input of the VCORE domain. The output of the HSION register is Hsi_on, and the reset value is 1, that is, the valid state. The HSION register can be configured by software. Ldo_on is connected to the enable end of the voltage-regulated power supply LDO. When the output voltage of the LDO reaches the threshold 10us later, the enable signal VCORE_OK_HV sent by the LDO to the HSI is set to 1, that is, the valid state. VCORE_OK_HV and Hsi_on are ANDed to obtain En_hsi and input to the enable end of the HSI clock source. When En_hsi is 1, the HSI starts working and outputs the clock Hsi_clk, otherwise the clock output is disabled. When the Standby_en signal output by the VCORE domain is 1, it indicates that the PMU is enabled to enter the low-power mode. The output signal of the VCORE domain is output to other modules after passing through the ISO isolation unit. When Iso_on is low, the isolation unit is valid. The APB bus output by the VCORE domain is connected to the HSION register after passing through ISO and is used to configure the HSION register.

[0072] like Figure 3 As shown, the control flow of PMU in this implementation case is described as follows:

[0073] 1) Por_rstn_dly is Por_rstn released after Hsi_clk clock count delay. Por_rstn is the power-on reset signal. Por_rstn_dly defaults to low level in the power-on reset state and resets all triggers and counters of PMU, among which Iso_on and Hsi_cnt are reset to 0, Ldo_on and Standby_rstn are reset to 1, enabling LDO output and isolating VCORE domain.

[0074] 2) 10us after the output voltage of the LDO reaches the threshold, VCORE_OK_HV is set to 1, enabling the HSI oscillator to generate the clock.

[0075] Por_rstn_dly and Standby_rstn are ANDed together to form Iso_release_in. Por_rstn_dly resets the release state to a high level, setting Iso_release_in to 1.

[0076] 3) Iso_release_in generates Iso_release through the delay chain. The rising edge of Iso_release triggers Iso_on to be set to 1, and ISO changes from being enabled when it is just powered on to being disabled.

[0077] 4) When entering low power mode, the low power mode switching enable signal Standby_en is set to 1, and after a delay in the delay chain, Iso_clamp is set to 1. The high level of Iso_clamp triggers Iso_on to be set to 0, and ISO is enabled to clamp Standby_en to 0.

[0078] At the same time, since the PMU does not rely on the clock signal, before the VCORE domain issues Standby_en, the HSI is turned off by configuring the HSION register through the APB bus via ISO.

[0079] 5) After Iso_on passes through the delay chain, Iso_on_dly is set to 0. The falling edge of Iso_on_dly triggers the LDO_ON output Ldo_on to be set to 0, and the LDO is turned off, completing the entire power-off process.

[0080] 6) When exiting low power mode, the input wake-up flag signal Stdby_wkup_src is set to 1. Ldo_on_dly is generated by Ldo_on through the delay chain, and the wake-up condition is met when it is 0. When Ldo_on_dly is 0 and Stdby_wkup_src is 1, Ldo_on_set is set to 1.

[0081] 7) After Ldo_on_set is set to 1, the LDO_ON trigger is reset, so that Ldo_on is set to 1 and the LDO is turned on. After the LDO output is valid, VCORE_OK_HV is set to 1.

[0082] At the same time, the rising edge of Ldo_on_set triggers Ldo_Hsi_on to be set to 1, enabling the counter to count Hsi_clk; the rising edge of Ldo_on_set triggers the inverting output terminal Standby_rstn of LDO_HSI_ON to be set to 0, resetting the VCORE domain register and resetting the HSION register at the same time, so that Hsi_on is set to 1, and the HSI oscillator generates a clock.

[0083] 8) When the Hsi_cnt count value reaches the comparator threshold, Hsi_stable is set to 1, resetting the LDO_HSI_ON trigger and counter.

[0084] 9) The LDO_HSI_ON trigger is reset, so that Ldo_Hsi_on is set to 0 to stop counting and enable, and Standby_rstn is set to 1 to release the VCORE domain reset.

[0085] 10) Iso_release_in will change with Standby_rstn. When Standby_rstn is released, Iso_release_in will have a rising edge.

[0086] 11) After the rising edge of Iso_release_in is delayed, the rising edge of Iso_release is generated, triggering Iso_on to be set to 1, completing the entire low-power wake-up process.

[0087] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A low-power MCU power management unit implemented using an asynchronous circuit, referred to as PMU, wherein the MCU includes LDO, HSI, ISO, VCORE domain, and HSION register; the output signal of the VCORE domain is output to other modules after passing through ISO; It is characterized in that The PMU includes an isolation control module, a power-on control module, and a delayed wake-up module; Among them, the isolation control module outputs Iso_on to ISO as an enable signal of ISO; The Isolation Control Module is configured as: When Por_rstn_dly is in the power-on reset state or Iso_clamp is in the valid state, Iso_on is set to the valid state; wherein, Por_rstn_dly is Por_rstn released after delay, and Por_rstn is the power-on reset signal; Iso_clamp is the signal obtained by Standby_en after delay chain delay, and Standby_en is the low power mode switching enable signal; When the first condition changes from an unsatisfied state to a satisfied state, after a delay in the delay chain, Iso_on is set to an invalid state, and the content of the first condition is that Por_rstn_dly is in a reset release state and Standby_rstn is in an invalid state; wherein Standby_rstn is a VCORE domain reset signal, and when Standby_rstn is valid, the VCORE domain is reset; The power-on control module outputs Ldo_on to the LDO as an enable signal of the LDO; The power-on control module is configured as: When Por_rstn_dly is in the power-on reset state or the wake-up condition is met, Ldo_on is set to the valid state; wherein the wake-up condition includes the wake-up flag signal Stdby_wkup_src being in the valid state, wherein Ldo_on_dly is Ldo_on after being delayed by the delay chain; When Iso_on_dly changes from invalid to valid, Ldo_on is set to invalid state; where Iso_on_dly is Iso_on after being delayed by the delay chain; Among them, the delayed wake-up module outputs Standby_rstn; The delayed wake-up module is configured as: When Por_rstn_dly is in the power-on reset state, Standby_rstn is set to the invalid state; When the wake-up condition changes from not satisfied to satisfied, Standby_rstn is set to a valid state. When the preset wake-up time is delayed, Standby_rstn is set to an invalid state.

2. According to claim 1, a low-power MCU power management unit implemented using an asynchronous circuit, referred to as PMU, is characterized in that: When the enable signals sent by LDO and HSION register to HSI are both valid, HSI is turned on, otherwise HSI is turned off; after the output voltage of LDO reaches the threshold and lasts for a preset time, the enable signal sent to HSI is valid; The external wiring of the PMU is configured as: When Por_rstn_dly is in the power-on reset state or Standby_rstn is in the valid state, the VCORE domain is reset, and the HSION register is reset, so that the enable signal sent by the HSION register to the HSI is set valid.

3. A low-power MCU power management unit implemented using an asynchronous circuit according to claim 1, referred to as PMU, characterized in that: The delayed wake-up module uses the clock signal Hsi_clk generated by HSI for timing when delaying the preset wake-up time.

4. A low-power MCU power management unit (PMU) implemented using an asynchronous circuit according to claim 1, wherein the wake-up condition also includes Ldo_on_dly being in an invalid state.

5. According to a low-power MCU power management unit implemented using an asynchronous circuit, referred to as PMU, according to claim 1, the isolation control module includes a DFF trigger ISO_ON and a delay chain; The data input terminal D of ISO_ON is always 1, and the positive output terminal Q is connected to Iso_on; Use a delay chain to delay Standby_en to get Iso_clamp, perform a logical OR operation on Iso_clamp and the inverted Por_rstn_dly, and then connect it to the high-level active reset input of ISO_ON; After the logical AND operation of Por_rstn_dly and Standby_rstn is performed, the operation result is delayed by the delay chain and then connected to the rising edge trigger clock input terminal of ISO_ON; Among them, Iso_on and Standby_rstn are valid at low level, Standby_en is valid at high level, Por_rstn_dly power-on reset state is low level, and reset release state is high level; Iso_on is set to 0 when ISO_ON is reset.

6. A low-power MCU power management unit implemented using an asynchronous circuit according to claim 1, referred to as PMU, wherein the power-on control module includes a DFF trigger LDO_ON and a delay chain; The data input terminal D of LDO_ON is always 1, and the inverting output terminal QN is connected to Ldo_on; Use a delay chain to delay Iso_on and then connect it to the falling edge trigger clock input of LDO_ON; After delaying Ldo_on using a delay chain, Ldo_on_dly is obtained. After Ldo_on_dly is inverted, a logical AND operation is performed with Stdby_wkup_src to obtain Ldo_on_set. After Ldo_on_set is inverted, a logical AND operation is performed with Por_rstn_dly, and then connected to the low-level effective reset input terminal of LDO_ON. in, Ldo_on and Stdby_wkup_src are valid at high level, and Iso_on is valid at low level; the power-on reset state of Por_rstn_dly is low level, and the reset release state is high level; Ldo_on is set to 1 when LDO_ON is reset.

7. According to a low-power MCU power management unit implemented using an asynchronous circuit, referred to as PMU, according to claim 1, wherein the delayed wake-up module includes a DFF trigger LDO_HSI_ON, a counter Standby_rstn_cnt, a comparator, and a delay chain; The data input terminal D of LDO_HSI_ON is always 1, the positive output terminal Q is connected to Ldo_hsi_on, and the inverting output terminal QN is connected to Standby_rstn; the result of the inverted Ldo_on_dly and the logical AND operation with Stdby_wkup_src is connected to the rising edge trigger input terminal of LDO_HSI_ON, where Ldo_on_dly is Ldo_on after the delay chain delay; Ldo_hsi_on is synchronized and input to the enable input terminal of Standby_rstn_cnt, and the clock signal Hsi_clk generated by HSI is connected to the rising edge trigger clock input terminal of Standby_rstn_cnt, and the count value H generated by Standby_rstn_cnt is si_cnt is connected to the input of the comparator, and the output of the comparator is connected to the Hsi_stable signal. When Hsi_cnt is equal to the set threshold n, Hsi_stable is set to 1, otherwise Hsi_stable is set to 0. Hsi_stable is delayed by a delay chain to obtain Hsi_stable_dly. Hsi_stable_dly is inverted and logically ANDed with Por_rstn_dly to obtain Ldo_hsi_on_rstn. Ldo_hsi_on_rstn is input to the low-level effective reset input of the LDO_HSI_ON trigger, and Ldo_hsi_on_rstn is input to the low-level effective reset input of Standby_rstn_cnt. Among them, Standby_rstn is valid at a low level, Ldo_hsi_on, Ldo_on, and Stdby_wkup_src are valid at a high level; the power-on reset state of Por_rstn_dly is a low level, and the reset release state is a high level; when LDO_HSI_ON is reset, Ldo_hsi_on is set to 0 and Standby_rstn is set to 1.

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