Chip power supply integrity sign-off method and device, storage medium and electronic device

Abstract

The invention discloses a chip power supply integrity signing method and device, a storage medium and an electronic device. The power supply integrity sign-off method of the chip comprises the following steps: extracting high-frequency upset rates of M devices of the chip from N waveform files, the high-frequency upset rates being not less than an initial global upset rate in a power supply integrity simulation model; reversely marking the high-frequency flip rates of the M devices into the power supply integrity simulation model; a simulation test is carried out, a simulation result is obtained, the M devices reach the respective high-frequency turnover rates in the simulation test process, and the rest devices of the chip reach the global turnover rate in the power supply integrity simulation model in the simulation test process; and under the conditions that the simulation result does not meet the sign-off standard and the global turnover rate setting in the power supply integrity simulation model is unreasonable, the global turnover rate is adjusted, and the simulation test is performed again, so that the technical problem of low accuracy of the power supply integrity sign-off method in the prior art is solved.

Description

Technical Field

[0001] The present application relates to computer-related fields, and in particular, to a power integrity signoff method, device, storage medium and electronic device for a chip. Background Art

[0002] In recent years, the strategic positioning of AI big models has become a new driving force for the whole society to reduce costs and increase efficiency. As the cornerstone of AI big models, high-computing AI chips face new challenges in the PI (Power integrity) Signoff method. There are two problems that need to be solved urgently. One is the high flip rate of AI chips, and the other is the large number of computing channels. The traditional Signoff method based on the reverse flip rate cannot accurately describe the behavior of certain high-frequency flip devices, resulting in large differences from the actual flip behavior of the chip, which in turn causes insufficient chip power supply, too high Vmin, substandard performance, and even test failure.

[0003] Although the traditional signoff method based on back-labeled power consumption inherits the relatively accurate power consumption information of PTPX (Prime Time PowerX), different EDA tools have large differences in the behavior of calculating the flip rate based on power consumption, and it is still unable to identify high-frequency flip devices.

[0004] The traditional vector-based Signoff method can accurately describe the flip rate of the chip in a fixed scenario, but the coverage is insufficient. Usually, a vector can only describe the flip behavior of a part of the logic devices, and the flip rate of the remaining devices is 0.0 for a long time. If all devices are expected to flip at least once, multiple waveform files need to be provided. For example, an AI chip has two computing modules, integer computing and floating-point computing. Each computing module has 128 computing channels. If it is expected that the logic devices of all channels are flipped once during the PI simulation process, waveform files for 256 channels are required. The simulation volume is large and the feasibility is not high. In related technologies, the power integrity signoff method is not accurate. Summary of the invention

[0005] The embodiments of the present application provide a power integrity signoff method, device, storage medium and electronic device for a chip, so as to at least solve the technical problem of low accuracy of the power integrity signoff method in the prior art.

[0006] According to one aspect of an embodiment of the present application, a power integrity sign-off method for a chip is provided, comprising: extracting high-frequency flip rates of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flip rate is not less than an initial global flip rate in a power integrity simulation model, and the initial global flip rate is determined based on initial design data of the chip; back-labeling the high-frequency flip rates of the M devices into the power integrity simulation model; performing simulation testing using the power integrity simulation model to obtain simulation results, wherein the M devices respectively reach their respective high-frequency flip rates during the simulation testing, and the remaining devices of the chip reach the global flip rate in the power integrity simulation model during the simulation testing; when the simulation result does not meet the sign-off standard and the global flip rate in the power integrity simulation model is set unreasonably, adjusting the global flip rate, and performing simulation testing again using the power integrity simulation model.

[0007] Optionally, the method also includes: when the simulation result does not meet the sign-off criteria and the global flip rate in the power integrity simulation model is set reasonably, modifying the design data of the chip, adjusting the global flip rate in the power integrity simulation model according to the modified design data, and performing simulation testing again using the power integrity simulation model.

[0008] Optionally, the high frequency toggle rate toggleRate_inst(m) of the mth device is:

[0009]

[0010] Wherein, m=1, ...M, toggleRate(i) is the toggle rate of the mth device in the ith waveform file, the toggleRate(i) is not less than the initial global toggle rate in the power integrity simulation model, and N' is not greater than N.

[0011] Optionally, extracting the high-frequency flip rates of M devices of the chip from N waveform files includes: screening out M devices as high-frequency flip devices by counting the flip rates of each device of the chip in the N waveform files, wherein the flip rates of the high-frequency flip devices in the N' waveform files are not less than the initial global flip rate in the power integrity simulation model; and for each high-frequency flip device, selecting the maximum flip rate thereof in the N' waveform files as its high-frequency flip rate.

[0012] Optionally, before back-annotating the high-frequency flip rates of the M devices into the power integrity simulation model, the method also includes: when there is a deviation between the waveform file and the actual measured results of the chip and the high-frequency flip rate distribution of the M devices conforms to a uniform distribution or a Gaussian distribution, calculating the standard deviation of the high-frequency flip rates of the M devices; for each of the M devices, adjusting the high-frequency flip rate by superimposing K times the standard deviation on the original high-frequency flip rate.

[0013] Optionally, K is a real number, and its value range is [1, 3].

[0014] According to another aspect of an embodiment of the present application, a power integrity sign-off device for a chip is provided, comprising: an extraction unit, for extracting high-frequency flip rates of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flip rate is not less than an initial global flip rate in a power integrity simulation model, and the initial global flip rate is determined according to initial design data of the chip; a back-labeling unit, for back-labeling the high-frequency flip rates of the M devices into the power integrity simulation model; a simulation unit, for performing simulation testing using the power integrity simulation model to obtain simulation results, wherein the M devices respectively reach their respective high-frequency flip rates during the simulation testing, and the remaining devices of the chip reach the global flip rate in the power integrity simulation model during the simulation testing; an adjustment unit, for adjusting the global flip rate when the simulation result does not meet the sign-off standard and the global flip rate in the power integrity simulation model is not set reasonably, and performing simulation testing again using the power integrity simulation model.

[0015] Optionally, the adjustment unit is also used to modify the design data of the chip when the simulation result does not meet the sign-off criteria and the global flip rate in the power integrity simulation model is set reasonably, adjust the global flip rate in the power integrity simulation model according to the modified design data, and perform simulation testing again using the power integrity simulation model.

[0016] According to another aspect of an embodiment of the present application, a computer-readable storage medium is provided, characterized in that a computer program is stored in the storage medium, wherein the computer program is configured to execute the power integrity signoff method of the above-mentioned chip when running.

[0017] According to another aspect of an embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the power integrity signoff method of the above-mentioned chip.

[0018] In an embodiment of the present application, high-frequency flip rates of M devices of a chip are extracted from N waveform files, wherein N and M are both positive integers, and the high-frequency flip rate is not less than an initial global flip rate in a power integrity simulation model, and the initial global flip rate is determined based on initial design data of the chip; the high-frequency flip rates of the M devices are back-labeled to the power integrity simulation model; a simulation test is performed using the power integrity simulation model to obtain a simulation result, wherein the M devices respectively reach their respective high-frequency flip rates during the simulation test, and the remaining devices of the chip reach the global flip rate in the power integrity simulation model during the simulation test; when the simulation result does not meet the sign-off standard and the global flip rate in the power integrity simulation model is set unreasonably, the global flip rate is adjusted, and the simulation test is performed again using the power integrity simulation model, thereby solving the technical problem of low accuracy of the power integrity sign-off method in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 It is a hardware structure block diagram of a mobile terminal according to an optional chip power integrity signoff method of an embodiment of the present application;

[0021] Figure 2 is a flow chart of an optional chip power integrity sign-off method according to an embodiment of the present application;

[0022] Figure 3 is a flow chart of an optional AI chip power integrity hybrid Sign Off method according to an embodiment of the present application;

[0023] Figure 4a is an optional reverse-label flip rate distribution schematic diagram according to an embodiment of the present application;

[0024] Figure 4b is a schematic diagram of an optional vector flip rate distribution according to an embodiment of the present application;

[0025] Figure 4c is a schematic diagram of an optional hybrid flip rate distribution according to an embodiment of the present application;

[0026] Figure 5a is a schematic diagram of an optional reverse-labeled heat map according to an embodiment of the present application;

[0027] Figure 5b is an optional vector heat map schematic diagram according to an embodiment of the present application;

[0028] Figure 5c is a schematic diagram of an optional hybrid heat map according to an embodiment of the present application;

[0029] Figure 6a is an optional reverse-standard voltage distribution schematic diagram according to an embodiment of the present application;

[0030] Figure 6b is a schematic diagram of an optional vector voltage distribution according to an embodiment of the present application;

[0031] Figure 6c is a schematic diagram of an optional hybrid voltage distribution according to an embodiment of the present application;

[0032] Figure 7 is a diagram of an optional chip power integrity signoff device according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a sequence of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] The power integrity check method for a chip provided in the present application can be executed in a computer terminal or a similar computing device. For example, running on a computer terminal, Figure 1 FIG. 1 is a hardware structure block diagram of a computer terminal of a chip power integrity sign-off method according to an embodiment of the present application. Figure 1 As shown, the computer terminal 10 may include one or more ( Figure 1Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Optionally, the computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0036] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the power integrity sign-off method of the chip in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0037] The transmission device 106 is used to receive or send data via a network. Specific examples of the above network may include a wireless network provided by a communication provider of the computer terminal 10 .

[0038] In this embodiment, a power integrity check method for a chip is also provided. Figure 2 is a flow chart of a power integrity sign-off method for a chip according to an embodiment of the present application. Figure 2 As shown, the power integrity sign-off method flow of the chip includes the following steps:

[0039] Step S202, extracting high-frequency flip rates of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flip rate is not less than an initial global flip rate in a power integrity simulation model, and the initial global flip rate is determined according to initial design data of the chip;

[0040] Step S204, reverse-labeling the high-frequency flip rates of the M devices into the power integrity simulation model;

[0041] Step S206, performing simulation test using the power integrity simulation model to obtain simulation results, wherein the M devices respectively reach their respective high-frequency flipping rates during the simulation test, and the remaining devices of the chip reach the global flipping rate in the power integrity simulation model during the simulation test;

[0042] Step S208 , when the simulation result does not meet the sign-off standard and the global toggle rate setting in the power integrity simulation model is unreasonable, adjust the global toggle rate and perform simulation test again using the power integrity simulation model.

[0043] In this embodiment, the waveform files include but are not limited to: fsdb / vcd waveform files. The high-frequency flip rate is extracted from multiple waveform files, and a unified flip rate is set, and the files are back-labeled for PI simulation.

[0044] In this embodiment, the toggle rate is first set globally. Secondly, the core devices with a higher toggle rate than the global toggle rate are directly extracted from PTPX. If there are waveforms of multiple operation channels, the toggle rate results are combined and the maximum toggle rate is taken for the same device. Finally, the obtained toggle rate collection is back-labeled to the PI Signoff tool, such as redhawk or voltus for Signoff, which can solve the problem of insufficient coverage of the vector method and the problem that the back-labeled toggle rate method cannot identify high-frequency toggle rate devices.

[0045] Through the embodiments provided by the present application, high-frequency flip rates of M devices of a chip are extracted from N waveform files, wherein N and M are both positive integers, the high-frequency flip rate is not less than the initial global flip rate in a power integrity simulation model, and the initial global flip rate is determined based on initial design data of the chip; the high-frequency flip rates of the M devices are back-labeled to the power integrity simulation model; a simulation test is performed using the power integrity simulation model to obtain a simulation result, wherein the M devices respectively reach their respective high-frequency flip rates during the simulation test, and the remaining devices of the chip reach the global flip rate in the power integrity simulation model during the simulation test; when the simulation result does not meet the sign-off standard and the global flip rate in the power integrity simulation model is set unreasonably, the global flip rate is adjusted, and the simulation test is performed again using the power integrity simulation model, thereby solving the technical problem of low accuracy of the power integrity sign-off method in the prior art.

[0046] Optionally, the above method may also include: when the simulation results do not meet the sign-off criteria and the global flip rate in the power integrity simulation model is set reasonably, modifying the design data of the chip, adjusting the global flip rate in the power integrity simulation model according to the modified design data, and performing simulation testing again using the power integrity simulation model.

[0047] Optionally, the high frequency toggle rate toggleRate_inst(m) of the mth device is:

[0048]

[0049] Wherein, m=1, ...M, toggleRate(i) is the toggle rate of the mth device in the ith waveform file, toggleRate(i) is not less than the initial global toggle rate in the power integrity simulation model, and N' is not greater than N.

[0050] Optionally, extracting the high-frequency flip rates of M devices of a chip from N waveform files may include: selecting M devices as high-frequency flip devices by counting the flip rates of each device of the chip in the N waveform files, wherein the flip rates of the high-frequency flip devices in the N' waveform files are not less than the initial global flip rate in the power integrity simulation model; and for each high-frequency flip device, selecting the maximum flip rate thereof in the N' waveform files as its high-frequency flip rate.

[0051] Optionally, before back-labeling the high-frequency flip rates of the M devices into the power integrity simulation model, the method may further include: when there is a deviation between the waveform file and the actual measured results of the chip and the high-frequency flip rate distribution of the M devices conforms to a uniform distribution or a Gaussian distribution, calculating the standard deviation of the high-frequency flip rates of the M devices; for each of the M devices, adjusting the high-frequency flip rate by superimposing K times the standard deviation on the original high-frequency flip rate.

[0052] In this embodiment, K is a real number, and its value range is [1, 3].

[0053] As an optional embodiment, the present application also provides a hybrid Sign Off method for power integrity of an AI chip. Figure 3 As shown, a schematic diagram of the hybrid Sign Off method for AI chip power integrity.

[0054] Based on the characteristics of AI chips, there are two problems that need to be solved urgently. One is the high flip rate of AI chips, and the other is the large number of computing channels.

[0055] In this embodiment, a hybrid PI Signoff method is proposed. First, since it is difficult for the vector method to solve the coverage problem, it is necessary to set the flip rate globally, such as 0.15 to 0.35; secondly, the core devices with a higher flip rate than the global flip rate are directly extracted from PTPX. If there are waveforms of multiple operation channels, the flip rate results are combined, and the maximum flip rate is taken for the same device; finally, the obtained flip rate collection is back-annotated to the PI Signoff tool, such as redhawk or voltus for signoff, which can solve the problem of insufficient coverage of the vector method and the problem that the back-annotated flip rate method cannot identify high-frequency flip rate devices.

[0056] In this embodiment, the high-frequency flipping rates are directly extracted from N waveform files. If a device has at least n high-frequency flippings in waveforms A to N, the maximum flipping rate is taken.

[0057] After extracting all high-frequency flip rate devices, they are uniformly reverse-annotated into PI simulation, overwriting the original global flip rate, and performing simulation to check whether the Signoff standard is met. If not, check whether the global flip rate is set reasonably, whether the design data needs to be modified, and repair the devices with voltage drop violations. If satisfied, perform Tap out.

[0058] In this embodiment, in addition to the hybrid Signoff method discussed above, a hybrid calibration method is also discussed during the chip design process. If there is a deviation between the waveform itself and the actual measured result of the chip, how to calibrate the high-frequency device flip rate extracted from the waveform with the actual measured result through simulation. First, it is necessary to observe the flip rate distribution of the high-frequency flip device. For example, if it conforms to the uniform distribution or Gaussian distribution, it can be adjusted by calculating its standard deviation and superimposing 1 to 3 times the standard deviation on the original flip rate.

[0059]

[0060] toggleRate_instA_mod=toggleRate_instA+1.5*toggleRate_sigma

[0061] toggleRate_instB_mod=toggleRate_instB+1.5*toggleRate_sigma

[0062] toggleRate_instC_mod=toggleRate_instC+1.5*toggleRate_sigma ......

[0064] toggleRate_instN_mod=toggleRate_instN+1.5*toggleRate_sigma

[0065] Then back-label all toggleRate_inst*_mod into the PI simulation and calibrate with the measured results.

[0066] In this embodiment, a method of extracting high-frequency flip rates from multiple waveform files, setting a unified flip rate, and back-labeling the PI simulation is used to calibrate the adjustment method of the high-frequency flip rate device in combination with the measured results.

[0067] It should be noted that the key factors in measuring the technical effectiveness of a signoff method are, first, whether the design risks introduced by solving the existing problems are identifiable and repairable, and second, whether it is feasible on the implementation side.

[0068] First, extract the high-frequency flip rate and perform back-labeling. By analyzing the back-labeled flip rate distribution, vector flip rate distribution, and mixed flip rate distribution, we can get Figures 4a to 4c , the horizontal axis is the flip rate value, and the vertical axis is the logarithmic coordinate of the number of devices.

[0069] like Figure 4a As shown in the figure, the reverse-standard flip rate distribution diagram shows that except for the peak at 2.0, the rest of the reverse-standard distribution basically presents a normal distribution trend, and the overall median value is 0.35.

[0070] like Figure 4b As shown in the figure, a large number of devices are at 0.0 and have not flipped. From 0.0 to 2.0, the distribution trend is basically uniform, and the overall median value is 0.0.

[0071] like Figure 4c As shown in the figure, the hybrid flip rate distribution diagram, the hybrid distribution not only retains the flip rate of high-frequency devices in the vector method, making up for the shortcomings of the reverse-label method, but also eliminates the problem of a large number of devices not flipping in the vector method. At the same time, the high flip rate devices extracted from multiple vectors can be set uniformly by finding the union. After excluding a large number of 0.0 factors in the vector, the overall median value is 0.37, that is, the flip rate introduced by the high-frequency device is 0.02 higher than the reverse-label method of 0.35.

[0072] Figure 5a to Figure 5c The heatmap shows that the hybrid method has both the hotspot features of the back-labeled method and the vector method. Since the same global flip rate is set as the back-labeled method, the overall distribution is similar to the back-labeled method. Figure 5a The A area shown is Figure 5cAt the same time, the high-frequency flip devices in key hot spots are consistent with the vector method, for example Figure 5b Middle B area and Figure 5c The distribution in the middle is similar, with key hot spots showing red semicircle shapes.

[0073] Figures 6a to 6c The voltage distribution of the three methods is shown, with the device voltage on the abscissa and the logarithm of the number of devices on the ordinate. Figure 6a The reverse-standard voltage distribution is shown, and all device voltage values ​​are above the critical voltage of 0.72V; Figure 6b The vector voltage distribution is shown. All device voltage values ​​are above 0.72V. Compared with the reverse standard results, the high flip rate devices are more concentrated at 0.72. Figure 6c The mixed voltage distribution is shown, and a small number of devices (about 7) are below the critical voltage of 0.72V. The repair can be completed by optimizing the design data, which proves the feasibility of this method. At the same time, the devices near 0.72V are more concentrated, which better reflects the voltage situation of the critical path under different working modes of the chip.

[0074] Combined with the measured results, the adjustment method of calibrating the high-frequency flip rate device is implemented.

[0075] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0076] In this embodiment, a power integrity signoff device for a chip is also provided, which is used to implement the above embodiments and preferred implementation modes, and will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0077] Figure 7 is a structural block diagram of a power integrity signoff device for a chip according to an embodiment of the present application, such as Figure 7 As shown, the power integrity signoff device of the chip includes:

[0078] The extraction unit 71 is used to extract the high-frequency flip rate of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flip rate is not less than the initial global flip rate in the power integrity simulation model, and the initial global flip rate is determined according to the initial design data of the chip.

[0079] The back-annotation unit 73 is used to back-annotate the high-frequency flipping rates of the M devices into the power integrity simulation model.

[0080] The simulation unit 75 is used to perform simulation test using the power integrity simulation model to obtain simulation results. The M devices reach their respective high-frequency flip rates during the simulation test, and the remaining devices of the chip reach the global flip rate in the power integrity simulation model during the simulation test.

[0081] The adjusting unit 77 is used to adjust the global toggle rate and perform simulation test again using the power integrity simulation model when the simulation result does not meet the sign-off standard and the global toggle rate setting in the power integrity simulation model is unreasonable.

[0082] Through the embodiment provided by the present application, the extraction unit 71 extracts the high-frequency flip rate of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flip rate is not less than the initial global flip rate in the power integrity simulation model, and the initial global flip rate is determined according to the initial design data of the chip; the reverse labeling unit 73 reverses the high-frequency flip rate of the M devices to the power integrity simulation model; the simulation unit 75 performs simulation test using the power integrity simulation model to obtain simulation results, and the M devices respectively reach their respective high-frequency flip rates during the simulation test, and the remaining devices of the chip reach the global flip rate in the power integrity simulation model during the simulation test; the adjustment unit 77 adjusts the global flip rate when the simulation result does not meet the sign-off standard and the global flip rate setting in the power integrity simulation model is unreasonable, and performs simulation test again using the power integrity simulation model. By extracting high-frequency flip rates from multiple waveform files, combining with the method of setting a unified flip rate, and reverse labeling back to PI simulation, the technical problem of low accuracy of the power integrity sign-off method in the prior art is solved.

[0083] Optionally, the above-mentioned adjustment unit is also used to modify the design data of the chip when the simulation result does not meet the sign-off standard and the global flip rate in the power integrity simulation model is set reasonably, adjust the global flip rate in the power integrity simulation model according to the modified design data, and perform simulation testing again using the power integrity simulation model.

[0084] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0085] An embodiment of the present application further provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0086] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:

[0087] S1, extracting high-frequency flipping rates of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flipping rate is not less than an initial global flipping rate in a power integrity simulation model, and the initial global flipping rate is determined according to initial design data of the chip;

[0088] S2, back-labeling the high-frequency flip rates of the M devices into a power integrity simulation model;

[0089] S3, performing simulation test using the power integrity simulation model to obtain simulation results, wherein the M devices respectively reach their respective high-frequency flipping rates during the simulation test, and the remaining devices of the chip reach the global flipping rate in the power integrity simulation model during the simulation test;

[0090] S4, when the simulation result does not meet the sign-off standard and the global toggle rate setting in the power integrity simulation model is unreasonable, adjust the global toggle rate and perform simulation test again using the power integrity simulation model.

[0091] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0092] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0093] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0094] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0095] S1, extracting high-frequency flipping rates of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flipping rate is not less than an initial global flipping rate in a power integrity simulation model, and the initial global flipping rate is determined according to initial design data of the chip;

[0096] S2, back-labeling the high-frequency flip rates of the M devices into a power integrity simulation model;

[0097] S3, performing simulation test using the power integrity simulation model to obtain simulation results, wherein the M devices respectively reach their respective high-frequency flipping rates during the simulation test, and the remaining devices of the chip reach the global flipping rate in the power integrity simulation model during the simulation test;

[0098] S4, when the simulation result does not meet the sign-off standard and the global toggle rate setting in the power integrity simulation model is unreasonable, adjust the global toggle rate and perform simulation test again using the power integrity simulation model.

[0099] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be described in detail here.

[0100] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0101] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip power integrity sign-off method, characterized in that: include: Extracting high-frequency flipping rates of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flipping rate is not less than an initial global flipping rate in a power integrity simulation model, and the initial global flipping rate is determined according to initial design data of the chip; Back-labeling the high-frequency flipping rates of the M devices into a power integrity simulation model; Performing simulation tests using the power integrity simulation model to obtain simulation results, wherein the M devices respectively reach their respective high-frequency flipping rates during the simulation test, and the remaining devices of the chip reach the global flipping rate in the power integrity simulation model during the simulation test; When the simulation result does not meet the sign-off standard and the global toggle rate setting in the power integrity simulation model is unreasonable, the global toggle rate is adjusted, and the simulation test is performed again using the power integrity simulation model.

2. The method according to claim 1, characterized in that The method further comprises: When the simulation result does not meet the sign-off criteria and the global flip rate in the power integrity simulation model is set reasonably, the design data of the chip is modified, the global flip rate in the power integrity simulation model is adjusted according to the modified design data, and the simulation test is performed again using the power integrity simulation model.

3. The method according to claim 1, characterized in that The high-frequency toggle rate toggleRate_inst(m) of the mth device is: Wherein, m=1, ...M, toggleRate(i) is the toggle rate of the mth device in the ith waveform file, the toggleRate(i) is not less than the initial global toggle rate in the power integrity simulation model, and N' is not greater than N.

4. The method according to claim 3, characterized in that The step of extracting high-frequency flipping rates of M devices of the chip from N waveform files includes: By counting the flip rates of the various devices of the chip in the N waveform files, M devices are selected as high-frequency flip devices, and the flip rates of the high-frequency flip devices in the N' waveform files are not less than the initial global flip rate in the power integrity simulation model; For each high-frequency flipping device, the maximum flipping rate of the device in N' waveform files is selected as the high-frequency flipping rate of the device.

5. The method according to claim 1, characterized in that: Before back-labeling the high-frequency flip rates of the M devices into the power integrity simulation model, the method further includes: When there is a deviation between the waveform file and the actual measurement result of the chip and the high-frequency flip rate distribution of the M devices conforms to the uniform distribution or the Gaussian distribution, calculate the standard deviation of the high-frequency flip rate of the M devices; For each of the M devices, the high-frequency flipping rate is adjusted by superimposing K times the standard deviation on the original high-frequency flipping rate.

6. The method according to claim 5, characterized in that The K is a real number, and its value range is [1, 3].

7. A chip power integrity sign-off device, characterized in that: include: An extraction unit, used for extracting high-frequency flipping rates of M devices of the chip from N waveform files, wherein N and M are both positive integers, and the high-frequency flipping rate is not less than an initial global flipping rate in a power integrity simulation model, and the initial global flipping rate is determined according to initial design data of the chip; A back-labeling unit, used for back-labeling the high-frequency flipping rates of the M devices into a power integrity simulation model; A simulation unit, used to perform simulation testing using the power integrity simulation model to obtain simulation results, wherein the M devices respectively reach their respective high-frequency flipping rates during the simulation testing process, and the remaining devices of the chip reach the global flipping rate in the power integrity simulation model during the simulation testing process; The adjusting unit is used to adjust the global flip rate when the simulation result does not meet the sign-off standard and the global flip rate setting in the power integrity simulation model is unreasonable, and perform simulation test again using the power integrity simulation model.

8. The device according to claim 7, characterized in that The adjustment unit is also used for: When the simulation result does not meet the sign-off criteria and the global flip rate in the power integrity simulation model is set reasonably, the design data of the chip is modified, the global flip rate in the power integrity simulation model is adjusted according to the modified design data, and the simulation test is performed again using the power integrity simulation model.

9. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 6 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 6.

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