PDN decoupling capacitor optimization method and system

Abstract

The invention provides a PDN decoupling capacitor optimization method and system, and the method comprises the steps: determining the target impedance and frequency range [0, f0] of a power distribution network; judging the relationship between the intersection frequency f1 and f0 of the actual impedance curve and the target impedance; perfecting a simplified circuit model of a power supply circuit; executing a first capacitance selection strategy; executing a capacitor bank scheme selection strategy; calculating whether the total impedance Zmodel of the simplified power supply circuit model meets the requirement of the target impedance Z0, and adjusting the first capacitor C1 or adjusting the capacitor bank based on the judgment condition; and decoupling capacitor optimization is completed. According to the scheme, better capacitor scheme selection is achieved, the problem that noise is affected by a deep valley shape existing in impedance after capacitor optimization is solved, invalid parallel capacitor combination is avoided, and the capacitor selection frequency and the calculation amount are effectively reduced; according to the simplified circuit model provided by the scheme, the impedance curve fitting degree is good.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a PDN decoupling capacitor optimization method and system. Background Art

[0002] With the development of VLSI technology, high speed, low power consumption and high density have become the mainstream development direction. In order to ensure the realization of greater computing power on smaller chips, the chip channel size will inevitably be further reduced in proportion; with the advancement of integrated circuit process technology, the power supply voltage of integrated circuits will continue to decrease, resulting in a decrease in chip ripple noise threshold and design margin; higher signal rates make power supply noise more sensitive to parasitic parameters such as packaging, printed circuit board (PCB) routing, and vias. In large integrated circuits that use a variety of high-speed transmission signals, the important power supply voltage may be lower than 1V, but the operating current increases to tens of amperes or even hundreds of amperes, so that the target value of PDN impedance can be as low as tens of milliohms or even less than ten milliohms, and the difficulty of power integrity design increases dramatically. The impact of power integrity on circuit design is also increasing, so the rationality of the design of the power distribution network (PDN) has become a current research hotspot.

[0003] In high-speed digital integrated circuits, due to the presence of parasitic parameters in the return path of the power supply, the parasitic parameters exist in parallel in the power path impedance and the ground path impedance, which will bring synchronous switching noise, track collapse noise, ground plane bounce noise, etc., thus causing signal integrity problems. How to ensure that the chip has a clean and stable voltage supply under different process, voltage and temperature conditions, as well as under various working conditions, is a huge challenge for power integrity design. Conventional power signal integrity design will be evaluated from two levels: DC power supply voltage drop and AC frequency domain impedance, and a collaborative design analysis of package and printed circuit board power integrity will be carried out. The DC power supply voltage drop can be improved by modifying the number, position, size, stacking structure, power ground layer thickness material, etc. of the power ground vias, and the purpose of improving the voltage drop is achieved by improving the current loop; the AC frequency domain impedance PDN is usually decoupled by capacitors to make the PDN meet the design requirements, so that it is less than the target impedance threshold within the target frequency range, so as to achieve the purpose of controlling power supply noise. Therefore, the fundamental way to solve the power integrity problem is to control the PDN impedance so that it does not exceed the target value.

[0004] The existing methods for selecting decoupling capacitors usually include the large "V" method, the Decade method, and the Flat response method, but all of the above methods have certain limitations. The large "V" method is to select multiple capacitors of the same capacitance in parallel, and achieve the design goal of PDN by continuously increasing the number of capacitors, but its impedance curve has a deep valley shape, and the number of capacitors is redundant, occupying a large amount of single board layout area; the Decade method is to select capacitors of different orders of magnitude, and only one capacitor is selected for each order of magnitude. The Flat response method is similar to the Decade method, but three capacitors are selected for each order of magnitude. By controlling the number of capacitors to achieve the PDN design goal, a relatively flat impedance curve can be obtained. However, the number and type of capacitors used in the Decade method and the Flat response method are limited, and may not meet the target impedance requirements of the power supply. At the same time, these decoupling capacitor selection methods are a repetitive process of estimation, verification, adjustment, verification, and re-adjustment. It is necessary to go through repeated manual selection, adjustment, and verification to find a satisfactory solution. It is highly complex, has a low degree of automation, takes a long simulation time, and the selection results are not intuitive. The above-mentioned prior art does not select capacitors in a targeted manner according to the frequency domain characteristics of each power supply network, which makes the selected decoupling capacitor parameters unreasonable and redundant, which to a certain extent causes the problems of complex circuit board wiring, space waste, poor decoupling effect, and large influence of parasitic parameters, and also increases the engineering cost. In the patent application with application number CN202210084293, for example, the impedance after optimization of the scheme still presents a deep valley shape, because the principle of selecting capacitors in technology one is to select capacitor models with large ESR, which is prone to the situation that the selected capacitors are invalidly connected in parallel, and there will be large fluctuations in the power supply noise; it is necessary to repeat the capacitor selection method for each capacitor, and it is manually selected, the process is relatively complicated, and it cannot effectively improve the optimization efficiency in the case of a large number of capacitor decoupling; in this scheme, the action frequency after adding the capacitor to the capacitor is equivalent to the self-resonant frequency of the capacitor. However, in the actual power supply network, the capacitor is not directly connected in parallel at the power port. Its vias and short traces will be parasitic on the capacitor branch and the power port branch in the form of inductance and resistance. As a result, after the capacitor is connected to the power supply network, its changed impedance effect will be offset relative to its own impedance curve, resulting in inaccurate judgment frequency points obtained by the above method.

[0005] In addition, some simulation software in the prior art can perform capacitor solution optimization operations based on the provided three-dimensional model, but there are still problems such as redundant capacitors, abuse of large-value capacitors, and insufficiently flat impedance curves. Summary of the invention

[0006] In view of the deficiencies of the prior art, the present invention provides a specific method and system for selecting a decoupling capacitor optimization scheme, establishing a simplified power supply circuit model to determine the first capacitor and the minimum capacitor for capacitor selection, and finally using the total impedance calculation as the evaluation criterion for ending the optimization process. Specifically, the present invention provides the following technical solutions:

[0007] On the one hand, the present invention provides a method for optimizing decoupling capacitors in a PDN, the method comprising:

[0008] S1. Determine the target impedance Z0 and the frequency range [0, f0] of the power distribution network;

[0009] S2. Obtain the actual impedance curve of the power distribution network, and judge the relationship between the intersection frequency f1 of the actual impedance curve and the target impedance and f0; if f < f0, execute step S3, if f ≥ f0, then execute step S7;

[0010] S3. Obtain the ratio between the parasitic inductance l4 of the power supply bump section and the parasitic inductance l2 from the capacitor position to the power supply plane layer according to the capacitor placement position and the via parasitic inductance, obtain the simplified inductance L_net and impedance value R_net at low frequency based on the impedance curve at the power supply position, and obtain the simplified inductance L_CAP and impedance value R_CAP at low frequency based on the impedance curve at the capacitor position; based on the ratio between l4 and l2, L_net, R_net, L_CAP and R_CAP, obtain a simplified power supply circuit model;

[0011] S4. Based on the simplified power supply circuit model, estimate the capacitor C corresponding to the intersection frequency f1 g to select the first capacitor C1;

[0012] S5. Determine the minimum specification capacitor Ci based on the first capacitor C1; select a capacitor group starting from C1 and ending with Ci;

[0013] S6. Calculate whether the total impedance Z_model of the simplified power supply circuit model meets the requirement of the target impedance Z0. If it meets the requirement, execute S7, otherwise adjust the first capacitor C1 or the capacitor group;

[0014] S7. Complete the optimization of the decoupling capacitor.

[0015] Preferably, in the S1, the determination method of the target impedance Z0 is:

[0016]

[0017] wherein, Z0 represents the target impedance, VDD represents the power supply voltage, Ripple represents the allowable voltage fluctuation ratio, α represents a constant factor, ΔI MAXIndicates the maximum current change value in the current model Iinput.

[0018] Preferably, in S3, the ratio relationship between l4 and l2 is determined as follows:

[0019]

[0020] Among them, h1 is the distance from the plane layer where the power bump end is located (i.e., the top layer or the bottom layer) to the power plane layer; module b is the capacitor part, h2 is the distance from the plane layer where the capacitor is located (i.e., the top layer or the bottom layer) to the power plane layer; d is the via diameter. Based on common sense in this field, the power supply is generally not set on the top layer or the bottom layer.

[0021] Preferably, in S3, obtaining a simplified power circuit model based on the ratio between l4 and l2, L_net, R_net, L_CAP and R_CAP further comprises:

[0022] The simplified power circuit model parameters are calculated as follows:

[0023] L_CAP=l1+l2

[0024] R_CAP=r1+r2

[0025] R_net=r1

[0026] Among them, r1 represents the equivalent resistance of the VRM branch, r2 represents the equivalent resistance of the capacitor C1 branch, and l1 represents the equivalent inductance of the VRM branch.

[0027] Preferably, in S4, the capacitor C g The calculation method is:

[0028]

[0029] Wherein, loop_L represents the maximum value of the loop inductance of each capacitor branch according to the design requirements.

[0030] Preferably, in S4, when selecting capacitor C1, a capacitor with the same specifications as C is selected from the capacitor library. g The closest capacitor;

[0031] If there are multiple capacitors with the same specifications but different models in the capacitor library, the selection method is as follows:

[0032] S41, preferentially select a capacitor with an ESR smaller than Z0 and a capacitance specification as large as possible, and then execute S42;

[0033] S42, calculating the total impedance Z_model after adding the first capacitor C1, if Z_model≤1.8Z0, completing the selection of C1, otherwise executing S43;

[0034] S43, increase the number of pre-selected first capacitors by 1, and then execute step S42. If there is a quantity constraint on the first capacitors, increase the capacitance value of the selected capacitors, and then execute step S42.

[0035] Preferably, in S5, the minimum specification capacitor Ci is selected as follows:

[0036]

[0037] Estimate Cgi based on the above formula, and then select a capacitor with capacitance specifications close to Cgi from the capacitor library as Ci.

[0038] Preferably, in S5, the capacitor bank is selected to meet the following conditions:

[0039] The impedances in the capacitor group are all smaller than Z0, and the ESR of the capacitor group should be close to the ESR of the first capacitor C1.

[0040] Preferably, in S6, after adding the capacitor group, the total impedance Z_model is calculated as follows:

[0041] Among them, X l4 represents the inductive reactance corresponding to the via inductance l4 of the net branch, X l1 represents the inductive reactance corresponding to the equivalent inductance l1 of the VRM branch, X C1 Represents the capacitive reactance corresponding to capacitor C1, r C1 Indicates the equivalent resistance corresponding to capacitor 1.

[0042] Preferably, the S6 further comprises:

[0043] S61, calculating |Z_model| at the intersection frequency f1, and determining whether |Z_model| is less than Z0, if so, executing S62, otherwise adjusting the first capacitor C1;

[0044] S62, calculate |Z_model| at frequency f0, and determine whether |Z_model| is less than Z0. If so, execute step S7; otherwise, add a capacitor of Ci specification to the capacitor group, set i=i+1, recalculate Z_model, and execute step S61.

[0045] Preferably, in S7, when optimizing and placing capacitors, capacitors are placed based on loop_L values ​​at different capacitor positions and in accordance with the principle of placing small capacitors with small loop_L values, wherein loop_L represents the maximum value of the loop inductance of each capacitor branch according to design requirements.

[0046] On the other hand, the present invention further provides a PDN decoupling capacitor optimization system, the system is used to implement the above method, the system comprising:

[0047] The impedance curve module is used to obtain the actual impedance curve of the power distribution network and obtain the intersection frequency f1 of the actual impedance curve and the target impedance; determine the relationship between f1 and f0; wherein the frequency range of the power distribution network is [0, f0];

[0048] The power circuit model simplification module is used to obtain the ratio between the parasitic inductance l4 of the power bump section and the parasitic inductance l2 from the capacitor position to the power plane layer based on the capacitor placement position and the via parasitic inductance, obtain the simplified inductance L_net and impedance value, R_net at low frequency based on the impedance curve at the power position, and obtain the simplified inductance L_CAP and impedance value R_CAP at low frequency based on the impedance curve at the capacitor position; based on the ratio between l4 and l2, L_net, R_net, L_CAP and R_CAP, obtain the simplified power circuit model;

[0049] The capacitance estimation module is used to estimate the capacitance C corresponding to the intersection frequency f1 based on the simplified power circuit model. g , to select a first capacitor C1; and determine a minimum specification capacitor Ci based on the first capacitor C1; select a capacitor group starting with C1 and ending with Ci; and

[0050] Calculate the total impedance Z_model of the simplified power circuit model and determine whether it meets the target impedance Z0 requirement.

[0051] Compared with the prior art, this solution has at least the following beneficial effects:

[0052] A better capacitor solution selection is achieved, the problem of the deep valley shape of impedance affecting noise after capacitor optimization is solved, impedance flattening is achieved within the target frequency band, and invalid parallel capacitor combinations are avoided. The capacitor combination selection can be completed by simply calculating the first capacitor selected corresponding to the target impedance intersection frequency, reducing the number of capacitor selections and the amount of calculation. The simplified circuit model proposed in this solution comprehensively considers the actual parasitic effects of the PCB, has a good impedance curve fit, and a high degree of matching with the actual added capacitor effect. It is suitable for various circuit conditions and solves the problems of large resonant frequency calculation errors and large deviations between capacitor effects and calculations in previous technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A flow chart of a capacitor optimization selection method according to an embodiment of the present invention;

[0055] Figure 2 A simplified model schematic diagram of a power network circuit according to an embodiment of the present invention;

[0056] Figure 3 A schematic diagram of a power supply network structure according to an embodiment of the present invention;

[0057] Figure 4 This is an example of a capacitor combination of an embodiment of the present invention, which is composed of C1: 2200n, C2: 1000n, C3: 470n, C4: 220n, and C5: 100n;

[0058] Figure 5 It is a comparison diagram of impedance curves before and after optimization of an embodiment of the invention. DETAILED DESCRIPTION

[0059] The following will be combined with the figures in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0060] In a specific embodiment, Figure 1 As shown, the decoupling capacitor optimization scheme selection method provided by the present invention includes:

[0061] Step 1: Set the target impedance and frequency range [0,f0].

[0062] 1.1 According to the chip design manual, the voltage fluctuation requirements and frequency range [0, f0] are obtained. Combined with the current model Iinput of the power network, the target impedance Z0 is calculated according to the following formula:

[0063]

[0064] Where Z0 represents the target impedance, VDD represents the power supply voltage, Ripple represents the allowable voltage fluctuation ratio, and α represents the constant factor, which can be set to a fixed value acceptable in engineering. For example, if α is set to 2, ΔIMAX Represents the maximum current change value in the current model Iinput.

[0065] Step 2: Determine whether the intersection frequency f1 of the curve of the actual impedance Z and the target impedance Z0 is less than f0. If f < f0, execute Step 3.1; if f ≥ f0, execute Step 7.2.

[0066] Step 3: Improve the power supply simplified circuit model. In an alternative embodiment, in combination with Figure 2 、 Figure 3 , Step 3 includes:

[0067] 3.1: Obtain the capacitor placement positions according to the chip manufacturer's design requirements, and obtain the inductances corresponding to each capacitor position, corresponding to Figure 3 the path part from module a to module b. Use loop_L to represent the maximum value among the loop inductances of each capacitor branch. According to the relationship loop_L = l2 + l4, and in combination with the following formula, the specific values of l2 and l4 can be obtained:

[0068]

[0069] Calculate the via parasitic inductance ESL according to the following method: And obtain the ratio relationship between l2 and l4 based on ESL.

[0070] Among them, for the structures and parameters involved in l2 and l4, reference can be made to Figure 3 , module a is the power supply network part, where l4 is the parasitic inductance from the power supply bump end to the power supply plane layer, and the distance between the two planes is h1; module b is the capacitor part, l2 is the parasitic inductance from the capacitor position to the power supply plane layer, and the distance between the two planes is h2; d is the via diameter.

[0071] 3.2: Simulate to obtain the impedance curve Z_net of the power supply position. From the curve, the simplified L and R values at low frequencies can be obtained as L_net and R_net;

[0072] 3.3: Simulate to obtain the impedance curve Z_CAP of the capacitor position. From the curve, the simplified L and R values at low frequencies can be obtained as L_CAP and R_CAP;

[0073] Determine the parameters of l1, r1, and r2 according to the following relational formulas:

[0074] L_CAP = l1 + l2

[0075] R_CAP = r1 + r2

[0076] R_net = r1

[0077] Among them, r1 represents the equivalent resistance of the VRM branch, r2 represents the equivalent resistance of the capacitor C1 branch, and l1 represents the equivalent inductance of the VRM branch.

[0078] 3.4: Substitute the parameter values ​​to complete the establishment of the simplified power circuit model and obtain the simplified power circuit model. Figure 2 .

[0079] Step 4: Execute the first capacitor selection strategy. In an optional embodiment, step 4 includes:

[0080] 4.1: Based on the simplified circuit model improved in step 3, use the formula Estimate the capacitance value C that needs to be added corresponding to the frequency f1 g , select capacitor specifications and C from the capacitor library g A similar capacitor is used as the first capacitor C1;

[0081] If there are multiple capacitors of different models with the same capacitance specifications, further selection should be made according to the following principles:

[0082] 4.2 Choose a capacitor with an ESR less than Z0 and as large as possible;

[0083] 4.3 Calculate the total impedance Z_model of the circuit model after adding the first capacitor. If Z_model is not greater than 1.8Z0 at this time, the first capacitor selection is completed, and then step (5) is executed, otherwise continue with step 4.4;

[0084] 4.4 Increase the number of first capacitors by 1 and execute step 4.3. When there is a quantity constraint on the selected first capacitor model, the capacitance value can be increased, that is, a capacitor with a larger capacitance value can be selected, and then execute step 4.3 for judgment;

[0085] Step 5: Execute the capacitor scheme selection strategy. In an optional embodiment, step 5 includes:

[0086] 5.1: According to the resonant frequency formula The corresponding relationship between capacitance and resonant frequency is obtained as follows:

[0087] It is used to estimate the minimum capacitance Cgi in the capacitor combination, and select a capacitor with a capacitance specification close to Cgi as Ci in the capacitor library;

[0088] 5.2: After determining the first capacitor C1 and the minimum specification capacitor Ci, select a capacitor combination starting with C1 and ending with Ci from the capacitor combination library. The capacitor combination effect is as follows Figure 4As shown, the impedance flattening within the action frequency band can be achieved. In the capacitor combination, the capacitance values ​​are represented by C2, C3, C4...Ci from large to small; more preferably, the selection of the capacitor combination needs to meet the following requirements: the impedance in the capacitor combination is less than Z0, and the capacitor with the equivalent resistance ESRi close to the first capacitor equivalent resistance ESR1 should be selected to avoid the failure of the capacitor parallel connection caused by excessive ESR.

[0089] Step 6: Calculate whether the total impedance Z_model of the circuit model meets the target impedance requirement.

[0090] 6.1: Add the RLC models of the i capacitors in the capacitor combination to the circuit model, and we get Among them, X l4 represents the inductive reactance corresponding to the via inductance l4 of the net branch, X l1 represents the inductive reactance corresponding to the equivalent inductance l1 of the VRM branch, X C1 Represents the capacitive reactance corresponding to capacitor C1, r C1 Indicates the equivalent resistance corresponding to capacitor 1.

[0091] 6.2 Calculate |Z_model| at the frequency of f1, and determine whether |Z_model| is less than Z0. If so, proceed to step 6.3; otherwise, return to step 4.4;

[0092] 6.3: Calculate |Z_model| at frequency f0 and determine whether |Z_model| is less than Z0. If so, proceed to step 7; otherwise, add a capacitor of Ci specification to the capacitor combination, set i=i+1, and proceed to step 6.1.

[0093] Step 7: Complete decoupling capacitor optimization.

[0094] 7.1: According to the loop_L values ​​of different capacitor branches obtained from the above simulation, capacitors are placed according to the principle of placing small capacitors for small loop_L;

[0095] 7.2: Complete the optimization selection of decoupling capacitors.

[0096] The following is a further explanation with an example, taking a printed circuit board as an example to verify the solution provided by the present invention. A DDR_PHY power network with a voltage level of 0.85V is selected as the verification object, the ripple factor is 5%, the chip operating current is set to 3.3A, and the decoupling target frequency is 10MHz. The solution is simulated and verified, and the simulation results are as follows: Figure 5 As shown, the dotted curve is the PDN impedance curve before optimization, and the realized curve is the PDN impedance curve after optimization. Figure 5In the figure, the horizontal axis represents frequency, the vertical axis represents impedance, and the number of decoupling capacitors used before and after optimization is shown in Table 1. From the simulation results, it can be seen that the number of decoupling capacitors used after the optimization of the present invention is less, and the power supply impedance can be optimized from the order of 100mohm to the target impedance of 12.8mohm, and the decoupling optimization effect is significant. Table 1 shows the results analysis before and after the optimization of the present invention:

[0097] Table 1 Comparison of the results of the decoupling capacitor scheme before and after optimization using the present invention

[0098]

[0099] This solution is well suited for all power systems and all networks that require power capacitor optimization, including but not limited to boards, packages, chips, boards + packages + chips, small voltage and high current, high voltage and high current and other application scenarios.

[0100] In another specific real-time example, the present solution can also be implemented in a system manner. The system is used to implement the decoupling capacitor optimization method described in the above embodiment. The system includes:

[0101] The impedance curve module is used to obtain the actual impedance curve of the power distribution network and obtain the intersection frequency f1 of the actual impedance curve and the target impedance; determine the relationship between f1 and f0; wherein the frequency range of the power distribution network is [0, f0];

[0102] The power circuit model simplification module is used to obtain the ratio between the parasitic inductance l4 of the power bump section and the parasitic inductance l2 from the capacitor position to the power plane layer based on the capacitor placement position and the via parasitic inductance, obtain the simplified inductance L_net and impedance value, R_net at low frequency based on the impedance curve at the power position, and obtain the simplified inductance L_CAP and impedance value R_CAP at low frequency based on the impedance curve at the capacitor position; based on the ratio between l4 and l2, L_net, R_net, L_CAP and R_CAP, obtain the simplified power circuit model;

[0103] The capacitance estimation module is used to estimate the capacitance C corresponding to the intersection frequency f1 based on the simplified power circuit model. g , to select a first capacitor C1; and determine a minimum specification capacitor Ci based on the first capacitor C1; select a capacitor group starting with C1 and ending with Ci; and

[0104] Calculate the total impedance Z_model of the simplified power circuit model and determine whether it meets the target impedance Z0 requirement.

[0105] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PDN decoupling capacitor optimization method, characterized in that: The method includes: S1. Determine the target impedance Z0 of the power distribution network and the frequency range [0, f0]; S2. Obtain the actual impedance curve of the power distribution network, and judge the relationship between the intersection frequency f1 of the actual impedance curve and the target impedance and f0; if f < f0, execute step S3, if f ≥ f0, then execute step S7; S3. Obtain the ratio between the parasitic inductance l4 of the power bump section and the parasitic inductance l2 from the capacitor position to the power plane layer according to the capacitor placement position and the via parasitic inductance. Based on the impedance curve at the power position, obtain the simplified inductance L_net and impedance value R_net at low frequency, and based on the impedance curve at the capacitor position, obtain the simplified inductance L_CAP and impedance value R_CAP at low frequency; based on the ratio between l4 and l2, L_net, R_net, L_CAP and R_CAP, obtain the simplified power circuit model; S4. Based on the simplified power circuit model, estimate the capacitance C corresponding to the intersection frequency f1 g , to select and obtain the first capacitor C1; S5. Determine the minimum specification capacitor Ci based on the first capacitor C1; select a capacitor group starting from C1 and ending with Ci; S6. Calculate whether the total impedance Z_model of the simplified power circuit model meets the requirement of the target impedance Z0. If it meets the requirement, execute S7, otherwise adjust the first capacitor C1 or the capacitor group; S7. Complete the decoupling capacitor optimization.

2. The method according to claim 1, characterized in that In the above S1, the determination method of the target impedance Z0 is: Among them, Z0 represents the target impedance, VDD represents the power supply voltage, Ripple represents the allowable voltage fluctuation ratio, α represents the constant factor, ΔI MAX Indicates the maximum current change value in the current model Iinput.

3. The method according to claim 1, characterized in that In the above S3, the determination method of the ratio relationship between l4 and l2 is: Wherein, h1 is the distance from the plane layer where the power bump end is located to the power plane layer; the b module is the capacitor part, h2 is the distance from the plane layer where the capacitor position is located to the power plane layer; d is the via diameter.

4. The method according to claim 3, characterized in that In the above S3, obtaining the simplified power circuit model based on the ratio between l4 and l2, L_net, R_net, L_CAP and R_CAP further includes: Calculate the parameters of the simplified power circuit model in the following way: L_CAP = l1 + l2 R_CAP = r1 + r2 R_net = r1 Wherein, r1 represents the equivalent resistance of the VRM branch, r2 represents the equivalent resistance of the capacitor C1 branch, and l1 represents the equivalent inductance of the VRM branch.

5. The method according to claim 1, characterized in that In S4, the capacitor C g The calculation method is: Wherein, loop_L represents the maximum value among the loop inductances of each capacitor branch according to the design requirements.

6. The method according to claim 1, characterized in that In S4, when selecting capacitor C1, select the capacitor specification and C from the capacitor library. g The closest capacitor; If there are multiple capacitors with the same specification but different models in the capacitor library, the selection method is as follows: S41. Prioritize selecting a capacitor with an ESR less than Z0 and the largest possible capacitor specification, and then execute S42; S42. Calculate the total impedance Z_model after adding the first capacitor C1. If Z_model ≤ 1.8Z0, complete the selection of C1, otherwise execute S43; S43. Increase the number of preselected first capacitors by 1, and then execute step S42. If there is a quantity constraint on the first capacitor, then increase the capacitance value of the selected capacitor, and then execute step S42.

7. The method according to claim 1, characterized in that In the above S5, the selection method of the minimum specification capacitor Ci is: Estimate Cgi based on the above formula, and select a capacitor in the capacitor library with a capacitance specification close to Cgi as Ci.

8. The method according to claim 1, characterized in that In the above S6, after adding the capacitor group, the calculation method of the total impedance Z_model is: Among them, X l4 represents the inductive reactance corresponding to the via inductance l4 of the net branch, X l1 represents the inductive reactance corresponding to the equivalent inductance l1 of the VRM branch, X C1 Represents the capacitive reactance corresponding to capacitor C1, r C1 Indicates the equivalent resistance corresponding to capacitor 1.

9. The method according to claim 1, characterized in that: The above S6 further includes: S61, calculating |Z_model| at the intersection frequency f1, and determining whether |Z_model| is less than Z0, if so, executing S62, otherwise adjusting the first capacitor C1; S62, calculate |Z_model| at frequency f0, and determine whether |Z_model| is less than Z0. If so, execute step S7; otherwise, add a capacitor of Ci specification to the capacitor group, set i=i+1, recalculate Z_model, and execute step S61.

10. A PDN decoupling capacitor optimization system, characterized in that: The system is used to implement the method according to any one of claims 1 to 9, and the system includes: The impedance curve module is used to obtain the actual impedance curve of the power distribution network and obtain the intersection frequency f1 of the actual impedance curve and the target impedance; determine the relationship between f1 and f0; wherein the frequency range of the power distribution network is [0, f0]; The power circuit model simplification module is used to obtain the ratio between the parasitic inductance l4 of the power bump section and the parasitic inductance l2 from the capacitor position to the power plane layer based on the capacitor placement position and the via parasitic inductance, obtain the simplified inductance L_net and impedance value, R_net at low frequency based on the impedance curve at the power position, and obtain the simplified inductance L_CAP and impedance value R_CAP at low frequency based on the impedance curve at the capacitor position; based on the ratio between l4 and l2, L_net, R_net, L_CAP and R_CAP, obtain the simplified power circuit model; The capacitance estimation module is used to estimate the capacitance C corresponding to the intersection frequency f1 based on the simplified power circuit model. g , to select a first capacitor C1; and determine a minimum specification capacitor Ci based on the first capacitor C1; select a capacitor group starting with C1 and ending with Ci; and Calculate the total impedance Z_model of the simplified power circuit model and determine whether it meets the target impedance Z0 requirement.

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