Power consumption seamless switching circuit suitable for high gain long endurance applications

Abstract

The application discloses a power consumption seamless switching circuit suitable for high-gain long-endurance application, solves the problem that direct switching of bias current through a switch brings electronic pulse interference and random noise to a system in the prior art, and comprises a voltage-current conversion circuit, a power consumption seamless switching circuit and a comparator circuit; the power consumption seamless switching circuit determines the states of Y2 and VSW signals by comparing the duration of high level in the VCTL signal with the size of the blanking time set in the blanking circuit; the VSML signal is obtained according to the Y2 and VSW signals; the voltage-current conversion circuit controls the size of the access resistance to realize voltage-current seamless switching and output the ISML signal; the comparator circuit controls the size of the resistance in the access comparator circuit according to the states of the VSW signal and the VSML signal to realize gain seamless switching and output the VCMP signal; the precision of the system is ensured, and the system disorder in the sleep mode is avoided.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of switching power supplies, in particular to a power consumption seamless switching circuit suitable for high-gain long-endurance applications. BACKGROUND

[0002] Portable electronic devices usually require very low power consumption to improve device endurance, and the traditional scheme is to set a sleep mode in the chip, and the system works between normal mode and sleep mode, and in sleep mode, very low static current can be achieved to improve work efficiency and prolong the working time of the device.

[0003] The traditional scheme is to directly switch the bias current through a switch to realize the conversion of the system from the normal working mode to the sleep mode, but directly switching the bias current through a switch will bring electronic pulse interference and random noise to the system. Taking a switching power supply as an example, the direct switching of the bias current may also cause the ring comparator to appear false flip and other situations, affecting the normal work of the system; at the same time, the power consumption and gain of the ring comparator are a compromise, and in the traditional scheme, the gain of the ring comparator in the sleep mode will decrease due to the decrease of the bias current, resulting in the decrease of the identification accuracy of the comparator, and further causing the increase of the comparator flip delay, and even the false flip situation, causing the disorder of the system. SUMMARY

[0004] The application provides a power consumption seamless switching circuit suitable for high-gain long-endurance applications, which solves the problem of electronic pulse interference and random noise caused by directly switching the bias current through a switch in the prior art, ensures the accuracy of the system and avoids the disorder of the system in the sleep mode.

[0005] The application provides a power consumption seamless switching circuit suitable for high-gain long-endurance applications, which includes a voltage-current conversion circuit, a power consumption seamless switching circuit and a comparator circuit.

[0006] The power consumption seamless switching circuit is used for determining the state of the Y2 signal and the state of the VSW signal by comparing the duration of the high level in the VCTL signal with the size of the blanking time set in the blanking circuit, and obtaining the VSML signal according to the state of the Y2 signal and the state of the VSW signal, wherein the state includes low level and high level.

[0007] The voltage-current conversion circuit is used for judging whether the first current mirror in the voltage-current conversion circuit is enabled according to the state of the VSML signal and the state of the VSW signal, and then controlling the size of the access resistance in the voltage-current conversion circuit to realize voltage-current seamless switching and output the ISML signal.

[0008] The comparator circuit is used to control the size of the resistor connected to the comparator circuit according to the state of the VSW signal, and to achieve seamless gain switching in combination with the second current mirror according to the VSML signal to output a VCMP signal.

[0009] In a possible implementation, comparing the duration of the high level in the VCTL signal with the blanking time set in the blanking circuit to determine the state of the Y2 signal and the state of the VSW signal respectively includes:

[0010] If the VCTL signal is a low level signal, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level;

[0011] If the VCTL signal is a high-level signal, and the duration of the high level of the VCTL signal is less than the blanking time, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level;

[0012] If the VCTL signal is a high-level signal, and the duration of the high level of the VCTL signal is greater than or equal to the blanking time, the state of the Y2 signal is low and the state of the VSW signal is high during the blanking time; outside the blanking time, the state of the Y2 signal is high and the state of the VSW signal is low.

[0013] In a possible implementation, the power consumption seamless switching circuit includes: a first inverter, a second inverter, a blanking circuit, a switch tube M7, a switch tube M8, a capacitor C1, a capacitor C2, a resistor R5, and a mirror tube M9;

[0014] The input end of the first inverter inputs the VCTL signal, and the output end of the first inverter is connected to the input end of the second inverter;

[0015] The output terminal of the second inverter is connected to the input terminal of the blanking circuit;

[0016] The output end of the blanking circuit is connected to the gate end of the switch tube M7 and the gate end of the switch tube M8 respectively;

[0017] The source end of the switch tube M7 is connected to the power supply VDD, and the drain end of the switch tube M7 is connected to the drain end of the switch tube M8;

[0018] The source end of the switch tube M8 is grounded;

[0019] The upper plate of the capacitor C1 is connected to the voltage-current conversion circuit, and the lower plate of the capacitor C1 is connected to the drain end of the mirror tube M9;

[0020] The upper plate of the capacitor C2 is connected with the voltage current conversion circuit, and the lower plate of the capacitor C2 is connected with the first end of the resistor R5.

[0021] The gate end of the mirror tube M9 is connected with the lower plate of the capacitor C1, and the source end of the mirror tube M9 is connected with the second end of the resistor R5 and the drain end of the switch tube M7.

[0022] In a possible implementation, the voltage current conversion circuit comprises an error amplifier EA, a power tube M2, a load resistor R1, a mirror tube M1, a mirror tube M3, a resistor R2 and a switch tube M4.

[0023] The positive input end of the error amplifier EA is connected with a reference voltage VREF, the negative input end of the error amplifier EA is connected with the source end of the power tube M2 and the first end of the load resistor R1, and the output end of the error amplifier EA is connected with the gate end of the power tube M2.

[0024] The source end of the mirror tube M1 is connected with a power supply VDD, the gate end of the mirror tube M1 is connected with the drain end of the mirror tube M1, the drain end of the power tube M2 and the comparator circuit.

[0025] The second end of the load resistor R1 is connected with the drain end of the mirror tube M3.

[0026] The gate end of the mirror tube M3 is connected with the power consumption seamless switching circuit, and the source end of the mirror tube M3 is connected with the second end of the resistor R2.

[0027] The first end of the resistor R2 is connected with the second end of the load resistor R1, and the second end of the resistor R2 is grounded.

[0028] The gate end of the switch tube M4 is connected with the power consumption seamless switching circuit, the drain end of the switch tube M4 is connected with the first end of the resistor R2, and the source end of the switch tube M4 is grounded.

[0029] In a possible implementation, the first current mirror comprises the mirror tube M9 in the power consumption seamless switching circuit and the mirror tube M3 in the voltage current conversion circuit.

[0030] In a possible implementation, the comparator circuit comprises a comparator CMP, a mirror tube M5, a switch tube M6, a resistor R3 and a load resistor R4.

[0031] The current bias input end of the comparator CMP is connected with the voltage current conversion circuit, and the output end of the comparator CMP is connected with the first end of the resistor R3.

[0032] The second end of the resistor R3 is connected with the drain end of the switch tube M6.

[0033] The source end of the switch tube M6 is grounded, and the gate end of the switch tube M6 is connected with the power consumption seamless switching circuit.

[0034] The source end of the mirror tube M5 is grounded, the gate end of the mirror tube M5 is connected with the power consumption seamless switching circuit, and the drain end of the mirror tube M5 is connected with the second end of the resistor R3.

[0035] The first end of the load resistor R4 is connected with the first end of the resistor R3, and the second end of the load resistor R4 is grounded.

[0036] In a possible implementation, the second current mirror comprises a mirror tube M9 in the power consumption seamless switching circuit and a mirror tube M5 in the comparator circuit.

[0037] The one or more technical solutions provided in the application have at least the following technical effects or advantages:

[0038] The application realizes seamless switching of current bias by combining the power consumption seamless switching circuit with the voltage-current conversion circuit, avoids problems such as random noise, electronic pulse and system stability caused by switching to the system, realizes seamless switching of current bias, maintains high gain in the low-power sleep mode through switching of the load resistor in the comparator circuit, ensures the accuracy of the system, and avoids disorder of the system in the sleep mode. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 The power consumption seamless switching circuit provided by the embodiment of the application is suitable for high-gain long-endurance applications.

[0040] Figure 2 The power consumption seamless switching circuit provided by the embodiment of the application is suitable for high-gain long-endurance applications.

[0041] Figure 3 The voltage-current conversion circuit provided by the embodiment of the application is suitable for high-gain long-endurance applications. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0043] The application provides a power consumption seamless switching circuit suitable for high-gain long-endurance applications, as shown in Figure 1As shown, the circuit comprises: a voltage-current conversion circuit, a power seamless switching circuit and a comparator circuit.

[0044] The ISML signal is an output voltage signal of the voltage-current conversion circuit, provides a bias current for the comparator, and is a voltage signal with a slow change.

[0045] The VSW signal is a switching signal for controlling the switching tubes M4 and M6.

[0046] The VSML signal is a gate voltage of the current mirror M9 in the power seamless switching circuit, controls the mirror tubes M3 and M5, and is a voltage signal with a slow change.

[0047] The VCTL signal is a control signal for power switching, and a high level represents a small bias current output by the voltage-current conversion circuit.

[0048] The VCMP signal is an output signal of the comparator.

[0049] The power seamless switching circuit is configured to determine the state of the Y2 signal and the state of the VSW signal by comparing the duration of the high level in the VCTL signal with the size of the blanking time set in the blanking circuit, and obtain the VSML signal according to the state of the Y2 signal and the state of the VSW signal; wherein the state includes: low level and high level; and the blanking circuit is configured to reduce the disturbance of the front-stage control signal and the influence caused by frequent switching.

[0050] Specifically, in the power seamless switching circuit, as shown in Figure 2 the power seamless switching circuit comprises: a first inverter, a second inverter, a blanking circuit, a switching tube M7, a switching tube M8, a capacitor C1, a capacitor C2, a resistor R5, and a mirror tube M9.

[0051] The input end of the first inverter inputs the VCTL signal, and the output end of the first inverter is connected with the input end of the second inverter; the output end of the second inverter is connected with the input end of the blanking circuit; the output end of the blanking circuit is connected with the gate end of the switching tube M7 and the gate end of the switching tube M8 respectively; the source end of the switching tube M7 is connected with a power supply VDD, and the drain end of the switching tube M7 is connected with the drain end of the switching tube M8; the source end of the switching tube M8 is grounded; the upper plate of the capacitor C1 is connected with the voltage-current conversion circuit, and the lower plate of the capacitor C1 is connected with the drain end of the mirror tube M9; the upper plate of the capacitor C2 is connected with the voltage-current conversion circuit, and the lower plate of the capacitor C2 is connected with the first end of the resistor R5; the gate end of the mirror tube M9 is connected with the lower plate of the capacitor C1, and the source end of the mirror tube M9 is connected with the second end of the R5 and the drain end of the switching tube M7.

[0052] Specifically, if the VCTL signal is a low-level signal, the state of the Y2 signal is low level, and the state of the VSW signal is high level;

[0053] If the VCTL signal is a high level signal and the duration of the high level of the VCTL signal is less than the blanking time, the state of the Y2 signal is low level and the state of the VSW signal is high level;

[0054] If the VCTL signal is a high level signal and the duration of the high level of the VCTL signal is greater than or equal to the blanking time, the state of the Y2 signal is low level and the state of the VSW signal is high level within the blanking time; the state of the Y2 signal is high level and the state of the VSW signal is low level outside the blanking time.

[0055] For example, as shown in FIG. 1, when the control signal VCTL signal is low level, the Y1 signal output is low, the switch tube M4 is turned on when the VSW is high level, the resistance R2 is short-circuited, and the voltage-current conversion circuit outputs a large bias current. Figure 2

[0056] When the control signal VCTL signal is high level but the duration is less than the blanking time, the Y1 signal first flips to high level, but because of the blanking circuit, the Y2 signal is still low level, and the Y1 signal flips low again before the end of the blanking time, so the VSW signal is always high in this process, and the voltage-current conversion circuit maintains output of a large bias current.

[0057] When the control signal VCTL signal is high level and the duration is longer than the blanking time, because the VSW signal is high level within the blanking time, the lower plate of the capacitor C1 and C2 is charged through the resistance R5, at this time CS is equal to the VSW signal being high level, at this time the VGS of the mirror tube M9 is 0 (gate-source voltage), so the mirror tube M9 and the mirror tube M3 in the first current mirror are not enabled.

[0058] For example, as shown in FIG. 1, when the control signal VCTL signal is low level, the Y1 signal output is low, the switch tube M4 is turned on when the VSW is high level, the resistance R2 is short-circuited, and the voltage-current conversion circuit outputs a large bias current. Figure 2 As shown in FIG. 1, the VCTL signal is the input signal of the power seamless circuit, the Y2 signal is generated after two-stage inverters and blanking circuits, the Y2 signal is connected to the gate end of the switch tube M7 and the switch tube M8, the source end of the switch tube M7 is connected to the power supply VDD, and the source end of the switch tube M8 is connected to the ground. The drain end of the switch tube M7 and the drain end of the switch tube M8 are connected to the second end of the resistance R5 and the source end of the mirror tube M9. The drain end and the gate end of the mirror tube M9 are connected to the first end of the resistance R5 and the lower plate of the capacitor C1 and the capacitor C2. The upper plate of the capacitor C1 and the capacitor C2 is connected to the second end of the load resistance R1 in the voltage-current conversion circuit. At the same time, the gate end of the mirror tube M9 as the output signal of the power seamless switching circuit is connected to the gate end of the mirror tube M5 of the comparator circuit and the gate end of the mirror tube M3 in the voltage conversion circuit.

[0059] ​A voltage-current conversion circuit is used to determine whether the first current mirror in the voltage-current conversion circuit is enabled based on the status of the VSML signal and the status of the VSW signal, thereby controlling the size of the access resistor in the voltage-current conversion circuit to achieve seamless switching of voltage and current, and outputting an ISML signal;

[0060] Specifically, such as Figure 3 As shown, the voltage-current conversion circuit includes: an error amplifier EA, a power tube M2, a load resistor R1, a mirror tube M1, a mirror tube M3, a resistor R2 and a switch tube M4;

[0061] The positive input terminal of the error amplifier EA is connected to the reference voltage VREF, the negative input terminal of the error amplifier EA is connected to the source terminal of the power tube M2 and the first end of the load resistor R1, and the output terminal of the error amplifier EA is connected to the gate terminal of the power tube M2;

[0062] The source end of the mirror tube M1 is connected to the power supply VDD, and the gate end of the mirror tube M1 is connected to the drain end of the mirror tube M1, the drain end of the power tube M2, and the comparator circuit;

[0063] The second end of the load resistor R1 is connected to the drain end of the mirror tube M3;

[0064] The gate end of the mirror tube M3 is connected to the power consumption seamless switching circuit, and the source end of the mirror tube M3 is connected to the second end of the resistor R2;

[0065] A first end of the resistor R2 is connected to the second end of the load resistor R1 , and a second end of the resistor R2 is grounded.

[0066] For example, Figure 3 As shown, the error amplifier EA clamps the voltage. Its output is connected to power transistor M2, its positive input is connected to the VREF voltage, and its negative input is connected to load resistor R1. The voltage-to-current conversion circuit achieves current switching by controlling resistor R2 through switch M4, which switches the output load. The key to seamless switching lies in mirror transistor M3, which serves as the mirror transistor for the current mirror. In normal system mode, since the mirror transistor for the current mirror draws no current, the load of the voltage-to-current conversion circuit is R1, connected to ground through switch M4. When the system switches from normal mode to sleep mode, the VCTL signal flips from low to high, enabling the current mirror.

[0067] The positive input terminal of the error amplifier EA is connected to the VREF voltage, the output terminal is connected to the gate terminal of the power transistor M2, the source terminal of the power transistor M2 is connected to the negative input terminal of the operational amplifier and the first terminal of the load resistor R1, the second terminal of the load resistor R1 is connected to the drain terminal of the mirror transistor M3, the switch transistor M4 and the first terminal of the resistor R2, the gate terminal of the mirror transistor M3 is connected to the output signal VSML of the power seamless switching circuit, the gate terminal of the switch transistor M4 is connected to the output signal VSW of the power seamless switching circuit, the source terminal of the mirror transistor M3, the switch transistor M4 and the second terminal of the resistor R2 are connected to the ground. The drain terminal of the power transistor M2 is connected to the drain terminal of the mirror transistor M1, and is connected to the gate terminal of the mirror transistor M1 at the same time, and is connected to the comparator circuit as an output signal. The source terminal of the mirror transistor M1 is connected to the power supply VDD.

[0068] When the control signal VCTL signal is high for a long time, the Y2 signal is flipped to high level, the voltage VSW signal between the drain terminal of M7 and the drain terminal of M8 is instantaneously low, at this time, the switch transistor M4 is turned off, and the resistor R2 is connected to the load of the voltage current conversion circuit; at the same time, the capacitor lower plate CS node is discharged through the switch transistor M8 and the resistor R5, compared with the VSW signal node, the capacitor discharge process is a slow process, at this time, the mirror transistor M9 is instantaneously low after the VSW signal, because the capacitor plate voltage will not change suddenly, at this time, the voltage difference between the CS node and the VSW signal node is VDD, that is, the VGS of the mirror transistor M9 is equal to VDD, at this time, the mirror transistor M9 and the mirror transistor M3 enable the current mirror to mirror a larger current to the voltage current conversion circuit, the addition of the mirror current avoids the output bias current change too fast caused by the instantaneous switching of the load resistor of the voltage current conversion circuit, with the discharge of the capacitor, the voltage of the lower plate of the capacitor C1, C2 gradually decreases, and the mirror current gradually decreases, until the voltage of the lower plate of the capacitor C1, C2 decreases to the threshold voltage of the mirror transistor M9, the mirror current of the current mirror decreases to 0, thus the bias current seamless switching is completed, and the system is converted from the normal working mode to the sleep mode. The bias current generated by the voltage current conversion circuit in this process is different from the bias current obtained by directly switching the voltage current circuit load, that is, the former obtains a slowly changing output current, thereby avoiding the problems of electronic pulse interference, random noise and system stability and the like to the system.

[0069] The comparator circuit controls the size of the resistor connected to the comparator circuit according to the state of the VSW signal, and realizes gain seamless switching according to the VSML signal combined with the second current mirror, and outputs the VCMP signal.

[0070] Specifically, as Figure 3The comparator CMP, the mirror tube M5, the switch tube M6, the resistor R3 and the load resistor R4 are shown; the current bias input end of the comparator CMP is connected with the voltage current conversion circuit, the output end of the comparator CMP is connected with the first end of the resistor R3; the second end of the resistor R3 is connected with the drain end of the switch tube M6; the source end of the switch tube M6 is grounded, the gate end of the switch tube M6 is connected with the power consumption seamless switching circuit; the source end of the mirror tube M5 is grounded, the gate end of the mirror tube M5 is connected with the power consumption seamless switching circuit, the drain end of the mirror tube M5 is connected with the second end of the resistor R3; the first end of the load resistor R4 is connected with the first end of the resistor R3, the second end of the load resistor R4 is grounded.

[0071] Here, the second current mirror includes: the mirror tube M9 in the power consumption seamless switching circuit and the mirror tube M5 in the comparator circuit.

[0072] For example, the seamless switching of the gain is realized by changing the comparator load resistor, and the gain seamless switching process is as follows: taking the loop comparator in the switching power supply as an example, the resistor R3 and the load resistor R4 represent the load resistor inside the comparator, and the gain seamless switching is realized through the mirror tube M5, the switch tube M6 and the load resistor R4. The same as the power consumption switching process, during the normal working process of the comparator circuit, the VSW signal is high, the load resistor R4 is short-circuited through the switch tube M6, at this time the load inside the comparator is the resistor R3, at this time the comparator gain is relatively small.

[0073] When the VCTL signal control signal is high and the duration is longer than the blanking time, the VSW signal is low, the switch tube M6 is off, and the load resistor R4 is connected to the comparator circuit, but through the analysis of the power consumption seamless switching process, at this time the mirror tube M5 will have a large mirror current, so at this time the current of the comparator almost flows into the ground through the mirror tube M5, at this time the mirror tube M5 is in the deep linear region, and the impedance is very small. Since a large resistor value is required to obtain high gain, the impedance of the mirror tube M5 is much smaller than that of the load resistor R4 at this moment, and the parallel equivalent impedance of the two is very small, which is equivalent to the mirror tube M5 short-circuiting the load resistor R4, so at this moment the gain of the comparator is the same as when the switch tube M6 is turned on. With the gradual decrease of the current mirror current, the impedance of the parallel connection of the load resistor R4 and the equivalent resistance of the mirror tube M5 gradually increases, and the gain of the comparator circuit gradually increases with the decrease of the mirror current. Because the mirror current of the mirror tube changes slowly, the gain of the comparator is also gradually and slowly increased, and this process realizes the seamless switching of the gain of the comparator.

[0074] The various embodiments in this specification are described in a progressive manner, and the same or similar parts among the various embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments. The whole or part of the present application can be used in a variety of general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, mobile communication terminals, multi-processor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like.

[0075] The above examples are only used to illustrate the technical solutions of the present application, and are not limited to the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or part or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the present application.

Claims

1. A power consumption seamless switching circuit suitable for high-gain and long-endurance applications, characterized in that: include: Voltage-current conversion circuit, power consumption seamless switching circuit and comparator circuit; The power consumption seamless switching circuit includes: a first inverter, a second inverter, a blanking circuit, a switch tube M7, a switch tube M8, a capacitor C1, a capacitor C2, a resistor R5, and a mirror tube M9; The input end of the first inverter inputs the VCTL signal, and the output end of the first inverter is connected to the input end of the second inverter; The output terminal of the second inverter is connected to the input terminal of the blanking circuit; The output terminal Y2 of the blanking circuit is connected to the gate terminal of the switch tube M7 and the gate terminal of the switch tube M8 respectively; The source terminal of the switch tube M7 is connected to the power supply VDD, and the drain terminal VSW of the switch tube M7 is connected to the drain terminal of the switch tube M8; The source end of the switch tube M8 is grounded; The upper plate of the capacitor C1 is connected to the second end of the load resistor R1 in the voltage-current conversion circuit, and the lower plate of the capacitor C1 is connected to the drain end of the mirror tube M9 and the lower plate of the capacitor C2; The upper plate of the capacitor C2 is connected to the second end of the load resistor R1 in the voltage-current conversion circuit, and the lower plate of the capacitor C2 is connected to the first end of the resistor R5; The gate end of the mirror tube M9 is connected to the VSML signal and the lower plate of the capacitor C1, and the source end of the mirror tube M9 is connected to the second end of the resistor R5 and the drain end of the switch tube M7. The voltage-current conversion circuit includes: an error amplifier EA, a power tube M2, a load resistor R1, a mirror tube M1, a mirror tube M3, a resistor R2 and a switch tube M4; The positive input terminal of the error amplifier EA is connected to the reference voltage VREF, the negative input terminal of the error amplifier EA is connected to the source terminal of the power tube M2 and the first end of the load resistor R1, and the output terminal of the error amplifier EA is connected to the gate terminal of the power tube M2; The source end of the mirror tube M1 is connected to the power supply VDD, and the gate end of the mirror tube M1 is connected to the ISML signal, the drain of the mirror tube M1, the drain end of the power tube M2, and the current bias input end of the comparator CMP in the comparator circuit; The second end of the load resistor R1 is connected to the drain end of the mirror tube M3; The gate end of the mirror tube M3 is connected to the VSML signal in the power consumption seamless switching circuit, and the source end of the mirror tube M3 is connected to the second end of the resistor R2; The first end of the resistor R2 is connected to the second end of the load resistor R1, and the second end of the resistor R2 is grounded; The gate terminal of the switch tube M4 is connected to the VSW signal in the power consumption seamless switching circuit, the drain terminal of the switch tube M4 is connected to the first end of the resistor R2, and the source terminal of the switch tube M4 is grounded. The comparator circuit includes: a comparator CMP, a mirror tube M5, a switch tube M6, a resistor R3 and a load resistor R4; The current bias input terminal of the comparator CMP is connected to the ISML signal in the voltage-to-current conversion circuit, and the output terminal of the comparator CMP is connected to the first end of the resistor R3; The second end of the resistor R3 is connected to the drain end of the switch tube M6; The source terminal of the switch tube M6 is grounded, and the gate terminal of the switch tube M6 is connected to the VSW signal in the power consumption seamless switching circuit; The source end of the mirror tube M5 is grounded, the gate end of the mirror tube M5 is connected to the VSML signal of the power consumption seamless switching circuit, and the second end of the drain end resistor R3 of the mirror tube M5 is connected; A first end of the load resistor R4 is connected to a first end of the resistor R3 , and a second end of the load resistor R4 is grounded.

2. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 1, characterized in that: The method of comparing the duration of the high level in the VCTL signal with the blanking time set in the blanking circuit to respectively determine the state of the Y2 signal and the state of the VSW signal includes: If the VCTL signal is a low level signal, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level; If the VCTL signal is a high-level signal, and the duration of the high level of the VCTL signal is less than the blanking time, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level; If the VCTL signal is a high-level signal, and the duration of the high level of the VCTL signal is greater than or equal to the blanking time, the state of the Y2 signal is low and the state of the VSW signal is high during the blanking time; outside the blanking time, the state of the Y2 signal is high and the state of the VSW signal is low.

3. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 1, characterized in that: The power consumption seamless switching circuit is used to determine the state of the Y2 signal and the state of the VSW signal by comparing the duration of the high level in the VCTL signal with the blanking time set in the blanking circuit; and obtain the VSML signal according to the state of the Y2 signal and the state of the VSW signal; wherein the state includes: low level and high level.

4. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 1, characterized in that: The voltage-current conversion circuit is used to determine whether the first current mirror in the voltage-current conversion circuit is enabled according to the state of the VSML signal and the state of the VSW signal, and then control the size of the access resistor in the voltage-current conversion circuit to achieve seamless switching of voltage and current, and output the ISML signal.

5. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 1, characterized in that: The comparator circuit is used to control the size of the resistor connected to the comparator circuit according to the state of the VSW signal, and to achieve seamless gain switching in combination with the second current mirror according to the VSML signal to output a VCMP signal.

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