Insertion method of sub-resolution auxiliary graph

Abstract

The invention discloses an insertion method of a sub-resolution auxiliary graph, and particularly relates to an optimization method of an insertion rule of the sub-resolution auxiliary graph and an insertion method of the sub-resolution auxiliary graph applying the optimization method.The method comprises the steps that firstly, parameters of the sub-resolution auxiliary graph are set, and a distance measurement function is selected according to a main graph; a signed distance function is adopted to convert the main graph into a horizontal set for representation; then, according to the set sub-resolution auxiliary graph parameters, multiple circles of sub-resolution auxiliary graphs are inserted around the main graph; and performing conflict clearing on the multiple circles of sub-resolution auxiliary patterns, and finally performing chamfering operation to finish optimization. And changing the sub-resolution auxiliary graph parameters, respectively inserting the sub-resolution auxiliary graph parameters, and selecting an insertion rule with the maximum improvement of the mask optimization effect as a finally used sub-resolution auxiliary graph insertion rule. The method has the advantages of simple parameters, high mask manufacturability, remarkable mask optimization effect and the like, and is suitable for the field of next-generation integrated circuit manufacturing.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for inserting sub-resolution auxiliary graphics. Background Art

[0002] With the rapid development of semiconductor technology, the feature size of integrated circuits has gradually entered the nanoscale era, which has brought unprecedented challenges to the photolithography process. As the most critical manufacturing process in semiconductor manufacturing, photolithography aims to accurately transfer the design pattern to the silicon wafer to form a micro-nano structure with specific functions. However, with the continuous reduction of feature size, the photolithography process faces a series of severe problems, the most notable of which is the sharp reduction of the process window. The process window refers to the range of photolithography conditions that can ensure that the pattern transfer quality (such as line width, edge roughness, etc.) meets the design requirements, including the fluctuation range of parameters such as exposure dose and focal length. The reduction of the process window means that the photolithography process is more sensitive to changes in process parameters, and any slight deviation may lead to a decrease in product yield. In order to effectively meet this challenge, the industry has widely adopted sub-resolution auxiliary graphics technology.

[0003] Sub-resolution auxiliary patterns (SRAFs) are auxiliary patterns located near the main pattern, which are not directly imaged on the silicon wafer. Their function is to reduce the impact of process parameter changes on pattern transfer quality by affecting the light field distribution during the lithography process and optimizing the light intensity contrast, thereby expanding the process window. The design of sub-resolution auxiliary patterns usually follows certain rules, such as being placed a certain distance from the edge of the main pattern, and the shape is mostly simple parallel strips, in order to maximize the robustness of the lithography process without affecting the final imaging results.

[0004] Sub-resolution auxiliary graphics are usually added in a rule-based way, and the process is as follows: establish a set of sub-resolution auxiliary graphics addition rules, and add sub-resolution auxiliary graphics around the target graphics according to the rules; the other is model-based sub-resolution auxiliary graphics addition, and after the model is established, the sub-resolution auxiliary graphics with the best effect are obtained through iterative fitting operations. Although the traditional sub-resolution auxiliary graphics insertion method has been widely used due to its fewer parameters, intuitive design, and relatively simple tuning, its limitations are also becoming increasingly prominent. First, this simple parallel strip structure has poor adaptability to complex graphics, and it is difficult to fully cope with process changes in different layouts and directions, resulting in limited improvement of the process window. Secondly, as the feature size continues to shrink, the physical effects in the lithography process (such as scattering and diffraction) become more complex, and simple sub-resolution auxiliary graphics design can no longer meet the growing accuracy requirements. Summary of the invention

[0005] The first objective of the present invention is to provide a method for optimizing sub-resolution auxiliary graphic insertion rules in view of the deficiencies in the prior art, which improves the effect of mask optimization while maintaining a simple form.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] A method for optimizing sub-resolution auxiliary graphics insertion rules comprises the following steps:

[0008] S1. Set the sub-resolution auxiliary graphics parameters, including the distance d between the sub-resolution auxiliary graphics and the main graphics. 1 , the distance between sub-resolution auxiliary graphics d 2 and the width w of the sub-resolution auxiliary pattern. The parameters used in the present invention are similar to those of the conventional sub-resolution auxiliary pattern insertion method, but the insertion method is different. The setting of these parameters depends on the experience of engineers. By setting them within a certain range with a reasonable step size, the balance between optimization accuracy and optimization effect can be ensured.

[0009] By properly setting 1 and d 2 , that is, inserting sub-resolution auxiliary graphics at appropriate locations can transform isolated graphics into dense graphics, thereby optimizing the intensity contrast of the main graphics edge, reducing the process variation bandwidth, and increasing the lithography process window. 1 and d 2 The sub-resolution auxiliary pattern may be inserted into the forbidden optical period, which will weaken the light intensity contrast at the edge of the main pattern and have a negative impact on the mask optimization effect. 1 and d 2 Perform detailed parameter tuning.

[0010] A larger w can generally provide a more obvious light intensity contrast optimization effect at the edge of the main pattern, but an overly large w will bring the risk of imaging sub-resolution auxiliary patterns on the silicon wafer, and also needs to be set reasonably.

[0011] S2. According to the given main figure, select a suitable distance metric function and use the signed distance function (SDF) to represent the distance between each point in the design layout and the boundary of the main figure. SDF is a scalar field, in which the value of each point represents the distance from the point to the nearest boundary, and the positive and negative signs indicate whether the point is outside or inside the boundary. Through SDF, the topological structure of the graph can be easily described.

[0012] Furthermore, the distance metric function includes Chebyshev distance, Manhattan distance, Euclidean distance, etc.

[0013] After SDF calculation, the main graphic is converted to a level set representation. Level set is a method to describe the evolution of a curve or surface, which represents the position and shape of the curve or surface through an implicit function. By converting the main graphic to a level set representation, the insertion position and width of the sub-resolution auxiliary graphics can be easily controlled.

[0014] S3, inserting multiple circles of sub-resolution auxiliary graphics around the main graphics according to the sub-resolution auxiliary graphics parameters set in step S1. Specifically, inserting multiple circles of sub-resolution auxiliary graphics around the main graphics that meet the condition "d 1 <SDF<d 1 +w" as the first circle of sub-resolution auxiliary graphics; the area that meets the condition "d 1 +d 2 +w <SDF<d 1 +d 2 +2w” as the second sub-resolution auxiliary graphics; the area that meets the condition “d 1 +2d 2 +2w <SDF<d 1 +2d 2 The area of ​​"+3w" is used as the third circle of sub-resolution auxiliary graphics. Similarly, multiple circles of sub-resolution auxiliary graphics can be inserted.

[0015] Preferably, the number of inserted circles of the sub-resolution auxiliary pattern is three.

[0016] S4, clearing conflicts of sub-resolution auxiliary graphics to ensure that sub-resolution auxiliary graphics and sub-resolution auxiliary graphics and main graphics meet the lithography design rules; after completing the insertion of sub-resolution auxiliary graphics, it is also necessary to consider the conflict between the sub-resolution auxiliary graphics and the minimum graphic spacing, the minimum graphic width, and the sub-resolution auxiliary graphic width w. For these problems, the present invention provides a graphic conflict processing mechanism to ensure that the processed sub-resolution auxiliary graphics meet the preset constraints.

[0017] In the minimum pattern spacing and minimum pattern width, the pattern includes the main pattern and the auxiliary pattern; that is, the minimum pattern distance is the minimum value of the spacing between SRAFs and the spacing between SRAF and the main pattern. When designing SRAF, it is necessary to ensure that the distance between SRAFs and the distance between SRAF and the main pattern is not less than the minimum pattern spacing allowed by the manufacturing process, otherwise it may affect the feasibility of photolithography manufacturing. The minimum pattern width refers to the minimum allowable width that all graphic elements (main pattern and SRAF) must meet.

[0018] S5. Perform chamfering operation on the sub-resolution auxiliary graphics to complete the optimization of the sub-resolution auxiliary graphics. Chamfering operation is a commonly used graphic processing method. By performing chamfering operation on the sub-resolution auxiliary graphics, the degree of the corner can be reduced and the probability of the sub-resolution auxiliary graphics being imaged on the silicon wafer can be reduced. At the same time, the shape of the sub-resolution auxiliary graphics can be made closer to a circle, and the distance between it and the edge of the main graphics can be made more uniform, so as to further improve the mask optimization effect.

[0019] Furthermore, the distance of the chamfering operation may be a fixed distance or a certain ratio of the side length.

[0020] S6. Using the lithography model, respectively correct the optical proximity effect of the lithography patterns into which the different sub-resolution auxiliary patterns are inserted, and evaluate the mask optimization effect. If the mask optimization effect is better than the previous optimal rule, then update the optimal rule.

[0021] Furthermore, the evaluation indicators of the above-mentioned mask optimization effect include process variation bandwidth, pattern fidelity, pattern edge light intensity contrast and number of lithography bad pixels.

[0022] A second object of the present invention is to provide a method for inserting a sub-resolution auxiliary graphic, comprising the following steps:

[0023] S1. According to the integrated circuit layout design rules and lithography process parameters, design the lithography pattern for testing and evaluation, and make it into a mask. After the mask is made, use the mask to expose the silicon wafer, collect measurement data to calibrate the lithography model, and lay the foundation for the subsequent evaluation of the mask optimization effect;

[0024] S2. Using the above optimization method of sub-resolution auxiliary pattern insertion rules, change the set sub-resolution auxiliary pattern parameters and insert different sub-resolution auxiliary patterns into the lithography pattern; the above insertion process can be quickly implemented through electronic design automation (EDA) software to shorten the process development cycle. Then, perform optical proximity effect correction respectively to evaluate the mask optimization effect under different insertion rules.

[0025] S3. Select the insertion rule that has the greatest improvement in mask optimization effect as the final sub-resolution auxiliary graphic insertion rule.

[0026] Furthermore, in the process of determining the insertion rule of the best sub-resolution auxiliary graphics, the optimization algorithms that can be used include grid search method, experimental design method and genetic algorithm.

[0027] A third object of the present invention is to provide a sub-resolution auxiliary graphics insertion device, comprising:

[0028] A rule optimization module, used to obtain an optimal insertion rule by using the above-mentioned optimization method of sub-resolution auxiliary graphics insertion rule;

[0029] The sub-resolution auxiliary pattern adding module is used to insert the sub-resolution auxiliary pattern into the lithography pattern according to the optimal insertion rule.

[0030] A fourth object of the present invention is to provide a computer-readable storage medium having a computer program stored thereon, which implements the above method when the program is executed by a processor.

[0031] A fifth object of the present invention is to provide an electronic device, comprising a processor and a storage medium, wherein the storage medium stores a computer program, and the processor implements the above method when executing the computer program.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention proposes a sub-resolution auxiliary graphic insertion rule optimization method and its insertion method. The method inserts a ring-shaped sub-resolution auxiliary graphic by converting the main graphic into a level set representation, and introduces a graphic conflict processing method and a chamfering operation, so that the insertion position of the sub-resolution auxiliary graphic is more reasonable. The method has the advantages of simple parameters, high mask manufacturability and outstanding mask optimization effect, and can be widely used in the field of next-generation integrated circuit manufacturing.

[0034] The present invention can improve the mask optimization effect, enhance the lithography process window to reduce imaging errors, optimize the sub-resolution auxiliary pattern distribution, and ensure that the final design complies with manufacturing rules, thereby improving the accuracy and yield of chip manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a flow chart of a method for inserting a sub-resolution auxiliary graphic in an example of the present invention.

[0036] Figure 2 It is a schematic diagram of a flow chart of generating sub-resolution auxiliary graphics under a specific insertion rule in an example of the present invention.

[0037] Figure 3 It is a schematic diagram of inserting a multi-circle sub-resolution auxiliary graphic according to SDF in an example of the present invention.

[0038] Figure 4 It is a schematic diagram of chamfering a sub-resolution auxiliary graphic in an example of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0040] Figure 1It is a flow chart of a method for inserting a sub-resolution auxiliary graphic in an example of the present invention.

[0041] Please refer to Figure 1 The insertion process of the sub-resolution auxiliary graphics includes:

[0042] Step S1: mask production and photolithography model calibration.

[0043] First, according to the integrated circuit layout design rules and lithography process parameters, a set of lithography patterns for testing and evaluation is designed. Taking the via layer of the 55-nanometer technology node as an example, these patterns contain key features such as isolated vias and dense vias of different sizes to ensure the accuracy and representativeness of the test results. Subsequently, the designed lithography patterns are made into masks for subsequent exposure experiments.

[0044] After the mask was made, the mask was used to perform exposure experiments on silicon wafers, and the post-exposure measurement data was collected. These data included the measurement values ​​of different key features. The lithography model was then calibrated using these data to ensure that the model can accurately reflect the various effects of the lithography process, laying the foundation for the subsequent evaluation of the mask optimization effect.

[0045] Step S2: design multiple sets of sub-resolution auxiliary pattern insertion rules to respectively perform optical proximity effect correction and mask optimization effect evaluation.

[0046] Next, based on the experience of engineers and the requirements of the lithography process, we designed several different sets of sub-resolution auxiliary pattern insertion rules and optimized the sub-resolution auxiliary pattern insertion rules. Figure 2 As shown, the following steps are included:

[0047] S21, setting sub-resolution auxiliary graphics parameters, including the distance d between the sub-resolution auxiliary graphics and the main graphics 1 , the distance between sub-resolution auxiliary graphics d 2 and the width w of the sub-resolution auxiliary graphic; each set of rules includes the distance d between the sub-resolution auxiliary graphic and the main graphic 1 , the distance between sub-resolution auxiliary graphics d 2 And parameters such as the width w of the sub-resolution auxiliary graphics.

[0048] Taking an isolated square through hole with a side length of 110 nm as an example, the distance d between the sub-resolution auxiliary pattern and the main pattern is set 1 The distance between the sub-resolution auxiliary patterns is 110nm. 2 The width w of the sub-resolution auxiliary pattern is 110nm, and the width w of the sub-resolution auxiliary pattern is 34nm. The effect of this set of insertion rules on the improvement of mask optimization effect is studied.

[0049] S22. Select a distance metric function according to the main pattern, and use the signed distance function (SDF) to represent the distance between each point in the lithography pattern and the boundary of the main pattern, and convert the main pattern into a level set representation.

[0050] The distance metric function adopts the Chebyshev distance, Manhattan distance or Euclidean distance. In this embodiment, the Chebyshev distance is selected as the distance metric function. The signed distance function (SDF) is used to represent the distance between each point and the boundary. A negative distance indicates inside the main pattern, and a positive distance indicates outside the main pattern. This representation method can conveniently control the insertion position and width of the sub-resolution assist features.

[0051] S23. Insert multiple rings of sub-resolution assist features around the main pattern according to the set sub-resolution assist feature parameters, as Figure 3 shown;

[0052] The first ring of sub-resolution assist features: the region satisfying the condition "110nm < SDF < 144nm".

[0053] The second ring of sub-resolution assist features: the region satisfying the condition "254nm < SDF < 288nm".

[0054] The third ring of sub-resolution assist features: the region satisfying the condition "398nm < SDF < 432nm".

[0055] In this way, multiple rings of annular sub-resolution assist features can be inserted around the main pattern.

[0056] Step S24: Clean up the conflicts of multiple rings of sub-resolution assist features;

[0057] After the insertion of the sub-resolution assist features is completed, it is also necessary to consider the conflict issues between the sub-resolution assist features and the minimum feature pitch, minimum feature width, and the width w of the sub-resolution assist features. For this reason, a graphic conflict handling mechanism is proposed. This mechanism detects and processes potential conflicts to ensure that the processed sub-resolution assist features meet the design rules, guarantee the manufacturability of the mask, and reduce the risk of the sub-resolution assist features imaging on the silicon wafer.

[0058] For the conflict that the pitch between the sub-resolution assist features violates the minimum feature pitch, if the number of rings they are in is different, keep the inner ring of sub-resolution assist features; if the number of rings is the same, randomly keep one of them. For the conflict that the width of the sub-resolution assist features violates the minimum feature width, expand the width of the sub-resolution assist features outward to meet the minimum feature width. For the conflict that the width of the sub-resolution assist features is greater than the preset parameter w, shrink the width of the sub-resolution assist features inward to w.

[0059] Step S25: performing a chamfering operation on the conflict-cleared sub-resolution auxiliary graphics to complete the optimization of the sub-resolution auxiliary graphics.

[0060] In order to reduce the probability of sub-resolution auxiliary graphics being imaged on the silicon wafer and further improve the mask optimization effect, the sub-resolution auxiliary graphics are chamfered. The chamfer distance is based on a certain ratio of the side length of the sub-resolution auxiliary graphics. Figure 4 As shown in the figure, for a square sub-resolution auxiliary pattern, chamfering is performed at 29% and 71% of the side length, and the outline of the chamfered sub-resolution auxiliary pattern is close to a regular octagon. This operation makes the outline of the sub-resolution auxiliary pattern closer to a circle and the distance from the edge of the main pattern more uniform, thereby improving the light intensity contrast at the edge of the mask. At the same time, increasing the corner of the sub-resolution auxiliary pattern also helps reduce the risk of imaging on the silicon wafer.

[0061] Step S26: Optical proximity effect correction and mask optimization effect evaluation.

[0062] For each set of sub-resolution auxiliary pattern insertion rules, the design layout is corrected for optical proximity effects using the corrected lithography model. The corrected layout fully considers various effects in the lithography process, thereby obtaining a silicon wafer pattern that is closer to the expected design.

[0063] Then, the mask correction evaluation index was used to evaluate the mask optimization effect of different sub-resolution auxiliary pattern insertion rules. The main reference is the process variation band (PVB). In the lithography process, the process variation bandwidth refers to the range of pattern size changes caused by various factors. The smaller the PVB, the larger the window of the lithography process.

[0064] According to the above method, the set sub-resolution auxiliary pattern parameters are changed, and sub-resolution auxiliary patterns under different rules are inserted into the lithography pattern. In order to ensure the balance between optimization accuracy and optimization effect, a uniform step size is set within a reasonable range. Each insertion rule corresponds to a split. In this experiment, d 1 The values ​​of include [90, 100, 110, 120, 130], d 2 The values ​​of include [90, 100, 110, 120, 130], the values ​​of w include [26, 30, 34, 38, 42, 46], each insertion rule corresponds to a sub-resolution auxiliary graphic split, the above parameters correspond to a total of 5*5*6=150 sub-resolution auxiliary graphic splits, and the best insertion rule needs to be found among them.

[0065] During the design process, electronic design automation (EDA) software was used to quickly insert sub-resolution auxiliary graphics and conduct subsequent evaluation, thereby shortening the photolithography process development cycle. Specifically, the design layout was imported into the EDA software, and sub-resolution auxiliary graphics were automatically inserted around the main graphics according to the set parameters, and subsequent evaluation was performed.

[0066] Step S3: Determine the optimal sub-resolution auxiliary graphics insertion rule.

[0067] After evaluating the mask optimization effects of different sub-resolution auxiliary graphics insertion rules, the insertion rule with the greatest improvement in mask optimization effect was selected as the sub-resolution auxiliary graphics insertion rule finally used by the production line. In order to find the best rule, the grid search method was used for parameter tuning. The final PVB of 150 sub-resolution auxiliary graphics splits was calculated using the lithography model, and the insertion rule corresponding to the split with the smallest PVB was selected as the sub-resolution auxiliary graphics insertion rule finally used by the production line.

[0068] The above description is merely a preferred embodiment of one or more embodiments of the present specification and is not intended to limit one or more embodiments of the present specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present specification shall be included in the scope of protection of one or more embodiments of the present specification.

Claims

1. A method for optimizing sub-resolution auxiliary graphics insertion rules, characterized in that: It includes the following steps: S1. Set the sub-resolution assist feature parameters, including the distance d1 between the sub-resolution assist feature and the main feature, the distance d2 between the sub-resolution assist features, and the width w of the sub-resolution assist feature; S2. Select a distance metric function according to the main feature, and use the signed distance function SDF to represent the distance between each point in the design layout and the boundary of the main feature, and convert the main feature into a level set representation; S3. Insert multiple circles of sub-resolution assist features around the main feature according to the set sub-resolution assist feature parameters; S4. Clean up the conflicts of the multiple circles of sub-resolution assist features; S5. Chamfer the multiple circles of sub-resolution assist features after conflict cleaning to complete the optimization of the insertion rules for the sub-resolution assist features; Perform optical proximity effect correction on the design layout and evaluate the mask optimization effect; S6. Change the sub-resolution assist feature parameters, repeat steps S2 to S5, and if the mask optimization effect is better than the previous insertion rules, update the insertion rules until the optimal insertion rules are obtained.

2. The method for optimizing sub-resolution auxiliary graphics insertion rules according to claim 1, characterized in that: The distance metric function described in step S2 uses the Chebyshev distance, Manhattan distance or Euclidean distance.

3. The method for optimizing sub-resolution auxiliary graphics insertion rules according to claim 1, characterized in that: Step S3 is specifically as follows: The area that satisfies the condition "d1 < SDF < d1 + w" is used as the first circle of sub-resolution assist features; The area that satisfies the condition "d1 + d2 + w < SDF < d1 + d2 + 2w" is used as the second circle of sub-resolution assist features; The area that satisfies the condition "d1 + 2d2 + 2w < SDF < d1 + 2d2 + 3w" is used as the third circle of sub-resolution assist features.

4. The method for optimizing sub-resolution auxiliary graphics insertion rules according to claim 1, characterized in that: Step S4 specifically includes: (1) Detect the spacing conflict between the sub-resolution assist features: If the spacing between adjacent sub-resolution assist features is less than the minimum feature spacing, it is determined that there is a conflict, otherwise there is no conflict; if the conflicting sub-resolution assist features are in different layers, retain the inner-layer sub-resolution assist features close to the main feature and delete the conflicting features in the outer layer; If the conflicting sub-resolution assist features are in the same layer, randomly delete one of them to eliminate the conflict; (2) Detect the width conflict of the sub-resolution assist features: If the width of the sub-resolution assist feature is less than the minimum feature width, it is determined that there is a conflict, and the width of the sub-resolution assist feature is extended outward to meet the minimum feature width requirement; otherwise there is no conflict; If the width of the sub-resolution assist feature is greater than the preset width parameter w, it is determined that there is a conflict, and the width of the sub-resolution assist feature is shrunk inward to w; otherwise there is no conflict.

5. The method for optimizing sub-resolution auxiliary graphics insertion rules according to claim 1, characterized in that: The evaluation indexes of the mask optimization effect in step S5 include process variation bandwidth, pattern fidelity, pattern edge light intensity contrast and the number of lithography defects.

6. A method for inserting a sub-resolution auxiliary graphic, characterized in that: It includes the following steps: S1. Design lithography patterns and their corresponding masks for testing and evaluation, fabricate the lithography patterns into photomasks, and collect measurement data to calibrate the lithography model; S2. Using the optimization method of the sub-resolution auxiliary pattern insertion rule according to any one of claims 1 to 5, changing the set sub-resolution auxiliary pattern parameters, inserting different sub-resolution auxiliary patterns into the lithography pattern, and performing optical proximity effect correction respectively, and evaluating the mask optimization effect; S3. Select the insertion rule that has the greatest improvement in mask optimization effect as the final sub-resolution auxiliary graphic insertion rule, and insert the sub-resolution auxiliary graphic.

7. A sub-resolution auxiliary graphics insertion device, characterized in that: include: A rule optimization module, used to obtain an optimal insertion rule by using the optimization method of the sub-resolution auxiliary graphics insertion rule according to any one of claims 1 to 5; The sub-resolution auxiliary pattern adding module is used to insert the sub-resolution auxiliary pattern into the lithography pattern according to the optimal insertion rule.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method described in any one of claims 1 to 5 or the method described in any one of claim 6 is implemented.

9. An electronic device comprising a processor and a storage medium, characterized in that: The storage medium stores a computer program, and when the processor executes the computer program, the method described in any one of claims 1 to 5 or the method described in any one of claim 6 is implemented.

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