Abnormity processing method and device for embedded system, equipment and storage medium

Abstract

The invention discloses an exception handling method and device for an embedded system, equipment and a storage medium, and relates to the technical field of embedding. The method comprises the steps of determining a current operation mode of a target processor according to a program state register of the target processor under the condition that abnormal codes appear in the operation process of the target processor in a target embedded system; according to the program state register, switching the current operation mode into a target operation mode, and obtaining a stack pointer value of a stack pointer register of the target processor in the target operation mode; and determining a target function address of a target function to which the abnormal code belongs and a call chain of the target function according to the stack pointer value. According to the technical scheme, the target function address is determined according to the stack pointer register, and before the target function address is determined, the target processor is switched to the target operation module and the interrupt is closed, so that interruption in the exception handling process can be effectively avoided, and the exception handling reliability can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, in particular to the field of embedded technology, and specifically to an exception handling method, apparatus, device and storage medium for an embedded system. Background Art

[0002] With the rapid development of embedded operating systems, solving the abnormal problems that are prone to occur during operating system operation and debugging has also become a topic of great concern to R&D engineers. Exceptions are some situations that occur when the processor executes program instructions, causing the program to fail to execute normally, and there are many types of exceptions.

[0003] Under the ARM (Advanced RISC Machine) architecture, exceptions include abort exceptions, prefetch instruction exceptions, undefined instruction exceptions, etc. The exception management function allows engineers to quickly classify and locate exceptions based on exception information. However, currently only some operating systems have exception management functions. For operating systems without exception management functions, you need to implement exception handling yourself so that you can quickly locate the corresponding problems when the program has problems.

[0004] The current stack backtracking methods all rely on the frame pointer (FP) register to find the address of the called function, but the register corresponding to FP is uncertain for different compilers, and some compilers do not even store FP. Therefore, the existing stack backtracking methods need to be modified specifically, otherwise they cannot be used. Summary of the invention

[0005] The present application provides an exception handling method, apparatus, device and storage medium for an embedded system to improve the reliability of exception handling.

[0006] According to one aspect of the present application, a method for handling exceptions in an embedded system is provided, the method comprising:

[0007] In the case of identifying that an abnormal code occurs in the target processor of the target embedded system during operation, determining the current operation mode of the target processor according to the program status register of the target processor;

[0008] According to the program status protection register of the target processor and the program status register, the current operation mode is switched to a target operation mode, and a stack pointer value of a stack pointer register of the target processor in the target operation mode is obtained;

[0009] According to the stack pointer value, the target function address of the target function to which the exception code belongs and the call chain of the target function are determined.

[0010] According to another aspect of the present application, an exception handling device for an embedded system is provided, the device comprising:

[0011] A mode determination module, for determining the current operation mode of the target processor according to the program status register of the target processor when an abnormal code appears in the operation of the target processor in the target embedded system;

[0012] A mode switching module, used to switch the current operation mode to a target operation mode according to the program status protection register of the target processor and the program status register, and obtain a stack pointer value of the stack pointer register of the target processor in the target operation mode;

[0013] The address determination module is used to determine the target function address and the call chain of the target function to which the exception code belongs according to the stack pointer value.

[0014] According to another aspect of the present application, an electronic device is provided, the electronic device comprising:

[0015] one or more processors;

[0016] A memory for storing one or more programs;

[0017] When the one or more programs are executed by the one or more processors, the one or more processors implement any one of the exception handling methods for embedded systems provided in the embodiments of the present application.

[0018] According to another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, any exception handling method for an embedded system provided in the embodiments of the present application is implemented.

[0019] According to another aspect of the present application, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the computer program implements any one of the exception handling methods for embedded systems provided in the embodiments of the present application.

[0020] The present application determines the current operation mode of the target processor according to the program status register of the target processor when identifying the abnormal code in the target processor of the target embedded system during operation; switches the current operation mode to the target operation mode according to the program status protection register and the program status register of the target processor, and obtains the stack pointer value of the stack pointer register of the target processor in the target operation mode; determines the target function address and the target function call chain of the target function to which the abnormal code belongs according to the stack pointer value. The above technical solution does not need to consider the stack base address of the function, determines the target function address according to the stack pointer register, and switches the operation mode of the target processor to the target operation mode and turns off the interrupt before determining the target function address, which can effectively avoid being interrupted in the process of handling exceptions and help improve the reliability of exception handling. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1a is a flowchart of an exception handling method for an embedded system provided according to Embodiment 1 of the present application;

[0022] Figure 1b It is a register architecture diagram of an ARM processor in various modes provided in an embodiment of the present application;

[0023] Figure 2a is a flowchart of an exception handling method for an embedded system provided according to Embodiment 2 of the present application;

[0024] Figure 2b is a flowchart of an exception handling method for an embedded system provided according to an embodiment of the present application;

[0025] Figure 3 It is a structural schematic diagram of an exception handling device for an embedded system provided according to Embodiment 3 of the present application;

[0026] Figure 4 It is a structural schematic diagram of an electronic device that implements the exception handling method of the embedded system of an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] In addition, it should be noted that the collection, storage, use, processing, transmission, provision and disclosure of relevant data such as the current operating mode and target operating mode involved in the technical solution of this application are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0030] Embodiment 1

[0031] Figure 1a This is a flowchart of an exception handling method for an embedded system provided according to the first embodiment of the present application. This embodiment is applicable to the case of exception handling of an ARM processor in an embedded system, and can be executed by an exception handling device of the embedded system. The exception handling device of the embedded system can be implemented in the form of hardware and / or software. The exception handling device of the embedded system can be configured in a computer device, such as a server. Figure 1a As shown, the method includes:

[0032] S110: When it is identified that an abnormal code occurs in the target processor of the target embedded system during operation, determine the current operation mode of the target processor according to the program status register of the target processor.

[0033] In this embodiment, the target embedded system refers to the hardware system on which the embedded application runs. The target processor refers to the central processing unit in the embedded system, which is responsible for executing program instructions and processing data; each processor has a different architecture and instruction set; the target processor of this application specifically refers to the ARM processor. The exception code refers to an identifier or error code generated by the processor or operating system when some special circumstances (such as errors, unexpected events, hardware failures, etc.) occur during the execution of the program; this code indicates a specific exception type or error cause. The Current Program Status Register (CPSR) is an important register in the ARM processor architecture, which is used to save multiple flag bits and control information related to the current program execution status, including the current execution mode (for example, user mode, privileged mode), interrupt enable flag, conditional code flag, etc.; CPSR can provide the current state of the processor and help the processor manage various control, exception, interrupt, conditional judgment and other functions during the execution of the program. The current operating mode refers to the current working state of the processor; the operating mode can be divided into different levels, such as user mode and privileged mode; in different modes, the program permissions and accessible resources are different; exceptions or interrupts usually cause a switch from user mode or system mode to the corresponding exception mode in order to access hardware or operating system resources.

[0034] It should be noted that ARM, as the most widely used architecture in the embedded field, usually has 7 operating modes, including user mode, system mode, privileged mode, abort mode, undefined instruction mode, external interrupt mode and fast interrupt mode.

[0035] In an alternative embodiment, if Figure 1b As shown, R0-R3 refer to parameter registers; R3-R11 refer to general registers; R12 refers to intra-procedure-call scratch Register (IP); R13 refers to stack pointer register (SP); R14 refers to link register (LR); R15 refers to program counter (PC); accordingly, before determining the current operation mode of the target processor according to the program status register of the target processor, it is found according to the assembly code that registers R4 and R5 will be modified in subsequent operations, so the values ​​of R4 and R5 are pushed onto the stack first; the values ​​of R0-R3 registers are saved to the specified area in the memory; R4 and R5 are popped from the stack, and the values ​​of R4-R15 are saved to the specified area in the memory.

[0036] In this embodiment, parameter registers refer to the main registers for passing function parameters and return values; in the ARM function calling convention, the caller passes up to 4 parameters through these registers; if the return value is small, it is usually stored in R0. General registers refer to registers used to store data or local variables of functions; they are usually modified during the function call process, so if the function needs to save the values ​​of these registers, they are usually saved and restored on the stack. In-procedure call temporary registers are usually used to store temporary data or pass information during the function call process, and usually do not need to retain their values ​​because they may be overwritten during the function call. The stack pointer register is used to indicate the current top position of the stack; the stack is usually used to store local variables, return addresses and other information during function calls; when an exception or interrupt occurs, the value of the stack pointer helps to save the current program context and ensure that the system can return to normal after handling the exception. The link register is used to store the return address of the function call; when a function is called, the return address (that is, the address after the function call instruction) will be saved in LR; when the function is executed and returns, the control flow will jump to the address saved in LR. The program counter is used to point to the address of the next instruction to be executed; each time an instruction is executed, the program counter is automatically incremented to point to the next instruction; for branch (jump) instructions, the value of the PC is modified according to the jump target.

[0037] S120. According to the program status protection register and the program status register of the target processor, the current operation mode is switched to the target operation mode, and the stack pointer value of the stack pointer register of the target processor in the target operation mode is obtained.

[0038] In this embodiment, the Saved Program Status Register (SPSR) is used to save the state of the CPSR so that the working state when the exception occurs can be restored after the exception returns. The target operating mode refers to the operating mode that the system needs to switch to during a specific operation or exception handling process; for example, when processing an interrupt or exception, the processor needs to switch to the exception handling mode in order to perform related error handling or recovery operations; in this application, the target operating mode specifically refers to the user mode, system mode, and general interrupt mode; it should be noted that the target operating mode refers to the mode represented by the program status protection register. The stack pointer value refers to the specific value stored in the stack pointer register, which indicates the top address of the current stack; the stack pointer value is the key to determining the allocation and recovery of stack space, and it is particularly important in function calls or exception handling.

[0039] Optionally, according to the program status saving register and program status register of the target processor, switching the current operating mode to the target operating mode can be performed by saving the current status data of the program status register to a general register; according to the program status saving register of the target processor, modifying the low bit of the program status register to switch the current operating mode to the target operating mode and disabling interrupts.

[0040] Exemplarily, the current CPSR is saved in R8, and then the lower 8 bits of the CPSR register are modified to switch the current state to the target operation mode and disable interrupts to prevent repeated entry.

[0041] It is understandable that the processor is often in user mode (system mode) during normal operation. When an exception or interrupt occurs, the corresponding mode will be entered. Different modes use different registers. In order to be able to trace back the function where the exception occurred, it is necessary to switch back to the normal operating mode. The current processor mode can be calculated through the CPSR register, and the stack space range of the corresponding mode can be obtained as a limit for stack backtracing. Modifying the CPSR register according to the SPSR register can switch the current mode. In order to avoid being interrupted during the handling of exceptions, interrupts need to be turned off.

[0042] S130. Determine the target function address and target function call chain of the target function to which the exception code belongs according to the stack pointer value.

[0043] In this embodiment, the target function refers to the function being executed in a specific execution environment or context; when handling an exception, it is necessary to locate the function address that caused the exception based on the stack pointer value for further debugging or error handling. The target function address refers to the memory address stored in the stack that points to the target function; through the stack pointer value, the specific function executed when the exception occurs and the call chain of the function can be found to help programmers diagnose problems or perform error recovery. The target function call chain refers to a function in the program calling another function, and the called function may call other functions to form a chain of function calls; this chain starts from the initial function call, passes through multiple levels of function calls, until it is finally executed and returned.

[0044] Optionally, the target function address of the target function to which the exception code belongs is determined based on the stack pointer value; and the target function call chain is determined based on the stack pointer value and the target function address.

[0045] The embodiment of the present application determines the current operation mode of the target processor according to the program status register of the target processor when identifying the occurrence of abnormal code during the operation of the target processor in the target embedded system; switches the current operation mode to the target operation mode according to the program status protection register and the program status register of the target processor, and obtains the stack pointer value of the stack pointer register of the target processor in the target operation mode; determines the target function address and the target function call chain of the target function to which the abnormal code belongs according to the stack pointer value. The above technical scheme does not need to consider the stack base address of the function, determines the target function address according to the stack pointer register, and switches the operation mode of the target processor to the target operation mode before determining the target function address, which can effectively avoid interruption in the process of handling exceptions and help improve the reliability of exception handling.

[0046] Embodiment 2

[0047] Figure 2a This is a flowchart of an exception handling method for an embedded system provided in accordance with the second embodiment of the present application. Based on the technical solutions of the above embodiments, this embodiment refines "determining the target function address of the target function to which the exception code belongs according to the stack pointer value" into "judging whether the stack pointer value satisfies the out-of-bounds condition, and when the stack pointer value does not satisfy the out-of-bounds condition, performing a first exception check on the stack pointer value according to the link file of the target embedded system; when the stack pointer value passes the first exception check, determining the candidate instruction address and candidate call address of the target function to which the exception code belongs according to the stack pointer value; determining the target function address of the target function according to the candidate call address and the candidate instruction address". It should be noted that for the parts not described in detail in the embodiments of the present application, please refer to the relevant statements of other embodiments. Figure 2a As shown, the method includes:

[0048] S210: When it is identified that an abnormal code occurs in the target processor of the target embedded system during operation, determine the current operation mode of the target processor according to the program status register of the target processor.

[0049] S220. Switch the current operation mode to the target operation mode according to the program status protection register and the program status register of the target processor, and obtain the stack pointer value of the stack pointer register of the target processor in the target operation mode.

[0050] Exemplarily, which of the seven operating modes the ARM processor is currently in is determined according to the CPSR register, and the stack bottom address of the corresponding mode is determined according to the link code, and the value of the SP register in the user mode is obtained.

[0051] S230, determining whether the stack pointer value satisfies an out-of-bounds condition, and if the stack pointer value does not satisfy the out-of-bounds condition, performing a first exception check on the stack pointer value according to the link file of the target embedded system.

[0052] In this embodiment, the out-of-bounds condition is pre-set; for example, the stack pointer value is less than the stack bottom address; the out-of-bounds condition is set to prevent the stack pointer from exceeding the range of the allocated stack space; stack out-of-bounds may cause the stack memory to overwrite other data (such as global variables, heap, etc.), thereby causing program errors or crashes. Link file refers to the file that describes the program memory layout and symbol mapping in the embedded system; it specifies the specific location and size of each segment of the program (such as code segment, data segment, stack segment, etc.) in the memory. The first exception check is to check whether the stack pointer value is within the code segment range of the abnormal code segment, so as to preliminarily screen whether the current round stack pointer value points to the abnormal code.

[0053] Exemplarily, it is determined whether the value of SP is less than the stack bottom address; if the value of SP is less than the stack bottom address, it is determined whether *SP is within the code segment range according to the connection file of the target embedded system.

[0054] In an optional implementation, when the stack pointer value meets the out-of-bounds condition, the exception handling of the target embedded system is terminated.

[0055] Exemplarily, if the value of SP is greater than or equal to the stack bottom address, the program ends.

[0056] S240. When the stack pointer value passes the first exception check, determine the candidate instruction address and candidate call address of the target function to which the exception code belongs according to the stack pointer value.

[0057] In this embodiment, the candidate instruction address refers to the address in the link register. In the ARM architecture, LR is used to store the address returned by a function call. Whenever a function is called, the link register stores the address of the next instruction, that is, the address after the call instruction. The candidate call address refers to the address of the call instruction, that is, the entry address of the program when calling a function. In this embodiment, the candidate call address specifically refers to the value of the CALL instruction.

[0058] Optionally, determining the candidate instruction address and candidate calling address of the target function to which the exception code belongs according to the stack pointer value may be: determining the candidate instruction address according to the stack pointer value; and determining the candidate calling address according to the candidate instruction address.

[0059] Exemplarily, the determination of the candidate instruction address may be implemented by the following formula:

[0060] LR = *SP;

[0061] Among them, LR refers to the candidate instruction address and SP refers to the stack pointer value.

[0062] Exemplarily, the determination of the candidate call address can be achieved by the following formula:

[0063] CALL = *(LR-4);

[0064] Among them, CALL refers to the candidate call address. LR refers to the candidate instruction address. LR-4 refers to the instruction address before the function call, that is, where the function is called.

[0065] In an optional implementation, when the stack pointer value passes the first exception check, the stack pointer value is modified, and it is re-determined whether the modified stack pointer value meets the out-of-bounds condition.

[0066] S250. Determine the target function address and the target function call chain of the target function according to the candidate call address and the candidate instruction address.

[0067] Optionally, a secondary exception check is performed on the candidate call address, and if the secondary exception check passes, the flag value of the candidate flag bit in the candidate call address is determined; the candidate flag bit is the sign bit of the candidate call address operand; according to the flag bit value, the target call address of the target function is determined; the operand of the target call address, the candidate instruction address, and a preset constant are added to obtain the target function address of the target function.

[0068] In this embodiment, the secondary exception check refers to the check of whether the upper eight bits of the candidate call address are the function call opcode in the ARM instruction set. The candidate flag bit is a flag bit in the candidate call address that is predetermined based on actual conditions or empirical values; illustratively, the candidate flag bit can be the 24th flag bit of the candidate call address. The flag bit value refers to the current value on the candidate flag bit in the candidate call address. The operand refers to the operand of the function call instruction (Call Instruction, CALL), which is used to indicate the offset of the function jump target; for instructions of the ARM architecture, it is usually an offset relative to the current instruction address.

[0069] Exemplarily, the target function address can be determined by the following formula:

[0070] func_addr=LR+4+delta_addr;

[0071] Among them, func_addr refers to the target function address. LR refers to the candidate instruction address. 4 refers to the preset constant. delta_addr refers to the operand of the candidate call address.

[0072] Furthermore, according to the flag value, the target calling address of the target function can be determined by, if the flag value satisfies the flag filling condition, performing high-bit filling and left-shifting operations on the candidate calling address to obtain the target calling address of the target function; if the flag value does not satisfy the flag filling condition, performing left-shifting operations on the candidate calling address to obtain the target calling address of the target function.

[0073] In this embodiment, the flag bit filling condition is preset; the flag bit filling condition may be whether the flag bit value is a preset value; illustratively, the preset value may be 1.

[0074] Exemplarily, it is determined whether the 24th bit of CALL is 1; if it is 1, the upper 8 bits of CALL are set to 0xFF, and CALL is shifted left by two bits; if it is not 1, CALL is shifted left by two bits.

[0075] It can be understood that in the stack backtracing process, LR is generally found through the stack bottom address (FP) of the function. Since the method of the present application does not use FP, LR is found by traversing the stack space pointed to by SP; according to the function calling rule, the previous instruction of LR must be a function call instruction, and its opcode is 0xEB (the opcode in the ARM instruction set, representing the BL instruction, which is often used for function call operations), representing the BL (Branch with Link) instruction; therefore, it is possible to determine whether the current instruction is LR by judging the opcode.

[0076] In an optional implementation, after obtaining the target function address of the target function, the stack pointer value may be modified, and whether the modified stack pointer value satisfies the out-of-bounds condition may be re-determined.

[0077] For example, Figure 2b As shown, the technical solution of the present application can be implemented by the following steps:

[0078] (1) Since registers R4 and R5 will be modified in subsequent operations, the values ​​of R4 and R5 are pushed onto the stack first;

[0079] (2) Save the values ​​of registers R1-R3 to the specified area in the memory;

[0080] (3) Pop R4 and R5 from the register stack and save the values ​​of R4-R15 to the specified area in the memory;

[0081] (4). Determine which of the seven modes is currently in accordance with the CPSR register, and determine the stack bottom address STACK_BOTTOM of the corresponding mode according to the link code;

[0082] (5) Save the current CPSR to R8, then modify the lower 8 bits of the CPSR register, switch the current state to the mode represented by the SPSR register and disable interrupts to prevent repeated entry;

[0083] (6). Get the value of SP register in non-exception mode;

[0084] (7) Determine whether the value of SP is less than STACK_BOTTOM (the bottom address of the stack, used to limit the upper limit of the stack backtrace). If SP is less than STACK_BOTTOM, execute (8), otherwise the entire program ends;

[0085] (8). Determine whether *SP is within the code segment range according to the link file of the operating system. If so, proceed to the next step; otherwise, proceed to step (15);

[0086] (9) Assuming LR = *SP, then CALL = *(LR-4);

[0087] (10). Determine whether the high 8 bits of CALL are 0xEB. If so, it indicates that step (9) is correct, and proceed to the next step. Otherwise, it indicates that step (9) is wrong, and proceed to step (15); where 0xEB is the opcode of the CALL instruction;

[0088] (11). Set delta_addr = CALL & 0x00FFFFFF, and determine whether the 24th bit of delta_addr, i.e. the sign bit, is 1. If it is 1, execute step (12). Otherwise, execute step (13);

[0089] (12). Let delta_addr=delta_addr||0xFF000000;

[0090] (13). Shift delta_addr left by two bits delta_addr = delta_addr << 2;

[0091] (14). Calculate the function address func_addr = LR + 4 + delta_addr;

[0092] (15).sp=sp+4, execute step (7).

[0093] The embodiment of the present application determines the current operation mode of the target processor according to the program status register of the target processor when the target processor in the target embedded system is identified to have an abnormal code during operation; switches the current operation mode to the target operation mode according to the program status protection register and the program status register of the target processor, and obtains the stack pointer value of the stack pointer register of the target processor in the target operation mode; determines whether the stack pointer value meets the out-of-bounds condition, and performs the first abnormal check on the stack pointer value according to the link file of the target embedded system when the stack pointer value does not meet the out-of-bounds condition; determines the candidate instruction address and candidate call address of the target function to which the abnormal code belongs according to the stack pointer value when the stack pointer value passes the first abnormal check; determines the target function address and the target function call chain of the target function according to the candidate call address and the candidate instruction address. The above technical scheme does not need to consider the stack base address of the function, and determines the target function address according to the stack pointer register, which helps to improve the reliability and applicability of exception handling.

[0094] Embodiment 3

[0095] Figure 3 This is a schematic diagram of the structure of an exception handling device for an embedded system provided in Embodiment 3 of the present application, which can be applied to the case of exception handling of an ARM processor in an embedded system. The exception handling device for the embedded system can be implemented in the form of hardware and / or software, and the exception handling device for the embedded system can be configured in a computer device, such as a server. Figure 3 As shown, the device comprises:

[0096] The mode determination module 310 is used to determine the current operation mode of the target processor according to the program status register of the target processor when it is identified that an abnormal code occurs during the operation of the target processor in the target embedded system;

[0097] A mode switching module 320, for switching the current operation mode to the target operation mode according to the program status protection register and the program status register of the target processor, and obtaining the stack pointer value of the stack pointer register of the target processor in the target operation mode;

[0098] The address determination module 330 is used to determine the target function address and the target function call chain of the target function to which the exception code belongs according to the stack pointer value.

[0099] The embodiment of the present application determines the current operation mode of the target processor according to the program status register of the target processor when identifying the abnormal code in the target embedded system during the operation; switches the current operation mode to the target operation mode according to the program status protection register and the program status register of the target processor, and obtains the stack pointer value of the stack pointer register of the target processor in the target operation mode; determines the target function address of the target function to which the abnormal code belongs according to the stack pointer value. The above technical scheme does not need to consider the stack base address of the function, determines the target function address and the target function call chain according to the stack pointer register, and switches the operation mode of the target processor to the target operation module and turns off the interrupt before determining the target function address, which can effectively avoid being interrupted in the process of handling exceptions and help improve the reliability of exception handling.

[0100] Optionally, the address determination module 330 includes:

[0101] An exception check unit is used to determine whether the stack pointer value meets the out-of-bounds condition, and if the stack pointer value does not meet the out-of-bounds condition, perform a first exception check on the stack pointer value according to the link file of the target embedded system;

[0102] A first address determination unit is used to determine, when the stack pointer value passes the first exception check, a candidate instruction address and a candidate call address of the target function to which the exception code belongs according to the stack pointer value; wherein the candidate instruction address refers to an address in a link register in the target processor;

[0103] The second address determination unit is used to determine the target function address and the target function call chain of the target function according to the candidate call address and the candidate instruction address.

[0104] Optionally, the second address determining unit includes:

[0105] An exception check subunit is used to perform a secondary exception check on the candidate call address, and if the secondary exception check passes, determine the flag bit value of the candidate flag bit in the candidate call address; the candidate flag bit is the sign bit of the candidate call address operand;

[0106] A call address determination subunit, used to determine a target call address of a target function according to a flag bit value;

[0107] The function address determination subunit is used to perform addition operation on the operand of the target call address, the candidate instruction address, and the preset constant to obtain the target function address and the target function call chain of the target function.

[0108] Optionally, call the address determination subunit, specifically for:

[0109] If the flag value satisfies the flag filling condition, the candidate call address is filled with high bits and left-shifted to obtain the target call address of the target function;

[0110] If the flag value does not satisfy the flag filling condition, a left shift operation is performed on the candidate call address to obtain the target call address of the target function.

[0111] Optionally, the anomaly checking unit is also used to:

[0112] When the stack pointer value meets the out-of-bounds condition, the exception handling of the target embedded system is terminated;

[0113] When the stack pointer value passes the first exception check, the stack pointer value is modified, and it is re-determined whether the modified stack pointer value meets the out-of-bounds condition.

[0114] Optionally, the mode switching module 320 is specifically configured to:

[0115] Save the current status data of the program status register to the general register;

[0116] According to the program status protection register of the target processor, the low bit of the program status register is modified to switch the current operation mode to the target operation mode and disable interrupts; wherein the target operation mode includes user mode, system mode and general interrupt mode.

[0117] The exception handling device for an embedded system provided in the embodiment of the present application can execute the exception handling method for an embedded system provided in any embodiment of the present application, and has functional modules and beneficial effects corresponding to executing the exception handling method of each embedded system.

[0118] According to an embodiment of the present application, the present application also provides an electronic device, a readable storage medium and a computer program product.

[0119] Embodiment 4

[0120] Figure 4 It is a structural diagram of an electronic device 410 that implements the exception handling method of the embedded system of the embodiment of the present application. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only examples, and are not intended to limit the implementation of the present application described herein and / or required.

[0121] like Figure 4 As shown, the electronic device 410 includes at least one processor 411, and a memory connected to the at least one processor 411 in communication, such as a read-only memory (ROM) 412, a random access memory (RAM) 413, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 411 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 412 or the computer program loaded from the storage unit 418 to the random access memory (RAM) 413. In RAM413, various programs and data required for the operation of the electronic device 410 can also be stored. The processor 411, ROM412 and RAM413 are connected to each other via a bus 414. An input / output (I / O) interface 415 is also connected to the bus 414.

[0122] Multiple components in the electronic device 410 are connected to the I / O interface 415, including: an input unit 416, such as a keyboard, a mouse, etc.; an output unit 417, such as various types of displays, speakers, etc.; a storage unit 418, such as a disk, an optical disk, etc.; and a communication unit 419, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 419 allows the electronic device 410 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0123] The processor 411 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 411 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 411 executes the various methods and processes described above, such as an exception handling method for an embedded system.

[0124] In some embodiments, the exception handling method of the embedded system can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 418. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 410 via ROM412 and / or communication unit 419. When the computer program is loaded into RAM413 and executed by processor 411, one or more steps of the exception handling method of the embedded system described above can be performed. Alternatively, in other embodiments, processor 411 can be configured as an exception handling method for an embedded system by any other appropriate means (e.g., by means of firmware).

[0125] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0126] The computer program for implementing the method of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to the processor of the exception handling device of a general-purpose computer, a special-purpose computer or other programmable embedded system, so that the computer program, when executed by the processor, implements the functions / operations specified in the flow chart and / or block diagram. The computer program can be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0127] In the context of the present application, a computer readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device or equipment. A computer readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer readable storage medium may be a machine readable signal medium. A more specific example of a machine readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0128] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0129] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0130] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0131] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution of this application can be achieved, and this document is not limited here.

[0132] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. An exception handling method for an embedded system, characterized in that: include: In the case of identifying that an abnormal code occurs in a target processor of a target embedded system during operation, determining a current operation mode of the target processor according to a program status register of the target processor; According to the program status protection register of the target processor and the program status register, the current operation mode is switched to a target operation mode, and a stack pointer value of a stack pointer register of the target processor in the target operation mode is obtained; According to the stack pointer value, the target function address of the target function to which the exception code belongs and the call chain of the target function are determined.

2. The method according to claim 1, characterized in that Determining the target function address of the target function to which the exception code belongs according to the stack pointer value includes: Determine whether the stack pointer value satisfies an out-of-bounds condition, and if the stack pointer value does not satisfy the out-of-bounds condition, perform a first exception check on the stack pointer value according to a link file of the target embedded system; In the case where the stack pointer value passes the first exception check, determining a candidate instruction address and a candidate call address of the target function to which the exception code belongs according to the stack pointer value; wherein the candidate instruction address refers to an address in a link register in the target processor; A target function address of the target function is determined according to the candidate call address and the candidate instruction address.

3. The method according to claim 2, characterized in that The step of determining the target function address of the target function according to the candidate call address and the candidate instruction address comprises: Performing a secondary exception check on the candidate call address, and determining a flag bit value of a candidate flag bit in the candidate call address if the secondary exception check passes; the candidate flag bit is a sign bit of the candidate call address operand; Determining a target calling address of the target function according to the flag value; The operand of the target call address, the candidate instruction address, and a preset constant are added to obtain a target function address of the target function.

4. The method according to claim 3, characterized in that Determining the target call address of the target function according to the flag bit value includes: If the flag value satisfies the flag filling condition, high-bit filling and left-shifting operations are performed on the candidate call address to obtain the target call address of the target function; If the flag value does not satisfy the flag filling condition, a left shift operation is performed on the candidate calling address to obtain the target calling address of the target function.

5. The method according to claim 2, characterized in that: The method further comprises: When the stack pointer value satisfies the out-of-bounds condition, ending the exception handling of the target embedded system; In the case where the stack pointer value passes the first exception check, the stack pointer value is modified, and it is re-determined whether the modified stack pointer value satisfies the out-of-bounds condition.

6. The method according to claim 1, characterized in that According to the program status protection register of the target processor and the program status register, switching the current operation mode to the target operation mode includes: Saving the current status data of the program status register into a general register; According to the program status protection register of the target processor, the low bit of the program status register is modified to switch the current operation mode to the target operation mode and disable interrupts; wherein the target operation mode includes user mode, system mode, management mode and general interrupt mode.

7. An exception handling device for an embedded system, characterized in that: include: A mode determination module, for determining the current operation mode of the target processor according to the program status register of the target processor when an abnormal code appears during operation of the target processor in the target embedded system; A mode switching module, used to switch the current operation mode to a target operation mode according to the program status protection register of the target processor and the program status register, and obtain a stack pointer value of a stack pointer register of the target processor in the target operation mode; The address determination module is used to determine the target function address and the call chain of the target function to which the exception code belongs according to the stack pointer value.

8. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the exception handling method for the embedded system as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the exception handling method for an embedded system as described in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the exception handling method for an embedded system according to any one of claims 1 to 6.

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