Fault-tolerant control method for resonant dual active bridge converter power semiconductor open-circuit fault

Abstract

The present application belongs to the field of circuit fault control, and particularly relates to a resonant dual active bridge converter power semiconductor open-circuit fault tolerance control method, aiming to solve the problem that in a DAB converter with small DC capacitor, power semiconductor open-circuit fault causes current asymmetry and it is difficult to achieve effective fault tolerance operation. The present application comprises: when any of S5 to S8 fails, locking these devices and recalculating the switching frequency and timing; if S1 or S3 fails, respectively maintaining S7 on / S8 off or S5 on / S6 off, and adjusting the switching period according to the high-frequency current negative half-wave; for the case of S2 or S4 failure, corresponding S8 or S6 is kept on, and S7 or S5 is off, and the switching period is also adjusted based on the high-frequency current positive half-wave. The present application adjusts the switching frequency and timing, improves the system reliability without increasing the hardware cost, and is particularly suitable for small DC capacitor applications, and can maintain high-efficiency and stable operation and protect the devices even under the condition of power semiconductor open-circuit fault.

Description

Technical Field

[0001] This invention belongs to the field of circuit fault control, and specifically relates to a fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter. Background Technology

[0002] Resonant dual active bridge converters can achieve soft switching of all power semiconductor devices without closed-loop control, offering significant advantages such as high operating efficiency and high power density. They are core components of intelligent electrical equipment such as power electronic transformers and are widely used in AC / DC hybrid distribution networks, renewable energy grid-connected power generation, and electrified rail transit. In recent years, the State Grid Corporation of China and CRRC Zhuzhou Times Electric Co., Ltd. have respectively led and implemented research and demonstration projects on power electronic transformers for AC / DC hybrid distribution networks and high-speed train traction power supply systems, both employing dual active bridge converters as the core components for high-frequency isolation and power conversion.

[0003] Most existing resonant dual active bridge converters have large DC-side capacitors, and the DC capacitor voltage remains essentially constant during operation. Their switching frequency is determined by the resonant frequency of the high-frequency circuit formed by the leakage inductance of the high-frequency transformer and the resonant capacitor. Furthermore, the power semiconductor devices in resonant dual active bridge converters have high switching frequencies and high current stress, making them prone to open-circuit faults. However, an open-circuit fault in any power semiconductor device does not affect the resonant frequency of the high-frequency link; fault-tolerant operation under open-circuit faults can be achieved simply through topology reconfiguration. The paper "A Fault-Tolerant Series-Resonant DC–DC Converter," published in *IEEE Transactions on Power Electronics*, Volume 32, Issue 2, proposes a topology reconfiguration method to achieve fault-tolerant operation of resonant dual active bridge converters under open-circuit faults. The paper "Open-Circuit Fault Diagnosis and Fault-Tolerant Strategies for Full-Bridge DC–DC Converters," published in *IEEE Transactions on Power Electronics*, Volume 27, Issue 5, proposes achieving open-circuit fault-tolerant operation of power semiconductor devices by changing the high-frequency transformer turns ratio. However, this method requires additional hardware, resulting in high costs. The paper "A Composite Fault-Tolerant Control Method for SR-DAB Interface Converters in DC Distribution Systems," published in *Automation of Electric Power Systems*, Volume 42, Issue 20, proposes using topology reconfiguration and asymmetric duty cycle to achieve fault-tolerant operation of resonant dual active bridge converters. However, this method requires some power semiconductor devices to perform hard switching, resulting in high losses.

[0004] However, the large DC-side capacitance of dual active bridge converters results in bulky energy storage components, severely limiting their power density improvement. Furthermore, as the DC-side capacitance of resonant dual active bridge converters decreases, especially when it becomes roughly equivalent to the resonant capacitance, the switching frequency becomes complex, depending not only on the high-frequency resonant frequency but also on the DC-side capacitance. In this situation, when an open-circuit fault occurs in the power semiconductor devices of the resonant dual active bridge converter, a severe asymmetry in the positive and negative half-wave currents will occur. Traditional topology reconfiguration methods struggle to achieve open-circuit fault-tolerant operation, and existing literature rarely addresses open-circuit fault-tolerant operation control of power semiconductors in resonant dual active bridge converters with small DC capacitances. Summary of the Invention

[0005] To address the aforementioned problems in existing technologies, namely the difficulty of achieving effective fault-tolerant operation due to current asymmetry caused by open-circuit faults in power semiconductors in DAB converters with small DC capacitors, and the challenge of traditional topology reconfiguration methods for such operation, this invention provides a fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter. This method is applied to a resonant dual active bridge converter, which consists of a high-voltage side DC capacitor C1, a low-voltage side DC capacitor C2, and a high-voltage side resonant capacitor C... rp Low-voltage side resonant capacitor C rs , high-frequency transformer leakage inductance L r The method comprises a first power semiconductor device S1, a second power semiconductor device S2, a third power semiconductor device S3, a fourth power semiconductor device S4, a fifth power semiconductor device S5, a sixth power semiconductor device S6, a seventh power semiconductor device S7, and an eighth power semiconductor device S8, and includes:

[0006] Step A1: Determine the location of the power semiconductor that has an open circuit fault. If the power semiconductor that has an open circuit fault is any one of the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, or the eighth power semiconductor device S8, then proceed to step A2.

[0007] If the power semiconductor that has an open circuit fault is the first power semiconductor device S1 or the third power semiconductor device S3, proceed to step A3; if the power semiconductor that has an open circuit fault is the second power semiconductor device S2 or the fourth power semiconductor device S4, proceed to step A4.

[0008] Step A2: Block the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8; calculate the switching frequency based on the initial phase of the high-frequency current; and allocate the switching sequence of the power semiconductor devices based on the switching frequency.

[0009] Step A3: If the first power semiconductor device S1 experiences an open-circuit fault, then the seventh power semiconductor device S7 will always be in the ON state, and the eighth power semiconductor device S8 will always be in the OFF state.

[0010] If the third power semiconductor device S3 experiences an open-circuit fault, the fifth power semiconductor device S5 will always be in the on state, and the sixth power semiconductor device S6 will always be in the off state.

[0011] The switching period is calculated based on the amplitude of the negative half-wave of the high-frequency current and the initial phase, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0012] Step A4: If the second power semiconductor device S2 experiences an open circuit fault, the eighth power semiconductor device S8 will always be in the on state, and the seventh power semiconductor device S7 will always be in the off state; if the fourth power semiconductor device S4 experiences an open circuit fault, the sixth power semiconductor device S6 will always be in the on state, and the fifth power semiconductor device S5 will always be in the off state.

[0013] The switching period is calculated based on the amplitude of the positive half-wave of the high-frequency current and the initial phase, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0014] Preferably, in step A2, the initial phase of the high-frequency current The calculation method is as follows:

[0015]

[0016] Where, λ F The ratio of the resonant capacitor to the DC-side capacitor in the resonant dual active bridge converter is given by n, where n is the turns ratio of the high-frequency transformer.

[0017] λ F The calculation method is as follows:

[0018]

[0019] Preferably, in step A2, the switching frequency is calculated as follows:

[0020]

[0021] Among them, f rF1 This is the resonant frequency of the resonant dual active bridge converter.

[0022] Preferably, in step A2, the method for allocating the switching timing of the power semiconductor device based on the switching frequency is as follows:

[0023] When k / 2f s ≤t<(k+1) / 2f sWhen the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned on, the second power semiconductor device S2 and the third power semiconductor device S3 are turned off.

[0024] When (k+1) / 2f s ≤t<(k+2) / 2f s When the second power semiconductor device S2 and the third power semiconductor device S3 are turned on, the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned off.

[0025] Where k is an integer and t is a time variable.

[0026] Preferably, in step A3, the amplitude of the negative half-wave of the high-frequency current and the initial phase of the negative half-wave of the high-frequency current are calculated as follows:

[0027]

[0028] Among them, I rn θ represents the amplitude of the negative half-wave of the high-frequency current. n i1 represents the initial phase of the negative half-wave of the high-frequency current, i1 is the high-voltage side input current of the resonant dual active bridge converter, and k is the voltage. n ω is the capacitance ratio coefficient for the negative half-cycle. rn This is the resonant angular frequency of the negative half-cycle;

[0029] k n and ω rn The calculation method is as follows:

[0030]

[0031] Preferably, in step A3, the switching period includes a positive half-wave switching period and a negative half-wave switching period, which are calculated as follows:

[0032]

[0033] Among them, t p For the positive half-wave switching period, t n For the negative half-wave switching period, t z1 and t z2 It refers to the zero-crossing moment adjacent to the negative half-cycle current, and its calculation method is as follows:

[0034]

[0035] Preferably, in step A3, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows:

[0036] When the first power semiconductor device S1 is open-circuited, kt p +kt n ≤t<(k+1)tp +kt n The fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned on, while the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned off.

[0037] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned on; the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned off.

[0038] When the third power semiconductor device S3 is open, kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned on, while the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned off.

[0039] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The second power semiconductor device S2 and the seventh power semiconductor device S7 are turned on; the first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned off.

[0040] Where k is an integer and t is a time variable.

[0041] Preferably, in step A4, the calculation method for the amplitude and initial phase of the positive half-wave of the high-frequency current is as follows:

[0042]

[0043] Among them, I rp θ represents the amplitude of the positive half-wave of the high-frequency current. p i1 represents the initial phase of the positive half-wave of the high-frequency current, i1 is the high-voltage side input current of the resonant dual active bridge converter, and k is the voltage. p ω is the capacitance ratio coefficient during the positive half-cycle. rp It is the resonant angular frequency of the positive half-cycle;

[0044] k p and ω rp The calculation method is as follows:

[0045]

[0046] Preferably, in step A4, the switching period includes a positive half-wave switching period and a negative half-wave switching period, which are calculated as follows:

[0047]

[0048] Among them, t p For the positive half-wave switching period, t n For the negative half-wave switching period, t z1 and t z2 The zero-crossing time adjacent to the negative half-cycle current is calculated as follows:

[0049]

[0050] Preferably, in step A4, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows:

[0051] When the second power semiconductor device S2 is open, kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned on, while the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned off.

[0052] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The third power semiconductor device S3 and the sixth power semiconductor device S6 are turned on, while the first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned off.

[0053] When the fourth power semiconductor device S4 is open, kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1 and the eighth power semiconductor device S8 are turned on, while the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned off.

[0054] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t nThe second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned on, while the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned off.

[0055] Where k is an integer and t is a time variable.

[0056] The beneficial effects of this invention are:

[0057] Improve system reliability: By using specific switching frequency and timing control strategies, the system can maintain stable operation even when power semiconductor devices experience open-circuit faults, thus avoiding the risk of the entire power electronic transformer failing due to the failure of a single device.

[0058] No additional hardware required: Compared with some methods that require additional hardware to achieve fault-tolerant operation, this invention relies solely on software algorithm adjustments, without the need for additional hardware investment, thus reducing costs and simplifying system design.

[0059] Suitable for applications with small DC-side capacitors: It is particularly suitable for applications with small DC-side capacitors, which helps to reduce the size of energy storage components and further improve the power density of the converter, making the converter more suitable for applications with limited space but high requirements for efficiency and power density.

[0060] Enhanced flexibility: Different control strategies are adopted according to open circuit faults at different locations, which improves the response capability and adaptability of the control system to different types of faults and enhances the overall flexibility of the system.

[0061] Improved efficiency: By accurately calculating and allocating switching cycles, unnecessary energy loss can be minimized, ensuring that the converter can operate efficiently even in fault-tolerant mode. Attached Figure Description

[0062] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0063] Figure 1 This is a resonant dual active bridge converter circuit topology;

[0064] Figure 2 This is a flowchart of the open-circuit fault-tolerant control method for power semiconductors in a resonant dual active bridge converter according to the present invention.

[0065] Figure 3 The high-frequency voltage and current waveforms of the fifth power semiconductor device S5 in a resonant dual active bridge converter under an open-circuit fault.

[0066] Figure 4The high-frequency voltage and current waveforms of the first power semiconductor device S1 in a resonant dual active bridge converter under an open-circuit fault are shown. Detailed Implementation

[0067] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0068] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0069] This invention provides a fault-tolerant control method for open-circuit faults in the power semiconductor of a resonant dual active bridge converter, applied to a resonant dual active bridge converter in the prior art. The resonant dual active bridge converter consists of a high-voltage side DC capacitor C1, a low-voltage side DC capacitor C2, and a high-voltage side resonant capacitor C... rp Low-voltage side resonant capacitor C rs , high-frequency transformer leakage inductance L r The method comprises a first power semiconductor device S1, a second power semiconductor device S2, a third power semiconductor device S3, a fourth power semiconductor device S4, a fifth power semiconductor device S5, a sixth power semiconductor device S6, a seventh power semiconductor device S7, and an eighth power semiconductor device S8, and includes:

[0070] Step A1: Determine the location of the power semiconductor that has an open circuit fault. If the power semiconductor that has an open circuit fault is any one of the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, or the eighth power semiconductor device S8, then proceed to step A2.

[0071] If the power semiconductor that has an open circuit fault is the first power semiconductor device S1 or the third power semiconductor device S3, proceed to step A3; if the power semiconductor that has an open circuit fault is the second power semiconductor device S2 or the fourth power semiconductor device S4, proceed to step A4.

[0072] Step A2: Block the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8; calculate the switching frequency based on the initial phase of the high-frequency current; and allocate the switching sequence of the power semiconductor devices based on the switching frequency.

[0073] Step A3: If the first power semiconductor device S1 experiences an open-circuit fault, then the seventh power semiconductor device S7 will always be in the ON state, and the eighth power semiconductor device S8 will always be in the OFF state.

[0074] If the third power semiconductor device S3 experiences an open-circuit fault, the fifth power semiconductor device S5 will always be in the on state, and the sixth power semiconductor device S6 will always be in the off state.

[0075] The switching period is calculated based on the amplitude of the negative half-wave of the high-frequency current and the initial phase, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0076] Step A4: If the second power semiconductor device S2 experiences an open circuit fault, the eighth power semiconductor device S8 will always be in the on state, and the seventh power semiconductor device S7 will always be in the off state; if the fourth power semiconductor device S4 experiences an open circuit fault, the sixth power semiconductor device S6 will always be in the on state, and the fifth power semiconductor device S5 will always be in the off state.

[0077] The switching period is calculated based on the amplitude of the positive half-wave of the high-frequency current and the initial phase, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0078] To more clearly explain the fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to the present invention, the following is in conjunction with... Figure 1 and Figure 2 The steps in the embodiments of the present invention are described in detail below:

[0079] Step A1: Determine the location of the power semiconductor that has an open circuit fault. If the power semiconductor that has an open circuit fault is any one of the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, or the eighth power semiconductor device S8, then proceed to step A2.

[0080] Step A2: Block the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8. The switching frequency of the resonant dual active bridge converter remains consistent with that when there is no fault. Calculate the switching frequency based on the initial phase of the high-frequency current and allocate the switching sequence of the power semiconductor devices based on the switching frequency.

[0081] In step A2, the initial phase of the high-frequency current The calculation method is as follows:

[0082]

[0083] Where, λ FThe ratio of the resonant capacitor to the DC-side capacitor in the resonant dual active bridge converter is given by n, where n is the turns ratio of the high-frequency transformer.

[0084] λ F The calculation method is as follows:

[0085]

[0086] In step A2 of this invention, the switching frequency is calculated as follows:

[0087]

[0088] Among them, f rF1 This is the resonant frequency of the resonant dual active bridge converter.

[0089] In step A2 of this invention, the switching timing of the power semiconductor device is allocated based on the switching frequency, and the method is as follows:

[0090] When k / 2f s ≤t<(k+1) / 2f s When the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned on, the second power semiconductor device S2 and the third power semiconductor device S3 are turned off.

[0091] When (k+1) / 2f s ≤t<(k+2) / 2f s When the second power semiconductor device S2 and the third power semiconductor device S3 are turned on, the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned off.

[0092] Where k is an integer used to divide the time interval, ensuring that different semiconductor devices are turned on or off in a predetermined order within different time intervals, thereby achieving power distribution and control. t is a time variable used to determine which semiconductor devices should be turned on or off within a specific time interval, thereby achieving power distribution and control.

[0093] If the power semiconductor that experiences an open-circuit fault is the first power semiconductor device S1 or the third power semiconductor device S3, proceed to step A3.

[0094] Step A3: If the first power semiconductor device S1 experiences an open-circuit fault, then the seventh power semiconductor device S7 will always be in the ON state, and the eighth power semiconductor device S8 will always be in the OFF state.

[0095] If the third power semiconductor device S3 experiences an open-circuit fault, the fifth power semiconductor device S5 will always be in the on state, and the sixth power semiconductor device S6 will always be in the off state.

[0096] The switching period is calculated based on the amplitude of the negative half-wave of the high-frequency current and the initial phase, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0097] In step A3, the amplitude of the negative half-wave of the high-frequency current and the initial phase of the negative half-wave of the high-frequency current are calculated as follows:

[0098]

[0099] Among them, I rn θ represents the amplitude of the negative half-wave of the high-frequency current. n i1 represents the initial phase of the negative half-wave of the high-frequency current, i1 is the high-voltage side input current of the resonant dual active bridge converter, and k is the voltage. n ω is the capacitance ratio coefficient for the negative half-cycle. rn This is the resonant angular frequency of the negative half-cycle;

[0100] k n and ω rn The calculation method is as follows:

[0101]

[0102] In step A3, the switching period includes the positive half-wave switching period and the negative half-wave switching period, and its calculation method is as follows:

[0103]

[0104] Among them, t p For the positive half-wave switching period, t n For the negative half-wave switching period, t z1 and t z2 It refers to the zero-crossing moment adjacent to the negative half-cycle current, and its calculation method is as follows:

[0105]

[0106] In step A3, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows:

[0107] When the first power semiconductor device S1 is open-circuited, kt p +kt n ≤t<(k+1)t p +kt n The fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned on, while the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned off.

[0108] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t nThe second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned on; the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned off.

[0109] When the third power semiconductor device S3 is open, kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned on, while the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned off.

[0110] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The second power semiconductor device S2 and the seventh power semiconductor device S7 are turned on; the first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned off.

[0111] Where k is an integer and t is a time variable.

[0112] If the power semiconductor that experiences an open-circuit fault is the second power semiconductor device S2 or the fourth power semiconductor device S4, proceed to step A4.

[0113] Step A4: If the second power semiconductor device S2 experiences an open circuit fault, the eighth power semiconductor device S8 will always be in the on state, and the seventh power semiconductor device S7 will always be in the off state; if the fourth power semiconductor device S4 experiences an open circuit fault, the sixth power semiconductor device S6 will always be in the on state, and the fifth power semiconductor device S5 will always be in the off state.

[0114] The switching period is calculated based on the amplitude of the positive half-wave of the high-frequency current and the initial phase, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0115] In step A4, the amplitude and initial phase of the positive half-wave of the high-frequency current are calculated as follows:

[0116]

[0117] Among them, I rp θ represents the amplitude of the positive half-wave of the high-frequency current. p i1 represents the initial phase of the positive half-wave of the high-frequency current, i1 is the high-voltage side input current of the resonant dual active bridge converter, and k is the voltage. p ω is the capacitance ratio coefficient during the positive half-cycle. rp It is the resonant angular frequency of the positive half-cycle;

[0118] k p and ω rp The calculation method is as follows:

[0119]

[0120] In step A4, the switching period includes the positive half-wave switching period and the negative half-wave switching period, which are calculated as follows:

[0121]

[0122] Among them, t p For the positive half-wave switching period, t n For the negative half-wave switching period, t z1 and t z2 The zero-crossing time adjacent to the negative half-cycle current is calculated as follows:

[0123]

[0124] In step A4, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows:

[0125] When the second power semiconductor device S2 is open, kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned on, while the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned off.

[0126] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The third power semiconductor device S3 and the sixth power semiconductor device S6 are turned on, while the first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned off.

[0127] When the fourth power semiconductor device S4 is open, kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1 and the eighth power semiconductor device S8 are turned on, while the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned off.

[0128] (k+1)t p +kt n≤t<(k+1)t p +(k+1)t n The second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned on, while the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned off.

[0129] Where k is an integer and t is a time variable.

[0130] An embodiment of the present invention is as follows:

[0131] In this embodiment, the main circuit parameters of the resonant dual active bridge converter are shown in the table below:

[0132]

[0133] The above fault-tolerant control method is explained using the example of an open-circuit fault occurring in the fifth power semiconductor device S5 and the first power semiconductor device S1.

[0134] When the fifth power semiconductor device S5 experiences an open-circuit fault, the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8 are blocked. The switching frequency of the resonant dual active bridge converter remains consistent with that under fault-free conditions. The calculation method for its switching frequency includes the following steps:

[0135] (1) Calculate the initial phase of the high-frequency current

[0136] The initial phase of the high-frequency current in a resonant dual active bridge converter satisfies the following equation:

[0137]

[0138] Where, λ F is the ratio of the resonant capacitor to the DC-side capacitor in a resonant dual active bridge converter, and n is the turns ratio of the high-frequency transformer.

[0139]

[0140] (2) Calculate the switching frequency

[0141] The switching frequency is calculated based on the initial phase of the high-frequency current obtained in (1), as shown below:

[0142]

[0143] Among them, f rF1 This is the resonant frequency of the resonant dual active bridge converter.

[0144] (3) Power semiconductor device switching timing

[0145] When k / 2fs ≤t<(k+1) / 2f s When (k is an integer, f) s =25kHz), the first power semiconductor device S1 and the fourth power semiconductor device S4 of the resonant dual active bridge converter are turned on, while the second power semiconductor device S2 and the third power semiconductor device S3 are turned off; when (k+1) / 2f s ≤t<(k+2) / 2f s When the resonant dual active bridge converter is in operation, the second power semiconductor device S2 and the third power semiconductor device S3 are turned on; the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned off.

[0146] When the first power semiconductor device S1 experiences an open-circuit fault, the seventh power semiconductor device S7 remains in the on state, and the eighth power semiconductor device S8 remains in the off state. The method for calculating its switching frequency includes the following steps:

[0147] (1) Calculate the amplitude and initial phase of the negative half-wave of the high-frequency current.

[0148] The amplitude of the negative half-wave of the high-frequency current in the resonant dual active bridge converter satisfies the following set of equations with respect to the initial phase.

[0149]

[0150] Among them, I rn θ represents the amplitude of the negative half-wave of the high-frequency current. n i1 represents the initial phase of the negative half-wave of the high-frequency current, i1 is the high-voltage side input current of the resonant dual active bridge converter, and k is the voltage. n and ω rn The expression is as follows

[0151]

[0152] (2) Calculate the switching period

[0153] The switching periods of the positive and negative half-waves of the resonant dual active bridge converter are calculated based on the high-frequency current negative half-wave amplitude and initial phase obtained in (1), as shown below.

[0154]

[0155] Among them, t p For the positive half-wave switching period, t n For the negative half-wave switching period, t z1 and t z2 The zero-crossing times adjacent to the negative half-cycle current are calculated according to the following formula.

[0156]

[0157] (3) Power semiconductor device switching timing

[0158] When the first power semiconductor device S1 is open-circuited, kt p +kt n ≤t<(k+1)t p +kt n (k is an integer), in the resonant dual active bridge converter, the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned on, while the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned off; (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n In the resonant dual active bridge converter, the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned on; the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned off.

[0159] Figure 3 The high-frequency voltage and current waveforms of the fifth power semiconductor device S5 in a resonant dual active bridge converter under an open-circuit fault are shown. Even after an open-circuit fault occurs in the fifth power semiconductor device S5, soft switching of the resonant dual active bridge converter can still be achieved by employing the proposed fault-tolerant control method.

[0160] Figure 4 The simulation waveforms show the high-frequency voltage and current waveforms of the first power semiconductor device S1 in a resonant dual active bridge converter under an open-circuit fault. As can be seen from the simulation waveforms, after the first power semiconductor device S1 experiences an open-circuit fault, the positive and negative half-waves of the high-frequency current in the resonant dual active bridge converter become asymmetrical. By employing the proposed fault-tolerant control method, soft switching of all power semiconductor devices can be achieved. Therefore, the control method of this invention can achieve fault-tolerant operation of the resonant dual active bridge converter under an open-circuit fault in the power semiconductor devices.

[0161] Although the steps in the above embodiments are described in the above order, those skilled in the art will understand that in order to achieve the effect of this embodiment, different steps do not need to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple variations are all within the protection scope of this invention.

[0162] The terms “first”, “second”, etc., are used to distinguish similar objects, not to describe or indicate a specific order or sequence.

[0163] The term "comprising" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent in such process, method, article, or apparatus / device.

[0164] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter, applied to a resonant dual active bridge converter, wherein the resonant dual active bridge converter includes a high-voltage side H-bridge and a low-voltage side H-bridge, wherein, The first power semiconductor device S1 and the second power semiconductor device S2 are connected in series to form one arm of the high-voltage side H-bridge, and the third power semiconductor device S3 and the fourth power semiconductor device S4 are connected in series to form the other arm of the high-voltage side H-bridge. The fifth power semiconductor device S5 and the sixth power semiconductor device S6 are connected in series to form one arm of the low-voltage side H-bridge, and the seventh power semiconductor device S7 and the eighth power semiconductor device S8 are connected in series to form the other arm of the low-voltage side H-bridge. The high-voltage side H-bridge and the low-voltage side H-bridge are connected through a high-frequency transformer. The method is characterized by comprising: Step A1: Determine the location of the power semiconductor that has an open circuit fault. If the power semiconductor that has an open circuit fault is any one of the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, or the eighth power semiconductor device S8, then proceed to step A2. If the power semiconductor that has an open circuit fault is the first power semiconductor device S1 or the third power semiconductor device S3, proceed to step A3; if the power semiconductor that has an open circuit fault is the second power semiconductor device S2 or the fourth power semiconductor device S4, proceed to step A4. Step A2: Block the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8; calculate the switching frequency based on the initial phase of the high-frequency current; and allocate the switching sequence of the power semiconductor devices based on the switching frequency. Step A3: If the first power semiconductor device S1 experiences an open-circuit fault, then the seventh power semiconductor device S7 will always be in the ON state, and the eighth power semiconductor device S8 will always be in the OFF state. If the third power semiconductor device S3 experiences an open-circuit fault, the fifth power semiconductor device S5 will always be in the on state, and the sixth power semiconductor device S6 will always be in the off state. The switching period is calculated based on the amplitude of the negative half-wave of the high-frequency current and the initial phase, and the switching timing of the power semiconductor device is allocated based on the switching period. Step A4: If the second power semiconductor device S2 experiences an open circuit fault, the eighth power semiconductor device S8 will always be in the on state, and the seventh power semiconductor device S7 will always be in the off state; if the fourth power semiconductor device S4 experiences an open circuit fault, the sixth power semiconductor device S6 will always be in the on state, and the fifth power semiconductor device S5 will always be in the off state. The switching period is calculated based on the amplitude of the positive half-wave of the high-frequency current and the initial phase, and the switching timing of the power semiconductor device is allocated based on the switching period.

2. The fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to claim 1, characterized in that, In step A2, the initial phase of the high-frequency current The calculation method is as follows: ； in, λ F This is the ratio of the resonant capacitor to the DC-side capacitor in a resonant dual active bridge converter. λ F The calculation method is as follows: ； in, This indicates the capacitance value of the high-voltage side resonant capacitor. This indicates the capacitance value of the low-voltage side resonant capacitor. This indicates the capacitance value of the DC capacitor on the high-voltage side. This indicates the capacitance value of the DC capacitor on the low-voltage side. n This refers to the turns ratio of a high-frequency transformer.

3. The fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to claim 2, characterized in that, In step A2, the switching frequency is calculated as follows: ； in, f r1 This is the resonant frequency of the resonant dual active bridge converter. L r This refers to the leakage inductance of a high-frequency transformer.

4. The fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to claim 3, characterized in that, In step A2, the switching timing of the power semiconductor device is allocated based on the switching frequency, and the method is as follows: when k / 2f s ≤t<(k+1) / 2f s When the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned on, the second power semiconductor device S2 and the third power semiconductor device S3 are turned off. when( k+1) / 2f s ≤t<(k+2) / 2f s When the second power semiconductor device S2 and the third power semiconductor device S3 are turned on, the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned off. in, k It is an integer. t It is a time variable.

5. The fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to claim 1, characterized in that, In step A3, the amplitude of the negative half-wave of the high-frequency current and the initial phase of the negative half-wave of the high-frequency current are calculated as follows: ； in, I rn This represents the amplitude of the negative half-wave of the high-frequency current. θ n This represents the initial phase of the negative half-wave of the high-frequency current. i 1 This refers to the high-voltage side input current of the resonant dual active bridge converter. k n This is the capacitance ratio coefficient for the negative half-cycle. ω rn This is the resonant angular frequency of the negative half-cycle; k n and ω rn ， The calculation method is as follows: ； in, This indicates the capacitance value of the high-voltage side resonant capacitor. This indicates the capacitance value of the low-voltage side resonant capacitor. This indicates the capacitance value of the DC capacitor on the high-voltage side. This indicates the capacitance value of the DC capacitor on the low-voltage side. L r The leakage inductance of the high-frequency transformer. n This refers to the turns ratio of a high-frequency transformer.

6. The fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to claim 5, characterized in that, In step A3, the switching period includes the positive half-wave switching period and the negative half-wave switching period, and its calculation method is as follows: ； in, t p The positive half-wave switching period, t n The negative half-wave switching period, t z1 and t z2 It refers to the zero-crossing moment adjacent to the negative half-cycle current, and its calculation method is as follows: 。 7. The fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to claim 6, characterized in that, In step A3, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows: When the first power semiconductor device S1 is open-circuited kt p +kt n ≤t<(k+1)t p +kt n The fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned on, while the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned off. (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned on; the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned off. When the third power semiconductor device S3 is open-circuited kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned on, while the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned off. (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The second power semiconductor device S2 and the seventh power semiconductor device S7 are turned on; the first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned off. in, k It is an integer. t It is a time variable.

8. The fault-tolerant control method for open-circuit faults in a resonant dual active bridge converter according to claim 7, characterized in that, In step A4, the amplitude and initial phase of the positive half-wave of the high-frequency current are calculated as follows: ； in, I rp This represents the amplitude of the positive half-wave of the high-frequency current. θ p This represents the initial phase of the positive half-wave of the high-frequency current. i 1 This refers to the high-voltage side input current of the resonant dual active bridge converter. k p ω is the capacitance ratio coefficient during the positive half-cycle. rp It is the resonant angular frequency of the positive half-cycle; k p and ω rp The calculation method is as follows: 。 9. The fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to claim 8, characterized in that, In step A4, the switching period includes the positive half-wave switching period and the negative half-wave switching period, which are calculated as follows: ； in, t z1 and t z2 The zero-crossing time adjacent to the negative half-cycle current is calculated as follows: 。 10. The fault-tolerant control method for open-circuit faults in power semiconductors of a resonant dual active bridge converter according to claim 9, characterized in that, In step A4, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows: When the second power semiconductor device S2 is open-circuited kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned on, while the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned off. (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The third power semiconductor device S3 and the sixth power semiconductor device S6 are turned on, while the first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned off. When the fourth power semiconductor device S4 is open-circuited kt p +kt n ≤t<(k+1)t p +kt n The first power semiconductor device S1 and the eighth power semiconductor device S8 are turned on, while the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned off. (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n The second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned on, while the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned off.

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