Adaptive bias circuit and power amplifier circuit

Abstract

The present disclosure provides an adaptive bias circuit and power amplifier circuit; wherein, the adaptive bias circuit includes a coupling module, a DC conversion module, and a current copy module. The coupling module is connected to the amplifier and is configured to sample the voltage at the output end of the amplifier to generate a sampling voltage; the DC conversion module is configured to receive the sampling voltage and convert the sampling voltage into a DC intermediate current; wherein the intermediate current is positively correlated with the sampling voltage; the current copy module is connected to the bipolar transistor and the DC conversion module respectively, and is configured to receive the intermediate current and proportionally copy the intermediate current into a bias current, and output the bias current to the input end of the bipolar transistor. In this way, the present disclosure can adjust the bias current based on changes in the input signal, so that the amplifier can have better linearity and noise performance.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to an adaptive bias circuit and a power amplifier circuit. Background Art

[0002] RF driver amplifiers play a crucial role in phased array and transceiver systems. Their performance directly impacts the overall system performance, placing stringent requirements on performance metrics such as output power and input noise figure. The bias circuit is crucial in amplifier design, as it directly affects the operating current of the amplifier tube, which in turn influences key parameters such as linearity and noise figure.

[0003] Heterojunction bipolar transistors (HBTs) are highly favored in driver amplifier designs due to their advantages in high-frequency performance, noise, and power consumption. However, HBTs are base-current controlled devices and are very sensitive to voltage changes. When an amplifier uses an HBT transistor as its amplifying transistor, the following problems arise:

[0004] 1. If the input signal power received by the amplifier is large, there will be a period of time when the HBT transistor cannot be turned on, which affects the current swing of the HBT transistor under large signals; in turn, it has a significant impact on the linearity performance of the amplifier.

[0005] 2. In the existing bias circuit, there is a low-resistance path to ground, which affects the noise figure performance when the input signal is a small signal.

[0006] Therefore, the bias circuit needs to meet the noise performance requirements at small signals and / or the linearity requirements at large signals. Summary of the Invention

[0007] In view of this, embodiments of the present disclosure provide an adaptive bias circuit and a power amplifier circuit to meet the noise performance requirements for small signals and / or the linearity requirements for large signals.

[0008] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0009] An embodiment of the present disclosure provides an adaptive bias circuit, wherein the amplifier includes a bipolar transistor; the bias circuit includes: a coupling module, a DC conversion module, and a current copy module. The coupling module is connected to the output end of the amplifier and is configured to sample the voltage at the output end of the amplifier to generate a sampling voltage, wherein the sampling voltage is an AC voltage. The DC conversion module is connected to the output end of the coupling module and is configured to receive the sampling voltage and convert the sampling voltage into a DC intermediate current; wherein the intermediate current is positively correlated with the sampling voltage. The current copy module is connected to the bipolar transistor and the DC conversion module respectively, and is configured to receive the intermediate current and proportionally copy the intermediate current into a bias current, and output the bias current to the input end of the bipolar transistor.

[0010] First, the coupling module is connected to the amplifier's output, and the coupling module does not affect the amplifier's input signal. Furthermore, the amplitude of the amplifier's output voltage is positively correlated with the amplitude of the input signal, reflecting the amplitude of the input signal. A voltage amplitude at the amplifier's output greater than the input signal's amplitude helps improve sampling accuracy.

[0011] Second, the DC conversion module converts the sampled voltage into a DC intermediate current. The intermediate current is positively correlated with the sampled voltage. Therefore, as the amplitude (voltage) of the input signal (RF signal) increases, the amplitude of the output signal increases, the amplitude of the sampled voltage increases, and the magnitude of the intermediate current increases.

[0012] Third, the current copy module receives the intermediate current, proportionally copies the intermediate current into a bias current, and outputs the bias current to the input of the bipolar transistor. In other words, the bias current input to the bipolar transistor varies with the voltage amplitude at the amplifier output. When the amplitude (voltage value) of the input signal increases, the sampling voltage amplitude increases accordingly, the intermediate current increases accordingly, the bias current increases, and the DC bias voltage (control terminal voltage) of the bipolar transistor increases, so that the sum of the input signal and the DC bias voltage is always greater than the turn-on voltage of the bipolar transistor. Consequently, the bipolar transistor is always on, and the operating current of the bipolar transistor increases, thereby improving the linearity of the amplifier.

[0013] Fourth, the current copy module can copy the current proportionally, and directly output the required bias current without the need for a DC conversion module. This can avoid the device area of ​​the DC conversion module being too large, reduce the integration area, and reduce power consumption.

[0014] In some embodiments, the coupling module includes a third voltage divider element and a fourth voltage divider element. When both the third voltage divider element and the fourth voltage divider element are resistors, the DC component of the sampled voltage is used as a bias voltage for the DC conversion module and is provided to the transistors in the DC conversion module. Thus, the present disclosure eliminates the need for additional devices for providing bias voltages to the transistors in the DC conversion module, thereby further reducing the area of ​​the bias circuit, improving integration, and reducing energy consumption.

[0015] In some embodiments, the resistance values ​​of the third and fourth voltage divider elements are both greater than 10 kilo-ohms. Thus, when the third and fourth voltage divider elements are used for voltage acquisition, current leakage is reduced, which can effectively reduce power loss.

[0016] In some embodiments, the current copy module includes a fifth resistor connected to the input terminal of the bipolar transistor. The resistance of the fifth resistor is greater than 10 kilo-ohms. Thus, the fifth resistor can increase the internal resistance of the bias circuit. Consequently, the higher internal resistance of the bias circuit can effectively prevent current leakage from the bipolar transistor through the bias circuit, thereby achieving better noise performance when the amplifier (e.g., a driver amplifier) ​​operates at small signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 An amplifier and a bias circuit thereof according to a technique provided by an embodiment of the present disclosure;

[0018] Figure 2 Schematic diagram of input signal provided by the embodiment of the present disclosure Figure 1 ;

[0019] Figure 3 Schematic diagram of input signal provided by the embodiment of the present disclosure Figure 2 ;

[0020] Figure 4 Schematic diagram of the bias circuit provided in the embodiment of the present disclosure Figure 1 ;

[0021] Figure 5 A schematic diagram of the structure of an amplifier in a bias circuit provided in an embodiment of the present disclosure;

[0022] Figure 6 Schematic diagram of the structure of the coupling module provided in the embodiment of the present disclosure Figure 1 ;

[0023] Figure 7 Schematic diagram of the structure of the coupling module provided in the embodiment of the present disclosure Figure 2 ;

[0024] Figure 8 The structure of the DC conversion module provided in the embodiment of the present disclosure is shown as follows: Figure 1 ;

[0025] Figure 9 The structure of the DC conversion module provided in the embodiment of the present disclosure is shown as follows: Figure 2 ;

[0026] Figure 10 The structure of the DC conversion module provided in the embodiment of the present disclosure is shown as follows: Figure 3 ;

[0027] Figure 11 Schematic diagram of the connection structure between the bias circuit and the amplifier provided in the embodiment of the present disclosure Figure 1 ;

[0028] Figure 12 Schematic diagram of the connection structure between the bias circuit and the amplifier provided in the embodiment of the present disclosure Figure 2 ;

[0029] Figure 13 A schematic diagram of intermediate current and bias current provided for an embodiment of the present disclosure;

[0030] Figure 14 A schematic diagram of the structure of a power amplifier circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0032] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0033] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0035] Figure 1 An amplifier 200 and a bias circuit 101 thereof are shown in the following. Figure 1 Taking the bias circuit 101 as an example, the principle of controlling the amplifier 200 in one technology is described as follows:

[0036] It should be noted that the reference Figure 1 The bias circuit 101 includes a bipolar transistor Q2 and resistors R11, R12, and R13. The bipolar transistor Q2 may also be other types of transistors, which is not limited here. Figure 1 The circuit system shown includes a current mirror, which includes a bipolar transistor Q2 and a bipolar transistor Q1 in the amplifier 200. Furthermore, the bias circuit 101 can provide a DC bias to the amplifier 200 by copying the current through the current mirror. Resistor R11 is connected in series between the power supply and the collector of the bipolar transistor Q2, and together with the bipolar transistor Q2, forms a constant current source structure. Resistor R11 is used to generate a reference current Iref. The reference current Iref serves as a reference source for the current mirror and is mirrored to the bipolar transistor Q1 in the amplifier 200, thereby providing a stable bias current for the bipolar transistor Q1. Resistors R12 and R13 are used to adjust the current copy ratio between the reference current Iref in the bias circuit 101 and the operating current Ic of the bipolar transistor Q1.

[0037] In the present disclosure, continue to refer to Figure 1 In order to ensure the accuracy of current copy, it is necessary to ensure Figure 1 The voltages at nodes A and B are the same. Therefore, when designing the bias circuit 101, the ratio of the resistors R12 and R13 between nodes A and B needs to be adjusted according to the current copy ratio. For example, if the current Iref in the bias circuit 101 and the operating current Ic of the bipolar transistor Q1 are 1:20, the ratio of the resistors R12 and R13 can be set to 20:1. In this case, the resistance of the resistor R13 close to the amplifier 200 is smaller, and the input signal may be Figure 1 The input signal is bypassed to ground as shown by path S. That is, the input signal is sequentially connected to ground via node B, node C, and bipolar transistor Q2, resulting in input signal loss. Furthermore, node B, located near amplifier 200, is a low-impedance node, making it more susceptible to coupling with power supply or substrate noise, adding an additional noise source. Consequently, the noise figure (NF) of amplifier 200 is reduced, severely impacting its noise performance. This is particularly true for small input signals, where noise performance significantly impacts the overall performance of the amplifier.

[0038] Figure 2 and Figure 3 The embodiment of the present disclosure provides Figure 1Schematic diagram of voltage changes of the amplifier 200 receiving different input signals, where the horizontal axis is time t, the unit is seconds (s), and the vertical axis is voltage U, the unit is volts (V). It should be noted that, Figure 2 and Figure 3 The DC bias voltage is proportional to the bias current. The DC bias voltage is Figure 1 The control terminal (base) voltage of the bipolar transistor Q1 in the circuit. Figure 2 The input signal L1 is a small signal, that is, the input signal L1 has a relatively low power, and the power range may be between a few milliwatts and a few watts. Figure 3 Input signal L2 is a large signal, meaning that input signal L1 has a high power range, ranging from a few watts to several kilowatts. Because power is proportional to the square of the voltage swing, the voltage swing of small-signal input signal L1 is smaller than that of large-signal input signal L2.

[0039] In the embodiments of the present disclosure, reference Figure 1 , when the input signal is a small signal, Figure 2 The swing ratio of the input signal L1 Figure 3 The swing of the input signal L2 is small, and the voltage value of the sum of the input signal L1 and the DC bias voltage is always greater than the turn-on voltage of the bipolar transistor Q1. The swing of the input signal L1 will not affect the working range of the transistor. However, when the input signal is a large signal, such as Figure 3 As shown in the L3 area, the sum of the input signal L2 and the DC bias voltage is less than the turn-on voltage of the bipolar transistor Q1. In the process of amplifying the input signal L2, there will be a period of time when the bipolar transistor Q1 cannot be turned on. Therefore, the equivalent DC level of the overall input signal will be slightly increased, that is, the average voltage of the input signal L2 will be slightly increased, making Figure 1 The voltage at point C rises, and thus the reference current Iref decreases, thereby affecting the swing of the operating current Ic of the bipolar transistor Q1 under large signals, and further having a greater impact on the linearity index of the amplifier 200.

[0040] Figure 4 Figure 1 is a schematic diagram of an optional bias circuit 100 provided in an embodiment of the present disclosure. Bias circuit 100 can be connected to amplifier 200. Amplifier 200 can be either a class AB driver amplifier or a class B driver amplifier. Class AB and class B driver amplifiers can be used in scenarios where the input signal is large, so linearity indicators under large signals are of particular concern.

[0041] In the embodiments of the present disclosure, reference Figure 4Amplifier 200 may include a bipolar junction transistor (BJT) Q1. Bipolar transistor Q1 may be the amplifier transistor of amplifier 200. A bipolar transistor is a base current-controlled transistor with a small base input resistance. Its operating current Ic is proportional to the base current and exponentially related to the base voltage. Therefore, it is very sensitive to voltage changes and has high noise figure requirements. For example, bipolar transistor Q1 may be a heterojunction bipolar transistor (HBT) or a homojunction bipolar transistor. HBTs have a lower base current, which reduces base current shot noise (Shot Noise) and base resistance thermal noise (Johnson Noise), significantly optimizing small-signal noise performance. HBTs have a breakdown voltage of over 15V, supporting a higher voltage swing, thereby reducing large-signal clipping distortion and improving linearity.

[0042] In the embodiments of the present disclosure, reference Figure 4 Amplifier 200 is configured to receive and amplify an input signal and generate an output signal. Bias circuit 100 can output a bias current to bipolar transistor Q1 of amplifier 200. Bias circuit 100 includes a coupling module 10, a DC conversion module 20, and a current copy module 30. Bias circuit 100 can control the operating current of bipolar transistor Q1 in amplifier 200 by adjusting the bias current, thereby adjusting parameters such as the linearity of amplifier 200.

[0043] In the embodiments of the present disclosure, reference Figure 4 The coupling module 10 is connected to the output terminal of the amplifier 200. The coupling module 10 is configured to sample the voltage at the output terminal of the amplifier 200 to generate a sampled voltage. The sampled voltage can be an AC voltage. In other words, the coupling module 10 can sample the output signal of the amplifier 200, thereby monitoring the power and / or amplitude changes of the input signal through changes in the output signal.

[0044] The sampling voltage can feed back the amplitude change of the output voltage of the output terminal of the amplifier 200. The amplitude of the output voltage of the output terminal of the amplifier 200 is positively correlated with the amplitude of the input signal, and the amplitude of the output voltage of the output terminal of the amplifier 200 can reflect the amplitude of the input signal.

[0045] Meanwhile, the coupling module 10 is connected to the output end of the amplifier 200 , and the coupling module 10 does not contact the input end of the amplifier 200 . Therefore, the coupling module 10 does not affect the input signal received by the input end of the amplifier 200 .

[0046] In addition, the amplifier 200 amplifies the power of the input signal. Therefore, the amplitude of the output voltage at the output end of the amplifier 200 is larger than the amplitude of the input signal. Compared with sampling the input signal, the embodiment of the present disclosure samples the output signal, which can improve the sampling accuracy.

[0047] In the embodiments of the present disclosure, reference Figure 4 The bias circuit 100 further includes a DC conversion module 20. The DC conversion module 20 is connected to the output terminal of the coupling module 10. The DC conversion module 20 is configured to receive a sampled voltage and convert the sampled voltage into a DC intermediate current. For example, the DC conversion module 20 may include a transistor, the sampled voltage may be a control terminal voltage of the transistor, and the intermediate current may be a drain current of the transistor. The bipolar transistor Q1 is a current-controlled device, and the DC conversion module 20 converts the sampled voltage into a DC intermediate current, facilitating subsequent conversion of the intermediate current into a bias current for controlling the bipolar transistor Q1.

[0048] In the embodiments of the present disclosure, reference Figure 4 , the bias circuit 100 also includes a current copy module 30. The current copy module 30 is respectively connected to the bipolar transistor Q1 and the DC conversion module 20. The current copy module 30 is configured to receive the intermediate current, proportionally copy the intermediate current into a bias current, and output the bias current to the input end of the bipolar transistor Q1. For example, the current copy module 30 may include a current mirror. The current mirror can proportionally copy the intermediate current into a bias current. By proportionally copying the intermediate current through the current copy module 30, there is no need for the DC conversion module 20 to directly output the required bias current, thereby avoiding the device area of ​​the DC conversion module 20 being too large, reducing the integration area, and reducing power consumption.

[0049] When the amplitude (voltage value) of the input signal increases, the amplitude of the sampling voltage increases accordingly, the intermediate current increases accordingly, the magnitude of the bias current increases, and the DC bias voltage (control terminal voltage) of the bipolar transistor Q1 increases, so that the sum of the input signal and the DC bias voltage is always greater than the turn-on voltage of the bipolar transistor Q1. The bipolar transistor Q1 is always turned on, so the operating current Ic of the bipolar transistor Q1 increases, thereby improving the linearity index of the amplifier.

[0050] Figure 5 1 is a schematic diagram of a circuit connection relationship between an optional bias circuit 100 and an amplifier 200 provided in an embodiment of the present disclosure. It should be noted that: Figure 5 The amplifier 200 exemplified in FIG. 1 is a cascode structure, and the amplifier 200 includes a bipolar transistor Q1 and a transistor Mb. The amplifier 200 may also be a common-source structure, a common-gate structure, or other structures, which are not limited here. Figure 5The transistor Mb shown is described by taking an NMOS (N-Metal-Oxide-Semiconductor) transistor as an example. The transistor Mb may also be a bipolar junction transistor (BJT) or other types of transistors, which is not limited here.

[0051] In the embodiments of the present disclosure, reference Figure 5 , Figure 5 Inductor L1 and capacitor C12 form the output matching circuit of amplifier 200, used to match the output impedance of amplifier 200. Capacitor C12 isolates the output signal from bias circuit 100. "In" is the input of amplifier 200; "Out" is the output of amplifier 200. "Vb1" is used to provide a bias voltage to transistor Mb. Transistor Mb and bipolar transistor Q1 form a cascode structure to increase the output impedance of amplifier 200, enabling amplifier 200 to have better constant current characteristics.

[0052] It should also be noted that the reference Figure 4 and Figure 5 The connection node between the current copy module 30 and the amplifier 200 is located between the capacitor C11 and the bipolar transistor Q1 to prevent the capacitor C11 from filtering out the DC component of the bias current. The connection node between the coupling module 10 and the amplifier 200 is located between the capacitor C12 and the bipolar transistor Q1. The sampling voltage of the coupling module 10 can retain the DC component of the voltage at the output of the amplifier 200.

[0053] In the embodiments of the present disclosure, reference Figure 5 The bias circuit 100 can sample the output of the amplifier 200 and adjust the bias current output to the amplifier 200 based on the sampling result. The bias current value can be calculated and simulated based on the swing required by the linearity indicator of the actual output of the amplifier 200. The sampling result can be the voltage at the output of the amplifier 200 (i.e., the sampling voltage), and the sampling result can be used to feedback the power of the input signal. In other words, the bias circuit 100 can adjust the bias current output to the amplifier 200 based on the feedback of the output signal of the amplifier 200. For example, the bias circuit 100 can increase the bias current as the power of the input signal increases. In this way, the bias circuit 100 of the embodiment of the present disclosure can increase the bias current as the power of the input signal increases, and thus, the sum of the DC bias voltage and the input signal voltage is greater than the turn-on voltage of the bipolar transistor Q1, thereby increasing the swing of the operating current Ic of the bipolar transistor Q1 and improving the linearity of the amplifier 200.

[0054] Figure 6 This is a schematic structural diagram of an optional coupling module 10 provided in an embodiment of the present disclosure. It should be noted that: Figure 6The directional coupler 110 shown in FIG. 1 is a four-port directional coupler. The directional coupler 110 may be of other types, which is not limited here.

[0055] In some embodiments, reference Figure 6 The coupling module 10 may be a directional coupler 110. The directional coupler 110 is generally composed of a through line (main line) 111 and a coupled line (sub-line) 112. The input port P1 of the directional coupler 110 may be connected to Figure 1 The collector of the bipolar transistor Q1 of the amplifier 200, the output signal enters the directional coupler 110 through the input port P1. The output port P2 of the directional coupler 110 can be connected to the output terminal Out of the amplifier 200. After passing through the coupled amplifier 200, the output signal is output from the output port P2 to the next stage circuit. The coupling port P3 of the directional coupler 110 is connected to the DC conversion module 20, which is used to extract and output the coupled signal from the output signal. The isolation port P4 of the directional coupler 110 is used to reduce signal reflection and interference. For example, the isolation port P4 can be connected to a load such as a resistor and a capacitor. In this way, the directional coupler 110 can couple the output signal of the output terminal of the amplifier 200 to the coupling line 112 according to a certain ratio. Then, the directional coupler 110 can process the coupled signal in the coupling line 112, generate a sampling voltage and output it to the DC conversion module 20. The directional coupler 110 realizes energy transfer through the electromagnetic field interaction between the through line 111 and the coupled line 112 . During the sampling process, the attenuation and interference of the output signal of the through line (main line) 111 are extremely small.

[0056] Figure 7 This is a schematic structural diagram of an optional coupling module 10 provided in an embodiment of the present disclosure. It should be noted that: Figure 7 The third voltage dividing element 11 and the fourth voltage dividing element 12 shown in FIG. 1 are both resistors. The third voltage dividing element 11 and the fourth voltage dividing element 12 may also be capacitors, which is not limited here.

[0057] In some embodiments, reference Figure 7 The coupling module 10 may include a third voltage divider element 11 and a fourth voltage divider element 12. The third voltage divider element 11 and the fourth voltage divider element 12 are connected in series between the output terminal Out of the amplifier and ground. The connection node D between the third voltage divider element 11 and the fourth voltage divider element 12 outputs a sampled voltage. For example, the third voltage divider element 11 may include a resistor R11, and the fourth voltage divider element 12 may include a resistor R12. In this way, the third voltage divider element 11 and the fourth voltage divider element 12 can sample the voltage of the output terminal Out of the amplifier by voltage division, thereby sampling the voltage swing of the output terminal Out of the amplifier.

[0058] In some embodiments of the present disclosure, reference Figure 7The resistance values ​​of the third and fourth voltage divider elements 11 and 12 are both greater than 10 kilo-ohms. Thus, when the third and fourth voltage divider elements 11 and 12 are used for voltage acquisition in the disclosed embodiment, current leakage is reduced, effectively reducing power loss and lowering the resolution requirements of the detection circuit, making the detection circuit design more convenient.

[0059] Figure 8 and Figure 9 This is a schematic structural diagram of an optional DC conversion module 20 provided in an embodiment of the present disclosure. It should be noted that: Figure 8 and Figure 9 Transistors M1 to M3 are illustrated using bipolar junction transistors (BJTs) as an example. The first terminals of transistors M1 to M3 are collectors, the second terminals of transistors M0 to Mn are emitters, and the control terminals of transistors M0 to M3 are bases. Transistors M0 to M3 can also be other types of transistors, such as NMOS (N-Metal-Oxide-Semiconductor), without limitation. Figure 8 and Figure 9 The node D in Figure 7 The third voltage dividing element 11 and the connection node of the third voltage dividing element 11 can be regarded as the output end of the coupling module 10. Figure 8 and Figure 9 The node D in can also be Figure 6 P3 port.

[0060] In some embodiments of the present disclosure, reference Figure 8The DC conversion module 20 includes a first voltage divider element 21, a second voltage divider element 22, a first capacitor C1, a tail current generating unit 23, a first transistor M1, a second transistor M2, and a third transistor M3. The first voltage divider element 21, the second voltage divider element 22, and the first capacitor C1 are sequentially connected in series between the output end of the coupling module 10 and the ground, and the first capacitor C1 is grounded. The control end of the first transistor M1 is connected to the node E1 between the coupling module 10 and the first voltage divider element 21. The control end of the second transistor M2 is connected to the node E2 between the first voltage divider element 21 and the second voltage divider element 22. The control end of the third transistor M3 is connected to the node E3 between the second voltage divider element 22 and the first capacitor C1. In this way, the first voltage divider element 21 and the second voltage divider element 22 divide the sampled voltage. The DC conversion module 20 can control the AC voltage swing and DC voltage at nodes E1, E2, and E3 by controlling the voltage division ratio of the first voltage divider element 21 and the second voltage divider element 22, thereby adjusting the conduction degree of the first transistor M1, the second transistor M2, and the third transistor M3. Thus, the greater the conduction degree of the first transistor M1 and the third transistor M3, the greater the proportion of the tail current Iee shunted by the first transistor M1 and the third transistor M3, which in turn increases the current value of the output intermediate current. In other words, as the sampling voltage increases, the greater the proportion of the tail current Iee shunted by the first transistor M1 and the third transistor M3, and the intermediate current also increases accordingly.

[0061] In the embodiments of the present disclosure, reference Figure 8 The first capacitor C1 is located between the second voltage divider 22 and the ground terminal. Therefore, at the same time, the first capacitor C1 can prevent the DC component of the sampled voltage from leaking from the ground terminal, thereby ensuring the accuracy of the intermediate current.

[0062] In the embodiments of the present disclosure, reference Figure 8The DC conversion module 20 also includes a third resistor R3, a fourth resistor R4, and a second capacitor C2. The tail current generation unit 23 is used to provide a stable operating current (tail current Iee). The first ends of the first transistor M1, the second transistor M2, and the third transistor M3 are all connected to the output end of the tail current generation unit 23 and receive the tail current Iee generated by the tail current generation unit 23. The first end of the second transistor M2 is respectively connected to the first end of the third resistor R3 and the first end of the second capacitor C2. The second end of the third resistor R3 is connected to the power supply. The first end of the first transistor M1 and the first end of the third transistor M3 are both connected to the first end of the fourth resistor R4 and the second end of the second capacitor C2. The second end of the fourth resistor R4 is used to output the intermediate current. For example, the equivalent dimensions of the first transistor M1, the second transistor M2, and the third transistor M3 are in a ratio of 1:5:1. When the input signal is small, the first transistor M1, the second transistor M2, and the third transistor M3 can divide the tail current Iee in a ratio of 1:5:1. In this case, the intermediate current between the first transistor M1 and the third transistor M3 is 2 / 7 Iee. In this way, the first transistor M1, the second transistor M2, and the third transistor M3 can distribute the tail current Iee generated by the tail current generation unit 23 according to the received control voltage. The second end of the first transistor M1 and the second end of the third transistor M3 are connected to the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the current copy module. The second end of the first transistor M1 and the third transistor M3 can output the intermediate current to the current copy module.

[0063] Furthermore, as the amplitude of the sampling voltage increases, the increase in the AC swing at node E2 is half that of node E1. That is, as the amplitude of the sampling voltage increases, the increase in the AC swing of the first transistor M1 becomes greater than that of the second transistor M2, and the intermediate current output by the first transistor M1 and the third transistor M3 receives a larger share of the tail current Iee. Thus, as the amplitude of the sampling voltage gradually increases, the DC conversion module 20 can utilize the difference in the increase in the swing of the AC voltages at nodes E1 and E2 to increase the proportion of the tail current Iee shunted by the first transistor M1 and the third transistor M3, thereby increasing the current value of the output intermediate current.

[0064] It should be noted that the voltage dividing ratio of the first voltage dividing element 21 and the second voltage dividing element 22, as well as the equivalent size ratio of the first transistor M1, the second transistor M2, and the third transistor M3, can be designed according to actual needs and are not limited here. The sizes of the first transistor M1 and the third transistor M3 can be different and are not limited here.

[0065] In some embodiments, reference Figure 8, the first voltage divider element 21 and the second voltage divider element 22 are both resistors. For example, the first voltage divider element 21 includes a first resistor R1. The second voltage divider element 22 includes a second resistor R2. In this way, the DC component of the sampled voltage can be used as a bias voltage for the DC conversion module 20 and provided to the transistors M1, M2, and M3 in the DC conversion module 20. Therefore, the present disclosure does not require the additional provision of a device for providing a bias voltage to the transistors M1, M2, and M3 in the DC conversion module 20, further reducing the area of ​​the bias circuit 100, improving the integration level, and reducing energy consumption.

[0066] In other embodiments, reference Figure 9 , the first voltage divider element 21 and the second voltage divider element 22 are both capacitors. The first voltage divider element 21 may include a capacitor C21. The second voltage divider element 22 may include a capacitor C22. The control terminals of the first transistor M1, the second transistor M2, and the third transistor M3 are connected to the second bias current Ib. In this way, the second bias current Ib can provide a DC bias to the transistors M1, M2, and M3 in the DC conversion module 20.

[0067] In some embodiments, reference Figure 8 The tail current generating unit 23 includes a first current mirror 231. The resistor R31 of the first current mirror 231 can generate a reference current Iref2. The input transistor M41 and the output transistor M42 copy the reference current Iref2 to generate the tail current Iee. The second terminals of the transistors M1, M2, and M3 can all be connected to the collector of the output transistor M42. The input transistor M41 and the output transistor M42 can be any type of transistor and are not limited here.

[0068] In other embodiments, reference Figure 9 , the tail current generating unit 23 includes a current source 232. In this way, the current source 232 can directly provide the tail current Iee to the transistors M1, M2 and M3.

[0069] Figure 8 and Figure 9 The detection circuit shown has a simple structure, low power consumption and high sensitivity, and can effectively improve the performance of the amplifier.

[0070] Figure 10 2 is a schematic structural diagram of another optional DC conversion module 20 provided in an embodiment of the present disclosure.

[0071] In other embodiments of the present disclosure, Figure 10The DC conversion module 20 includes an RMS detector 210 and a voltage-to-current unit 220. The RMS detector 210 is configured to receive a sampled voltage, convert the sampled voltage into a DC voltage, and output it. The voltage-to-current unit 220, connected to the output terminal of the RMS detector 210, is configured to receive a DC voltage and convert the DC voltage into an intermediate current.

[0072] In the embodiments of the present disclosure, reference Figure 10 Root mean square (RMS) detector 210 may include an operational amplifier OP and a diode D1. The cathode of diode D1 and the positive input of operational amplifier OP are connected to the output terminal D of the coupling module. The negative input of operational amplifier OP is grounded. Operational amplifier OP amplifies the sampled voltage, and diode D1 detects the sampled voltage. In this way, RMS detector 210 can accurately measure the RMS value of the sampled voltage and convert it into a stable DC voltage output.

[0073] In the embodiments of the present disclosure, reference Figure 10 The voltage-to-current unit 220 may include a transistor M21. The output terminal of the operational amplifier OP is connected to the control terminal of the transistor M21. A first terminal of the transistor M21 outputs a bias current, and a second terminal of the transistor M21 is grounded. In this way, the DC voltage output by the RMS detector 210 provides a bias for the transistor M21, varying the degree of conduction of the transistor M21 and thereby adjusting the intermediate current output by the transistor M21.

[0074] Figure 11 and Figure 12 1 is a schematic diagram of a circuit connection structure of an optional bias circuit 100 and an amplifier 200 provided in an embodiment of the present disclosure. Figure 11 and Figure 12 The structure of the current copy module 30 is illustrated in more detail. Figure 11 and Figure 12 The intermediate coupling module 10 and the DC conversion module 20 can be understood with reference to the above embodiments and will not be described in detail here. Figure 11 and Figure 12 The transistor M31 is the input transistor of the second current mirror 31, and the transistor M32 is the output transistor of the second current mirror 31. It should be noted that the current amplification ratio of the second current mirror 31 can be adjusted by adjusting parameters such as the width-to-length ratio (W / L) of the transistors M31 and M32.

[0075] In some embodiments of the present disclosure, reference Figure 11The current copy module 30 includes a second current mirror 31 and a fifth resistor R5. The input of the second current mirror 31 receives the intermediate current, and the output of the second current mirror 31 passes the bias current of the output mirror. As the amplitude of the input signal increases, the magnitude of the intermediate current increases, and the magnitude of the bias current also increases. This increases the operating current swing of the amplifier 200 and improves the linearity of the amplifier 200.

[0076] In the embodiments of the present disclosure, reference Figure 11 , the fifth resistor R5 is located between the output end of the second current mirror 31 and the input end of the bipolar transistor Q1. In this solution, the resistance setting of the fifth resistor R5 is relatively free and is not limited by the mirror ratio of the second current mirror 31. Therefore, the resistance of the fifth resistor R5 can be greater than 10kΩ. In this way, when the input signal is a small signal, the bias circuit 100 of the embodiment of the present disclosure can prevent the input signal from being bypassed to the ground at the output end of the bias circuit 100, and can effectively prevent the current of the bipolar transistor Q1 from leaking through the bias circuit 100, avoiding input signal loss, and thus improving the noise performance of the amplifier 200. In addition, there is a DC conversion module between the transistor M31 and the ground, which can also reduce current leakage.

[0077] In other embodiments of the present disclosure, Figure 12 The current copy module 30 also includes a fourth transistor M4 and a sixth resistor R6. The output end of the second current mirror 31 is connected to the first end of the fourth transistor M4, the first end of the fifth resistor R5, and the first end of the sixth resistor R6, respectively. The second end of the fourth transistor M4 is grounded. The control end of the fourth transistor M4 is connected to the second end of the sixth resistor R6. The second end of the fifth resistor R5 is connected to the control end of the bipolar transistor Q1. In this way, as the amplitude of the input signal increases, the magnitude of the intermediate current increases, and the magnitude of the bias current increases. This increases the output swing of the amplifier 200 and improves the linearity of the amplifier 200. At the same time, the fifth resistor R5 and the sixth resistor R6 can shunt the bias current. The current copy module 30 can adjust the bias current by adjusting the ratio of the fifth resistor R5 to the sixth resistor R6. In addition, the fourth transistor M4 is connected in series to the output end of the transistor M32 of the second current mirror 31, increasing the output impedance of the second current mirror 31 and providing the second current mirror 31 with better constant current characteristics.

[0078] In some embodiments of the present disclosure, reference Figure 12 The ratio of the fifth resistor R5 to the sixth resistor R6 is inversely proportional to the amplification factor of the second current mirror 31. In this way, the present disclosure can further improve the amplification factor of the second current mirror 31 by adjusting the resistance ratio of the fifth resistor R5 to the sixth resistor R6.

[0079] It should be noted that the ratio of the sixth resistor R6 to the fifth resistor R5 can be less than 20. The resistance value of the fifth resistor R5 can be designed according to actual needs. For example, the fifth resistor R5 can be in the order of kilo-ohms. In this way, when the input signal is a small signal, the bias circuit 100 of the embodiment of the present disclosure can prevent the input signal from being bypassed to the ground at the output end of the bias circuit 100, and can effectively prevent the current of the bipolar transistor Q1 from leaking through the bias circuit 100, thereby avoiding input signal loss and improving the noise performance of the amplifier 200. In addition, a DC conversion module is provided between the transistor M31 and the ground, which can also reduce current leakage.

[0080] Figure 13 This is a schematic diagram of an optional intermediate current and bias current provided by an embodiment of the present disclosure. It should be noted that: Figure 13 L4 is a curve showing the variation of bias current and power of input signal, and L5 is a curve showing the variation of intermediate current and power of input signal.

[0081] In the embodiment of the present disclosure, Figure 13 As shown, as the power of the input signal increases, the power of the input signal gradually increases, and the intermediate current output by the DC conversion module 20 gradually increases as shown by L5. In other words, as the power of the input signal increases, the amplitude (voltage value) of the input signal increases, the amplitude of the output signal increases, and the amplitude of the sampled voltage increases. Consequently, the intermediate current is positively correlated with the sampled voltage, and the magnitude of the intermediate current also increases.

[0082] In the embodiment of the present disclosure, Figure 13 As shown, as the input signal power increases, the input signal amplitude gradually increases, and the bias current output by current copy module 30 gradually increases as shown by L4. Thus, as the input signal amplitude (voltage) increases, the intermediate current increases, and the bias current also increases. The operating current of bipolar transistor Q1 in amplifier 200 is positively correlated with the bias current. As the input signal swing increases, the operating current swing of bipolar transistor Q1 also increases, improving the linearity of amplifier 200.

[0083] Figure 13 The slope of the L4-L6 region is greater than that of the other regions; the slope of the L5-L7 region is greater than that of the other regions, indicating that the bias circuit's adaptive sensitivity is higher when the input signal power is within this range. The larger slope of L4 than that of L5 indicates that the second current mirror has a larger mirror ratio, amplifying the intermediate current during mirroring and improving the adaptive sensitivity.

[0084] Figure 14 This is a schematic diagram of an optional power amplifier circuit provided by an embodiment of the present disclosure, with reference to Figure 14The present disclosure further provides a power amplifier circuit 300. The power amplifier circuit 300 includes a bipolar transistor Q1 and the bias circuit 100 described in the above embodiment. The bipolar transistor Q1 is an amplifying transistor of the power amplifier circuit 300. The control terminal of the bipolar transistor Q1 is connected to the output terminal of the bias circuit and receives the bias current output by the bias circuit 100.

[0085] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0086] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0087] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. An adaptive bias circuit, characterized in that: Applied to an amplifier, the amplifier comprising a bipolar transistor; The bias circuit comprises: a coupling module, connected to the output terminal of the amplifier, and configured to sample the voltage of the output terminal of the amplifier to generate a sampling voltage, wherein the sampling voltage is an AC voltage; a DC conversion module, connected to the output end of the coupling module, configured to receive the sampled voltage and convert the sampled voltage into a DC intermediate current; wherein the intermediate current is positively correlated with the sampled voltage; a current copy module, connected to the bipolar transistor and the DC conversion module, respectively, configured to receive the intermediate current, copy the intermediate current in proportion to a bias current, and output the bias current to the input terminal of the bipolar transistor; The DC conversion module includes: a first voltage dividing element, a second voltage dividing element, and a first capacitor, wherein the first voltage dividing element, the second voltage dividing element, and the first capacitor are sequentially connected in series between an output terminal of the coupling module and a ground, and the first capacitor is grounded; a tail current generating unit configured to generate a stable tail current; a first transistor, a second transistor, and a third transistor, wherein the control end of the first transistor is connected to a node between the coupling module and the first voltage divider; the control end of the second transistor is connected to a node between the first voltage divider and the second voltage divider; the control end of the third transistor is connected to a node between the second voltage divider and the first capacitor; the first ends of the first transistor, the second transistor, and the third transistor are all connected to the output end of the tail current generating unit for receiving the tail current; and the second end of the first transistor and the second end of the third transistor are connected together for outputting the intermediate current.

2. The bias circuit according to claim 1, wherein: The first voltage dividing element and the second voltage dividing element are both resistors; or, The first voltage dividing element and the second voltage dividing element are both capacitors, and the control terminals of the first transistor, the second transistor and the third transistor are further connected to a second bias current.

3. The bias circuit according to claim 2, wherein: The DC conversion module further includes: a third resistor, a fourth resistor and a second capacitor; wherein, The first end of the second transistor is connected to the first end of the third resistor and the first end of the second capacitor respectively; the second end of the third resistor is connected to the power supply end; The first end of the first transistor and the first end of the third transistor are both connected to the first end of the fourth resistor and the second end of the second capacitor; the second end of the fourth resistor is connected to the current copy module for outputting the intermediate current.

4. The bias circuit according to claim 1, wherein: The tail current generating unit includes: a first current mirror and / or a current source.

5. The bias circuit according to claim 1, wherein: The DC conversion module includes: a root mean square detector connected to the output end of the coupling module, configured to receive the sampled voltage, convert the sampled voltage into a DC voltage, and output the DC voltage; The voltage-to-current unit is connected to the output end of the root mean square detector and is configured to receive the DC voltage and convert the DC voltage into the intermediate current.

6. The bias circuit according to claim 1, wherein: The coupling module is a directional coupler; or, The coupling module includes: a third voltage dividing element and a fourth voltage dividing element; wherein, The third voltage dividing element and the fourth voltage dividing element are connected in series between the output terminal of the amplifier and the ground, and a connection node between the third voltage dividing element and the fourth voltage dividing element outputs the sampling voltage.

7. The bias circuit according to claim 6, wherein: The third voltage dividing element and the fourth voltage dividing element are both resistors; or the third voltage dividing element and the fourth voltage dividing element are both capacitors.

8. The bias circuit according to claim 7, wherein: The resistance values ​​of the third voltage dividing element and the fourth voltage dividing element are both greater than 10 kilo-ohms.

9. The bias circuit according to claim 1, wherein: The current copy module includes: a second current mirror, wherein the input terminal receives the intermediate current and the output terminal outputs the bias current; a fifth resistor, located between the output terminal of the second current mirror and the input terminal of the bipolar transistor; and a resistance value of the fifth resistor is greater than 10 kilo-ohms.

10. The bias circuit according to claim 9, wherein: The current copy module further includes: a fourth transistor and a sixth resistor; wherein, The output end of the second current mirror is further connected to the first end of the fourth transistor, the first end of the fifth resistor, and the first end of the sixth resistor respectively; The second end of the fourth transistor is grounded; the control end of the fourth transistor is connected to the second end of the sixth resistor; The second end of the fifth resistor is connected to the input end of the bipolar transistor.

11. The bias circuit according to claim 10, wherein: The ratio of the fifth resistor to the sixth resistor is inversely proportional to the amplification factor of the second current mirror.

12. The bias circuit according to claim 1, wherein: The bipolar transistor is a heterojunction bipolar transistor; and the amplifier is a class AB driver amplifier or a class B driver amplifier.

13. A power amplifier circuit, characterized in that: include: A bipolar transistor and a bias circuit according to any one of claims 1 to 12; wherein, The control terminal of the bipolar transistor receives the bias current output by the bias circuit.

Images