An automatic frequency detection circuit and method based on COT architecture DCDC

Abstract

This invention discloses an automatic frequency detection circuit and method based on a COT architecture DC-DC converter (DC-DC). The circuit comprises a detection time generator circuit (DET_TIMER), an FPWM duration generator circuit (FPWM_TIMER), and a detection logic circuit (DET_LOGIC). The circuit uses a signal HSON as frequency information input and a signal RCP as a timing start signal. After detection is complete, the circuit outputs a signal FPWM_EN to the ZCD module, disabling the zero-crossing limit and placing the DC-DC converter system in FPWM mode. This method detects frequency changes in real time without sampling the output current or voltage information.

Description

Technical Field

[0001] The present invention relates to a frequency detection circuit and method, in particular to an automatic frequency detection circuit and method based on a COT architecture DCDC, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] With the continued growth of electronic products in consumer, industrial, and automotive electronics, demand for power management ICs continues to rise. For example, DC-DC switching power supplies are widely used. Simultaneously, as the load and power of electronic devices increase, the demand for high-voltage, high-current DC-DC converters is also increasing. Further increasing the input voltage requires a further reduction in the duty cycle, which is typically achieved through a COT control method. This method reduces the frequency as the input voltage rises, thus meeting the extremely low duty cycle requirement.

[0003] The traditional COT control method of DC-DC switching power supply has a fast dynamic response speed, but when switching from heavy load to light load, it is limited by the fixed on-time. The frequency is very low under light load, and the inductor current regulation is slow, which leads to slow output voltage regulation. There are several main ways to optimize the dynamic performance, and the key is to introduce the information of the inductor current change through the loop for adaptive adjustment. One is to change the fixed on-time, such as Figure 1 As shown in Figure 1, the first approach uses an AOT structure for regulation; the second approach uses sampled inductor current information to adjust the PWM signal. All of these optimization methods allow the switching frequency to change slowly when the output voltage or load current changes suddenly, thereby improving dynamic response speed.

[0004] However, the problem with adaptive frequency regulation is that it requires the use of inductor current signals for feedback. First, there is a speed delay in sampling, and second, there is also a delay in the feedback loop, which makes it impossible to provide feedback and adjust the sudden change in time. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an automatic frequency detection circuit and method based on COT architecture DCDC, which can detect frequency changes in real time without sampling output current and voltage information.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] An automatic frequency detection circuit based on a COT architecture DC-DC converter (DC-CDC) comprises a detection time generation circuit DET_TIMER, an FPWM duration generation circuit FPWM_TIMER, and a detection logic circuit DET_LOGIC. The detection time generation circuit DET_TIMER measures time T_DET. The detection logic circuit DET_LOGIC detects whether N cycles are exceeded within the time T_DET. If so, the detection time generation circuit DET_TIMER is reset. If not, the FPWM duration generation circuit FPWM_TIMER is started. After receiving a start signal, the FPWM duration generation circuit FPWM_TIMER starts measuring time T_FPWM and outputs a signal FPWM_EN to a ZCD module within the time T_FPWM to disable zero-crossing restriction, so that the DC-CDC system enters FPWM mode.

[0008] Furthermore, the detection time generation circuit DET_TIMER includes a current source IDET, a detection capacitor CDET, an NMOS transistor NM1, an NMOS transistor NM2 and a Schmitt trigger SMIT1. The positive electrode of the current source IDET is connected to the power supply AVDD, the negative electrode of the current source IDET is connected to the input end of the Schmitt trigger SMIT1, one end of the detection capacitor CDET, the drain of the NMOS transistor NM1 and the drain of the NMOS transistor NM2 to generate a signal VC_DET, the gate of the NMOS transistor NM1 is connected to the signal TIME_OUT_CLRB, the gate of the NMOS transistor NM2 is connected to the signal TIMER_START, the source of the NMOS transistor NM1, the source of the NMOS transistor NM2 and the other end of the detection capacitor CDET are grounded, and the output end of the Schmitt trigger SMIT1 outputs the signal TIMER_OUT.

[0009] Furthermore, the FPWM duration generation circuit FPWM_TIMER includes a current source IEXT, a charging capacitor CEXT, an NMOS tube NM3, an NMOS tube NM4, a PMOS tube PM1, a Schmitt trigger SMIT2 and a NOT gate INV4, the positive electrode of the current source IEXT and the source electrode of the PMOS tube PM1 are connected to the power supply AVDD, the negative electrode of the current source IEXT is connected to the drain electrode of the NMOS tube NM4, the gate electrode of the NMOS tube NM4 and the gate electrode of the PMOS tube PM1 are connected to the signal TFPWM_START, NM The source of the OS transistor NM4 is connected to the drain of the PMOS transistor PM1, the input end of the Schmitt trigger SMIT2, one end of the charging capacitor CEXT, and the drain of the NMOS transistor NM3 to generate a signal VC_EXT. The gate of the NMOS transistor NM3 is connected to the signal TFPWM_CLR. The source of the NMOS transistor NM3 and the other end of the charging capacitor CEXT are grounded. The output end of the Schmitt trigger SMIT2 is connected to the input end of the inverter INV4 and outputs a signal FPWM_EN. The output end of the inverter INV4 outputs a signal FPWM_ENB.

[0010] Furthermore, the detection logic circuit DET_LOGIC includes an AND gate AND1, an AND gate AND3, D flip-flops DFF1 to DFFN, an N-1 input AND gate AND4, an INVERT gate INV1, an INVERT gate INV2, an INVERT gate INV3, an OR gate OR1, a pulse generator OS1, a pulse generator OS2, a pulse generator OS3, a three-input AND gate AND2, a D flip-flop DFF_CO and a D flip-flop DFF_TS, the first input end of the AND gate AND1 is connected to the signal HSON, the second input end of the AND gate AND1 is connected to the signal COUNT_OVERB, the output end of the AND gate AND1 is connected to the CK end of the D flip-flop DFF1, and the nth D flip-flop among the D flip-flops DFF1 to DFFN DFFn, n=2, 3, ..., N, the Q terminal of the D flip-flop DFF1 generates a signal Q1, the QN terminal of the D flip-flop DFFn-1 is connected to the D terminal of the D flip-flop DFFn-1 and the CK terminal of the D flip-flop DFFn, the Q terminals of the D flip-flops DFF2 to DFFN are sequentially connected to the N-1 input terminals of the N-1 input AND gate AND4, the output terminal of the N-1 input AND gate AND4 is connected to the input terminal of the inverter INV1 and the CK terminal of the D flip-flop DFF_CO and generates a signal COUNT_OVER, the output terminal of the inverter INV1 outputs the signal COUNT_OVERB, the first input terminal of the AND gate AND3 is connected to the signal COUNT_OVERB, and the second input terminal of the AND gate AND3 is connected to the N-1 input terminals of the N-1 input AND gate AND4. The output of the AND gate AND3 is connected to the first input of the three-input AND gate AND2, the input of the pulse generator OS1 is connected to the signal TIMER_OUT, the output of the pulse generator OS1 is connected to the input of the inverter INV2 and generates the signal TIME_OUT_CLRB, the output of the inverter INV2 is connected to the second input of the three-input AND gate AND2 and generates the signal TIME_OUT_CLR, the first input of the OR gate OR1 is connected to the signal FPWM_ENB, the second input of the OR gate OR1 is connected to the signal Q1, the output of the OR gate OR1 is connected to the input of the pulse generator OS2, the output of the pulse generator OS2 is connected to the input of the inverter INV3 and generates signal TIMER_START, the output of the invertor INV3 is connected to the third input of the three-input AND gate AND2 and the RN of the D flip-flop DFF_CO to generate the signal RESET1_B, the output of the three-input AND gate AND2 is connected to the RN of the D flip-flops DFF1 to DFFN to generate the signal RESET2_B, the QN of the D flip-flop DFF_CO is connected to the D of the D flip-flop DFF_CO, the Q of the D flip-flop DFF_CO is connected to the RN of the D flip-flop DFF_TS, the CK of the D flip-flop DFF_TS is connected to the signal RCP, and the Q of the D flip-flop DFF_TS is connected to the input of the pulse generator OS3 to generate the signal TFPWM_START.The output end of OS3 generates the signal TFPWM_CLR, and the SN ends of the D flip-flops DFF1 to DFFN, the SN end of the D flip-flop DFF_CO, the SN end of the D flip-flop DFF_TS, and the D end of the D flip-flop DFF_TS are connected to the power supply AVDD.

[0011] Furthermore, the signal HSON is output by the LOGIC module.

[0012] Furthermore, the signal RCP is output by the ZCD module.

[0013] A detection method for an automatic frequency detection circuit based on a COT architecture DCDC includes the following steps:

[0014] In the detection time generation circuit DET_TIMER, when the first cycle arrives, the signal TIMER_START inputs a narrow pulse signal that turns high. The NMOS transistor NM2 turns on and discharges the residual charge on the detection capacitor CDET to the ground. Then the NMOS transistor NM2 is turned off to ensure that the timing start signal VC_DET is 0. At this time, the current of the current source IDET flows to the detection capacitor CDET to charge the detection capacitor CDET. The signal VC_DET begins to gradually increase. After the time T_DET, the signal TIMER_OUT turns high and returns to the detection logic circuit DET_LOGIC. After the detection, the detection logic circuit DET_LOGIC returns the signal TIME_OUT_CLRB, pulls the signal VC_DET low, and the signal TIMER_OUT is also pulled low.

[0015] In the FPWM duration generation circuit FPWM_TIMER, when the signal TFPWM_START turns high, the signal VC_EXT is pulled low when the signal TFPWM_CLR turns high. Then, because the signal TFPWM_START is high, the PMOS tube PM1 is turned off, the NMOS tube NM4 is turned on, and the current of the current source IEXT flows to the charging capacitor CEXT and charges the charging capacitor CEXT. The signal VC_EXT on the upper plate of the charging capacitor CEXT begins to gradually increase. After the time T_FPWM, the signal FPWM_EN turns high and is output to the ZCD module to control the FPWM mode; the signal FPWM_ENB turns low and returns to the detection logic circuit DET_LOGIC;

[0016] In the detection logic circuit DET_LOGIC, when the signal HSON turns high, since the signal COUNT_OVERB is initially high, the output signal of the AND gate AND1 turns high. After the CK terminal of the D flip-flop DFF1 turns high, since the D terminal of the D flip-flop DFF1 is connected to the QN terminal and the initial value is high, the signal Q1 turns high. At this time, the output signal of the OR gate OR1 turns high. After the pulse generator OS2 pulse processing, the output signal TIMER_START is a narrow pulse high signal. The narrow pulse of the signal TIMER_START is output to the detection time generation circuit DET_T IMER, after the timing time T_DET, the signal TIMER_OUT turns high; if the signal COUNT_OVER turns high during this period, it means that the frequency of the signal HSON is high; if the signal COUNT_OVER does not turn high, it means that the frequency of the signal HSON is low, then the signals TFPWM_START and TFPWM_CLR turn high and are output to the FPWM duration generation circuit FPWM_TIMER. After the timing time T_FPWM, the signal FPWM_EN is output to the ZCD module to control the DCDC system to enter the FPWM mode within the time T_FPWM.

[0017] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides an automatic frequency detection circuit and method based on a COT architecture DCDC, which does not require sampling of output current and voltage information and can detect frequency changes in real time; when the load current suddenly changes and the DCDC system enters DCM from CCM, the frequency change can be detected through the cyclic T_DET time window, and FPWM is turned on in the first cycle of the frequency change, and the T_FPWM time is maintained. After the inductor current is regulated, the system returns to DCM. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of an automatic frequency detection circuit based on a COT architecture DCDC of the present invention.

[0019] Figure 2 4 is a circuit diagram of the detection time generating circuit DET_TIMER of the present invention.

[0020] Figure 3 4 is a circuit diagram of an FPWM duration generating circuit FPWM_TIMER of the present invention.

[0021] Figure 4 1 is a circuit diagram of the detection logic circuit DET_LOGIC of the present invention.

[0022] Figure 5 This is a detection timing diagram of an automatic frequency detection circuit based on a COT architecture DCDC of the present invention.

[0023] Figure 6 FIG. 1 is a schematic diagram of a DCDC system using an automatic frequency detection technology in the prior art. DETAILED DESCRIPTION

[0024] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0025] like Figure 1 As shown, the present invention discloses an automatic frequency detection circuit based on a COT architecture DC-DC system. The circuit comprises a detection time generation circuit DET_TIMER, an FPWM duration generation circuit FPWM_TIMER, and a detection logic circuit DET_LOGIC. The detection time generation circuit DET_TIMER measures time T_DET. The detection logic circuit DET_LOGIC detects whether N cycles have been exceeded within T_DET. If so, the detection time generation circuit DET_TIMER is reset, and the detection time generation circuit DET_TIMER begins the next measurement. If not, the FPWM duration generation circuit FPWM_TIMER is activated. Upon receiving a start signal, the FPWM duration generation circuit FPWM_TIMER begins measuring time T_FPWM and, within T_FPWM, outputs a signal FPWM_EN to the ZCD module to disable the zero-crossing limit, placing the DC-DC system in FPWM mode. The present invention detects frequency changes within the cyclic T_DET time window. When the frequency suddenly decreases due to a heavy load-to-light load transition, the FPWM is activated during the first cycle of the frequency change and maintained for the T_FPWM duration. After the inductor current is regulated, the frequency returns to the low frequency of the light load. The present invention uses the HSON signal output by the system LOGIC as the frequency information input, and uses the RCP signal output by the system zero-crossing detection module ZCD as the timing start signal. After the detection is completed, the FPWM_EN signal is output, the ZCD module of the system is connected, the zero-crossing limit is turned off, and the system enters the FPWM mode.

[0026] like Figure 2As shown, the detection time generation circuit DET_TIMER includes a current source IDET, a detection capacitor CDET, an NMOS transistor NM1, an NMOS transistor NM2 and a Schmitt trigger SMIT1. The positive electrode of the current source IDET is connected to the power supply AVDD, the negative electrode of the current source IDET is connected to the input end of the Schmitt trigger SMIT1, one end of the detection capacitor CDET, the drain of the NMOS transistor NM1 and the drain of the NMOS transistor NM2 to generate a signal VC_DET, the gate of the NMOS transistor NM1 is connected to the signal TIME_OUT_CLRB, the gate of the NMOS transistor NM2 is connected to the signal TIMER_START, the source of the NMOS transistor NM1, the source of the NMOS transistor NM2 and the other end of the detection capacitor CDET are grounded, and the output end of the Schmitt trigger SMIT1 outputs the signal TIMER_OUT.

[0027] like Figure 3 As shown, the FPWM duration generating circuit FPWM_TIMER includes a current source IEXT, a charging capacitor CEXT, an NMOS transistor NM3, an NMOS transistor NM4, a PMOS transistor PM1, a Schmitt trigger SMIT2 and an inverter INV4. The positive electrode of the current source IEXT and the source electrode of the PMOS transistor PM1 are connected to the power supply AVDD, the negative electrode of the current source IEXT is connected to the drain electrode of the NMOS transistor NM4, the gate electrode of the NMOS transistor NM4 and the gate electrode of the PMOS transistor PM1 are connected to the signal TFPWM_START, and the NMOS transistor The source of transistor NM4 is connected to the drain of PMOS transistor PM1, the input terminal of Schmitt trigger SMIT2, one end of charging capacitor CEXT, and the drain of NMOS transistor NM3 to generate signal VC_EXT. The gate of NMOS transistor NM3 is connected to signal TFPWM_CLR. The source of NMOS transistor NM3 and the other end of charging capacitor CEXT are grounded. The output terminal of Schmitt trigger SMIT2 is connected to the input terminal of inverter INV4 and outputs signal FPWM_EN. The output terminal of inverter INV4 outputs signal FPWM_ENB.

[0028] like Figure 4As shown, the detection logic circuit DET_LOGIC includes AND gates AND1, AND gates AND3, D flip-flops DFF1~DFFN, N-1-input AND gates AND4, NOT gates INV1, INV2, INV3, OR gate OR1, pulse generators OS1, OS2, OS3, three-input AND gates AND2, D flip-flops DFF_CO and D flip-flops DFF_TS, the first input terminal of AND gate AND1 is connected to the signal HSON, the second input terminal of AND gate AND1 is connected to the signal COUNT_OVERB, the output terminal of AND gate AND1 is connected to the CK terminal of D flip-flop DFF1, and the nth D flip-flop DFF among the D flip-flops DFF1~DFFN is connected. n, n=2, 3, ..., N, the Q terminal of the D flip-flop DFF1 generates the signal Q1, the QN terminal of the D flip-flop DFFn-1 is connected to the D terminal of the D flip-flop DFFn-1 and the CK terminal of the D flip-flop DFFn, the Q terminals of the D flip-flops DFF2 to DFFN are sequentially connected to the N-1 input terminals of the N-1 input AND gate AND4, the output terminal of the N-1 input AND gate AND4 is connected to the input terminal of the inverter INV1 and the CK terminal of the D flip-flop DFF_CO and generates the signal COUNT_OVER, the output terminal of the inverter INV1 outputs the signal COUNT_OVERB, the first input terminal of the AND gate AND3 is connected to the signal COUNT_OVERB, and the second input terminal of the AND gate AND3 is connected to the signal COUNT_OVERB. The output of the AND gate AND3 is connected to the first input of the three-input AND gate AND2, the input of the pulse generator OS1 is connected to the signal TIMER_OUT, the output of the pulse generator OS1 is connected to the input of the inverter INV2 and generates the signal TIME_OUT_CLRB, the output of the inverter INV2 is connected to the second input of the three-input AND gate AND2 and generates the signal TIME_OUT_CLR, the first input of the OR gate OR1 is connected to the signal FPWM_ENB, the second input of the OR gate OR1 is connected to the signal Q1, the output of the OR gate OR1 is connected to the input of the pulse generator OS2, the output of the pulse generator OS2 is connected to the input of the inverter INV3 and generates the signal Signal TIMER_START, the output end of the invertor INV3 is connected to the third input end of the three-input AND gate AND2 and the RN end of the D flip-flop DFF_CO to generate the signal RESET1_B, the output end of the three-input AND gate AND2 is connected to the RN ends of the D flip-flops DFF1 to DFFN to generate the signal RESET2_B, the QN end of the D flip-flop DFF_CO is connected to the D end of the D flip-flop DFF_CO, the Q end of the D flip-flop DFF_CO is connected to the RN end of the D flip-flop DFF_TS, the CK end of the D flip-flop DFF_TS is connected to the signal RCP, and the Q end of the D flip-flop DFF_TS is connected to the input end of the pulse generator OS3 to generate the signal TFPWM_START.The output end of OS3 generates the signal TFPWM_CLR, and the SN ends of the D flip-flops DFF1 to DFFN, the SN end of the D flip-flop DFF_CO, the SN end of the D flip-flop DFF_TS, and the D end of the D flip-flop DFF_TS are connected to the power supply AVDD.

[0029] The signal HSON is output by the LOGIC module, and the signal RCP is output by the ZCD module.

[0030] A detection method for an automatic frequency detection circuit based on a COT architecture DCDC includes the following steps:

[0031] In the detection time generation circuit DET_TIMER, when the first cycle arrives, the signal TIMER_START inputs a narrow pulse signal that turns high. The NMOS transistor NM2 turns on and discharges the residual charge on the detection capacitor CDET to ground. Then the NMOS transistor NM2 turns off, ensuring that the timing start signal VC_DET is 0. At this time, the current of the current source IDET flows to the detection capacitor CDET to charge the detection capacitor CDET. The signal VC_DET begins to gradually increase. After time T_DET, the signal TIMER_OUT turns high and returns to the detection logic circuit DET_LOGIC. After detection, the detection logic circuit DET_LOGIC returns the signal TIME_OUT_CLRB, pulls the signal VC_DET low, and the signal TIMER_OUT is also pulled low.

[0032] In the FPWM duration generation circuit FPWM_TIMER, when the signal TFPWM_START turns high, the signal VC_EXT is pulled low when the signal TFPWM_CLR turns high. Then, since the signal TFPWM_START is high, the PMOS tube PM1 is turned off, the NMOS tube NM4 is turned on, and the current of the current source IEXT flows to the charging capacitor CEXT and charges the charging capacitor CEXT. The signal VC_EXT on the top plate of the charging capacitor CEXT begins to gradually increase. After the time T_FPWM, the signal FPWM_EN turns high and is output to the ZCD module for controlling the FPWM mode; the signal FPWM_ENB turns low and is returned to the detection logic circuit DET_LOGIC.

[0033] In the detection logic circuit DET_LOGIC, when the signal HSON turns high, since the signal COUNT_OVERB is initially high, the output signal of the AND gate AND1 turns high. After the CK terminal of the D flip-flop DFF1 turns high, since the D terminal of the D flip-flop DFF1 is connected to the QN terminal and the initial value is high, the signal Q1 turns high. At this time, the output signal of the OR gate OR1 turns high. After the pulse generator OS2 pulse processing, the output signal TIMER_START is a narrow pulse high signal. The narrow pulse of the signal TIMER_START is output to the detection time generation circuit DET_T IMER, after the timing time T_DET, the signal TIMER_OUT turns high; if the signal COUNT_OVER turns high during this period, it means that the frequency of the signal HSON is high; if the signal COUNT_OVER does not turn high, it means that the frequency of the signal HSON is low, then the signals TFPWM_START and TFPWM_CLR turn high and are output to the FPWM duration generation circuit FPWM_TIMER. After the timing time T_FPWM, the signal FPWM_EN is output to the ZCD module to control the DCDC system to enter the FPWM mode within the time T_FPWM.

[0034] like Figure 5 As shown, the frequency of the DCDC system's signal HSON remains high until time t4. Signal Q1 first transitions at time t1, and the detection time generation circuit DET_TIMER begins timing. At time t3, after time T_DET, signal TIMER_OUT transitions high. Simultaneously, signals Q2 and QN are ANDed, and at time t2, signal COUNT_OVER transitions high. This indicates that before time t3, signal HSON maintains a consistently high frequency, preventing T_FPWM timing from starting. The detected frequency result is consistent with the actual frequency of signal HSON. At time t4, signal HSON suddenly drops in frequency. After time T_DET, signal TIMER_OUT transitions high at time t5. During this time, signal COUNT_OVER remains low, indicating a low frequency. At time t6, when signal RCP of the DCDC system transitions high, signal TFPWM_START transitions high. After time T_FPWM, signal TFPWM_START transitions low at time t7, ending timing. The system operates in FPWM mode throughout this process. After time t7, FPWM mode is exited, and the frequency of signal HSON decreases. The value of T_DET, the number of D flip-flops DFFN, and the time T_FPWM can be set according to the actual switching frequency of the application, so that it can be applied to the DCDC system of COT architecture at any frequency.

[0035] The present invention provides an automatic frequency detection circuit and method based on a COT architecture DC-DC system. This circuit and method detect frequency changes in real time without sampling output current and voltage information. When the load current suddenly changes and the DC-DC system switches from CCM to DCM, the frequency change can be detected through a cyclic T_DET time window. FPWM is turned on in the first cycle of the frequency change, and the T_FPWM time is maintained. The system then returns to DCM after the inductor current is regulated.

[0036] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. An automatic frequency detection circuit based on a COT architecture DCDC, characterized by: The system comprises a detection time generation circuit DET_TIMER, an FPWM duration generation circuit FPWM_TIMER and a detection logic circuit DET_LOGIC. The detection time generation circuit DET_TIMER counts the time T_DET. The detection logic circuit DET_LOGIC detects whether N cycles are exceeded within the time T_DET. If exceeded, the detection time generation circuit DET_TIMER is reset. If not exceeded, the FPWM duration generation circuit FPWM_TIMER is started. After receiving a start signal, the FPWM duration generation circuit FPWM_TIMER starts counting the time T_FPWM and outputs a signal FPWM_EN to the ZCD module within the time T_FPWM to turn off the zero-crossing limit and enable the DCDC system to enter the FPWM mode.

2. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The detection time generation circuit DET_TIMER includes a current source IDET, a detection capacitor CDET, an NMOS transistor NM1, an NMOS transistor NM2 and a Schmitt trigger SMIT1. The positive electrode of the current source IDET is connected to the power supply AVDD, the negative electrode of the current source IDET is connected to the input end of the Schmitt trigger SMIT1, one end of the detection capacitor CDET, the drain of the NMOS transistor NM1 and the drain of the NMOS transistor NM2 to generate a signal VC_DET, the gate of the NMOS transistor NM1 is connected to the signal TIME_OUT_CLRB, the gate of the NMOS transistor NM2 is connected to the signal TIMER_START, the source of the NMOS transistor NM1, the source of the NMOS transistor NM2 and the other end of the detection capacitor CDET are grounded, and the output end of the Schmitt trigger SMIT1 outputs the signal TIMER_OUT.

3. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The FPWM duration generating circuit FPWM_TIMER includes a current source IEXT, a charging capacitor CEXT, an NMOS transistor NM3, an NMOS transistor NM4, a PMOS transistor PM1, a Schmitt trigger SMIT2 and an inverter INV4. The positive electrode of the current source IEXT and the source electrode of the PMOS transistor PM1 are connected to the power supply AVDD, the negative electrode of the current source IEXT is connected to the drain electrode of the NMOS transistor NM4, the gate electrode of the NMOS transistor NM4 and the gate electrode of the PMOS transistor PM1 are connected to the signal TFPWM_START, and the NMOS transistor NM4 is connected to the gate electrode of the PMOS transistor PM1. The source of transistor NM4 is connected to the drain of PMOS transistor PM1, the input terminal of Schmitt trigger SMIT2, one end of charging capacitor CEXT, and the drain of NMOS transistor NM3 to generate signal VC_EXT. The gate of NMOS transistor NM3 is connected to signal TFPWM_CLR. The source of NMOS transistor NM3 and the other end of charging capacitor CEXT are grounded. The output terminal of Schmitt trigger SMIT2 is connected to the input terminal of inverter INV4 and outputs signal FPWM_EN. The output terminal of inverter INV4 outputs signal FPWM_ENB.

4. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The detection logic circuit DET_LOGIC includes AND gates AND1, AND gates AND3, D flip-flops DFF1 to DFFN, an N-1-input AND gate AND4, an IN gate INV1, an IN gate INV2, an IN gate INV3, an OR gate OR1, a pulse generator OS1, a pulse generator OS2, a pulse generator OS3, a three-input AND gate AND2, a D flip-flop DFF_CO and a D flip-flop DFF_TS, a first input end of the AND gate AND1 connected to a signal HSON, a second input end of the AND gate AND1 connected to a signal COUNT_OVERB, an output end of the AND gate AND1 connected to a CK end of the D flip-flop DFF1, and an nth D flip-flop DFFn among the D flip-flops DFF1 to DFFN. , n=2, 3, ..., N, the Q terminal of the D flip-flop DFF1 generates the signal Q1, the QN terminal of the D flip-flop DFFn-1 is connected to the D terminal of the D flip-flop DFFn-1 and the CK terminal of the D flip-flop DFFn, the Q terminals of the D flip-flops DFF2 to DFFN are sequentially connected to the N-1 input terminals of the N-1 input AND gate AND4, the output terminal of the N-1 input AND gate AND4 is connected to the input terminal of the inverter INV1 and the CK terminal of the D flip-flop DFF_CO and generates the signal COUNT_OVER, the output terminal of the inverter INV1 outputs the signal COUNT_OVERB, the first input terminal of the AND gate AND3 is connected to the signal COUNT_OVERB, and the second input terminal of the AND gate AND3 is connected to the signal RCP, the output terminal of the AND gate AND3 is connected to the first input terminal of the three-input AND gate AND2, the input terminal of the pulse generator OS1 is connected to the signal TIMER_OUT, the output terminal of the pulse generator OS1 is connected to the input terminal of the inverter INV2 and generates the signal TIME_OUT_CLRB, the output terminal of the inverter INV2 is connected to the second input terminal of the three-input AND gate AND2 and generates the signal TIME_OUT_CLR, the first input terminal of the OR gate OR1 is connected to the signal FPWM_ENB, the second input terminal of the OR gate OR1 is connected to the signal Q1, the output terminal of the OR gate OR1 is connected to the input terminal of the pulse generator OS2, the output terminal of the pulse generator OS2 is connected to the input terminal of the inverter INV3 and generates the signal Signal TIMER_START, the output end of the invertor INV3 is connected to the third input end of the three-input AND gate AND2 and the RN end of the D flip-flop DFF_CO to generate the signal RESET1_B, the output end of the three-input AND gate AND2 is connected to the RN ends of the D flip-flops DFF1 to DFFN to generate the signal RESET2_B, the QN end of the D flip-flop DFF_CO is connected to the D end of the D flip-flop DFF_CO, the Q end of the D flip-flop DFF_CO is connected to the RN end of the D flip-flop DFF_TS, the CK end of the D flip-flop DFF_TS is connected to the signal RCP, and the Q end of the D flip-flop DFF_TS is connected to the input end of the pulse generator OS3 to generate the signal TFPWM_START.The output end of OS3 generates the signal TFPWM_CLR, and the SN ends of the D flip-flops DFF1 to DFFN, the SN end of the D flip-flop DFF_CO, the SN end of the D flip-flop DFF_TS, and the D end of the D flip-flop DFF_TS are connected to the power supply AVDD.

5. The automatic frequency detection circuit based on COT architecture DCDC according to claim 4, characterized in that: The signal HSON is output by the LOGIC module.

6. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The signal RCP is output by the ZCD module.

7. A detection method for an automatic frequency detection circuit based on a COT architecture DCDC according to any one of claims 1 to 6, characterized in that The following steps are involved: In the detection time generation circuit DET_TIMER, when the first cycle arrives, the signal TIMER_START inputs a narrow pulse signal that turns high. The NMOS transistor NM2 turns on and discharges the residual charge on the detection capacitor CDET to the ground. Then the NMOS transistor NM2 is turned off to ensure that the timing start signal VC_DET is 0. At this time, the current of the current source IDET flows to the detection capacitor CDET to charge the detection capacitor CDET. The signal VC_DET begins to gradually increase. After the time T_DET, the signal TIMER_OUT turns high and returns to the detection logic circuit DET_LOGIC. After the detection, the detection logic circuit DET_LOGIC returns the signal TIME_OUT_CLRB, pulls the signal VC_DET low, and the signal TIMER_OUT is also pulled low. In the FPWM duration generation circuit FPWM_TIMER, when the signal TFPWM_START turns high, the signal VC_EXT is pulled low when the signal TFPWM_CLR turns high. Then, because the signal TFPWM_START is high, the PMOS tube PM1 is turned off, the NMOS tube NM4 is turned on, and the current of the current source IEXT flows to the charging capacitor CEXT and charges the charging capacitor CEXT. The signal VC_EXT on the upper plate of the charging capacitor CEXT begins to gradually increase. After the time T_FPWM, the signal FPWM_EN turns high and is output to the ZCD module to control the FPWM mode; the signal FPWM_ENB turns low and returns to the detection logic circuit DET_LOGIC; In the detection logic circuit DET_LOGIC, when the signal HSON turns high, since the signal COUNT_OVERB is initially high, the output signal of the AND gate AND1 turns high. After the CK terminal of the D flip-flop DFF1 turns high, since the D terminal of the D flip-flop DFF1 is connected to the QN terminal and the initial value is high, the signal Q1 turns high. At this time, the output signal of the OR gate OR1 turns high. After the pulse generator OS2 pulse processing, the output signal TIMER_START is a narrow pulse high signal. The narrow pulse of the signal TIMER_START is output to the detection time generation circuit DET_T IMER, after the timing time T_DET, the signal TIMER_OUT turns high; if the signal COUNT_OVER turns high during this period, it means that the frequency of the signal HSON is high; if the signal COUNT_OVER does not turn high, it means that the frequency of the signal HSON is low, then the signals TFPWM_START and TFPWM_CLR turn high and are output to the FPWM duration generation circuit FPWM_TIMER. After the timing time T_FPWM, the signal FPWM_EN is output to the ZCD module to control the DCDC system to enter the FPWM mode within the time T_FPWM.

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