Method for removing silicon substrate in chip based on C2W bonding

Abstract

The invention provides a method for removing a silicon substrate in a chip based on C2W bonding, and belongs to the technical field of electro-optical modulators, and the method specifically comprises the steps that a waveguide core and metal electrodes are sequentially formed on a first substrate, the waveguide core and the metal electrodes are covered with passivation layers, and the metal electrodes are located on the two sides of the waveguide core; opening a hole above the metal electrode to form a hole structure; forming a protective layer in an area corresponding to the metal electrode above the passivation layer, wherein the protective layer covers the metal electrode through the hole structure; preparing a chip, wherein the chip comprises a second substrate, a sacrificial layer, a silicon oxide layer and an electro-optical material layer which are sequentially laminated; bonding an area, corresponding to the waveguide core, above the passivation layer with an electro-optical material layer of the chip; after bonding, removing the second substrate by removing the sacrificial layer; and removing the protective layer. The sacrificial layer is arranged, so that the risk of silicon residue or over-etching of lower silicon oxide does not exist when the silicon substrate is removed, and the modulation performance of the electro-optical material is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electro-optic modulators, and in particular to a method for removing a silicon substrate in a chip based on C2W bonding. Background Art

[0002] Compared with traditional silicon photonics, silicon photonics based on silicon nitride (SiN) materials have many individual advantages such as low loss, wide spectrum, and high optical power. Therefore, SiN has gradually become an important platform for ultra-low loss photonic integration with CMOS compatibility. However, due to the lack of electro-optical properties of SiN, it is difficult to realize active devices such as efficient electro-optical modulators.

[0003] Lithium niobate (LN) crystals are known as the "silicon" in the field of photonics due to their excellent electro-optical, nonlinear optical, acousto-optic and photorefractive properties. However, their etching process is complex and incompatible with CMOS technology, so they are very challenging to mass produce.

[0004] Heterogeneous integration of SiN and thin-film lithium niobate (TFLN) can fully utilize the high light transmittance of SiN as an optical waveguide medium. At the same time, based on the performance advantages of TFLN such as high optoelectronic bandwidth, it can meet the needs of 200Gbps / lane and higher rate applications. Using chip to wafer (C2W) can avoid etching process and achieve compatibility with CMOS process.

[0005] After C2W bonding, the silicon substrate on the chip needs to be removed to ensure the modulation performance of TFLN. The existing technology is to first perform C2W bonding, then form a protective layer to protect the lower wafer, and then use chemical solution corrosion or dry etching to remove the silicon substrate. When TFLN modulates SIN, it is necessary to ensure that the silicon substrate is completely removed without any residue, and the upper silicon oxide cannot be damaged. However, when removing the silicon substrate with the existing technology, there is a risk of silicon residue or over-etching the lower silicon oxide, both of which will affect the modulation performance of TFLN. Summary of the invention

[0006] In view of this, an embodiment of the present application provides a method for removing the silicon substrate in a chip based on C2W bonding, which at least partially solves the problem in the prior art that when removing the silicon substrate, there is a risk of silicon residue or over-etching the underlying silicon oxide, thereby affecting the modulation performance of the TFLN.

[0007] The embodiment of the present application provides a method for removing a silicon substrate in a chip based on C2W bonding, the method comprising:

[0008] forming a waveguide core and a metal electrode in sequence on a first substrate, wherein the waveguide core and the metal electrode are covered with a passivation layer, and the metal electrode is located on both sides of the waveguide core;

[0009] Opening a hole above the metal electrode to form a hole structure;

[0010] forming a protective layer in a region above the passivation layer corresponding to the metal electrode, wherein the protective layer covers the metal electrode through the hole structure;

[0011] preparing a chip, wherein the chip comprises a second substrate, a sacrificial layer, a silicon oxide layer and an electro-optical material layer stacked in sequence;

[0012] Bonding the region above the passivation layer corresponding to the waveguide core to the electro-optical material layer of the chip;

[0013] After bonding, removing the second substrate by removing the sacrificial layer;

[0014] The protective layer is removed.

[0015] According to a specific implementation of the embodiment of the present application, the waveguide core and the metal electrode are sequentially formed on the first substrate, and the waveguide core and the metal electrode are covered with a passivation layer, including:

[0016] forming the waveguide core on the first substrate;

[0017] Depositing the passivation layer to cover the first substrate and the waveguide core;

[0018] Forming metal grooves on both sides of the waveguide core respectively, and forming metal electrodes in the metal grooves;

[0019] The passivation layer is deposited to cover the metal electrode.

[0020] According to a specific implementation of the embodiment of the present application, the chip preparation includes:

[0021] depositing the sacrificial layer on the second substrate;

[0022] depositing the silicon oxide layer on the sacrificial layer;

[0023] Performing ion implantation on the electro-optic material block, wherein the ions penetrate to a preset depth in the electro-optic material block to form an ion implantation layer;

[0024] bonding the electro-optical material block with the ion implantation layer to the silicon oxide layer;

[0025] Heating to peel off the ion implantation layer from the electro-optical material block;

[0026] performing annealing treatment on the stripped ion implantation layer;

[0027] Performing chemical mechanical polishing on the ion implantation layer to form the electro-optical material layer;

[0028] Slicing is performed to complete the preparation of the chip.

[0029] According to a specific implementation of the embodiment of the present application, the chip preparation includes:

[0030] depositing a first sacrificial layer on the second substrate;

[0031] Performing ion implantation on the electro-optic material block, wherein the ions penetrate to a preset depth in the electro-optic material block to form an ion implantation layer;

[0032] depositing the silicon oxide layer on the ion implantation layer;

[0033] depositing a second sacrificial layer on the silicon oxide layer;

[0034] Bonding the first sacrificial layer and the second sacrificial layer at a preset heating temperature, and peeling the ion implantation layer from the electro-optical material block, so that the bonded first sacrificial layer and the second sacrificial layer form the sacrificial layer;

[0035] performing annealing treatment on the stripped ion implantation layer;

[0036] Performing chemical mechanical polishing on the ion implantation layer to form the electro-optical material layer;

[0037] Slicing is performed to complete the preparation of the chip.

[0038] According to a specific implementation of the embodiment of the present application, the method further includes:

[0039] Before bonding, etching the first sacrificial layer to form a plurality of first through holes, one end of the first through hole being connected to the second substrate;

[0040] Etching the second sacrificial layer to form second through holes, one end of the second through holes being connected to the silicon oxide layer, the number of the second through holes being the same as the number of the first through holes, and the positions of the second through holes and the first through holes corresponding to each other one by one;

[0041] The first sacrificial layer and the second sacrificial layer are bonded at a preset heating temperature, and after bonding, the other end of the first through hole is connected to the other end of the second through hole.

[0042] According to a specific implementation of the embodiment of the present application, bonding the area above the passivation layer corresponding to the waveguide core to the electro-optical material layer of the chip includes:

[0043] Sequentially cleaning and plasma activating the area above the passivation layer corresponding to the waveguide core and the chip;

[0044] Pre-bonding the region above the passivation layer corresponding to the waveguide core and the electro-optical material layer at room temperature to form a pre-bonded device;

[0045] The pre-bonded device is annealed at 50-300° C. for 1-12 hours to complete the bonding.

[0046] According to a specific implementation of the embodiment of the present application, removing the second substrate by removing the sacrificial layer after the bonding includes:

[0047] After bonding, the sacrificial layer is removed by wet etching using a first chemical solution, and the second substrate is removed at the same time, wherein the first chemical solution is set to be an acid etching solution.

[0048] According to a specific implementation of the embodiment of the present application, removing the protective layer includes:

[0049] The protective layer is removed by soaking in a second chemical liquid, wherein the second chemical liquid is N-methylpyrrolidone or acetone.

[0050] According to a specific implementation of the embodiment of the present application, the method further includes:

[0051] The second substrate is etched to form a plurality of third through holes, one end of each of the third through holes being connected to the sacrificial layer.

[0052] According to a specific implementation of the embodiment of the present application, the thickness of the sacrificial layer is set to 1-5 μm.

[0053] Beneficial effects:

[0054] The method for removing the silicon substrate in a chip based on C2W bonding in an embodiment of the present application introduces a sacrificial layer into the structure of the chip. The silicon substrate can be removed simultaneously during the process of removing the sacrificial layer after bonding. Therefore, there is no risk of silicon residue or over-etching of the underlying silicon oxide, thereby improving the modulation performance of the electro-optical material. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 A schematic diagram of a process of removing a silicon substrate from a chip based on C2W bonding according to an embodiment of the present invention;

[0057] Figure 2 A schematic diagram of forming a protective layer according to an embodiment of the present invention;

[0058] Figure 3 is a bonding schematic diagram according to an embodiment of the present invention;

[0059] Figure 4 is a schematic diagram of removing a silicon substrate according to an embodiment of the present invention;

[0060] Figure 5 is a schematic diagram of removing a protective layer according to an embodiment of the present invention;

[0061] Figure 6 A schematic diagram of forming a sacrificial layer and a silicon oxide layer according to an embodiment of the present invention;

[0062] Figure 7 A schematic diagram of forming an ion implantation layer according to an embodiment of the present invention;

[0063] Figure 8 A schematic diagram of bonding an electro-optical material to silicon oxide according to an embodiment of the present invention;

[0064] Fig. 9 is a schematic diagram of ion implantation layer stripping according to an embodiment of the present invention;

[0065] Fig.10 A schematic diagram of forming a first sacrificial layer according to an embodiment of the present invention;

[0066] Fig.11 A schematic diagram of forming a second sacrificial layer according to an embodiment of the present invention;

[0067] Fig.12 A schematic diagram of bonding a first sacrificial layer and a second sacrificial layer according to an embodiment of the present invention;

[0068] Fig.13 is another bonding schematic diagram according to an embodiment of the present invention;

[0069] Fig.14 A schematic diagram of forming a third through hole according to an embodiment of the present invention;

[0070] Fig.15 A schematic diagram of forming a first through hole according to an embodiment of the present invention;

[0071] Fig.16 A schematic diagram of forming a second through hole according to an embodiment of the present invention;

[0072] Fig.17 FIG. 4 is another schematic diagram of bonding the first sacrificial layer and the second sacrificial layer according to an embodiment of the present invention.

[0073] In the figure: 10, first substrate; 11, metal electrode; 12, waveguide core; 13, electro-optic material layer; 14, silicon oxide layer; 15, second substrate; 16, protective layer; 17, sacrificial layer; 18, electro-optic material block; 19, hole structure; 20, first sacrificial layer; 21, second sacrificial layer; 22, third through hole; 23, first through hole; 24, second through hole. DETAILED DESCRIPTION

[0074] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0075] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0076] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0077] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0078] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0079] The present application embodiment provides a method for removing silicon substrate from a chip based on C2W bonding. Figures 1 to 17 Describe in detail.

[0080] Reference Figure 1 This embodiment provides a method for removing a silicon substrate from a chip based on C2W bonding, the method comprising:

[0081] Step S101, forming a waveguide core 12 and a metal electrode 11 in sequence on a first substrate 10, wherein the waveguide core 12 and the metal electrode 11 are covered with a passivation layer, and the metal electrode 11 is located on both sides of the waveguide core 12;

[0082] Step S102, opening a hole above the metal electrode 11 to form a hole structure 19;

[0083] Step S103, forming a protective layer 16 in a region above the passivation layer corresponding to the metal electrode 11, wherein the protective layer 16 covers the metal electrode 11 through the hole structure 19, referring to Figure 2 ;

[0084] Step S104, preparing a chip, wherein the chip includes a second substrate 15, a sacrificial layer 17, a silicon oxide layer 14 and an electro-optical material layer 13 stacked in sequence;

[0085] Step S105: Bond the region above the passivation layer corresponding to the waveguide core 12 to the electro-optical material layer 13 of the chip, referring to Figure 3 ;

[0086] Step S106: After bonding, the second substrate 15 is removed by removing the sacrificial layer 17. Figure 4 ;

[0087] Step S107: removing the protective layer 16, referring to Figure 5 .

[0088] In a specific implementation, the first substrate 10 is generally configured as a wafer substrate, and the second substrate 15 in the chip is generally configured as a silicon substrate.

[0089] In this embodiment, by introducing a sacrificial layer 17 into the structure of the chip, the silicon substrate can be removed simultaneously during the process of removing the sacrificial layer 17 after bonding. Therefore, there is no risk of silicon residue or over-etching of the underlying silicon oxide, thereby improving the modulation performance of the electro-optical material.

[0090] In addition, by forming a protective layer 16 before C2W bonding and then removing the silicon substrate, there is no step on the wafer before bonding, and the glue layer (protective layer 16) is evenly spread by a glue spreader, and no bubbles or other undesirable phenomena will occur; there is no need to use a glue sprayer, which improves the utilization rate of the photoresist and reduces the cost of device preparation. At the same time, there is no step on the wafer before bonding, and only one photolithography is required, which shortens the time and reduces the cost. There is no need to consider the impact of the overlay accuracy on the product; there is no need to use a double-sided exposure machine, which reduces the cost.

[0091] In one embodiment, the waveguide core 12 and the metal electrode 11 are sequentially formed on the first substrate 10, and the waveguide core 12 and the metal electrode 11 are covered with a passivation layer, including:

[0092] forming the waveguide core 12 on the first substrate 10;

[0093] Depositing the passivation layer to cover the first substrate 10 and the waveguide core 12;

[0094] Metal grooves are formed on both sides of the waveguide core 12, and metal electrodes 11 are formed in the metal grooves;

[0095] The passivation layer is deposited to cover the metal electrode 11 .

[0096] In a specific implementation, a waveguide core 12 is formed on a first substrate 10, wherein the first substrate 10 is set as a wafer substrate. The waveguide core 12 is formed on the substrate, including:

[0097] depositing a waveguide layer on the substrate;

[0098] The waveguide layer is etched to form the waveguide core 12 .

[0099] In specific implementation, the passivation layer can be set to silicon oxide, and the material of the waveguide core 12 can be set to silicon nitride (SiN). The silicon photonics technology of SiN material has many individual advantages such as low loss, wide spectrum, and high optical power. Specifically, SiN has a wide transparent spectrum range from ultraviolet to mid-infrared, which makes it very suitable for optical communication systems of different wavelengths; in the bands commonly used in optical communications, SiN waveguides can achieve lower propagation losses, which is crucial for maintaining signal strength and reducing noise; SiN materials exhibit higher nonlinear optical effects and can respond more effectively to small changes in electrical signals, thereby improving modulation efficiency and supporting high-speed data transmission; SiN deposition and other processing steps can be well integrated into the existing complementary metal oxide semiconductor (CMOS) microelectronics manufacturing process, facilitating large-scale production and integrated design.

[0100] In specific implementation, the metal groove can be formed by an etching process. Metal grooves are formed on both sides of the waveguide core 12, and then metal is deposited. The metal covers the passivation layer and the metal groove. The metal on the passivation layer is etched, and the metal in the metal groove forms a metal electrode 11.

[0101] In one embodiment, for the hole structure 19 formed by opening a hole above the metal electrode 11, the hole structure 19 penetrates the passivation layer above the metal electrode 11 to expose the metal electrode 11. The shape of the hole structure 19 can be set to be square or rectangular. When opening the hole, the hole can be opened above a portion of the metal electrode 11 to facilitate subsequent packaging lead bonding.

[0102] In one embodiment, referring to Figure 2 The protective layer 16 can be set as photoresist or bonding glue, etc., and can adopt deposition etching or stripping process. The thickness of the protective layer 16 is generally set to 5-100μm to protect the metal electrode 11 that has been opened in the PIC wafer.

[0103] In a specific implementation, after forming the entire protective layer 16, the area corresponding to the waveguide core 12 needs to be exposed, and an area for bonding is reserved, that is, the area corresponding to the waveguide core 12 is not provided with the protective layer 16, and the entire protective layer 16 can be etched by a photolithography process to remove the protective layer 16 above the area corresponding to the waveguide core 12. Figure 2 The structure shown in the figure can then be directly bonded. Therefore, before bonding, there is no step on the wafer, and only one photolithography is required, which shortens the time and reduces the cost, and there is no need to consider the impact of overlay accuracy on the product. In addition, there is no need to use a double-sided exposure machine, which reduces costs.

[0104] In one embodiment, referring to Figure 6 The chip preparation comprises the following steps:

[0105] Depositing the sacrificial layer 17 on the second substrate 15;

[0106] Depositing the silicon oxide layer 14 on the sacrificial layer 17;

[0107] Ions are implanted into the electro-optic material block 18, and the ions penetrate into the electro-optic material block 18 to a preset depth, thereby forming an ion implantation layer. Figure 7 ;

[0108] The electro-optical material block 18 with the ion implantation layer is bonded to the silicon oxide layer 14. Figure 8 ;

[0109] Heating is performed to peel off the ion implantation layer from the electro-optical material block 18, referring to Fig. 9 ;

[0110] performing annealing treatment on the stripped ion implantation layer;

[0111] Performing chemical mechanical polishing on the ion implantation layer to form the electro-optical material layer 13;

[0112] Slicing is performed to complete the preparation of the chip.

[0113] In this embodiment, the chip is prepared by bonding the electro-optic material to silicon oxide, that is, firstly depositing a sacrificial layer 17 and a silicon oxide layer 14 on the second substrate 15 in sequence, and then preparing the electro-optic material layer 13, including: performing ion implantation on the electro-optic material block 18, the ions penetrate into the electro-optic material block 18, lose energy and stay at a specific depth inside the block, forming an ion implantation layer; then bonding the electro-optic material (ion implantation layer) to the silicon oxide layer 14 at room temperature, such as Figure 8 As shown; at 150°C-250°C, bubbles are formed in the damaged layer, and the ion implanted layer is peeled off from the block. The peeled ion implanted layer is subjected to high temperature thermal annealing treatment, usually at 400-500°C, to improve the quality of the prepared electro-optical material.

[0114] The ion implantation layer is subjected to CMP and polished to a specified position. Generally, the ion implantation layer is polished to a thickness of 200-900 nm to form the electro-optical material layer 13 .

[0115] The chip is diced to complete the preparation of the chip, and the chip size is generally 1mm*1mm-12mm*12mm.

[0116] In one embodiment, the chip can also be prepared by bonding the sacrificial layer 17. Specifically, the chip preparation includes the following steps:

[0117] A first sacrificial layer 20 is deposited on the second substrate 15. Fig.10 ;

[0118] Performing ion implantation on the electro-optic material block 18, wherein the ions penetrate to a preset depth in the electro-optic material block 18 to form an ion implantation layer;

[0119] Depositing the silicon oxide layer 14 on the ion implantation layer;

[0120] A second sacrificial layer 21 is deposited on the silicon oxide layer 14. Fig.11 ;

[0121] The first sacrificial layer 20 and the second sacrificial layer 21 are bonded at a preset heating temperature, and the ion implantation layer is peeled off from the electro-optical material block 18. Fig.12, the first sacrificial layer 20 and the second sacrificial layer 21 are bonded to form the sacrificial layer 17;

[0122] performing annealing treatment on the stripped ion implantation layer;

[0123] Performing chemical mechanical polishing on the ion implantation layer to form the electro-optical material layer 13;

[0124] Slicing is performed to complete the preparation of the chip.

[0125] In this embodiment, a sacrificial layer 17 bonding method is adopted to prepare the chip, and the method of this embodiment is applicable to the case where the sacrificial layer 17 is metal. Specifically, a part of the sacrificial layer 17 is first deposited on the silicon substrate; ion implantation is performed on the electro-optical material block 18, and the ions penetrate into the electro-optical material block 18, lose energy and stay at a specific depth inside the block to form an ion implantation layer; then silicon oxide is deposited and another part of the sacrificial layer 17 is deposited; the two parts of the sacrificial layer 17 are bonded at high temperature, the temperature range is 150℃-250℃, and bubbles are formed in the damaged layer at the same time, the ion implantation layer is peeled off from the block, and the ion implantation layer after peeling is subjected to high temperature thermal annealing treatment, usually at 400-500℃, to improve the quality of the prepared electro-optical material.

[0126] The ion implantation layer is subjected to CMP and polished to a specified position, generally polished to a thickness of 200-900 nm, to form the electro-optical material layer 13 .

[0127] The chip is diced to complete the preparation of the chip, and the chip size is generally 1mm*1mm-12mm*12mm.

[0128] In one embodiment, bonding the region above the passivation layer corresponding to the waveguide core 12 to the electro-optical material layer 13 of the chip comprises:

[0129] The area above the passivation layer corresponding to the waveguide core 12 and the chip are sequentially cleaned and plasma activated;

[0130] Pre-bonding the region above the passivation layer corresponding to the waveguide core 12 and the electro-optical material layer 13 at room temperature to form a pre-bonded device;

[0131] The pre-bonded device is annealed at 50-300° C. for 1-12 hours to complete the bonding.

[0132] When implementing it, refer to Figure 3, C2W bonding is performed, and the chip size is set to 1mm*1mm-12mm*12mm. Before bonding, both the chip and wafer are cleaned and plasma activated, then pre-bonded at room temperature, and annealed at 50-300℃ for 1-12h to complete the bonding process.

[0133] For the specific structure of the chip, the material of the electro-optical material layer 13 can be lithium niobate (LN), the thickness of the electro-optical material layer 13 is set to 300-400nm, the thickness of the silicon oxide layer 14 is set to 0.5-2μm, the thickness of the silicon substrate is set to 500-675μm, and the material of the sacrificial layer 17 can be set to metal aluminum or other materials that can be corroded by chemical solutions, and the thickness of the sacrificial layer 17 is set to 1-5μm.

[0134] In one embodiment, referring to Figure 4 After the bonding, the second substrate 15 is removed by removing the sacrificial layer 17, comprising:

[0135] After bonding, the sacrificial layer 17 is removed by wet etching using a first chemical solution, and the second substrate 15 is removed at the same time. The first chemical solution is set to be an acid etching solution, such as phosphoric acid or nitric acid.

[0136] In this embodiment, the sacrificial layer 17 is removed by wet etching with chemical solution, and the silicon substrate can be removed at the same time. The method in this embodiment is used to remove the silicon substrate without the risk of silicon residue or over-etching, thereby improving the modulation performance of the electro-optical material.

[0137] In one embodiment, referring to Figure 5 , the removing the protective layer 16 comprises:

[0138] The protective layer 16 is removed by soaking in a second chemical solution, wherein the second chemical solution is N-methylpyrrolidone or acetone.

[0139] In order to make the removal efficiency of the silicon substrate higher during the wet etching removal process, a through-hole structure may be introduced. The through-hole structure may be arranged in at least one of the second substrate 15 and the sacrificial layer 17. The preparation process of the through-hole is described in detail below.

[0140] In one embodiment, the method further comprises:

[0141] Before bonding, the first sacrificial layer 20 is etched to form a plurality of first through holes 23, one end of each of the first through holes 23 is connected to the second substrate 15. Fig.15 ;

[0142] The second sacrificial layer 21 is etched to form a second through hole 24, one end of the second through hole 24 is connected to the silicon oxide layer 14, the number of the second through holes 24 is the same as the number of the first through holes 23, and the positions of the second through holes 24 and the first through holes 23 correspond one to one. Fig.16 ;

[0143] The first sacrificial layer 20 and the second sacrificial layer 21 are bonded at a preset heating temperature, and after bonding, the other end of the first through hole 23 is connected to the other end of the second through hole 24. Fig.17 .

[0144] In this embodiment, the preparation of the through hole is completed in the process of chip preparation. The through hole preparation method of this embodiment is aimed at the method of preparing the chip by bonding with the sacrificial layer 17. Holes are formed by etching to facilitate the subsequent wet etching to remove the sacrificial layer 17, thereby improving the corrosion efficiency, completely removing the silicon substrate without residue, and the upper silicon oxide layer will not be damaged, thereby adjusting the modulation performance of the electro-optical material.

[0145] Preferably, in order to further improve the silicon substrate removal efficiency, after the through hole is prepared in the sacrificial layer 17, a third through hole 22 is prepared on the second substrate 15, referring to Fig.17 As shown, at this time, both the sacrificial layer 17 and the second substrate 15 are provided with through holes, and the liquid can further penetrate into the sacrificial layer 17, further increasing the efficiency of removing the silicon substrate.

[0146] In another embodiment, referring to Fig.14 and Fig.17 , the method further comprises:

[0147] The second substrate 15 is etched to form a plurality of third through holes 22 , and one end of the third through hole 22 is connected to the sacrificial layer 17 .

[0148] In specific implementation, by etching and introducing the third through hole 22 on the second substrate 15, it is convenient for the subsequent wet etching solution to penetrate into the sacrificial layer 17 for etching, thereby improving the efficiency of etching. The size of the third through hole 22 is greater than 1*1μm. The number of the third through holes 22 can be set according to the shape characteristics or performance requirements of the specific structure. Preferably, in order to etch uniformly, the third through holes 22 can be evenly arranged.

[0149] The preparation of the third through hole 22 can be achieved in the process of preparing the chip, for example, referring to Fig.14 , the specific preparation process includes:

[0150] Depositing the sacrificial layer 17 on the second substrate 15;

[0151] Depositing the silicon oxide layer 14 on the sacrificial layer 17;

[0152] Performing ion implantation on the electro-optic material block 18, wherein the ions penetrate to a preset depth in the electro-optic material block 18 to form an ion implantation layer;

[0153] bonding the electro-optic material block 18 with the ion implantation layer to the silicon oxide layer 14;

[0154] The second substrate 15 is etched to form a plurality of third through holes 22, wherein one end of the third through hole 22 is connected to the sacrificial layer 17;

[0155] Heating is performed to peel off the ion implantation layer from the electro-optical material block 18, and high-temperature thermal annealing is performed on the peeled ion implantation layer;

[0156] Performing CMP on the ion implantation layer to form the electro-optical material layer 13;

[0157] Slicing is performed to complete the preparation of the chip.

[0158] In this embodiment, the preparation of the third through hole 22 on the second substrate 15 is only an exemplary description. The preparation sequence of the third through hole 22 can be adjusted according to specific process requirements and is not limited to the preparation process listed in this embodiment.

[0159] In one embodiment, the thickness of the sacrificial layer 17 is set to 1-5 μm.

[0160] The embodiment provided by the present invention uses a specially made electro-optical material wafer, introduces a sacrificial layer 17 (which may be metal) in the middle, and removes the silicon substrate at the same time during the process of removing the sacrificial layer 17 after bonding. The method for removing the silicon substrate in the present application does not have the risk of silicon residue or over-etching, thereby improving the modulation performance of the electro-optical material.

[0161] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for removing silicon substrate from a chip based on C2W bonding, characterized in that: The method comprises: A waveguide core (12) and a metal electrode (11) are sequentially formed on a first substrate (10), wherein the waveguide core (12) and the metal electrode (11) are covered with a passivation layer, and the metal electrode (11) is located on both sides of the waveguide core (12); Opening a hole above the metal electrode (11) to form a hole structure (19); forming a protective layer (16) in a region above the passivation layer corresponding to the metal electrode (11), wherein the protective layer (16) covers the metal electrode (11) through the hole structure (19); Preparing a chip, the chip comprising a second substrate (15), a sacrificial layer (17), a silicon oxide layer (14) and an electro-optical material layer (13) stacked in sequence; Bonding the region above the passivation layer corresponding to the waveguide core (12) to the electro-optical material layer (13) of the chip; After bonding, the second substrate (15) is removed by removing the sacrificial layer (17); The protective layer (16) is removed.

2. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The waveguide core (12) and the metal electrode (11) are sequentially formed on the first substrate (10), and the waveguide core (12) and the metal electrode (11) are covered with a passivation layer, comprising: forming the waveguide core (12) on the first substrate (10); Depositing the passivation layer to cover the first substrate (10) and the waveguide core (12); Metal grooves are respectively formed on both sides of the waveguide core (12), and metal electrodes (11) are formed in the metal grooves; The passivation layer is deposited to cover the metal electrode (11).

3. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The chip preparation comprises: Depositing the sacrificial layer (17) on the second substrate (15); Depositing the silicon oxide layer (14) on the sacrificial layer (17); Performing ion implantation on the electro-optic material block (18), wherein the ions penetrate to a preset depth in the electro-optic material block (18), thereby forming an ion implantation layer; Bonding the electro-optical material block (18) with the ion implantation layer to the silicon oxide layer (14); Heating is performed to peel off the ion implantation layer from the electro-optical material block (18); performing annealing treatment on the stripped ion implantation layer; Performing chemical mechanical polishing on the ion implantation layer to form the electro-optical material layer (13); Slicing is performed to complete the preparation of the chip.

4. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The chip preparation comprises: Depositing a first sacrificial layer (20) on the second substrate (15); Performing ion implantation on the electro-optic material block (18), wherein the ions penetrate to a preset depth in the electro-optic material block (18), thereby forming an ion implantation layer; Depositing the silicon oxide layer (14) on the ion implantation layer; Depositing a second sacrificial layer (21) on the silicon oxide layer (14); Bonding the first sacrificial layer (20) and the second sacrificial layer (21) at a preset heating temperature, and peeling the ion implantation layer from the electro-optical material block (18), so that the bonded first sacrificial layer (20) and the second sacrificial layer (21) form the sacrificial layer (17); performing annealing treatment on the stripped ion implantation layer; Performing chemical mechanical polishing on the ion implantation layer to form the electro-optical material layer (13); Slicing is performed to complete the preparation of the chip.

5. The method for removing silicon substrate from a chip based on C2W bonding according to claim 4, characterized in that: The method further comprises: Before bonding, the first sacrificial layer (20) is etched to form a plurality of first through holes (23), one end of the first through hole (23) being connected to the second substrate (15); The second sacrificial layer (21) is etched to form a second through hole (24), one end of the second through hole (24) being connected to the silicon oxide layer (14), the number of the second through holes (24) being the same as the number of the first through holes (23), and the positions of the second through holes (24) and the first through holes (23) being in one-to-one correspondence; The first sacrificial layer (20) and the second sacrificial layer (21) are bonded at a preset heating temperature, and after bonding, the other end of the first through hole (23) is connected to the other end of the second through hole (24).

6. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The step of bonding the region above the passivation layer corresponding to the waveguide core (12) to the electro-optical material layer (13) of the chip comprises: The area above the passivation layer corresponding to the waveguide core (12) and the chip are sequentially cleaned and plasma activated; Pre-bonding the region above the passivation layer corresponding to the waveguide core (12) and the electro-optical material layer (13) at room temperature to form a pre-bonded device; The pre-bonded device is annealed at 50-300° C. for 1-12 hours to complete the bonding.

7. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: After the bonding, the second substrate (15) is removed by removing the sacrificial layer (17), comprising: After bonding, the sacrificial layer (17) is removed by wet etching using a first chemical liquid, and the second substrate (15) is removed at the same time, wherein the first chemical liquid is an acid etching liquid.

8. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The removing of the protective layer (16) comprises: The protective layer (16) is removed by soaking in a second chemical liquid, wherein the second chemical liquid is N-methylpyrrolidone or acetone.

9. The method for removing silicon substrate from a chip based on C2W bonding according to any one of claims 1 to 8, characterized in that: The method further comprises: The second substrate (15) is etched to form a plurality of third through holes (22), one end of each of the third through holes (22) being connected to the sacrificial layer (17).

10. The method for removing silicon substrate from a chip based on C2W bonding according to any one of claims 1 to 8, characterized in that: The thickness of the sacrificial layer (17) is set to 1-5 μm.

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