Computing system in memory and method for reducing power consumption thereof

Abstract

A computing in memory (CIM) system includes a first boot-follow (L / F) flip-flop (FF), a pause unit, and a multiplication unit. The first L / F flip-flop is configured to receive a data signal. The first L / F flip-flop includes: a first pilot FF configured to receive a data signal; a first follow FF configured to generate a signal first Qfollow representing an output signal of the first L / F flip-flop; the multiplication unit is configured to receive a weight signal W and a signal first Qfollow, and to generate a first product signal. In a given period of the first clock signal, the pause unit is configured to detect that a first scenario in which all bits b (k) of the data signal are equal to logic zero is true, and correspondingly suppress the first L / F flip-flop from performing latching, and control the multiplication unit to generate a first product signal equal to logic zero.

Description

Technical Field

[0001] Embodiments of the present application relate to a computing system in memory and a method for reducing power consumption thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry produces a variety of analog and digital devices to solve problems in many different fields. The development of semiconductor process technology nodes has gradually reduced component size and tightened spacing, resulting in a gradual increase in transistor density. ICs have become smaller. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a computing-in-memory (CIM) system is provided, comprising: a first leader-follower (L / F) flip-flop (FF), configured to receive a multi-bit data signal and generate a multi-bit output signal, the first L / F flip-flop comprising: a first leader flip-flop, configured to receive a data signal and generate a signal first_Q_lead; and a first follower flip-flop, configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing an output signal of the first L / F flip-flop; in the i-1th cycle of a first clock signal, at least one bit b(k) of the data signal is equal to logic 1, where i and k are corresponding integers; a multiplication unit, configured to receive a multi-bit weight signal and the signal first_Q_follow, and generate a first product signal; and a pause unit, configured to perform the following operations during the i-th cycle of the first clock signal, including: detecting that a first scenario in which all bits b(k) of the data signal are equal to logic zero is true; and when the first scenario is true, inhibiting latching performed by the first L / F flip-flop, and controlling the multiplication unit to generate a first product signal equal to logic zero.

[0004] According to another aspect of an embodiment of the present application, a method for reducing power consumption of a computing-in-memory (CIM) system is provided, the method comprising: performing the following operations within the i-th cycle of a first clock signal: detecting that a first scenario is true, wherein all bits b(k) of a multi-bit data signal are equal to logic zero, wherein i and k are corresponding integers; and when the first scenario is true, suppressing the latching performance of a first lead-follower (L / F) flip-flop (FF), wherein within the i-1th cycle of the first clock signal, at least one bit b(k) of the data signal is equal to logic 1, the first L / F flip-flop is configured to receive the data signal and generate a multi-bit output signal, the first LF flip-flop comprises a first lead flip-flop and a first follow flip-flop, the first lead flip-flop is configured to receive a digital signal and generate a signal first_Q_lead, the first follow flip-flop is configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing the output signal of the first lead-follow flip-flop; and when the first scenario is true, for a multiplication unit configured to receive a multi-bit weight signal and a signal first_Q_follow and generate a first product signal, controlling the multiplication unit to generate the first product signal with all bits equal to logic zero.

[0005] According to another aspect of an embodiment of the present application, a computing-in-memory (CIM) system is provided, comprising: a first leader-follower (L / F) flip-flop (FF), which is configured to receive a multi-bit data signal and generate a multi-bit output signal, the first L / F flip-flop comprising: a first leader flip-flop, configured to receive the data signal and generate a signal first_Q_lead, and a first follower flip-flop, configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing the output signal of the first L / F flip-flop; in the i-1th cycle of a first clock signal, at least one bit b(k) of the data signal is equal to logic 1, where i and k are corresponding integers; a multiplier, configured to receive a multi-bit weight signal and the signal first_Q_follow, and generate a first product signal; and a pause unit, configured to perform the following operations during the i-th cycle of the first clock signal, including: detecting that a first scenario in which all bits b(k) of the data signal are equal to logic zero is true; and when the first scenario is true, triggering a reset operation performed by the first L / F flip-flop so that all bits of the signal first_Q_follow are equal to logic zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A-1B is a corresponding schematic diagram according to some embodiments.

[0008] Figure 2 is a collection of waveforms according to some embodiments.

[0009] Figure 3A-3B is a corresponding schematic diagram according to some embodiments.

[0010] Figure 4 is a collection of waveforms according to some embodiments.

[0011] Figure 5-Figure 6 is a flow chart of a corresponding method according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] In addition, for ease of description, spacing relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figure. In addition to the orientation shown in the figure, the spacing relationship terms are intended to include different orientations of the device in use or operating processes. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relationship descriptors used in this article can be interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their library and used as components in a layout diagram representing a circuit.

[0014] In some embodiments, a computing-in-memory (CIM) system includes a first leader-follower (L / F) flip-flop (FF), a pause unit, and a multiplication unit. The first L / F FF is configured to receive a multi-bit data signal and generate a multi-bit output signal. The first L / F FF includes: a first leader FF configured to receive the data signal and generate a signal first_Q_lead; and a first follower FF configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing an output signal of the first L / F FF. During the i-1_th cycle of the first clock signal, at least one bit b(k) of the data signal is equal to logic 1, where i and k are corresponding integers. The multiplication unit is configured to receive a multi-bit weight signal and the signal first_Q_follow, and generate a first product signal. During the i_th cycle of the first clock signal, the pause unit is configured to perform the following operations: detect whether a first scenario in which all bits b(k) of the data signal are equal to logic zero is true; and when the first scenario is true, inhibit the first L / F FF from performing latching, and control the multiplication unit to generate a first product signal equal to logic zero. In some embodiments, the multiplication unit includes a multiplier and a zeroing logic unit. In some embodiments, the multiplication unit does not include a zeroing logic unit.

[0015] According to another method, the corresponding system does not include a counterpart of the pause unit. According to another method, for a period in which the value of all bits b(k) of the corresponding portion of the data signal is logic zero, all bits b(k) are still propagated through the corresponding portion of the first L / F FF in another manner, so that the corresponding portion of another form of multiplication unit (i.e., multiplier) multiplies the corresponding portion of the weight signal by logic zero, resulting in all bits of the corresponding portion of the first product signal being logic zero. In developing at least some of the present embodiments, one or more of the inventors recognized at least the following points: regardless of the bit value, propagating all bits b(k) of the corresponding data signal through the corresponding portion of the first L / F FF consumes energy; and the corresponding first product signal can be made equal to logic zero without having to propagate all bit values ​​of the bits b(k) of the corresponding data signal through the corresponding first L / F FF, which provides an opportunity to reduce energy consumption compared to other methods. Therefore, when all bits b(k) of the data signal are logic zero, the pause unit (in some embodiments, combined with the multiplication unit) enables the generation of a first product signal in which all b(k) are equal to logic zero, without having to propagate the bit values ​​of all bits b(k) of the data signal through the first L / F FF. By avoiding such propagation, the system according to some embodiments reduces energy consumption when all bits b(k) of the data signal are logic zero compared to other methods.

[0016] Figure 1A is a schematic diagram of a system 100A according to some embodiments.

[0017] The system 100A includes a compute-in-memory (CIM) system 102 and an input enable buffer 104. The system 100A is configured to reduce power consumption of the CIM system 102.

[0018] The CIM system 102 includes multi-bit leader / follower (L / F) flip-flops (FFs) 106{0}, 106{1}, ..., 106{N-2}, and 106{N-1}, where N is a positive integer. The nth instance of L / F FFs 106{0}-106{N-1}, i.e., L / F FF 106{n}, is as follows: Figure 1B As shown. In some embodiments, the L / F FF is called a master / slave (M / S) FF. In some embodiments, FF 106{0}-106{N-1} is a type of FF called a D FF. In some embodiments, the L / F FF 106{0}-106{N-1} is a type of FF other than a D FF.

[0019] L / F FFs 106{0}, 106{1}, ..., 106{N-2}, and 106{N-1} are configured to receive corresponding multi-bit data signals prv_XIN{0}, prv_XIN{1}, ..., prv_XIN{N-2}, and prv_XIN{N-1} from input enable buffer 104. Each data signal prv_XIN{0}-prv_XIN{N-1} has bits b(0)-b(L-1), where L is an integer. Therefore, for 0≤k≤(L-1), bit b(k) represents bit b(0)-b(L-1).

[0020] L / F FFs 106{0}, 106{1}, ..., 106{N-2}, and 106{N-1} are also configured to generate corresponding data signals pub_XIN{0}, pub_XIN{1}, ..., pub_XIN{N-2}, and pub_XIN{N-1}. The outputs of L / F FFs 106{0}, 106{1}, ..., 106{N-2}, and 106{N-1} are coupled to corresponding multipliers 108{0}, 108{1}, ..., 108{N-2}, and 108{N-1}.

[0021] Multipliers 108{0}-108{N-1} are correspondingly configured to operate as follows: receive signals pub_XIN{0}, pub_XIN{1}, …, pub_XIN{N-2} and pub_XIN{N-1} as multiplicands; receive multi-bit weight signals W{0}, W{1}, …, W{N-2} and W{N-1} as multipliers; and generate private product signals prv_prod{0}, prv_prod{1}, …, prv_prod{N-2} and prv_prod{N-1}.

[0022] The CIM system 102 also includes zeroing logic units (zeroers) 114{0}, 114{1}, …, 114{N-2}, and 114{N-1}, which are correspondingly configured to perform the following operations, including: receiving private product signals prv_prod{0}-prv_prod{N-1}; receiving public zeroing signals pub_all_0s{0}, pub_all_0s{1}, …, pub_all_0s{N-2}, and pub_all_0s{N-1}; and generating public product signals pub_prod{0}, pub_prod{1}, …, pub_prod{N-2}, and pub_prod{N-1}. The zeroers 114{0}-114{N-1} will be discussed below. In some embodiments, each zeroer 114{0}-114{N-1} includes a corresponding logic NOR (negation of OR) gate.

[0023] Taking everything into consideration, multiplier 108{0} and zeroer 114{0} represent multiplication unit 115{0}. Similarly, taking everything into consideration, multipliers 108{1}-108{N-1} and zeroers 114{1}-114{N-1} represent corresponding multiplication units 115{1}-115{N-1}.

[0024] The CIM system 102 also includes an adder tree 110, and the adder tree 110 includes instances of summing units (adders) 112. The adder tree 110 is configured to receive the public product signals pub_prod{0}-pub_prod{N-1} from the corresponding zeroers 114{0}-114{N-1} and add them together. The adder tree 110 has stages of instances of adders 112, where these stages are cascaded together. In some embodiments, the adder tree 110 has J stages crs(0), …, crs(J-1) of adders 112, where J is a positive integer and J < N. In some embodiments, the relationship between the number J of stages in the adder tree 110 and the number N of signals pub_XIN{0}, pub_XIN{1}, …, pub_XIN{N-2}, and pub_XIN{N-1} is as follows: N is equal to 2 to the power of J, i.e., N = 2^J. The adder tree 110 is configured to receive N signals pub_XIN{0}, pub_XIN{1}, …, pub_XIN{N-2}, and pub_XIN{N-1], and generate a single word as the output signal OUT1. Each instance of the adder 112 is configured to receive two single-word inputs. In some embodiments, the bit capacity of the instances of the adder 112 in each successive stage increases by one bit. For example, in stage crs(0), if each instance of the adder 112 is a j-bit adder, then each instance of the adder 112 in stage crs(1) is a j+1-bit adder, where j is a positive integer.

[0025] The public reset signal pub_all_0s{0}-pub_all_0s{N-1} indicates the i-th cycle CLK(i) of the global clock CLK (see Figure 1B ), whether all bits b(k) of the corresponding data signals prv_XIN{0}, prv_XIN{1}, ..., prv_XIN{N-2} and prv_XIN{N-1} are logic zeros, where i is an integer. Public reset signals pub_all_0s{0}-pub_all_0s{N-1} are generated by the pause units 116{0}, 116{1}, ..., 116{N-2} and 116{N-1} accordingly (see Figure 1B ).

[0026] The input enable buffer 104 includes an array of pause cells 116{0}-116{N-1} and a one-bit memory cell (not shown) (see Figure 1B 132 in). The array of one-bit memory cells generates buffer data signals prv_XIN{0}-prv_XIN{N-1} accordingly. Figure 1A Assume that each data signal prv_XIN{0}-prv_XIN{N-1} is a four-bit signal. In some embodiments, each data signal prv_XIN{0}-prv_XIN{N-1} is a multi-bit signal whose bit number is not 4. Figure 1A In the embodiment, it is assumed that the 1-bit memory cell is a static random access memory (SRAM) cell. In some embodiments, the 1-bit memory cell is a memory cell other than SRAM.

[0027] The pause units 116{0}-116{N-1} also generate corresponding local clocks CLK_XIN{0}, CLK_XIN{1}, ..., CLK_XIN{N-2} and CLK_XIN{N-1} (see Figure 1B ). The global clock CLK is received by each of the pause units 116{0}-116{N-1}, and the local clocks CLK_XIN{0}-CLK_XIN{N-1} are received by the L / F FFs 106{0}-106{N-1} accordingly, so the corresponding adjectives are global and local.

[0028] To simplify the discussion, Figure 1AIt is also assumed that the example values ​​of each of the data signals prv_XIN{0}-prv_XIN{N-1} are for the i-1th cycle and the i-th cycle of the global clock CLK, ie, CLK(i-1) and CLK(i). For CLK(i-1), the values ​​of the data signals prv_XIN{0}-prv_XIN{N-1} and the corresponding public reset-to-zero signals pub_all_0s{0}-pub_all_0s{N-1} are assumed to be: prv_XIN{0}(i-1)={0,0,1,1}, pub_all_0s{0}(i-1)=0; prv_XIN{1}(i-1)={1,0,1,1} and pub_all_0s{1}(i-1)=0; prv_XIN{N-2}(i-1)={1,0,1,0}, and pub_all_0s{N-2}(i-1)=0; and prv_XIN{N-1}(i-1)={1,1,0,1}, and pub_all_0s{N-1}{i-1)=0. Figure 1A , for CLK(i), example values ​​of data signals prv_XIN{0}-prv_XIN{N-1} are assumed to be: prv_XIN{0}(i)={1,1,0,1}, pub_all_0s{0}(i)=0; prv_XIN{1}(i)={0,0,0,0}, pub_all_0s{1}(i)=1; prv_XIN{N-2}(i)={1,1,0,0}, pub_all_0s{N-2}(i)=0; and prv_XIN{N-1}(i)={1,1,0,1}, and pub_all_0s{N-1}(i)=0.

[0029] Recalling that the public set-to-zero signals pub_all_0s{0}-pub_all_0s{N-1} indicate whether all bits b(k) of the corresponding data signals prv_XIN{0}, prv_XIN{1}, ..., prv_XIN{N-2}, and prv_XIN{N-1} are logic zeros for the corresponding cycles of the clock signal CLK, Figure 1A It is further assumed that: each public reset signal pub_all_0s{0}(i-1)-pub_all_0s{N-1}{i-1) is assumed to be logic zero; it is assumed that each of the public reset signals pub_all_0s{0}(i) and pub_all_0s{2}(i-1)-pub_all_0s{N-1}(il) is logic zero; and it is assumed that the public reset signal pub_all_0s{1}(i) is logic 1.

[0030] According to the public zeroing signal pub_all_0s{0}-pub_all_0s{N-1}, the zeroing devices 114{0}-114{N-1} are correspondingly configured to selectively zero the public product signals pub_prod{0}-pub_prod{N-1}. That is, according to the public zeroing signal pub_all_0s{0}-pub_all_0s{N-1}, the zeroing devices 114{0}-114{N-1} are correspondingly configured to generate the public product signals pub_prod{0}-pub_prod{N-1} selectively equal to the private product signals prv_prod{0}-prv_prod{N-1} or all bits are equal to logic zero.

[0031] To simplify the discussion, zeroer 114{n} is considered to be a representative of zeroers 114{0}-114{N-1}, and public zeroing signal pub_all_0s{n} is considered to be a representative of public zeroing signals pub_all_0s{0}-pub_all_0s{N-1}. In some embodiments, zeroer 114{n} represents an instance of zeroer 114{n} for each bit b(k) of data signal prv_XIN{n}.

[0032] As used herein, generating the public set-to-zero signal pub_all_0s{n} to have all bits equal to logic zero within a given global clock CLK cycle is understood to be set to zero, ie, making the public set-to-zero signal pub_all_0s{n} zero within a given cycle.

[0033] In some embodiments, the zeroer 114{n} is configured to generate a truth table for bit b(k) of the public product signal pub_prod{n} as follows:

[0034]

[0035]

[0036] Truth Table

[0037] The context of rows 1-2 of the truth table is as follows: the latching of L / F FF 106{n} is not inhibited, so that the value of bit b(k) of the public data signal pub_XIN{n} (column 3 of the truth table) is equal to the value of bit b(k) of the private data signal prv_XIN{n} of the current global clock cycle CLK(i); and the value of bit b(k) of the private product signal prv_prod{n} (column 2 of the truth table) corresponds to the value of bit b(k) of the private data signal prv_XIN{n} of the global clock cycle CLK(i), so that the value of bit b(k) of the public data signal pub_XIN{n} is valid for the current global clock cycle CLK(i).

[0038] In contrast, the context of rows 3-4 of the truth table is as follows: the latching of L / F FF 106{n} is inhibited, so that the value of bit b(k) of the public data signal pub_XIN{n} (column 3 of the truth table) is equal to the value of bit b(k) of the private data signal prv_XIN{n} of the previous global clock cycle CLK(i-1); wherein the value of bit b(k) of the private product signal prv_prod{n} of the current global clock cycle CLK(i) is different from the value of bit b(k) of the private product signal prv_prod{n} of the previous global clock cycle CLK(i-1), causing bit b(k) of the private product signal prv_prod{n} of the current global clock cycle CLK(i) to be equal to bit b(k) of the private product signal prv_prod{n} of the previous global clock cycle CLK(i-1). )(row 2 of the truth table) does not correspond to the value of bit b(k) of the private data signal prv_XIN{n} of the current global clock cycle CLK(i); and wherein, the value of bit b(k) of the private product signal prv_prod{n} of the current global clock cycle CLK(i) is different from the value of bit b(k) of the private product signal prv_prod{n} of the previous global clock cycle CLK(i-1), the value of bit b(k) of the private data signal prv_XIN{n} of the current global clock cycle CLK(i) is invalid, and accordingly, the value of bit b(k) of the private product signal prv_prod{n} is invalid. However, the validity of the value of bit b(k) of the private data signal prv_XIN{n} of the current global clock cycle CLK(i) is not important in the context of rows 3-4 for at least the following reasons. The reason is as follows. With respect to rows 3-4 of the truth table, under the control of the zeroing signal pub_all_0x{n}, the zeroer 114{n} forces the value of bit b(k) of the public product signal pub_prod{n} to logic zero, regardless of the value of bit b(k) of the private data signal prv_XIN{n}.

[0039] Figure 1B is a schematic diagram of a system 100B according to some embodiments.

[0040] According to some embodiments, system 100B is a version of system 100A showing the components of the latter in more detail. Figure 1B In the discussion, it is assumed that the pause unit 116{n} represents the pause units 116{0}-116{N-1}. To simplify the discussion, the following will also be used as a representative: the data signal prv_XIN{n} is as Figure 1A The data signals prv_XIN{0}-prv_XIN{N-1} are representative; L / FFF 106{n} is Figure 1A The L / F FF 106{0}-106{N-1} represents; the data signal pub_XIN{n} is used as Figure 1A The data signals pub_XIN{0}-pub_XIN{N-1} represent; the local clock CLK_XIN{n} is Figure 1A as a representative of the local clocks CLK_XIN{0}-CLK_XIN{N-1}; and the public reset-to-zero signal pub_all_0s{n} as a representative of the public reset-to-zero signals pub_all_0s{0}-pub_all_0s{N-1}.

[0041] System 100B includes a representation Figure 1A The input enables a SRAM array 132 of a one-bit memory cell (not shown) that is a portion of the buffer 104. The SRAM array 132 is configured to output a data signal prv_XIN{n}.

[0042] exist Figure 1B In the embodiment, the L / F FF 106{n} includes a multi-bit alpha (alpha, α) lead FF 118{n} and a multi-bit alpha follow FF 120{n}. In some embodiments, the alpha lead FF 118{n} is referred to as an alpha master FF 118{n}, and the alpha follow FF 120{n} is referred to as an alpha slave FF 120{n}. In some embodiments, the alpha lead FF 118{n} and the alpha follow FF 120{n} are a type of FF referred to as a D FF. In some implementations, the alpha lead FF 118{n} and the alpha follow FF 120{n} are a type of FF that is not a D FF. Each of the alpha lead FF 118{n} and the alpha follow FF 120{n} has an output Q and a Q_bar (~Q, the inverse of Q), but the output Q_bar is not shown for simplicity of illustration.

[0043] The alpha-lead FF 118{n} is configured to receive the data signal prv_XIN{n} and generate a signal α_Q_lead{n}. The alpha-lead FF 118{n} is also configured to receive an inverted version of the local clock CLK_XIN{n} and be triggered at its falling edge.

[0044] The alpha follower FF 120{n} is configured to receive the signal α_Q_lead{n} and generate a signal α_Q_follow representing the output signal of the L / FFF 106{n}. The alpha follower FF 120{n} is also configured to receive the local clock CLK_XIN{n} and be triggered at its rising edge.

[0045] exist Figure 1B In the embodiment, the pause unit 116{n} includes: a logic NOR gate 128{n}; a single-bit L / F FF 122{n}; and a logic AND gate 130{n}. The NOR gate 128{n} is configured to perform a logic NOR operation on all bits b(k) of the data signal prv_XIN{n} and generate a private reset signal prv_all_0s{n}.

[0046] The L / F FF 122{n} includes a single-bit beta (Beta, β) guide FF 124{n} and a single-bit beta follower FF 126{n}. In some embodiments, the beta guide FF 124{n} is referred to as a beta master FF 124{n}, and the beta follower FF 126{n} is referred to as a beta slave FF 126{n}. In some embodiments, the beta guide FF 124{n} and the beta follower FF 126{n} are a type of FF referred to as a D FF. In some embodiments, the beta guide FF 124{n} and the beta follower FF 126{n} are a type of FF that is not a D FF. Each of the beta guide FF 124{n} and the beta follower FF 126{n} has a Q and Q_bar (~Q) output, but for simplicity of description, the output Q_bar is not shown.

[0047] The beta-lead FF 124{n} is configured to receive the private reset-to-zero signal prv_all_0s{n} and generate a signal β_Q_lead{n}. The beta-lead FF 124{n} is also configured to receive an inverted version of the global clock CLK and be triggered at the falling edge of the latter.

[0048] The beta follower FF 126{n} is configured to receive the signal β_Q_lead{n} and generate a signal β_Q_follow representing the output signal of the L / FFF 122{n}, that is, representing the public reset signal pub_all_0s{n}. The beta follower FF 126{n} is also configured to receive the global clock CLK and be triggered at its rising edge. The AND gate 130{n} is configured to receive the inverted version of the global clock CLK and the signal β_Q_lead{n} and generate a local clock CLK_XIN{n}.

[0049] To recap, Figure 1A It is also assumed that for the i-1th and i-th cycles of the global clock CLK (ie, CLK(i-1) and CLK(i)), the values ​​of each data signal prv_XIN{0}-prv_XIN{N-1}, Figure 1B Assumptions Figure 1A The value of the data signal prv_XIN{0} is equal to the value of the data signal prv_XIN{n}, again to simplify the discussion. Therefore, for the i-1th cycle of the global clock CLK, i.e., CLK(i-1), the global NOR gate 128{n} generates a private reset-to-zero signal prv_all_0s{n} equal to logic zero, because at least one bit b(k) of the data signal prv_XIN{0} is logic 1. Similarly, for the i-th cycle of the global clock CLK, i.e., CLK(i), the global NOR gate 128{n} generates a private reset-to-zero signal prv_all_0s{n} equal to logic 1, because all bits b(k) of the data signal prv_XIN{0} are logic zero.

[0050] exist Figure 2 The operation of systems 100A-100B is discussed in more detail in the context of a collection of waveforms.

[0051] Figure 2 is a set of waveforms 240 according to some embodiments.

[0052] The set 240 includes: a waveform 242, which represents the i-th, i+1-th, i+2-th, and i+3-th cycles of the global clock CLK; a waveform 244, which represents the data signal prv_XIN{n} output by the SRAM array 132{n}; a waveform 246, which represents the reset signal prv_all_0s{n} output by the NOR gate 128{n}; a waveform 248, which represents the signal β_Q_lead{n} output by the beta-lead FF 124{n}; a waveform 250, which represents the inverted version of the signal β_Q_lead{n}, i.e., ~(β_Q_lead{n}); a waveform 252, which represents the local clock CLK_XIN{n} output by the AND gate 130{n} of the pause unit 116{n}; and a waveform 254, which represents the reset signal prv_all_0s{n} output by the beta-follower FF The signal β_Q_follow{n} output by 126{n} represents the signal pub_all_0s{n} output by the pause unit 126{n}.

[0053] When all bits b(k) of the data signal prv_XIN{n} (waveform 244) become logic zero at the falling edge of the global clock CLK (waveform 242) at cycle CLK(i), the private reset-to-zero signal prv_all_0s{n} (waveform 246) becomes logic one at the rising edge of the global clock cycle CLK(i+1). Because the private reset-to-zero signal prv_all_0s{n} (waveform 246) is logic one at the falling edge of the global clock cycle CLK(i+1), the signal β_Q_lead{n} (waveform 248) becomes logic one at the falling edge of the global clock cycle CLK(i+1), and the signal ~(β_Q_lead{n}) (waveform 250) becomes logic zero. Because the signal β_Q_lead{n} (waveform 248 ) is logic 1 at the rising edge of the global clock cycle CLK(i+2), the signal β_Q_follow{n} becomes logic 1 at the rising edge of the global clock cycle CLK(i+2).

[0054] For CLK(i) and CLK(i+1), the local clock signal CLK_XIN{n} follows the global clock signal CLK{n}. However, since the signal ~(β_Q_lead{n}) (waveform 250) is logic zero at the rising edge of the global clock cycle CLK(i+2), the local clock CLK_XIN{n} is at logic 0 in the first half of the i+2 cycle of the global clock CLK (i.e., CLK(i+2)).

[0055] For the second half of the i+2th cycle of the global clock CLK, i.e., for the first half of CLK(i+2), the global clock CLK is logic zero, which causes the local clock CLK_XIN{n} to remain at logic zero. As a result, during the i+2th cycle of the global clock CLK, the latching of the L / F FF 106{n}, i.e., the latching of each of the alpha-leading FF 118{n} and the alpha-following FF 120{n} is suspended / inhibited. That is, when all bits b(k) of the private data signal prv_XIN{n} are logic zero, the latching of each of the alpha-leading FF 118{n} and the alpha-following FF 120{n} is suspended / inhibited.

[0056] According to another method, the corresponding portion of the system 100A-100B does not include the corresponding portion of the pause unit 116{n} and the zero setter 114{n}. According to another method, for the period in which the value of all bits b(k) of the corresponding portion of the data signal prv_XIN{n} is logic zero, all bits b(k) still propagate through the corresponding portion of the L / F FF 106{n} of the other method, so that the corresponding portion of the multiplier 108{n} of the other method multiplies the corresponding portion of the weight signal W{n} by logic zero, thereby obtaining that all bits of the corresponding portion of the product signal are logic zero. In developing at least some of the present embodiments, one or more of the present inventors recognized at least the following: propagating all bits b(k) of the corresponding data signal prv_XIN{n} through the corresponding portion of the L / F FF 106{n} consumes energy regardless of the bit value; and the product signal can be made equal to logic zero without propagating all bit values ​​of the bits b(k) of the corresponding data signal prv_XIN{n} through the corresponding portion of the L / F FF 106{n}, which provides an opportunity to reduce energy consumption compared to other methods. Therefore, when all bits b(k) of the private data signal prv_XIN[n} are logic zero, the pause unit 106{n} and the zeroer 114{n} of the system 100A-110B work together to achieve the generation of a public product signal pub_prod{n} with all bits b(k) equal to logic zero without propagating the bit values ​​of all bits b(k) of the private data signal prv_XIN{n} through the L / F FF 106{n}. By avoiding such propagation, the systems 100A-100B reduce power consumption when all bits b(k) of the private data signal prv_XIN[n} are logic zeros, compared to other approaches.

[0057] Figure 3A is a schematic diagram of a system 300A according to some embodiments.

[0058] The system 300A includes a CIM system 302 and an input enable buffer 304. The system 300A is configured to reduce power consumption of the CIM system 302.

[0059] The CIM system 302 includes a plurality of L / F FFs 306{0}, 306{1}, ..., 306{N-2}, and 306{N-1}. The nth instance of L / F FFs 306{0}-306{N-1}, i.e., L / F FF 306{n}, is as follows: Figure 3B shown. Figure 3A The system 300A is similar to Figure 1A For the sake of brevity, the discussion will focus on the differences between system 300A and system 100A, rather than the similarities. System 300A does not include zeroers 114{0}-114{N-1}. Instead, in system 300A, adder tree 110 is configured to receive product signals prdct{0}-prdct{N-1} from corresponding zeroers 114{0}-114{N-1}.

[0060] Pause unit 316{0}-316{N-1} (see Figure 3B ) are similar in some respects to the pause units 116{0}-116{N-1}. The pause units 316{0}-316{N-1} generate corresponding zeroing signals all_0s{0}, all_0s{1}, ..., all_0s{n-1}, and all_0{N-1}, which correspond to the private zeroing signals prv_all_0s{0}, prv_all_0s{1}, ..., prv_all_0s{n-1}, and prv_all_0{N-1} generated by the pause units 116{0}-116{N-1}.

[0061] The L / F FF units 306{0}-306{N-1} are different from the L / F FF units 106{0}-106{N-1} in that the L / F FF units 306{0}-306{N-1} are configured to receive reset signals. More specifically, the L / F FF units 306{0}-306{N-1} are configured to receive zeroing signals all_0s{0}, all_0s{1}, ..., all_0s{n-1}, and all_0s{N-1} as corresponding reset signals.

[0062] Figure 3B is a schematic diagram of a system 300B according to some embodiments.

[0063] According to some embodiments, system 300B is a version of system 300A showing the components of the latter in more detail. Figure 3BFor the discussion, it is assumed that the pause unit 316{n} represents Figure 3A The pause units 316{0}-316{N-1}. Figure 3B The system 300B is similar to Figure 1B For the sake of brevity, the discussion will focus on the differences between system 300B and system 100A, rather than the similarities.

[0064] The pause unit 316{n} does not include the L / F FF 122{n} nor the AND gate 130{n} of the pause unit 116{n}. The reset input of each of the alpha lead FF 318{n} and the alpha follower FF 320{n} is configured to receive the reset signal all_0s{n} from the NOR gate 128{n} of the pause unit 316{n}.

[0065] exist Figure 4 The operation of systems 300A-300B is discussed in more detail in the context of a set of waveforms.

[0066] Figure 4 is a set of waveforms 440 according to some embodiments.

[0067] Set 440 includes: waveform 242 (with Figure 2 ), representing the i-th, i+1-th, i+2-th, and i+3-th cycles of the global clock CLK; waveform 244 (same as Figure 2 ), representing the data signal prv_XIN{n} output by the SRAM array 132{n}; waveform 456, representing the reset signal all_0s{n} output by the NOR gate 128{n}; waveform 458, representing the alpha-leading FF 318{n} reset mode; and waveform 460, representing the alpha-following FF 320{n} reset mode.

[0068] Since at the rising edge of the global clock cycle CLK(i), the reset signal all_0s{n} (waveform 456) is logic zero, the waveform 458 is logic one, indicating that the reset of the alpha guide FF 318{n} is triggered to be false, that is, not reset. In addition, since at the rising edge of the global clock cycle CLK(i), the reset signal all_0s{n} (waveform 456) is logic zero, the waveform 460 is logic one, indicating that the reset of the alpha follower FF 320{n} is triggered to be false, that is, not reset.

[0069] Because at the rising edge of the global clock cycle CLK(i+1), the reset signal all_0s{n} (waveform 456) is logic one, the waveform 458 is logic zero, indicating that the reset of the alpha-leading FF 318{n} is triggered to be true. In addition, because at the rising edge of the global clock cycle CLK(i), the reset signal all_0s{n} (waveform 456) is logic one, the waveform 460 is logic zero, indicating that the reset of the alpha-following FF 320{n} is triggered to be true.

[0070] Since at the rising edge of the global clock cycle CLK(i+2), the reset signal all_0s{n} (waveform 456) is logic zero, the waveform 458 is logic one, indicating that the reset of the alpha guide FF 318{n} is triggered to be false, that is, not reset. In addition, since at the rising edge of the global clock cycle CLK(i+2), the reset signal all_0s{n} (waveform 456) is logic zero, the waveform 460 is logic one, indicating that the reset of the alpha follower FF 320{n} is triggered to be false, that is, not reset.

[0071] For each of the alpha pilot FF 318{n} and the alpha follower FF 320{n}, performing a reset operation is mutually exclusive from performing a latching operation. Therefore, since the alpha pilot FF 318{n} and the alpha follower FF 320{n} are triggered to reset, in effect, when all bits b(k) of the private data signal prv_XIN{n} are logic zero, the latching of each of the alpha pilot FF 318{n} and the alpha follower FF 320{n} is suspended / inhibited. When all bits b(k) of the private data signal prv_XIN[n] are logic zero, by suspending / inhibiting latching of each of the alpha pilot FF 318{n} and the alpha follower FF 320{n}, the value of all bits b(k) of the public product signal pub_prod{n} must be propagated through the L / F FF 306{n}. By avoiding such propagation, the systems 100A- 110B reduce energy consumption when all bits b(k) of the private data signal prv_XIN{n} are logic zeros, compared to other approaches.

[0072] Figure 5 is a flow chart of a method 500 according to some embodiments.

[0073] Method 500 is a method of operating a CIM system (eg, Figure 1A The method 500 includes blocks 504-522. The flow according to the method 500 starts from the start block 504 and continues to the decision block 506.

[0074] At decision block 506, a determination is made as to whether a first scenario is true. The first scenario is when all bits b(k) of the data signal XIN{n} are equal to logic zero. Examples of data signals XIN{n} include Figure 1A-1B , Figure 3A-3B In decision block 506 , the flow proceeds to block 508 .

[0075] At block 508, a logical NOR operation is performed on all bits of the data signal XIN{n} to generate a zeroing signal. Examples of zeroing signals include Figure 1B The private reset signal prv_all_0s{n}, Figure 3B The zeroing signal all_0s{n}, etc. The flow proceeds from block 508 to decision block 510.

[0076] At decision block 510, a determination is made as to whether the zeroing signal is equal to logic zero. If the zeroing signal is equal to zero, then the flow continues from the “yes” exits of decision block 510 and decision block 506, respectively, and proceeds to block 512. If the zeroing signal is not equal to zero, then the flow continues from the “no” exits of decision block 510 and decision block 506, respectively, and proceeds to block 518.

[0077] At block 512, the latching of the first L / F FF is inhibited. An example of the first L / F FF is Figure 1B The L / F FF 106{n} of the first L / F FF is inhibited, etc. An example of latching in which the first L / F FF is inhibited is discussed below in the context of block 514. Within block 512, the flow proceeds to block 514.

[0078] At block 512, a local clock signal is generated as a logic zero. An example of a local clock signal is Figure 1B The local clock signal CLK_XIN{n} is a logic zero. Figure 2 The value of waveform 252 during global clock cycle CLK(i+2), etc. From block 514 , flow leaves block 512 and continues to block 516 .

[0079] At block 516, the multiplication unit is controlled to generate the first product signal with all bits equal to logic zero. Examples of multiplication units include, for example Figure 1A The multiplication units 115{0}-115{N-1}, etc. Examples of the first product signal include, for example Figure 1A The common product signals pub_prod{0}-pub_prod{N-1}, etc. are generated by the multiplication unit. One example of controlling the multiplication unit to generate the first product signal with all bits equal to logic zero is to Figure 1A The zeroing device 114 {1} etc. provides a public zeroing signal pub_all_0s {1}. More specifically, Figure 2 The reset signal pub_all_0s{n} (waveform 256) for the global clock cycle CLK(i+2) is equal to logic one. From block 516, the flow loops back to decision block 506 to iterate one or more of blocks 506-510 and blocks 512-522 for the next global clock cycle.

[0080] At block 518, the latching of the first L / F FF is not inhibited. Again, an example of the first L / F FF is Figure 1B The example in which the latching of the first L / F FF is not inhibited is discussed below in the context of block 520. Within block 518, the flow proceeds to block 520.

[0081] At block 520, a local clock signal is generated following the global clock. Again, an example of a local clock signal is Figure 1B The local clock signal CLK_XIN{n} is a clock signal of the same type as CLK_XIN{n}. An example of a global clock is Figure 1A-1B An example of a local clock signal CLK_XIN{n} following the global clock signal CLK is Figure 2 The values ​​of waveform 252 during global clock cycles CLK(i), CLK(i+1), and CLK(i+3), etc. From block 520, flow leaves block 518 and proceeds to block 522.

[0082] At block 522, the multiplication unit is controlled to generate the first product signal with all bits equal to all bits of the second product signal. Again, examples of the multiplication unit include, for example Figure 1A The multiplication units 115{0}-115{N-1}, etc. Similarly, examples of the first product signal include, for example Figure 1A The public product signals pub_prod{0}-pub_prod{N-1}, etc. Examples of the second product signal include, for example Figure 1A The private product signals prv_prod{0}-prv_prod{N-1}, etc. are controlled by the multiplication unit to generate the first product signal so that all bits are equal to all bits of the second product signal. Figure 1A The zeroing device 114 {1} etc. provides a public zeroing signal pub_all_0s {1}. More specifically, Figure 2 For global clock cycles CLK(i), CLK(i+1), and CLK(i+3), etc., the reset signal pub_all_0s{n} (waveform 256) is equal to logic zero. From block 522, the process loops back to decision block 506 to iterate one or more of blocks 506-510 and blocks 512-522 for the next global clock cycle.

[0083] Figure 6is a flow chart of method 600 according to some embodiments.

[0084] Method 600 is a method of operating a CIM system (eg, Figure 3A The method 600 includes blocks 604-610 and 630-636. The flow according to the method 600 starts from the start block 604 and continues to the decision block 606.

[0085] Decision block 606 and Figure 5 Similarly, block 608 and decision block 610 are corresponding to Figure 5 The same as block 508 and decision block 510. If the zeroing signal is equal to zero, the flow continues from the "yes" exit of decision block 610 and decision block 606, respectively, and proceeds to block 630. If the zeroing signal is not equal to zero, the flow exits from the "no" exit of decision block 610 and decision block 606, respectively, and proceeds to block 634.

[0086] At block 630, the latching of the first L / F FF is inhibited. An example of the first L / F FF is Figure 3B The L / F FF 306 {n} of the first L / F FF is inhibited, etc. An example in which latching of the first L / F FF is inhibited is discussed below in the context of block 632. Within block 630, the flow proceeds to block 632.

[0087] At block 632, a reset of the first L / F FF is triggered. Recalling that the L / F FF 306 includes the alpha lead FF 318 {n} and the alpha follow FF 320 {n}, an example of triggering a reset of the first L / F is, Figure 4 Each of waveforms 458 and 460 is logic zero at the rising edge of the global clock cycle CLK(i+1), and so on. It should be recalled that: Figure 4 The waveform 458 of is logic zero at the rising edge of the global clock cycle CLK(i+1), which indicates that the reset of the alpha-lead FF 318{n} is triggered to be true; Figure 4 The waveform 460 is logic zero at the rising edge of the global clock cycle CLK(i+1), which indicates that the reset triggering the alpha follower FF 320{n} is true; for each of the alpha lead FF 318{n} and the alpha follower FF 320{n}, the reset operation and the latch operation are mutually exclusive; for each of the alpha lead FF 318{n} and the alpha follower FF 320{n}, the reset operation actually suspends / inhibits the latch operation.

[0088] From block 632, flow exits block 630 and loops back to decision block 606 to iterate one or more of blocks 606-610 and blocks 630-632 for the next global clock cycle.

[0089] At block 634, the latching of the first L / F FF is inhibited. An example of the first L / F FF is Figure 3B The example in which the latching of the first L / F FF is not inhibited is discussed below in the context of block 636. Within block 634, the flow proceeds to block 636.

[0090] At block 636, the reset of the first L / F FF is not triggered. Recalling that the L / F FF 306 includes the alpha lead FF 318 {n} and the alpha follow FF 320 {n}, an example of not triggering the reset of the first L / F is, Figure 4 Each of waveforms 458 and 460 is a logic 1 at the rising edge of global clock cycles CLK(i), CLK(i+2), CLK(i+3), etc. Recall that: Figure 4 The waveform 458 of is logic one at the rising edges of the global clock cycles CLK(i), CLK(i+2), and CLK(i+3), which indicates that the reset of the alpha-lead FF 318{n} is not triggered to be true; Figure 4 The waveform 460 is logic one at the rising edge of the global clock cycles CLK(i), CLK(i+2) and CLK(i+3), indicating that the reset of the alpha follower FF 320{n} is not triggered and is true; for each of the alpha guide FF 318{n} and the alpha follower FF 320{n}, the reset operation and the latch operation are mutually exclusive; for each of the alpha guide FF 318{n} and the alpha follower FF 320{n}, not performing the reset operation does not actually pause / inhibit the latch operation.

[0091] From block 636, flow exits block 634 and loops back to decision block 606 to iterate one or more of blocks 606-610 and blocks 634-636 for the next global clock cycle.

[0092] In some embodiments, a computing-in-memory (CIM) system includes: a first leader-follower (L / F) flip-flop (FF) configured to receive a multi-bit data signal and generate a multi-bit output signal, the first L / F flip-flop including: a first leader flip-flop configured to receive the data signal and generate a signal first_Q_lead; and a first follower flip-flop configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing an output signal of the first L / F flip-flop; at least one bit b(k) of the data signal is equal to logic 1 in the i-1th cycle of a first clock signal, where i and k are corresponding integers; a multiplication unit configured to receive a multi-bit weight signal and the signal first_Q_follow, and generate a first product signal; and a pause unit configured to perform the following operations during the i-th cycle of the first clock signal, including: detecting that a first scenario in which all bits b(k) of the data signal are equal to logic zero is true; and when the first scenario is true, inhibiting latching performed by the first L / F flip-flop, and controlling the multiplication unit to generate a first product signal equal to logic zero.

[0093] In some embodiments, the multiplication unit includes: a multiplier configured to receive a weight signal and a signal first_Q_follow, and multiply the two to generate a second product signal; and the pause unit is further configured to control the multiplication unit to generate a first product signal equal to the second product signal when the first scenario is false.

[0094] In some embodiments, the pause unit is also configured to generate a first scenario state signal in an activated state when the first scenario is true; and the multiplication unit also includes a logic unit, which is configured to receive the second product signal and the first scenario state signal, and generate the first product signal equal to the second product signal or generate it with all bits equal to logic zero according to the first scenario state signal.

[0095] In some embodiments, for bit b(k) of the second product signal, relative to the first context state signal, the logic unit is configured to generate bit b(k) of the first product signal to have the following truth table:

[0096]

[0097] In some embodiments, the pause unit includes: a first scenario state detector, configured to generate a first scenario state signal in an activated state when the first scenario is true; and a second L / F trigger, configured to receive the first scenario state signal and generate a multi-bit output signal, the second L / F trigger including: a second guide trigger, configured to receive the first scenario state signal and generate a signal second_Q_guide, and a second follower trigger, configured to receive the signal second_Q_guide and generate a signal second_Q_follow representing the output signal of the second L / F trigger; the multiplication unit includes: a multiplier, configured to receive a weight signal and a signal first_Q_follow, and multiply the two to generate a second product signal; and the multiplication unit is also configured to generate the first product signal equal to the second product signal or to generate all bits equal to logic zero according to the first scenario state signal.

[0098] In some embodiments, the first context state detector is a logic NOR gate configured to receive all bits of the data signal and generate a first context state signal.

[0099] In some embodiments, the pause unit also includes an inhibition unit, which is configured to receive the first clock signal and the signal second_Q_lead, and generate a second clock signal based thereon: when the first scenario is true, it is in an inactive state; and when the first scenario is true, it follows the first clock signal; the first lead trigger is also configured to be enabled according to the second clock signal; and the first follow trigger is also configured to be enabled according to an inverted version of the second clock signal.

[0100] In some embodiments, the suppression unit includes a logic AND gate configured to receive the first clock signal and an inverted version of the signal Second_Q_Boot and generate the second clock signal.

[0101] In some embodiments, a method (of reducing power consumption of a compute-in-memory (CIM) system) includes: performing the following operations during an i-th cycle of a first clock signal: detecting a first scenario as true, wherein all bits b(k) of a multi-bit data signal are equal to logic zero, wherein i and k are corresponding integers; and when the first scenario is true, inhibiting a latching performance of a first leader-follower (L / F) flip-flop (FF), wherein during an i-1-th cycle of the first clock signal, at least one bit b(k) of the data signal is equal to logic 1, the first L / F flip-flop being configured to receive the data signal and generate a multi-bit output signal, the first LF flip-flop comprising a first leader flip-flop and a first follower flip-flop, the first leader flip-flop being configured to receive a digital signal and generate a signal first_Q_lead, the first follower flip-flop being configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing an output signal of the first leader-follow flip-flop; and when the first scenario is true, for a multiplication unit configured to receive a multi-bit weight signal and a signal first_Q_follow and generate a first product signal, controlling the multiplication unit to generate the first product signal with all bits equal to logic zero.

[0102] In some embodiments, the multiplication unit includes a multiplier configured to receive the weight signal and the signal first_Q_follow and multiply the two together to generate a second product signal; and the method also includes: when the first scenario is false, controlling the multiplication unit to generate a first product signal equal to the second product signal.

[0103] In some embodiments, the method further includes: generating a first scenario state signal in an activated state when the first scenario is true; and wherein: according to the first scenario state signal, controlling the multiplication unit to generate a first product signal resulting in the first product signal being equal to the second product signal or all bits being equal to logic zero.

[0104] In some embodiments, for bit b(k) of the second product signal, controlling the multiplication unit to generate the first product signal relative to the first context state signal causes bit b(k) of the first product signal to represent a truth table as shown below:

[0105]

[0106] In some embodiments, the method also includes: when the first scenario is true, generating a first scenario state signal in an activated state; and the CIM system also includes a second L / F trigger, which is configured to receive the first scenario state signal and generate a multi-bit output signal, the second L / F trigger includes a second guide trigger and a second follower trigger, the second guide trigger is configured to receive the first scenario state signal and generate a signal second_Q_guide, the second follower trigger is configured to receive the signal second_Q_guide and generate a signal second_Q_follow representing the output signal of the second L / F trigger, and the multiplication unit includes a multiplier, the multiplier is configured to receive a weight signal and a signal first_Q_follow and multiply the two to generate a second product signal; and the method also includes: according to the first scenario state signal, controlling the multiplication unit to generate the first product signal to be equal to the second product signal or to generate all bits equal to logic zero.

[0107] In some embodiments, inhibiting the latching capability includes performing a logical NOR operation on all bits of the data signal to generate the first context state signal.

[0108] In some embodiments, the method also includes: generating a second clock signal based on the first clock signal and the signal second_Q_lead: when the first scenario is true, it is in an inactive state; and when the first scenario is not true, it follows the first clock signal; selecting the first lead trigger according to the second clock signal; and selecting the first follow trigger according to the inverted version of the second clock signal.

[0109] In some embodiments, generating the second clock signal includes performing a logical AND operation on the first clock signal and an inverted version of signalSecond_Q_Boot to obtain the second clock signal.

[0110] In some embodiments, a computing-in-memory (CIM) system includes: a first leader-follower (L / F) flip-flop (FF) configured to receive a multi-bit data signal and generate a multi-bit output signal, the first L / F flip-flop including: a first leader flip-flop configured to receive the data signal and generate a signal first_Q_lead, and a first follower flip-flop configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing an output signal of the first L / F flip-flop; at least one bit b(k) of the data signal is equal to logic 1 during the i-1th cycle of a first clock signal, where i and k are corresponding integers; a multiplier configured to receive a multi-bit weight signal and the signal first_Q_follow and generate a first product signal; and a pause unit configured to perform the following operations during the i-th cycle of the first clock signal, including: detecting that a first scenario in which all bits b(k) of the data signal are equal to logic zero is true; and when the first scenario is true, triggering a reset operation performed by the first L / F flip-flop so that all bits of the signal first_Q_follow are equal to logic zero.

[0111] In some embodiments, the pause unit comprises a first context state detector configured to generate a first context state signal at its output node; and the first context state detector is further configured to generate the first context state signal in an activated state when the first context is true.

[0112] In some embodiments, the first context state detector is a logic NOR gate configured to receive all bits of the data signal and generate a first context state signal.

[0113] In some embodiments, each of the first lead trigger and the first follow trigger includes a reset node, which is coupled to the output node of the first scene state detector, so that the first scene state detector is also configured to trigger a reset operation by generating a first scene state signal in an activated state.

[0114] Those skilled in the art will readily appreciate that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the above description, those skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the attached claims and their equivalents.

Claims

1. A computing-in-memory system, comprising: A first leader-follower trigger is configured to receive a multi-bit data signal and generate a multi-bit output signal, wherein the first leader-follower trigger comprises: a first bootstrap flip-flop configured to receive the data signal and generate a signal first_Q_bootstrap; and a first follower flip-flop configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing the output signal of the first lead-follow flip-flop; In the (i-1)th cycle of the first clock signal, at least one bit b(k) of the data signal is equal to logic 1, where i and k are corresponding integers; a multiplication unit configured to receive a multi-bit weight signal and the signal first_Q_follow, and generate a first product signal; and A pause unit is configured to perform the following operations during the i-th cycle of the first clock signal, including: detecting as true a first scenario in which all bits b(k) of the data signal are equal to logic zero; and When the first scenario is true, inhibits latching performed by the first leader-follower flip-flop, and The multiplication unit is controlled to generate the first product signal equal to logic zero.

2. The in-memory computing system of claim 1, wherein: The multiplication unit comprises: a multiplier configured to receive the weight signal and the signal first_Q_follow, and multiply the two to generate a second product signal; and The pause unit is further configured to control the multiplication unit to generate the first product signal equal to the second product signal when the first scenario is false.

3. The in-memory computing system of claim 2, wherein: The pausing unit is further configured to: When the first scenario is true, generating a first scenario state signal in an activated state; as well as The multiplication unit also includes: The logic unit is configured to receive the second product signal and the first context state signal, and generate the first product signal to be equal to the second product signal or to have all bits equal to logic zero according to the first context state signal.

4. The in-memory computing system of claim 3, wherein: For the bit b(k) of the second product signal, and With respect to the first context state signal, the logic unit is configured to generate a bit b(k) of the first product signal to have the following truth table:

5. The in-memory computing system of claim 1 , wherein: The suspension unit comprises: A first context state detector configured to generate a first context state signal in an activated state when the first context is true; and A second lead-follow trigger is configured to receive the first context state signal and generate a multi-bit output signal, the second lead-follow trigger comprising: a second guidance trigger configured to receive the first context state signal and generate a signal second_Q_guidance, and a second follower flip-flop configured to receive the signal second_Q_lead and generate a signal second_Q_follow representing the output signal of the second lead-follow flip-flop; The multiplication unit comprises: a multiplier configured to receive the weight signal and the signal first_Q_follow, and multiply the two to generate a second product signal; and The multiplication unit is further configured to generate the first product signal to be equal to the second product signal or to have all bits equal to logic zero according to the first context state signal.

6. The in-memory computing system of claim 5, wherein: The pausing unit further comprises: A suppression unit is configured to receive the first clock signal and the signal second_Q_lead, and generate a second clock signal based thereon as: When the first scenario is true, being in an inactive state; and When the first scenario is true, following the first clock signal; The first boot flip-flop is further configured to be gated according to the second clock signal; and The first follower flip-flop is further configured to be gated according to an inverted version of the second clock signal.

7. A method for reducing power consumption of a computing system in a memory, the method comprising: In the i-th cycle of the first clock signal, the following operations are performed: detecting a first scenario as true in which all bits b(k) of the multi-bit data signal are equal to logic zeros, where i and k are corresponding integers; as well as When the first scenario is true, the latching performance of the first leader-follower flip-flop is inhibited, and during the (i-1)th cycle of the first clock signal, at least one bit b(k) of the data signal is equal to logic 1, The first lead-follow flip-flop is configured to receive the data signal and generate a multi-bit output signal, the first lead-follow includes a first lead flip-flop and a first follow flip-flop, the first lead flip-flop is configured to receive the digital signal and generate a signal First_Q_Lead, the first follow flip-flop is configured to receive the signal First_Q_Lead and generate a signal First_Q_Follow representing an output signal of the first lead-follow flip-flop; as well as When the first scenario is true, for a multiplication unit configured to receive a multi-bit weight signal and the signal First_Q_Follow and generate a first product signal, The multiplication unit is controlled to generate the first product signal so that all bits are equal to logic zero.

8. The method according to claim 7, wherein: The multiplication unit includes a multiplier configured to receive a weight signal and the signal first_Q_follow, and multiply the two together to generate a second product signal; as well as The method further comprises: When the first scenario is false, the multiplication unit is controlled to generate the first product signal equal to the second product signal.

9. The method according to claim 8, wherein: The method further comprises: When the first scenario is true, generating a first scenario state signal in an activated state; and in: According to the first context state signal, controlling the multiplication unit to generate the first product signal causes the first product signal to be equal to the second product signal or all bits to be equal to logic zero.

10. A computing-in-memory system, comprising: A first leader-follower trigger is configured to receive a multi-bit data signal and generate a multi-bit output signal, wherein the first leader-follower trigger comprises: a first bootstrap flip-flop configured to receive the data signal and generate a signal first_Q_bootstrap, and a first follower flip-flop configured to receive the signal first_Q_lead and generate a signal first_Q_follow representing an output signal of the first lead-follow flip-flop; At least one bit b(k) of the data signal is equal to logic 1 during the i-1th cycle of the first clock signal, where i and k are corresponding integers; a multiplier configured to receive a multi-bit weight signal and the signal first_Q_follow and generate a first product signal; and A pause unit is configured to perform the following operations during an i-th cycle of the first clock signal, including: detecting a first scenario as true in which all bits b(k) of the data signal are equal to logic zero; and When the first scenario is true, A reset operation performed by the first lead-follow flip-flop is triggered so that all bits of the signal first_Q_follow are equal to logic zero.

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