Method for highly selective silicon oxide removal

Abstract

A semiconductor processing method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing zone. The substrate may include exposed regions of a silicon and oxygen containing material. The substrate may include an exposed region of a backing material. The method may include providing a hydrogen-containing precursor to a semiconductor processing region. A method may include contacting a substrate with a fluorine-containing precursor and a hydrogen-containing precursor. The method may include selectively removing at least a portion of the exposed silicon and oxygen containing material.

Description

Cross-application in related fields

[0001] This case claims the benefit of priority to U.S. patent application Ser. No. 17 / 944,540, filed on Sept. 14, 2022, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0002] The present invention relates to semiconductor systems, processes, and equipment. More particularly, the present invention relates to systems and methods for selectively etching material layers on semiconductor devices. Background Art

[0003] Integrated circuits can be manufactured by processes that produce intricately patterned layers of material on a substrate surface. Producing patterned material on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring patterns in a photoresist into underlying layers, thinning layers, or thinning the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that processes one material faster than another, which facilitates, for example, pattern transfer processes or individual material removal. Such etching processes are referred to as being selective for a first material. Due to the diversity of materials, circuits, and processes, etching processes have been developed to have selectivity for a variety of materials. However, deposition processes that are continuously performed across a substrate typically utilize blanket coating or conformal filling.

[0004] As device geometries continue to shrink in next generation devices, selectivity plays a larger role when only a few nanometers of material are formed in a particular layer, especially when this material is critical in transistor formation. Many different etch process selectivities have been developed between various materials, although standard selectivities may no longer be appropriate for current and future device geometries. Additionally, when patterning and formation are performed elsewhere on the substrate, the latency for processing continues to increase based on the number of masking, formation, and removal operations required to form and protect the various critical dimensions of features throughout the device.

[0005] Therefore, there exists a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present invention. Summary of the invention

[0006] An example semiconductor processing method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region. The substrate may include an exposed region containing a silicon and oxygen material. The substrate may include an exposed region containing a liner material. The method may include providing a hydrogen-containing precursor to the semiconductor processing region. The method may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The method may include selectively removing at least a portion of the exposed silicon and oxygen-containing material.

[0007] In some embodiments, the fluorine-containing precursor may be or include hydrogen fluoride. The fluorine-containing precursor may be or include ammonia. The exposed area of ​​the silicon-and-oxygen-containing material may be an oxidized surface of the substrate. The exposed area of ​​the liner material may be a low-k spacer material. The temperature within the semiconductor processing chamber may be maintained at less than or about 200° C. The pressure within the semiconductor processing chamber may be maintained at less than or about 20 Torr. The method may include performing a thermal anneal after contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The thermal anneal may selectively remove portions of the exposed area of ​​the silicon-and-oxygen-containing material by sublimation.

[0008] Some embodiments of the present invention include a semiconductor processing method. The method may include i) providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate including an exposed region containing a silicon and oxygen material may be disposed in the processing region. The method may include ii) contacting the exposed region containing the silicon and oxygen material with the fluorine-containing precursor and the hydrogen-containing precursor. The method may include iii) forming a silicon and oxygen byproduct on the substrate. The method may include iv) annealing the substrate. Annealing may sublime at least a portion of the silicon and oxygen byproduct.

[0009] In some embodiments, operations i) to iv) may be cycles. The semiconductor processing method may include at least two cycles. Each cycle may be performed for less than or about 200 seconds. The portion containing silicon and oxygen byproducts may be removed with a selectivity greater than or about 3:1 relative to the exposed area of ​​the liner material. The flow rate of the fluorine-containing precursor may be less than or about 500 sccm. The flow rate of the hydrogen-containing precursor may be less than or about 100 sccm.

[0010] Some embodiments of the present invention include semiconductor processing methods. The method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate is disposed in the processing region. The substrate may include an exposed region containing a silicon and oxygen material. The substrate may include an exposed region of a liner material. The method may include providing a hydrogen-containing precursor to the semiconductor processing region. The method may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The method may include annealing the substrate. Annealing the substrate may cause at least a portion of the exposed region containing the silicon and oxygen material to sublime relative to the exposed region of the liner material.

[0011] In some embodiments, annealing the substrate may include positioning the substrate closer to a showerhead of a semiconductor processing chamber. The selectivity between exposed areas of the silicon-and-oxygen-containing material relative to exposed areas of the liner material may be greater than or about 3:1. The flow rate ratio of the fluorine-containing precursor relative to the hydrogen-containing precursor may be less than or about 10:1. The removal rate of the exposed areas of the silicon-and-oxygen-containing material may be greater than or about The processing region may be maintained plasma-free during semiconductor processing methods.

[0012] The invention described herein may provide many benefits over conventional systems and techniques. For example, the invention described herein may allow removal to be performed which may protect other features or materials on the substrate. In addition, the process may selectively remove silicon- and oxygen-containing materials relative to other exposed materials on the substrate. These and other embodiments, and many of their advantages and features, are described in more detail in the combined description and accompanying drawings that follow. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A further understanding of the nature and advantages of the disclosed invention may be realized by reference to the remaining portions of the specification and the accompanying drawings.

[0014] Figure 1 A top plan view of an exemplary processing system in accordance with an embodiment of the present technology is shown.

[0015] Figure 2A A schematic cross-sectional view of an exemplary processing system in accordance with an embodiment of the present technology is shown.

[0016] Figure 2B A detailed view of an exemplary showerhead in accordance with an embodiment of the present technology is shown.

[0017] Figure 3 A bottom plan view of an exemplary showerhead in accordance with embodiments of the present technology is shown.

[0018] Figure 4 Selected operations in a method of forming a semiconductor structure are illustrated in accordance with embodiments of the present technology.

[0019] Figure 5A-Figure 5C A schematic cross-sectional view of an exemplary substrate in accordance with an embodiment of the present technology is shown.

[0020] Several drawings are included as schematic diagrams. It will be understood that the drawings are for illustrative purposes and are not to be considered to scale unless clearly stated to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0021] In the accompanying drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished by a letter following the reference numeral, which distinguishes among the similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the letter. DETAILED DESCRIPTION

[0022] Diluted acids can be used in many different semiconductor processes for cleaning substrates and removing materials from these substrates. For example, diluted hydrofluoric acid can be an effective etchant for silicon oxide and other materials, and can be used to remove these materials from the substrate surface. After the etching or cleaning operation is completed, the acid can be dried from the wafer or substrate surface. The use of diluted hydrofluoric acid ("DHF") can be referred to as "wet" etching, and the diluent is usually water. Additional etching operations using precursors delivered to the substrate can be used. For example, plasma enhanced processing can also selectively etch materials by enhancing the precursors passing through the plasma to perform dry etching (including reactive ion etching).

[0023] Although wet etching using aqueous solutions or water-based processes can operate effectively for certain substrate structures, these processes may not be able to selectively remove silicon oxide and other materials from the substrate surface. For example, when the substrate includes metal materials, the use of water during the etching process may cause problems. For example, certain subsequent manufacturing processes (such as recessing gaps, removing oxide dielectrics, or other processes to remove oxygen-containing materials) may be performed after a certain amount of metallization has been formed on the substrate. If water is used in some way during etching, electrolytes may be generated, which, when contacting metallic materials, may cause galvanic corrosion between dissimilar metals, and the metals may be corroded or displaced in various processes. In addition, when such as removing silicon oxide from the substrate surface, conventional techniques using dilute acids suffer from selectivity performance issues and may undesirably remove liner and / or spacer materials.

[0024] The present invention overcomes these problems by developing a selective etching process for removal or cleaning. By utilizing a selective etching process performed in a specific apparatus, the described process can overcome the problems associated with conventional techniques by performing a dry etching process that can limit impact on the surface while performing a reaction that can promote removal of the target material. In addition, the materials and conditions used can allow for improved material removal relative to conventional techniques.

[0025] Although the remainder of the description will routinely identify a particular etching process utilizing the disclosed technology, it will be readily understood that the systems and methods can be equally applied to a variety of other etching and cleaning processes such as may occur in the described chamber. Therefore, the present invention should not be considered as being so limited to use with the described etching process alone. Prior to describing the operation of an exemplary processing sequence according to the present invention, this description will discuss one possible system and chamber for performing some removal operations utilizing the present technology.

[0026] Figure 1A top plan view of one embodiment of a processing system 100 of deposition, etching, baking, and curing chambers according to an embodiment is shown. In the illustration, a pair of front opening unification units (FOUPs) 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f, which are positioned in series sections 109a-c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f may be equipped to perform a number of substrate processing operations, including dry etching processes and selective deposition as described herein, as well as cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, orientation, and other substrate processing.

[0027] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing and / or etching dielectric films on substrate wafers. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit dielectric materials or metal-containing materials on substrates, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to etch dielectric films on substrates. Any one or more of the described processes may be performed in chambers that are distinguished in the manufacturing system shown in different embodiments.

[0028] In some embodiments, the chamber explicitly includes at least one etching chamber and at least one deposition chamber. By including these chambers on the processing side of the factory interface, all etching and deposition processes discussed later can be performed in a controlled environment. For example, a vacuum environment can be maintained on the processing side of the holding area 106 so that all chambers and transfers in the embodiment are maintained under vacuum. This can also limit water vapor and other air components from contacting the substrate being processed. It will be understood that additional configurations for deposition, etching, annealing, and curing chambers for dielectric films are contemplated by the system 100.

[0029] Figure 2AA cross-sectional view of an exemplary processing chamber system 200 with a plasma generation zone separated within the processing chamber is shown. During etching of films (e.g., titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), a process gas may flow into a first plasma zone 215 through a gas inlet assembly 205. A remote plasma system (RPS) 201 may optionally be included in the system and may process a first gas, which then travels through the gas inlet assembly 205. The gas inlet assembly 205 may include two or more different gas supply channels, wherein a second channel (not shown) may bypass the RPS 201 if included.

[0030] The cooling plate 203, the faceplate 217, the ion suppressor 223, the showerhead 225, and the pedestal 265 with the substrate 255 seated thereon are shown in accordance with an embodiment and may be included in accordance with an embodiment. The pedestal 265 or substrate support may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate, which may be operated to heat and / or cool the substrate or wafer during processing operations. The wafer support platter of the pedestal 265 (which may include aluminum, ceramic, or a combination of the foregoing) may also be resistively heated using embedded resistive heater elements to achieve relatively high temperatures, such as from up to or about 100° C. to above or about 1100° C.

[0031] The faceplate 217 may be in the shape of a pyramid, a cone, or other similar structure having a narrow top portion extending to a wide bottom portion. The faceplate 217 may additionally be flat as shown and include a plurality of through-channels for distributing process gases. Depending on the use of the RPS 201, the plasma generating gas and / or plasma exciting species may pass through a plurality of holes (e.g., Figure 2B ) for more uniform delivery into the first plasma region 215.

[0032] An exemplary configuration may include opening the gas inlet assembly 205 into a gas supply region 258 that is separated from the first plasma region 215 by a faceplate 217 such that gas / species flow through holes in the faceplate 217 into the first plasma region 215. Structural and operational features may be selected to avoid significant backflow of plasma from the first plasma region 215 back to the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The faceplate 217, or the conductive top portion of the chamber, and the showerhead 225 are shown with an insulating ring 220 located between the features, which allows an AC potential to be applied to the faceplate 217 relative to the showerhead 225 and / or the ion suppressor 223. The insulating ring 220 may be positioned between the faceplate 217 and the showerhead 225 and / or the ion suppressor 233 so that a capacitively coupled plasma (CCP) can be formed in the first plasma region. Baffles (not shown) may additionally be located in the first plasma zone 215 or coupled to the gas inlet assembly 205 to affect the flow of fluid entering this zone through the gas inlet assembly 205 .

[0033] The ion suppressor 223 may include a plate or other geometry defining a plurality of holes through the structure configured to suppress migration of ionic charged species away from the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 into an activated gas transfer region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may include a perforated plate having various hole configurations. These uncharged species may include highly reactive species that may be conveyed through the holes with a less reactive carrier gas. As described above, migration of ionic species through the holes may be reduced, and in some instances completely suppressed. Controlling the amount of ionic species passing through the ion suppressor 223 may advantageously provide increased control over the gas mixture that is brought into contact with the underlying wafer substrate, which in turn may increase control over the deposition and / or etching characteristics of the gas mixture. For example, adjustment of the ion concentration of the gas mixture may significantly change the etch selectivity, e.g., SiNx:SiOx etch ratio, Si:SiOx etch ratio, and the like. In alternative embodiments where deposition is performed, the balance for deposition of the dielectric material in a conformal-to-flowable manner may also be shifted.

[0034] The plurality of holes in the ion suppressor 223 can be configured to control the passage of activated gas (i.e., ions, radicals, and / or neutral species) through the ion suppressor 223. For example, the aspect ratio of the holes, or the hole diameter to length, and / or the geometry of the holes can be controlled so that the flow of ionic charged species in the activated gas traveling through the ion suppressor 223 is reduced. The holes in the ion suppressor 223 can include a tapered portion facing the plasma excitation region 215, and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and sized to control the flow of ionic species through the showerhead 225. An adjustable electrical bias can also be applied to the ion suppressor 223 as an additional means to control the flow of ionic species through the suppressor.

[0035] The ion suppressor 223 may be used to reduce or eliminate the amount of ionic charged species that travel from the plasma generation region to the substrate. Uncharged neutral and radical species may still pass through the openings in the ion suppressor to react with the substrate. It should be noted that in embodiments, complete elimination of ionic charged species in the reaction region surrounding the substrate may not be performed. In certain instances, ionic species tend to reach the substrate to perform etching and / or deposition processes. In these instances, the ion suppressor may help control the concentration of ionic species in the reaction region to a level that aids the process.

[0036] The showerhead 225 and ion suppressor 223 combination can allow plasma to exist in the first plasma region 215 to avoid directly exciting gases in the substrate processing region 233, but still allow excited species to travel from the chamber plasma region 215 into the substrate processing region 233. In this way, the chamber can be configured to avoid plasma contacting the substrate 255 being etched. This can advantageously protect various complex structures and films patterned on the substrate, which can be damaged, displaced, or otherwise warped if directly contacted by the generated plasma. In addition, the etch rate of oxide species increases when the plasma is allowed to contact the substrate or near the level of the substrate. Therefore, if the exposed area of ​​the material is an oxide, the material can be further protected by maintaining the plasma away from the substrate.

[0037] The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the faceplate 217, the ion suppressor 223, the showerhead 225, and / or the pedestal 265 to generate a plasma in the first plasma region 215 or the processing region 233. The power supply may be configured to deliver an adjustable amount of power to the chamber depending on the process being performed. Such a configuration may allow a tunable plasma to be used in the process being performed. Unlike a remote plasma unit that typically presents functionality that is turned on or off, a tunable plasma may be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow the development of specific plasma characteristics so that precursors are dissociated in a specific manner to enhance the etch profile produced by these precursors.

[0038] Plasma may be ignited in the chamber plasma region 215 above the showerhead 255 or in the substrate processing region 233 below the showerhead 255. In an embodiment, the plasma formed in the substrate processing region 233 may be a DC bias plasma formed with the pedestal as an electrode. Plasma may exist in the chamber plasma region 215 to generate radical precursors from, for example, an incoming flow of a fluorine-containing precursor or other precursor. An AC voltage, typically in the radio frequency (RF) range, may be applied between a conductive top portion of the processing chamber (such as a face plate 217) and the showerhead 225 and / or the ion suppressor 223 to ignite plasma in the chamber plasma region 215 during deposition. The RF power source may generate a high RF frequency of 13.56 MHz, but other frequencies alone or in combination with the 13.56 MHz frequency may also be generated.

[0039] Figure 2B A detailed view 253 of features affecting the distribution of process gases through the panel 217 is shown. Figure 2A and Figure 2B As shown, the faceplate 217, the cooling plate 203, and the gas inlet assembly 205 intersect to define a gas supply region 258 into which a process gas may be delivered from the gas inlet 205. The gas may fill the gas supply region 258 and flow through the holes 259 in the faceplate 217 to the first plasma region 215. The holes 259 may be configured to direct the flow in a substantially unidirectional manner such that the process gas may flow into the processing region 233, but may partially or completely avoid flowing back into the gas supply region 258 after passing through the faceplate 217.

[0040] The gas distribution assembly used in the processing chamber section 200, such as the showerhead 225, may be referred to as a dual channel showerhead (DCSH) and is Figure 2BThe dual-pass showerhead can provide an etch process that allows for separation of the etchant outside of the processing region 233 to provide limited interaction of the etchant with chamber components and with each other before being delivered into the processing region.

[0041] The showerhead 225 may include an upper plate 214 and a lower plate 216. The plates may be coupled to one another to define a volume 218 between the plates. The plates may be coupled to provide a first fluid channel 219 through the upper and lower plates, and a second fluid channel 221 through the lower plate 216. The channels formed may be configured to provide fluid access from the volume 218 through the lower plate 216 solely via the second fluid channel 221, and the first fluid channel 219 may be fluidically isolated from the volume 218 and the second fluid channel 221 between the plates. The volume 218 may be fluidly accessed through the sides of the showerhead 225.

[0042] Figure 3 FIG. 3 is a bottom view of a showerhead 325 for use with a processing chamber according to an embodiment. The showerhead 325 may be used with Figure 2A The through-holes 365 showing a view of the first fluid channel 219 can have a variety of shapes and configurations to control and influence the flow of precursors through the showerhead 225. The small holes 375 showing a view of the second fluid channel 221 can be substantially evenly distributed over the surface of the showerhead, even in the middle of the through-holes 365, and can help provide more uniform mixing of the precursors as they exit the showerhead compared to other configurations.

[0043] Figure 4 A method 400 of forming a semiconductor structure is illustrated, many of the operations of which may be performed, for example, in the chamber 200 described previously. The method 400 may include one or more operations prior to the initiation of the method, including front-end processing, polishing, cleaning, deposition, etching, or any other operations that may be performed prior to the operations described. The method may include several optional operations as represented in the figures, which may or may not be explicitly related to the method according to the present invention. For example, many of the operations are described to provide a broader scope of structural information, but are not critical to the present invention, or may be performed by alternative methods, as will be discussed further below. The method 400 describes a method 400 diagrammatically shown in FIG. Figure 5A-Figure 5C The operations in the figure will be described in conjunction with the operations of method 400. It will be understood that Figures 5A-5CThe figure depicts only a partial schematic view, and the substrate may contain any number of transistor segments having aspects as depicted in the figure. The operations of method 400 may be performed to form a bottom insulating layer to avoid leakage current through the bottom nanowire channel. The operations of method 400 may also be performed to limit or eliminate RIE and / or ion implantation processes, and avoid damaging silicon-containing surfaces for defect-free source or drain formation. The operations of method 400 may further be performed to limit or eliminate masking operations and / or RIE processes, and reduce processing latency.

[0044] like Figure 5A As shown in , method 400 may begin at optional operation 405 by forming a multilayer structure over substrate 505 and by performing post-processing of structure 500. Substrate 505 may be made of or contain silicon or some other semiconductor substrate material. The multilayer structure may include layers of different silicon-containing materials. The multilayer structure may include polysilicon material 510. Polysilicon material 510 may be formed on substrate 505. Silicon nitride material 515 may be formed over polysilicon material 510. Oxide material 520 may be formed over silicon nitride material 515. Oxide material 520 may include, for example, silicon oxide or any other oxide material. Liner material 525, or spacer material, may be formed over substrate 505, polysilicon material 510, silicon nitride material 515, and oxide material 520. Liner material 525 may be, for example, a silicon- and nitrogen-containing material. In an embodiment, the liner material may be silicon nitride. In other embodiments, the liner material 525 may be a low dielectric constant material, such as silicon oxynitride (SiON) or silicon oxycarbonitride (SiOCN). As will be discussed in more detail later, the multi-layer structure may be developed into substantially various transistor structures.

[0045] Still at optional operation 405, post-forming processing may be performed on structure 500. As previously discussed, front-end processing, polishing, cleaning, deposition, etching, or any other operation may be performed, such as Figure 5B As shown, for example, an etching operation (such as a reactive ion etching operation) may be performed to form a recess in the substrate 505. The reactive ion etching operation, which may utilize an oxygen-containing precursor, may form a silicon-and-oxygen-containing material 530 on the substrate 505. In an embodiment, the silicon-and-oxygen-containing material 530 may be an oxidized surface of the substrate 505. The reactive ion etching operation may also remove a portion of the liner material 515, such as the liner material 525 covering the substrate 505. The reactive ion etching operation may also damage or remove a portion of the liner material 525 covering the oxide material 520.

[0046] At operation 410, method 400 may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, such as chamber 200 described above. Figure 5BAs shown, substrate 505 may include exposed areas of silicon and oxygen containing material 530 and exposed areas of liner material 525. An example fluorine-containing precursor may be hydrogen fluoride (HF). Other sources of fluorine may be used in combination with or as a substitute for hydrogen fluoride. In some embodiments, the fluorine-containing precursor may be or include atomic fluorine, diatomic fluorine, hydrogen fluoride, nitrogen trifluoride, carbon tetrafluoride, xenon difluoride, and various other fluorine-containing precursors used or available in semiconductor processing.

[0047] The flow rate of the fluorine-containing precursor may be less than or about 500 sccm, and may be less than or about 450 sccm, less than or about 400 sccm, less than or about 350 sccm, less than or about 300 sccm, less than or about 250 sccm, less than or about 200 sccm, less than or about 150 sccm, less than or about 100 sccm, less than or about 75 sccm, less than or about 50 sccm, or less.

[0048] At operation 415, method 400 may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The hydrogen-containing precursor may also include nitrogen. Thus, the hydrogen-containing precursor may include an amine group. An amine group is defined as having nitrogen (typically represented as N:) with a lone pair of electrons. For example, the hydrogen-containing precursor may be or include ammonia, methylamine, ethylamine, diethylamine, methylethyldiamine, and various other hydrogen-containing precursors used or available in semiconductor processing.

[0049] The flow rate of the hydrogen-containing precursor may be less than or about 100 sccm, and may be less than or about 90 sccm, less than or about 80 sccm, less than or about 70 sccm, less than or about 60 sccm, less than or about 50 sccm, less than or about 40 sccm, less than or about 30 sccm, less than or about 20 sccm, less than or about 15 sccm, less than or about 10 sccm, or less. The flow rates of the fluorine-containing precursor and the hydrogen-containing precursor may be sufficiently low to minimize etching or removal of other materials in the structure 500 while etching and / or forming byproducts that will sublime in exposed areas of the silicon-and-oxygen-containing material 530.

[0050] As previously discussed, the flow rate of the fluorine-containing precursor may be, for example, less than or about 500 sccm and the flow rate of the hydrogen-containing precursor may be, for example, less than or about 100 sccm. The flow rate ratio of the fluorine-containing precursor relative to the hydrogen-containing precursor is less than or about 10:1. At a flow rate ratio greater than or about 10:1, the partial pressure of the fluorine-containing material may increase to a point where the selectivity in the removal of silicon- and oxygen-containing materials is reduced. Thus, the flow rate ratio of the fluorine-containing precursor relative to the hydrogen-containing precursor may be less than or about 9:1, less than or about 8:1, less than or about 7:1, less than or about 6:1, less than or about 5:1, less than or about 4:1, less than or about 3:1, less than or about 2:1, or less. However, an increased flow rate of the fluorine-containing precursor relative to the hydrogen-containing precursor may increase the etching rate of the silicon- and oxygen-containing materials. Thus, the flow rate ratio of the fluorine-containing precursor to the hydrogen-containing precursor may be greater than or about 2:1, greater than or about 3:1, greater than or about 4:1, greater than or about 5:1, or higher.

[0051] The fluorine-containing precursor and the hydrogen-containing precursor may be provided to the processing region separately, or in embodiments, may be mixed or combined prior to being provided to the processing region. The fluorine-containing precursor and the hydrogen-containing precursor may also be provided with any number of carrier gases, which may include nitrogen, helium, argon, or other inert gases.

[0052] At operation 420, method 400 may include contacting substrate 505 and the multilayer structure with a fluorine-containing precursor and a hydrogen-containing precursor. By contacting substrate 505 with the fluorine-containing precursor and the hydrogen-containing precursor, byproducts may be formed from exposed areas of silicon- and oxygen-containing material 530 on substrate 505. The fluorine-containing precursor and the hydrogen-containing precursor may interact with the exposed areas of silicon- and oxygen-containing material 530 on substrate 505 to form solid byproducts, which may include ammonium fluorosilicate ((NH4)2SiF6). Gaseous byproducts, which may include silicon tetrafluoride (SiF4) and hydrogen, such as diatomic hydrogen (H2), may also be formed, which may be outgassed. As discussed later, solid byproducts, such as fluorosilicic acid ((NH4)2SiF6), may be removed, such as by sublimation.

[0053] The processing state may affect the operations performed in method 400. Each of the operations of method 400 may be performed during a constant temperature in an embodiment, and the temperature may be adjusted during different operations in some embodiments. In some embodiments of the present invention, method 400 may be performed when the substrate, pedestal, and / or chamber temperature is less than or about 200° C., and may be performed when the temperature is less than or about 180° C., less than or about 160° C., less than or about 140° C., less than or about 120° C., less than or about 100° C., less than or about 80° C., less than or about 60° C., less than or about 40° C., less than or about 30° C., less than or about 20° C., less than or about 15° C., less than or about 10° C., or lower. The temperature may also be maintained within these ranges, within smaller ranges contained within these ranges, or at any temperature between any of these ranges.

[0054] The pressure within the semiconductor processing chamber can also affect the operations performed. Therefore, in some embodiments, the pressure can be maintained at less than about 20 Torr, less than about 15 Torr, less than about 10 Torr, less than about 9 Torr, less than about 8 Torr, less than about 7 Torr, less than about 6 Torr, less than about 5 Torr, less than about 4 Torr, less than about 3 Torr, less than about 2 Torr, less than about 1 Torr, less than about 0.8 Torr, less than about 0.6 Torr, less than about 0.4 Torr, less than about 0.2 Torr, or less. The pressure can also be maintained within these ranges, within a smaller range contained within these ranges, or any pressure between any of these ranges. Adding further control to the process, the partial pressure of the fluorine-containing precursor can be adjusted to adjust the selectivity. For example, when the partial pressure of the fluorine-containing precursor increases, the selectivity of the removal of the silicon-containing and oxygen-containing material 530 will decrease. Therefore, the partial pressure of the fluorine-containing precursor can be maintained at less than or about 0.05 Torr to maintain the selectivity of the removal of the silicon-containing and oxygen-containing material 530. For example, the partial pressure of the fluorine-containing precursor may be maintained at less than or about 0.045 Torr, less than or about 0.04 Torr, less than or about 0.035 Torr, less than or about 0.03 Torr, less than or about 0.025 Torr, less than or about 0.02 Torr, less than or about 0.015 Torr, less than or about 0.01 Torr, or less.

[0055] In an embodiment, method 400 may be a purely thermal operation. In such embodiments, the processing region is maintained free of plasma during method 400. It is also contemplated that the plasma may be formed from a fluorine-containing precursor and / or a hydrogen-containing precursor. The plasma of either or both of the precursors may be formed in the processing region of the semiconductor chamber, or alternatively, may be formed in a remote plasma system. However, unlike conventional techniques, the present invention may not require the formation of a plasma to effectively remove exposed silicon- and oxygen-containing materials selectively to other materials as described herein.

[0056] At optional operation 425, method 400 may include performing a thermal anneal after contacting substrate 505 with the fluorine-containing precursor and the hydrogen-containing precursor. The thermal anneal may selectively remove portions of exposed silicon-and-oxygen-containing materials, such as byproducts formed by contacting substrate 505 and silicon-and-oxygen-containing materials 530 with the fluorine-containing precursor and the hydrogen-containing precursor, by sublimation. During operation 425, substrate 505 may be positioned closer to a showerhead of a semiconductor processing chamber, such as by being lifted by lift pins in a substrate support. The showerhead may have a higher temperature than the substrate support, thereby increasing the temperature of the substrate during operation 425. Operation 425 may increase the temperature of the substrate to greater than or about 80°C, greater than or about 90°C, greater than or about 100°C, greater than or about 110°C, greater than or about 120°C, greater than or about 130°C, greater than or about 140°C, greater than or about 150°C, or more. During operation 425, one or more inert gases may be provided to the processing chamber to facilitate sublimation of the byproducts. For example, one or more of hydrogen (such as diatomic hydrogen), argon, neon, or xenon may be provided during operation 425.

[0057] like Figure 5C As shown, at operation 430, method 400 may include selectively removing at least a portion of the exposed silicon-and-oxygen-containing material 530. The removal rate of the exposed region of the silicon-and-oxygen-containing material 530 may be greater than or about and may be greater than or approximately Greater than or approximately and may be greater than or approximately Greater than or approximately and may be greater than or approximately Greater than or approximately and may be greater than or approximately However, in order to maintain high selectivity, the flow rate of the fluorine-containing precursor and / or the hydrogen-containing precursor may be provided to maintain the removal rate of the exposed area of ​​the silicon-and-oxygen-containing material 530 at less than or about Such as less than or about or less than or about

[0058] At optional operation 435, method 400 may include repeating operations 410-430 for one or more additional cycles. Operations 410-430 may define one cycle of method 400. At removal times greater than or about 200 seconds, selectivity may begin to decrease due to extended contact between the precursor and the liner material 525. Thus, each cycle may be less than or about 200 seconds, less than or about 190 seconds, less than or about 180 seconds, less than or about 170 seconds, less than or about 160 seconds, less than or about 150 seconds, less than or about 140 seconds, less than or about 130 seconds, less than or about 120 seconds, less than or about 110 seconds, less than or about 100 seconds, less than or about 90 seconds, less than or about 80 seconds, less than or about 70 seconds, less than or about 60 seconds, less than or about 50 seconds, less than or about 40 seconds, less than or about 30 seconds, less than or about 20 seconds, less than or about 10 seconds, or less. Operations 410-430 may be repeated at least two times, at least three times, at least four times, at least five times, at least six times, or more to remove a desired amount of exposed silicon-and-oxygen-containing material 530. The cyclic etching and byproduct sublimation process may inhibit etching or removal of liner material 525 and allow for highly selective etching or removal of silicon-and-oxygen-containing material 530.

[0059] By performing operations according to embodiments of the present invention, silicon-and-oxygen-containing materials may be selectively etched relative to other materials, including any of the materials previously described. For example, the present invention may selectively etch silicon-and-oxygen-containing materials relative to low dielectric constant materials, including SiON, SiOCN, or other dielectrics and / or silicon nitride, as previously mentioned. Embodiments of the present invention may etch silicon-and-oxygen-containing materials relative to low dielectric constant materials at a rate of at least about 1.5:1, and may etch silicon-and-oxygen-containing materials with a selectivity relative to exposed low dielectric constant materials that is greater than or about 2.0:1, greater than or about 2.5:1, greater than or about 3.0:1, greater than or about 3.5:1, greater than or about 4.0:1, greater than or about 4.5:1, greater than or about 5.0:1, or greater. Embodiments of the present invention may etch silicon-and-oxygen containing materials at a rate of at least about 30:1 relative to silicon nitride, and may etch silicon-and-oxygen containing materials at a selectivity relative to exposed silicon nitride of greater than or about 35:1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 55:1, greater than or about 60:1, or greater. For example, etches performed according to some embodiments of the present invention may etch silicon-and-oxygen containing materials while substantially or essentially maintaining any of the other silicon-containing materials described above.

[0060] In the foregoing description, for the purpose of explanation, many details have been described to provide an understanding of various embodiments of the present invention. However, it is apparent to those skilled in the art that certain embodiments can be practiced without some of these details or with additional details.

[0061] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative architectures, and equivalents may be used without departing from the spirit of the embodiments. In addition, several well-known processes and components have not been described to avoid unnecessary confusion of the present invention. Therefore, the above description should not be taken as limiting the scope of the present invention.

[0062] When a numerical range is provided, unless the context clearly indicates otherwise, it is understood that each intervening value between the upper and lower limits of the range to the smallest fraction of the unit of the lower limit is also expressly disclosed. Any narrower range between any stated value or unstated intervening value in the stated range and any other stated or intervening value in the stated range is covered. The upper and lower limits of those smaller ranges may be independently included or excluded in this range, and subject to any explicitly excluded limits in the stated range, ranges in which any limit is included, none of the limits are included, or both of the limits are also covered in the invention. When a stated range includes one or both of the limits, ranges excluding either or both of these included limits are also included.

[0063] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a material" includes a plurality of such materials and reference to "the precursor" includes reference to one or more precursors and equivalents thereof known to those of ordinary skill in the art, and so forth.

[0064] Furthermore, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including” when used in this specification and in the following claims are intended to indicate the presence of stated features, integers, components, or operations, but they do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing method comprising the following steps: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region, wherein the substrate includes an exposed region of a silicon-and-oxygen-containing material, and wherein the substrate includes an exposed region of a liner material; providing a hydrogen-containing precursor to the semiconductor processing region; exposing the substrate to the fluorine-containing precursor and the hydrogen-containing precursor; and At least a portion of the exposed region of the silicon and oxygen containing material is selectively removed.

2. The semiconductor processing method of claim 1, wherein the fluorine-containing precursor comprises hydrogen fluoride.

3. The semiconductor processing method of claim 1 wherein the hydrogen-containing precursor comprises ammonia.

4. The semiconductor processing method of claim 1, wherein the exposed area of ​​silicon and oxygen containing material is an oxidized surface of the substrate.

5. The semiconductor processing method of claim 1 wherein said exposed regions of said liner material comprise a low dielectric constant spacer material.

6. The semiconductor processing method of claim 1, wherein the temperature within the semiconductor processing chamber is maintained at less than or about 200°C.

7. The semiconductor processing method of claim 1, wherein the pressure within the semiconductor processing chamber is maintained at less than or about 20 Torr.

8. The semiconductor processing method according to claim 1, further comprising the steps of: A thermal anneal is performed after the substrate is contacted with the fluorine-containing precursor and the hydrogen-containing precursor, wherein the thermal anneal selectively removes the portion of the exposed region of silicon-and-oxygen-containing material by sublimation.

9. A semiconductor processing method comprising the following steps: i) providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region, the substrate comprising an exposed region of a silicon-and-oxygen-containing material; ii) contacting the exposed area of ​​the silicon-and-oxygen-containing material with the fluorine-containing precursor and the hydrogen-containing precursor; iii) forming silicon and oxygen containing byproducts on the substrate; and iv) annealing the substrate, wherein the annealing sublimes at least a portion of the silicon and oxygen containing byproducts.

10. The semiconductor processing method of claim 9, wherein operations i) to iv) comprise cycles, and wherein the semiconductor processing method comprises at least two cycles.

11. The semiconductor processing method of claim 10, wherein each cycle is performed for less than or about 200 seconds.

12. The semiconductor processing method of claim 9, wherein the portion of the silicon and oxygen containing byproducts is removed with a selectivity of greater than or about 3:1 relative to the exposed area of ​​liner material.

13. The semiconductor processing method of claim 9, wherein the flow rate of the fluorine-containing precursor is less than or about 500 seem.

14. The semiconductor processing method of claim 9, wherein the flow rate of the hydrogen-containing precursor is less than or about 100 seem.

15. A semiconductor processing method comprising the following steps: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region, wherein the substrate includes an exposed region of a silicon-and-oxygen-containing material, and wherein the substrate includes an exposed region of a liner material; providing a hydrogen-containing precursor to the semiconductor processing region; exposing the substrate to the fluorine-containing precursor and the hydrogen-containing precursor; and The substrate is annealed, wherein annealing the substrate sublimates at least a portion of the exposed region of the silicon-and-oxygen containing material relative to the exposed region of the liner material.

16. The semiconductor processing method of claim 15, wherein annealing the substrate comprises positioning the substrate closer to a showerhead of the semiconductor processing chamber.

17. The semiconductor processing method of claim 15, wherein the selectivity between the exposed regions of the silicon and oxygen containing material relative to the exposed regions of the liner material is greater than or about 3:

1.

18. The semiconductor processing method of claim 15, wherein a flow rate ratio of the fluorine-containing precursor to the hydrogen-containing precursor is less than or about 10:

1.

19. The semiconductor processing method of claim 15, wherein the removal rate of the exposed regions of the silicon and oxygen containing material is greater than or about 20. The semiconductor processing method of claim 15, wherein the processing region is maintained plasma-free during the semiconductor processing method.

Images