Substrate structuring method

Abstract

The invention relates to a method and an apparatus for structuring a semiconductor substrate. In one embodiment, a substrate structuring method includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portion of the resist layer is then transferred onto the substrate by micro-blasting to form desired features in the substrate while the unexposed or unablated portion of the resist layer shields the remainder of the substrate. The substrate is then exposed to an etch process and a lift-off process to remove the resist layer and release the carrier.

Description

[0001] This application is a divisional application of the invention patent application with an application date of April 6, 2020, application number "202080034737.9", and invention name "Substrate Structuring Method". Background Art Technical Field

[0002] Embodiments of the present disclosure generally relate to methods and apparatus for structuring semiconductor substrates. More specifically, embodiments described herein relate to methods and apparatus for structuring semiconductor substrates using micro-blasting and laser ablation techniques. Related technical notes

[0003] Due to the growing demand for miniaturized electronic devices and components, integrated circuits have evolved into complex 2.5D and 3D devices that can contain millions of transistors, capacitors, and resistors on a single chip. The development of chip design has led to greater circuit density, thereby increasing the processing power and speed of integrated circuits. The demand for faster processing power with greater circuit density has placed corresponding demands on the materials, structures, and processes used in the manufacture of such integrated circuit chips. However, in addition to these trends toward higher integration and higher performance, there has also been a pursuit to reduce manufacturing costs.

[0004] Conventionally, integrated circuit chips have been manufactured on organic packaging substrates due to the ease of forming features and connections via the features and the relatively low packaging manufacturing costs associated with organic composites. However, with the increase in circuit density and the further miniaturization of electronic components, the use of organic packaging substrates has become impractical due to the limitations of material structure resolution for maintaining device scale and associated performance requirements. Recently, passive silicon interposers placed on organic packaging substrates have been used as redistribution layers to manufacture 2.5D and 3D integrated circuits to compensate for certain limitations associated with organic packaging substrates. The use of silicon interposers is driven by the potential for high bandwidth density, low-power chip-to-chip communication, and heterogeneous integration requirements in advanced packaging applications. However, it is still difficult and costly to form features (such as through silicon vias (TSVs)) in silicon interposers. In particular, high costs are imposed by high aspect ratio through silicon via etching, chemical mechanical planarization, and semiconductor back-end process (BEOL) interconnections.

[0005] Therefore, there is a need in the art for improved substrate structuring methods for advanced packaging applications. Summary of the invention

[0006] In one embodiment, a method for structuring a substrate is provided. The method includes: bonding the substrate to a carrier with a first adhesive layer; bonding a resist layer to the substrate with a second adhesive layer; and patterning the resist layer with electromagnetic radiation. The method also includes: advancing powder particles against the patterned resist layer to form a structured pattern in the substrate, and exposing the substrate to an etching process to remove debris from the structured pattern and smooth one or more surfaces of the substrate. The resist layer is peeled off from the substrate by releasing the second adhesive layer, and the substrate is peeled off from the carrier by releasing the first adhesive layer.

[0007] In one embodiment, a method for substrate structuring is provided. The method includes forming a resist layer on a silicon solar substrate, patterning the resist layer by exposing the resist layer to electromagnetic radiation, propelling a stream of powder particles toward the substrate at high pressure to remove and remove material from the substrate and form a structured pattern, and exposing the substrate to an etching process to remove debris from the structured pattern and smooth one or more surfaces of the substrate.

[0008] In one embodiment, a method for structuring a substrate is provided. The method includes: bonding a first resist layer to a first surface of the substrate with a first adhesive layer; bonding a second resist layer to a second surface of the substrate with a second adhesive layer; and patterning the first resist layer and the second resist layer. The method also includes: advancing powder particles toward the first surface of the substrate to form one or more patterned structures in the first surface of the substrate, advancing powder particles toward the second surface of the substrate to extend the one or more patterned structures across the entire thickness of the substrate between the first surface and the second surface, and exposing the substrate to an etching process to remove debris from the substrate and smooth one or more surfaces of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more detailed description of the present disclosure briefly summarized above can be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope thereof, and other equivalent embodiments may be allowed.

[0010] Figure 1 A flow chart of a substrate structuring process according to embodiments described herein is illustrated.

[0011] FIG. 2A to FIG. 2F Schematically illustrated are cross-sectional views of a substrate at different stages of a substrate structuring process according to embodiments described herein.

[0012] FIG. 3A to FIG. 3FSchematically illustrated are cross-sectional views of a substrate at different stages of a substrate structuring process according to embodiments described herein.

[0013] FIG. 4A to FIG. 4E Schematically illustrated are cross-sectional views of a substrate at different stages of a substrate structuring process according to embodiments described herein.

[0014] Figure 5 A flow chart of a substrate structuring process according to embodiments described herein is illustrated.

[0015] FIG. 6A to FIG. 6D Schematically illustrated are cross-sectional views of a substrate at different stages of a substrate structuring process according to embodiments described herein.

[0016] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0017] The present disclosure relates to methods and apparatus for structuring semiconductor substrates. In one embodiment, a method for structuring a substrate includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portion of the resist layer is then transferred to the substrate by micro-sandblasting, while the unexposed or unablated portion of the resist layer shields the rest of the substrate. The substrate is then exposed to an etching process and a stripping process to remove the resist layer and release the carrier. In another embodiment, desired features are formed in the substrate by laser ablation.

[0018] Figure 1 A flow chart of a representative method 100 for structuring a substrate 102 is illustrated. FIG. 2A to FIG. 2F and FIG. 3A to FIG. 3F Picture shows Figure 1 Schematic cross-sectional views of the substrate 102 at different stages of the structuring process. FIG. 2A to FIG. 2F and FIG. 3A to FIG. 3F The reference will be included in Figure 1 and method 100. In addition, the method 100 for structuring a substrate 102 has multiple operations. The operations may be performed in any order or simultaneously (unless the context excludes the possibility), and the method may include one or more other operations that are performed before any of the defined operations, between two defined operations, or after all defined operations (unless the context excludes the possibility).

[0019] In general, the method 100 includes applying a resist film to a substrate 102 at operation 110. In some embodiments, the substrate 102 is optionally coupled to a carrier before applying the resist film. At operation 120, the method 100 includes exposing the substrate 102 to electromagnetic or laser radiation to pattern the resist film. At operation 130, the substrate 102 is micro-blasted to form structures such as blind holes, through holes, or cavities in the substrate 102. The method also includes etching the substrate 102 at operation 140 to remove debris and surface microcracks formed during the micro-blasting process, while the patterned resist film remains intact. Subsequently, the patterned resist layer is removed at operation 150, after which the substrate can be further exposed to a carrier stripping process at operation 160.

[0020] The substrate 102 is formed of any suitable substrate material, including but not limited to III-V compound semiconductor materials, silicon, crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, borosilicate glass, glass, sapphire, aluminum oxide, and ceramics. In one embodiment, substrate 102 is a packaging substrate. In one embodiment, substrate 102 is a single crystal p-type or n-type silicon substrate. In one embodiment, substrate 102 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, substrate 102 is a p-type or n-type silicon solar substrate. Unless otherwise stated, the embodiments and examples described herein are performed with a substrate having a thickness between about 50 μm and about 1000 μm, such as between about 90 μm and about 780 μm. For example, substrate 102 has a thickness between about 100 μm and about 300 μm, such as between about 110 μm and about 200 μm.

[0021] In an embodiment where the substrate 102 has a thickness of less than about 200 μm, such as a thickness of about 50 μm, the substrate 102 is coupled to a carrier 106 during the substrate structuring process 100. The carrier 106 provides mechanical support for the substrate 102 during the substrate structuring process 100 and prevents the substrate 102 from cracking. The carrier 106 is formed of any suitable chemically and thermally stable rigid material, including but not limited to glass, ceramic, metal, etc. The carrier 106 has a thickness between about 1 mm and about 10 mm, such as a thickness between about 2 mm and about 5 mm. In one embodiment, the carrier 106 has a textured surface and the substrate 102 is coupled to the textured surface. In another embodiment, the carrier 106 has a polished surface and the substrate 102 is coupled to the polished surface.

[0022] In one embodiment, the substrate 102 is coupled to the carrier 106 via an adhesive layer 108. The adhesive layer 108 is formed by any suitable temporary adhesive material, including but not limited to wax, glue and similar adhesives. The adhesive layer 108 can be applied to the carrier 106 by mechanical rolling, pressing, lamination, spin coating, scraping, etc. In one embodiment, the adhesive layer 108 is a water-soluble or solvent-soluble adhesive layer. In other embodiments, the adhesive layer 108 is a UV release adhesive layer. In yet other embodiments, the adhesive layer 108 is a thermal release adhesive layer. In such embodiments, the adhesive properties of the adhesive layer 108 are reduced when exposed to elevated temperatures, such as exposure to temperatures above 110°C, for example, temperatures above 150°C. The adhesive layer 108 may further include one or more films (not shown), such as a liner, a thermal release adhesive film, a base film, a pressure-sensitive film and other suitable layers.

[0023] At operation 110, corresponding to Figure 2A and Figure 3A , a resist film is applied to the substrate 102 to form a resist layer 104. The resist layer 104 is used to transfer a desired pattern to the substrate 102 during subsequent processing operations. After being patterned at operation 120, the resist layer 104 protects selected areas of the underlying substrate 102 during the micro-sandblasting process at operation 130.

[0024] The substrate 102 has one or more substantially planar surfaces on which the resist layer 104 may be formed. Figure 3A In the illustrated embodiment, the resist layer 104 is bonded to the substrate 102 via a resist bonding layer 109. The resist bonding layer 109 is formed of any suitable temporary bonding material, including but not limited to polyvinyl alcohol, triesters with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and other water-soluble or solvent-soluble materials. In one embodiment, the resist bonding layer 109 is formed of a different material than the bonding layer 108. In one embodiment, the resist bonding layer 109 is substantially similar in composition to the bonding layer 108. The resist bonding layer 109 can be applied to the substrate 102 by mechanical rolling, pressing, laminating, spin coating, doctor blade coating, or similar processes. In another embodiment, such as Figure 2A In the illustrated embodiment, the resist layer 104 is formed of a temporary adhesive material such as polyvinyl alcohol, thereby enabling the resist layer 104 to be directly applied and bonded to the surface of the substrate 102. The resist layer 104 may further include one or more layers, for example, a first resist layer and a second resist layer (not shown).

[0025] In one embodiment, such as Figure 2AIn the embodiment shown, the resist layer 104 is a photoresist. The resist layer 104 may include a solvent, a photoresist resin and a photoacid generator. The photoresist resin may be any positive photoresist resin or any negative photoresist resin. Representative photoresist resins include acrylates, novolac resins, poly(methyl methacrylate) and poly(olefin sulfone). Other photoresist resins may also be used. After exposure to electromagnetic radiation, the photoacid generator may generate charged species, such as acid cations and anions. The photoacid generator may also generate polarized species. The photoacid generator makes the resin sensitive to electromagnetic radiation. Representative photoacid generators include sulfonate compounds, such as, for example, sulfonated salts, sulfonated esters and sulfonyloxy ketones. Other suitable photoacid generators include onium salts, such as aryl diazonium salts, halogen onium salts, aromatic sulfonium salts and sulfoxide salts or selenium salts. Other representative photoacid generators include nitrobenzyl esters, s-triazine derivatives, ionic iodonium sulfonates, perfluoroalkane sulfonates, aryl trifluoromethanesulfonic acids and their derivatives and analogs, pyrogallol derivatives, and alkyl disulfones. Other photoacid generators may also be used.

[0026] In one embodiment, such as Figure 3A In the embodiment shown, the resist layer 104 is a laser-sensitive resist. The resist layer 104 can be formed of any material having a hardness suitable for laser ablation. For example, the resist layer 104 is formed of a material having a Shore A hardness value between about 40 and about 90, such as between about 60 and about 70. In one embodiment, the resist layer 104 is formed of a material having a Shore A hardness value of about 65. In a further embodiment, the resist layer 404 is formed of a material having a tensile strength between about 0.5 MPa and about 10 MPa, such as between about 1 MPa and about 8 MPa. For example, the resist layer 104 is formed of a material having a tensile strength of about 7 MPa. In some embodiments, the resist layer 104 is formed of a polydimethylsiloxane material. In other embodiments, the laser-sensitive resist layer 104 is formed of polyvinyl alcohol, triesters with 2-ethyl-2-(hydroxymethyl)-1,3-propylene glycol, and the like.

[0027] At operation 120, corresponding to Figure 2B and Figure 3B , the substrate 102 having the resist layer 104 formed thereon is exposed to electromagnetic radiation to pattern the resist layer 104. Figure 2B In the illustrated embodiment, the substrate 102 having the resist layer 404 formed thereon is exposed to electromagnetic radiation in the ultraviolet (UV) range. Portions of the resist layer 104 are selectively exposed, and portions of the resist layer 104 are selectively not exposed to the UV radiation. Figure 2BAs depicted, when exposed to UV radiation, the selectively exposed portions of the resist layer 104 become structurally weakened, while the selectively unexposed portions maintain their structural integrity. In one embodiment, a mask 112 having a desired pattern is formed on or adjacent to the resist layer 104 prior to UV radiation exposure. In some embodiments, the mask 112 is a mask sheet positioned between the resist layer 104 and a UV radiation source. The mask 112 is configured to transfer the desired UV radiation pattern to the resist layer 104, and the mask 112 is formed of any suitable polymer material, including but not limited to PTFE, PVDF, FEP, polyimide, etc.

[0028] exist Figure 3B In the illustrated embodiment, the substrate 102 having the resist layer 104 formed thereon is exposed to electromagnetic radiation generated by a laser source 303 instead of a UV radiation source. In this way, patterning is accomplished by targeted laser ablation without the use of a mask. The laser source 303 may be any suitable type of laser source for patterning the laser-sensitive resist layer 104. In some examples, the laser source 303 is a femtosecond green laser. In other examples, the laser source 303 is a femtosecond UV laser. The laser source 303 generates a continuous or pulsed laser beam for patterning the resist layer 104. For example, the laser source 303 may generate a pulsed laser beam having a frequency between about 100 kHz and about 1200 kHz, such as between about 200 kHz and about 1000 kHz. It is further contemplated that in some embodiments, the electromagnetic radiation at operation 120 may alternatively or additionally include an electron beam or an ion beam.

[0029] At operation 130, corresponding to Figure 2C and Figure 3C , a substrate 102 having a resist layer 104 formed thereon is micro-blasted to form a desired pattern in the substrate 102. During the micro-blasting process, a stream of powder particles 205 is propelled toward the substrate 102 under high pressure to remove exposed portions of the substrate 102 and / or layers formed on the substrate 102. The micro-blasting process is performed using any suitable substrate grinding system. In one embodiment, the powder particles 205 are propelled using a fluid stream of an inert gas, including but not limited to helium, argon, and nitrogen. In another embodiment, the powder particles 205 are propelled using a fluid stream of air.

[0030] The micro-sandblasting process is determined by the material properties of the powder particles 205, the momentum of the powder particles 205 that strike the exposed surface of the substrate 102, and the material properties of the substrate 102 together with (when applicable) the selectively exposed portion of the resist layer 104. In order to achieve the desired substrate patterning characteristics, the type and size of the powder particles 205, the size of the applicator nozzle of the grinding system and the distance to the substrate 102, the pressure used to propel the powder particles 205, and the density of the powder particles 205 in the fluid stream are adjusted. For example, the desired fluid pressure of the carrier gas used to propel the powder particles 205 toward the substrate 102 for the desired fixed micro-sandblasting equipment nozzle hole size can be determined based on the material of the substrate 102 and the powder particles 205. In one embodiment, the fluid pressure used to micro-blast the substrate 102 is generally between about 50 psi and about 150 psi, such as between about 75 psi and about 125 psi, to achieve a carrier gas and particle velocity between about 300 meters per second (m / s) and about 1000 m / s and / or a flow rate of about 0.001 cubic meter per second (m 3 / s) and about 0.002m 3 For example, the inert gas (e.g., nitrogen (N)) used to propel the powder particles 205 during micro-sandblasting may be 2 ), CDA, argon) is about 95 psi to achieve a carrier gas and particle velocity of about 2350 m / s. In one embodiment, the applicator nozzle for micro-blasting the substrate 102 has an inner diameter between about 0.1 millimeters (mm) and about 2.5 mm, and the inner diameter is set at a distance between about 1 mm and about 5 mm from the substrate 102, such as between about 2 mm and about 4 mm. For example, during micro-blasting, the applicator nozzle is set at a distance of about 3 mm from the substrate 102.

[0031] Typically, the micro-sandblasting process is performed with powder particles 205 having sufficient hardness and a high melting point to prevent the particles from sticking when in contact with the substrate 102 and / or any layers formed on the substrate 1020. For example, the micro-sandblasting process is performed with powder particles 205 formed of a ceramic material. In one embodiment, the powder particles 205 used in the micro-sandblasting process are made of aluminum oxide (Al2O3). 2 O 3 ). In another embodiment, the powder particles 205 are formed of silicon carbide (SiC). Other suitable materials for the powder particles 205 are also contemplated. The size range of the powder particles 205 is generally between about 15 μm and about 60 μm in diameter, such as between about 20 μm and about 40 μm in diameter. For example, the average particle size of the powder particles 205 is about 27.5 μm in diameter. In another example, the powder particles 205 have an average particle size of about 23 μm in diameter.

[0032] The effectiveness of the micro-blasting process at operation 120 further depends on the material properties of the resist layer 104. Using a material with too high a Shore A hardness may result in unwanted bouncing of the powder particles 205 between the sidewalls of the resist layer 104, thereby reducing the rate at which the powder particles 205 bombard the substrate 102 and ultimately reducing the effectiveness of the powder particles 205 in eroding or removing exposed areas of the substrate 102. Conversely, using a material with too low a Shore A hardness may result in unwanted adhesion of the powder particles 205 to the resist layer 104. It is contemplated that, as described above, the resist layer 104 material uses a Shore A hardness value between about 40 and about 90.

[0033] The resist layer 104 is such as Figure 2C In the depicted embodiment of the photoresist, the substrate 102 remains unexposed at the start of operation 130. Therefore, the powder particles 205 first bombard the surface of the resist layer 104, thereby removing and removing material from the UV-exposed and structurally weakened portions of the photoresist. The powder particles 205 eventually penetrate and remove the brittle UV-exposed portions to form voids in the resist layer 104, thereby exposing the desired areas of the substrate 102, while other areas are still shielded by the non-UV-exposed portions of the photoresist. Micro-sandblasting is then continued until the powder particles 205 remove and remove the desired amount or depth of material from the exposed areas of the substrate 102, thereby forming a desired pattern in the substrate 102.

[0034] In embodiments where the resist layer 104 is patterned by laser ablation, as Figure 3C As depicted, prior to micro-sandblasting at operation 130, desired areas of the substrate 102 have been exposed via voids in the resist layer 104. Thus, during the micro-sandblasting process, at operation 130, minimal or no removal of the resist layer 104 is expected. In one embodiment, the micro-sandblasting process is optional, and laser ablation alone may be used to pattern the substrate 102.

[0035] At operation 140, corresponding to Figure 2D and Figure 3D After micro-blasting the desired pattern into the substrate 102, the substrate 102 is exposed to an etching process. The etching process at operation 140 is used to smooth the surface of the substrate 102 and remove any unwanted mechanical defects on the surface of the substrate 102. The etching process is performed for a predetermined duration to flatten the surface of the substrate 102, especially the surface exposed to the micro-blasting process at operation 130. In one aspect, the etching process at operation 140 is used to remove unwanted debris remaining in the micro-blasting process at operation 130. During the etching process at operation 140, residual powder particles 205 adhered to the substrate 102 can be removed.

[0036] In one embodiment, the etching process at operation 140 is a wet etching process using a buffered etching process that preferentially etches the substrate surface above the material of the resist layer 104. For example, the buffered etching process may be selective to polyvinyl alcohol. In one embodiment, the etching process is a wet etching process using an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the wet etching process. In one embodiment, the substrate 102 is immersed in an HF etching aqueous solution for etching. In other embodiments, the substrate 102 is immersed in a KOH etching aqueous solution for etching. In one embodiment, the etching solution is heated to a temperature between about 40°C and about 80°C, such as between about 50°C and about 70°C, during the etching process. For example, the etching solution is heated to a temperature of about 60°C. The etching process may further be isotropic or anisotropic. In one embodiment, the etching process at operation 140 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes.

[0037] At operation 150, corresponding to Figure 2E and Figure 3E , the substrate 102 is exposed to a resist stripping process. The stripping process at operation 150 is used to strip the resist layer 104 from the substrate 102. In one embodiment, the resist layer 104 is stripped from the substrate 102 using a wet process by dissolving / solubilizing the resist adhesion layer 109 and / or the resist layer 104. Other types of etching processes are also contemplated for releasing the resist adhesion layer 109 and / or the resist layer 104. In one embodiment, a mechanical rolling process is used to strip the resist layer 104 from the substrate 102 by physically stripping the resist layer 104 or the resist adhesion layer 109. In one embodiment, an ashing process is used to remove the resist layer 104 from the substrate 102 by using, for example, an oxygen plasma assisted process.

[0038] At operation 160, corresponding to Figure 2F and Figure 3F , the substrate 102 is exposed to an optional carrier stripping process. The use of the carrier stripping process depends on whether the substrate 102 is coupled to the carrier 106 and the type of adhesive material used to couple the substrate 102 to the carrier 106. FIG. 2A to FIG. 2F and FIG. 3A to FIG. 3FAs depicted, in embodiments where the substrate 102 has a thickness of less than about 200 μm, the substrate is coupled to a carrier 106 for mechanical support during the substrate structuring process 100. In some embodiments, the substrate 102 is coupled to the carrier 106 via an adhesive layer 108. Thus, at operation 160, the substrate 102 coupled to the carrier 106 is exposed to a carrier peeling process to peel the substrate 102 from the carrier 106 by releasing the adhesive layer 108.

[0039] In one embodiment, the adhesive layer 108 is released by exposing the substrate 102 to a baking process. In one embodiment, the substrate 102 is exposed to a temperature between about 50° C. and about 300° C., such as between about 100° C. and about 250° C. For example, the substrate 102 is exposed to a temperature between about 150° C. and about 200° C., such as about 160° C., for a desired period of time to release the adhesive layer 108. In other embodiments, the adhesive layer 108 is released by exposing the substrate 102 to UV radiation.

[0040] Figure 2F and Figure 3F The structured substrate 102 is illustrated after the method 100 is completed. Figure 2F and Figure 3F The substrate 102 depicted in FIG. 1 has three structures 220 formed through the substrate 102. The method 100 is used to form patterned structures 220 in the substrate 102 having various desired depths, sizes, and shapes. In one embodiment, the depth of the structure 220 is equal to the thickness of the substrate 102, thereby forming a hole through two opposing surfaces of the substrate 102. In one embodiment, the structure 220 has a depth less than the thickness of the substrate 102, thereby forming a hole only on one surface of the substrate 102. For example, depending on the thickness of the substrate 102, the structure 220 formed in the substrate 102 may have a depth between about 10 μm and about 600 μm, such as a depth between about 25 μm and about 200 μm. In one embodiment, depending on the size of the substrate 102, the structure 220 has a lateral dimension between about 20 μm and about 15 mm, such as about 50 μm and about 5 mm. In one embodiment, the structure 220 formed in the substrate 102 has an ellipsoidal or conical shape. In another embodiment, the structure 220 formed in the substrate 102 has a rectangular parallelepiped shape. It is contemplated that the structure 220 formed by the method 100 can have any desired shape, size, and depth as permitted by the substrate 102.

[0041] FIG. 4A to FIG. 4E 1 shows a schematic cross-sectional view of a substrate 102 during an alternative structuring sequence similar to the above-described embodiment. FIG. 4A to FIG. 4EThe alternative sequence depicted in involves patterning the substrate 102 on two major opposing surfaces, thereby enabling increased efficiency during structuring of the substrate 102 . FIG. 4A to FIG. 4E The substrate structure sequence depicted in the reference is essentially as described in Figure 1 , FIG. 2A to FIG. 2F as well as FIG. 3A to FIG. 3F All the features and operations described. For example, Figure 4A Corresponding to operation 110 and Figure 2A and Figure 3A ; Figure 4B Corresponding to operation 120 and Figure 2B and Figure 3B ; Figure 4C Corresponding to operation 130 and Figure 2C and Figure 3C ; Figure 4D Corresponding to operation 140 and Figure 2D and Figure 3D ; Figure 4E Corresponding to operation 150 and Figure 2F and Figure 3F However, unlike the previous embodiments, FIG. 4A to FIG. 4E The depicted embodiment includes a substrate 102 having two resist layers 104 formed on opposing surfaces 405 , 407 of the substrate 102 , thereby enabling structuring operations to be performed on both surfaces 405 , 407 .

[0042] For example, at operation 120, Figure 4B As shown, after the resist layer 104 formed on the surface 405 of the substrate 102 is exposed to electromagnetic radiation for patterning, the substrate 102 is optionally flipped (e.g., inverted) so that the resist layer 104 on the opposite surface 407 of the substrate 102 can be exposed to electromagnetic radiation for patterning. Similarly, as Figure 4C As shown, after performing the micro-sandblasting process of operation 130 on the surface 405 of the substrate 102, the substrate 102 may be optionally flipped again so that micro-sandblasting may be performed on the opposite surface 407 of the substrate 102. By using two resist layers 104 on the opposite surfaces 405, 407 of the substrate 102 and performing the micro-sandblasting process on both surfaces, the taper of the structure formed through the entire thickness of the substrate 102 during micro-sandblasting may also be reduced or eliminated.

[0043] Figure 5 A flow chart of another representative method 500 for structuring a substrate 102 is illustrated. FIG. 6A to FIG. 6D The diagram shows Figure 5 Schematic cross-sectional views of the substrate 102 at different stages of the structuring process. Figure 5 The discussion of method 500 will include FIG. 6A to FIG. 6DSimilar to the above methods, the method 500 for structuring a substrate 102 has multiple operations. The operations may be performed in any order or simultaneously (unless the context excludes the possibility), and the method may include one or more other operations that are performed before any of the defined operations, between two defined operations, or after all defined operations (unless the context excludes the possibility).

[0044] Generally, the method 500 includes placing the substrate 102 on a support 606 of a laser ablation system at operation 510. In some embodiments, the substrate 102 is optionally coupled to a carrier prior to being placed on the support 606. At operation 520, the substrate 102 is exposed to laser radiation to pattern the substrate 102 and form desired features in the substrate 102. At operation 530, the substrate 102 is exposed to an etching process to remove debris and surface microcracks caused by the laser patterning. In embodiments where the substrate 102 is coupled to a carrier, after performing the etching process, the substrate 102 is further peeled from the carrier.

[0045] like Fig. 6A As depicted and corresponding to operation 510, a substrate 102, such as a solar substrate, is placed on a support 606 of a laser ablation system (not shown). The support 606 may be any suitable rigid and flat surface to provide mechanical support for the substrate 102 during laser ablation. In some embodiments, the support 606 includes an electrostatic chuck for electrostatically attaching the substrate 102 to the support 606. In some embodiments, the support 606 includes a vacuum chuck for vacuum attaching the substrate 102 to the support 606.

[0046] like Figure 6B As depicted and corresponding to operation 520, after placing the substrate 102 on the support 606, a desired pattern is formed in the substrate 102 by laser ablation. The laser ablation system may include any suitable type of laser source 603 for patterning the substrate 102. In some examples, the laser source 603 is an infrared (IR) laser. In some examples, the laser source 603 is a picosecond UV laser. In other examples, the laser source 603 is a femtosecond UV laser. In yet other examples, the laser source 603 is a femtosecond green laser. The laser source 603 generates a continuous or pulsed laser beam 607 for patterning the substrate 102. For example, the laser source 603 can generate a pulsed laser beam 607 having a frequency between 100 kHz and 1200 kHz, such as a frequency between 200 kHz and about 1000 kHz. The laser source 603 is configured to form any desired pattern and feature in the substrate 102, including cavities and through holes.

[0047] Similar to micro-sandblasting, the process of direct laser patterning the substrate 102 may cause unwanted mechanical defects, including chipping and cracking, on the surface of the substrate 102. Therefore, after the desired features are formed in the substrate 102 by direct laser patterning, the substrate 102 is exposed to an etching process substantially similar to the etching process described with reference to operation 140 at operation 530 to remove any remaining debris and smooth the surface of the substrate 102. FIG. 6C to FIG. 6D The substrate 102 is illustrated before and after performing an etching process that ends with the structured substrate 102 having three features 620 (eg, vias) formed therein.

[0048] The embodiments described herein advantageously provide improved substrate structuring methods for advanced integrated circuit packaging. By utilizing the above methods, high aspect ratio features can be formed on glass and / or silicon substrates at significantly reduced manufacturing costs, which can be used as an economical alternative to silicon interposers.

[0049] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A method for structuring a substrate, include: bonding the silicon substrate to a carrier board; Adsorbing the carrier plate and the silicon substrate onto a supporting bracket; patterning the substrate to form one or more cavities and one or more through-holes in the substrate; as well as The substrate is exposed to an etching process to remove debris from the cavities and vias, the etching process further smoothing one or more surfaces of the substrate. The method of claim 1 , wherein the substrate is patterned via laser ablation.

3. The method of claim 2, wherein the laser ablation is performed using an infrared (IR) laser. The method of claim 2 , wherein the laser ablation is performed using an ultraviolet (UV) laser. The method of claim 4 , wherein the laser ablation is performed using a picosecond UV laser. The method of claim 4 , wherein the laser ablation is performed using a femtosecond UV laser. The method of claim 2 , wherein the laser ablation is performed using a green laser. The method of claim 7 , wherein the laser ablation is performed using a femtosecond green laser.

9. The method of claim 2, wherein the laser ablation is performed using a pulsed laser beam having a frequency between about 100 kHz and about 1200 kHz.

10. The method of claim 9, wherein the laser ablation is performed using a pulsed laser beam having a frequency between about 200 kHz and about 1000 kHz.

11. The method of claim 2, wherein the laser ablation is performed using a continuous laser beam. 12 . The method of claim 1 , wherein the etching process is a wet etching process comprising an HF etching aqueous solution or a KOH etching aqueous solution.

13. The method of claim 1, wherein the etching process is a plasma-based dry etching process.

14. A method for structuring a substrate, include: Bonding the silicon substrate to a carrier via an adhesive; Adsorbing the carrier plate and the silicon substrate onto a supporting bracket; laser patterning the substrate to form one or more conical cavities and one or more conical through-holes in the substrate; exposing the substrate to an etching process to remove debris from the cavities and vias, the etching process further smoothing one or more surfaces of the substrate; as well as The substrate is peeled from the carrier by releasing the adhesive.

15. The method of claim 14, wherein the laser patterning is performed using an infrared (IR) laser.

16. The method of claim 15, wherein the laser patterning is performed using an ultraviolet (UV) laser.

17. The method of claim 14, wherein the laser patterning is performed using a pulsed laser beam having a frequency between about 100 kHz and about 1200 kHz.

18. The method of claim 14, wherein the laser patterning is performed using a continuous laser beam.

19. A method for structuring a substrate, include: bonding the silicon substrate to a carrier; Vacuuming the carrier plate and the silicon substrate onto a supporting bracket; laser patterning the substrate to form one or more conical cavities and one or more conical through-holes in the substrate; exposing the substrate to a wet etching process to remove debris from the cavities and vias, the etching process further smoothing one or more surfaces of the substrate; as well as The substrate is peeled off from the carrier.

20. The method of claim 19, wherein the laser patterning is performed using an infrared (IR) laser or an ultraviolet (UV) laser.

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