Semiconductor wafer boundary structure and manufacturing method thereof

Abstract

A semiconductor wafer boundary structure includes a first substrate on which a boundary region and a device region are defined, a first material layer covering a first surface and a side surface of the boundary region, and a second material layer covering a second surface and a side surface of the device region. And the second material layer covers the first material layer, and the section structure of the second material layer is gradually reduced in a direction from the element area to the boundary area.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing technology, and in particular to a method for improving the quality of wafer boundaries and reducing wafer cracking after bonding. Background Art

[0002] With the advancement of semiconductor technology, various semiconductor components are moving towards miniaturization. In current technology, the necessary components can be formed on two wafers respectively, and then the two wafers can be bonded together using hybrid bond technology. In this way, the difficulty of the manufacturing process can be effectively reduced and the density of the components can be increased.

[0003] However, there are still some shortcomings in the heterogeneous bonding technology. For example, the wafer structure after bonding may face some difficulties in the subsequent manufacturing process, resulting in a decrease in the yield of the manufacturing process. Therefore, this is also a problem that needs to be solved in this field. Summary of the invention

[0004] The present invention provides a semiconductor wafer boundary structure, comprising a first substrate, a boundary area and a component area defined on the first substrate, a first material layer covering a first surface and a side surface of the boundary area, and a second material layer covering the first material layer, wherein the cross-sectional structure of the second material layer presents a gentle decline from a direction from the component area to the boundary area.

[0005] The present invention further provides a method for manufacturing a semiconductor wafer boundary structure, comprising providing a first substrate, on which a component area and a boundary area are defined, and the first substrate includes a first component layer, providing a second substrate, on which a second component layer is included, bringing the first component layer and the second component layer into face-to-face contact, performing a boundary cutting step on the boundary area to remove a portion of the second substrate, forming a first surface in the boundary area of ​​the first substrate, forming a first material layer and a second material layer on the first surface, and performing a boundary etching step to remove a portion of the second material layer.

[0006] At the boundary of the bonded semiconductor structure, cracks are easily generated after cutting with a cutter. Therefore, the present invention is characterized in that, in addition to cutting the boundary with a cutter, an additional boundary etching step is performed. The boundary etching step is performed chemically, so that a flatter boundary profile can be formed, which can greatly reduce the probability of wafer cracks in the subsequent manufacturing process, which is beneficial to improving the overall manufacturing process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading the present invention. The specific embodiments of the present invention are explained in detail through the specific embodiments in this article and with reference to the corresponding drawings, and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the sizes of some features in some drawings may be deliberately enlarged or reduced.

[0008] Figure 1 It is a schematic diagram of the local cross-sectional structure near the boundary area of ​​the structure after two wafers are bonded by heterogeneous bonding technology;

[0009] Figure 2 for Figure 1 A schematic diagram of a structure after a planarization step;

[0010] Figure 3 for Figure 2 A schematic diagram of a structure after a cutting step is performed;

[0011] Figure 4 for Figure 3 A schematic diagram of a structure after a deposition step is performed;

[0012] Figure 5 for Figure 4 A schematic diagram of a structure after a boundary etching step is performed;

[0013] Figure 6 for Figure 5 A schematic diagram of the structure after forming a back wiring layer and back contact.

[0014] Explanation of symbols

[0015] 10: First base

[0016] 12: First component layer

[0017] 20: Second base

[0018] 22: Second component layer

[0019] 30: Bonding semiconductor structures

[0020] 40: First material layer

[0021] 42: Second material layer

[0022] BL: Backside wiring layer

[0023] BV: Backside contact

[0024] E: Boundary side

[0025] L: Length

[0026] P1: Grinding Steps

[0027] P2: Boundary cutting step

[0028] P3: Border etching step

[0029] R1: Border area

[0030] R2: Component area

[0031] T1: First top surface

[0032] T2: Top surface

[0033] T3: Top surface DETAILED DESCRIPTION

[0034] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0035] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.

[0036] Although the present invention uses the terms first, second, third, etc. to describe elements, components, regions, layers, and / or blocks (Section), it should be understood that these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and / or block from another element, component, region, layer, and / or block, and they themselves do not mean and represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

[0037] The term "about" or "substantially" mentioned in the present invention generally means within 20% of a given value or range, such as within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0038] The terms "coupled", "coupled", and "electrically connected" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0039] Although the invention of the present invention is described below by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and the omitted details belong to the knowledge scope of ordinary technicians in the relevant technical field.

[0040] Please refer to Figure 1 , Figure 1 The structure of two wafers after being bonded by heterogeneous bonding technology is shown, and a partial cross-sectional structure schematic diagram near the boundary area is shown. First, two wafers are provided for mutual bonding, wherein the lower wafer includes a first substrate 10, and the upper wafer includes a second substrate 20, a first component layer 12 is formed on the first substrate 10, and a second component layer 22 is formed on the second substrate 20, and the structure after bonding is defined as a bonded semiconductor structure 30. The first substrate 10 and the second substrate 20 described here are, for example, silicon substrates such as wafers, and the first component layer 12 and the second component layer 22 may include various electronic components, such as transistors, capacitors, inductors, memories, power amplifiers, multi-layer dielectric layers and metal wires. A heterogeneous contact structure (hybrid bond contact) is formed on the top of the first component layer 12 and the second component layer 22, and the two heterogeneous contact structures can touch each other to bond the two wafers. In other words, after the majority of components (i.e., the first component layer 12 and the second component layer 22) of the lower wafer and the upper wafer are completed, the upper wafer is turned over, and the heterogeneous contact structures of the lower wafer and the upper wafer are brought into contact with each other, and the two wafers are bonded to each other. In this way, since most of the components have been formed on the substrates of the two wafers, the manufacturing process of the semiconductor structure completed by the heterogeneous bonding technology is relatively simple compared to stacking multiple layers on the same wafer, and the component density can also be greatly improved.

[0041] Afterwards, if Figure 2 As shown, after the wafers are bonded to each other, it is planned to form a back wiring layer on the bonded first component layer 12 and the second component layer 22. The back wiring layer mentioned here includes, for example, contact holes, wire layers or contact pads, which are formed on the bonded first component layer 12 and the second component layer 22 and electrically connected thereto. The function of the back wiring layer is to electrically connect the bonded first component layer 12 and the second component layer with other components.

[0042] Please continue to refer to Figure 2 and Figure 3 , Figure 2 Drawing basis Figure 1 , a schematic diagram of the structure after a grinding step. Figure 3 Drawing basis Figure 2 The structure of the structure after a cutting step. In order to continue to form the back wiring layer, the Figure 2 As shown, a grinding step P1 is performed to reduce the thickness of the second substrate 20 to a certain extent (e.g., below 1000 microns, but not limited thereto), so that the contact structure in the back wiring layer, for example, can pass through the second substrate 20 to electrically connect the first component layer 12 and the second component layer 22. However, if only a grinding step such as chemical mechanical polishing (CMP) is used to grind the second substrate 20 and reduce its thickness, after the grinding step P1 is performed, the second substrate 20 will produce the following Figure 2 The protruding sharp corner portion T shown in the figure has a fragile structure and a large force arm length (such as Figure 2 If the protruding corner portion T exists in the structure during the subsequent manufacturing process, it will be easy to break and may even damage the second substrate 20 and the bonded component layer below.

[0043] Therefore, in order to avoid the protruding sharp corner portion T from existing in the structure and affecting the yield of the manufacturing process, Figure 3 As shown, a boundary cutting step P2 is performed, and the second substrate 20 of a boundary area R1 of the bonded semiconductor structure 30 is removed by a physical cutting method (for example, cutting with a knife). It is worth noting that the boundary area R1 mentioned here refers to the area at the boundary of the wafer, wherein some components may also be included in the boundary area R1, that is, the above-mentioned component layer may also extend into the boundary area R1, but because the boundary cutting step P2 will be performed in the boundary area R1, when the boundary cutting step P2 is performed, these components will also be removed together, so it can be understood that the components located in the boundary area R1 are sacrificial components. Opposite to the boundary area R1 is the component area R2, and the component layer in the component area R2 will not be removed by the boundary cutting step P2 in this step, so the components in the component area R2 will continue to be electrically connected to other components in the subsequent steps.

[0044] After the boundary cutting step P2 is performed, a first surface S1 is formed in the boundary region R1, wherein the first surface S1 is lower than the top surface T1 of the original first substrate 10. The first surface S1 is formed by the cutting step, and it may have an uneven profile. The reason is that the boundary cutting step P2 is a physical cutting using a tool or the like, and the fineness of the cutting step is relatively rough, so the surface may be uneven after cutting. If the material layer continues to be stacked on the uneven first surface S1 in the subsequent manufacturing process, stress accumulation will gradually occur, and when the stress accumulation is too much, it may cause the first substrate 10 to break.

[0045] Please continue to refer to Figure 4 , Figure 4 Drawing basis Figure 3 The structure of is a schematic diagram of the structure after a deposition step. Figure 4 As shown, a first material layer 40 and a second material layer are continuously formed and stacked on the first substrate 10, wherein the material of the first material layer 40 is, for example, a tetraethoxysilane (TEOS) layer, and the material of the second material layer 42 is, for example, silicon nitride, but not limited thereto. In addition, when the first material layer 40 is formed, it may cover the first surface S1 of the first substrate 10 and its boundary side E, the side walls of the first element layer 12 and the second element layer 22, and the top surface and side walls of the second substrate 20. However, after the first material layer 40 is formed, a planarization step (not shown) is also included to remove the first material layer 40 on the top surface of the second substrate 20 in the element region R2, and then the second material layer 42 is formed. Therefore, from the cross-sectional view, the second material layer 42 may be directly located on the top surface of the second substrate 20 in the element region R2, and located on the top surface of the first material layer 40 in the boundary region R1. In addition, from the cross-sectional view, the top surface T2 of the first material layer 40 is also flush with the top surface T3 of the second substrate 20.

[0046] The purpose of forming the first material layer here is mainly to protect the sidewalls of the first substrate 10. The first material layer 40 covers part of the sidewalls of the first substrate 10 to prevent it from being affected by the subsequent manufacturing process and cracking from the side of the first substrate 10, thereby affecting the yield of the semiconductor structure. The main purpose of forming the second material layer 42 is to serve as a dielectric layer for the subsequently formed components. For example, structures such as contact structures, wire layers or conductive pads may be further formed in the component region R2, and these structures can be formed in the dielectric layer.

[0047] In addition, since the first surface S1 may have an uneven profile when being formed, the uneven profile will also affect the first material layer 40 and the second material layer 42 formed above the first surface S1, thereby causing a second surface S2 of the second material layer 42 to also have an uneven profile.

[0048] The applicant has found that the presence of the above-mentioned uneven profile will increase the probability of the first substrate 10 being cracked when the subsequent components are stacked. Therefore, in the present invention, an additional boundary etching step is performed to flatten the uneven profile of the second surface S2. Figure 5 , Figure 5 Drawing basis Figure 4 The structure of is a schematic diagram of the structure after a boundary etching step. Figure 5 As shown, a boundary etching step P3 is performed, wherein the boundary etching step P3 in this embodiment is firstly carried out with sulfur hexafluoride (SF 6 ) for dry etching, and then cleaning with diluted hydrofluoric acid (DHF), the total time is about 30 seconds, but not limited to this. The above-mentioned boundary etching P3 is etched by chemical solvent, so compared with Figure 3 The etched components are physically cut, and the fineness of the components after etching will be higher. In addition, after etching, the cross-sectional structure of the second material layer 42 in the direction from the center to the boundary in the boundary area R1 (i.e., the direction from the component area R2 to the boundary area R1) gradually becomes thinner, that is, the thickness of the second material layer 42 gradually becomes thinner from the center to the boundary of the wafer. This gradually thinning cross-sectional structure is smoother, has a better protection effect on the wafer boundary, and is not easy to cause the wafer to break due to the protruding sharp corners.

[0049] In addition, according to the experimental results of the applicant, the roughness of the surface of the second material layer 42 near the boundary of the semiconductor structure formed by this step is significantly reduced, thereby effectively reducing the probability of wafer breakage in subsequent manufacturing processes and improving the yield of the overall semiconductor manufacturing process.

[0050] It is worth noting that in this embodiment, Figure 5 As shown, after the boundary etching step P3 is completed, a small portion of the second material layer 42 may still cover the side of the first material layer 40, that is, the surface of the first material layer 40 outside the boundary side surface E. Or in other embodiments, if the etching parameters are adjusted, the second material layer 42 covering the side wall of the first material layer 40 may be completely removed, that is, the side wall of the first material layer 40 is exposed, which also falls within the scope of the present invention.

[0051] Subsequent, such as Figure 6As shown, a back wiring layer BL and a back contact BV are formed on the second wafer 20, wherein the back contact BV passes through the second material layer 42 and the second substrate 20 and is electrically connected to the first component layer 12 and the second component layer 22. The material of the back wiring layer BL and the back contact BV is, for example, metal, such as tungsten, cobalt, copper, aluminum, gold, silver, etc., but not limited thereto. The back wiring layer BL can be used to connect other structures such as conductive pads, and to connect other electronic components or signal sources. Other features belong to the prior art in this field and will not be elaborated here.

[0052] In summary, the present invention provides a semiconductor wafer boundary structure, comprising a first substrate 10, on which a boundary region R1 and a component region R2 are defined, a first material layer 40 covers a first surface S1 and a side surface (boundary side surface E) of the boundary region R1, and a second material layer 42 covers the first material layer 40, wherein the cross-sectional structure of the second material layer 42 shows a gentle decline from a direction from the component region R2 to the boundary region R1.

[0053] In some embodiments of the present invention, the cross-sectional structure of the first material layer 40 on the first surface S1 is flat in a direction from the device region R2 to the boundary region R1 .

[0054] In some embodiments of the present invention, a device layer (ie, a bonding structure of the first device layer 12 and the second device layer 22 ) is further included in the device region R2 on the first substrate 10 .

[0055] Some embodiments of the present invention further include a second substrate 20 located on the device layer ( 12 + 22 ).

[0056] In some embodiments of the present invention, the materials of the first substrate 10 and the second substrate 20 both include silicon.

[0057] In some embodiments of the present invention, a thickness of the second substrate 20 is smaller than a thickness of the first substrate 10 .

[0058] In some embodiments of the present invention, the first material layer 40 directly contacts one side of a portion of the component layer (ie, the bonding structure between the first component layer 12 and the second component layer 22 ).

[0059] In some embodiments of the present invention, the second material layer 42 further covers the second substrate 20 in the device region R2 .

[0060] In some embodiments of the present invention, a top surface S1 of the first substrate 10 in the boundary region R1 is lower than a top surface T1 of the first substrate 10 in the device region.

[0061] In some embodiments of the present invention, the first material layer 40 includes a tetraethoxysilane (TEOS) layer, and the second material layer 42 includes silicon nitride.

[0062] The present invention further provides a method for manufacturing a semiconductor wafer boundary structure, comprising providing a first substrate 10, on which a device region R2 and a boundary region R1 are defined, and the first substrate 10 includes a first device layer 12, providing a second substrate 20, on which a second device layer 22 is included, the first device layer 12 and the second device layer 22 are brought into face-to-face contact, a boundary cutting step P2 is performed on the boundary region R1 to remove a portion of the second substrate 20, and a first surface S1 is formed in the boundary region R1 of the first substrate 10, a first material layer 40 and a second material layer 42 are formed on the first surface S1, and a boundary etching step P3 is performed to remove a portion of the second material layer.

[0063] In some embodiments of the present invention, the boundary etching step P3 includes first etching with sulfur hexafluoride (SF 6 ) for etching and then cleaning with diluted hydrofluoric acid (DHF).

[0064] In some embodiments of the present invention, the boundary cutting step P2 is performed by using a cutter to perform a physical cutting to remove a portion of the first substrate 10 , a portion of the first device layer 12 , and a portion of the second device layer 22 , and form the first surface S1 .

[0065] In some embodiments of the present invention, after the first device layer 12 and the second device layer 22 are brought into face-to-face contact and before the boundary cutting step P2 is performed, a grinding step P1 is further performed to reduce the thickness of the second substrate 20 .

[0066] In some embodiments of the present invention, after the boundary etching step P3 , a back contact BV is further formed, penetrating through the second material layer 42 and the second substrate 20 , and electrically connected to the second device layer 22 .

[0067] In some embodiments of the present invention, a circuit layer (back wiring layer BL) is further formed on the second material layer 42 and electrically connected to the back contact layer BV.

[0068] In some embodiments of the present invention, the first material layer 40 directly contacts a portion of a side edge of the first component layer 12 .

[0069] In some embodiments of the present invention, a top surface of the first surface S1 is lower than a top surface T1 of the first substrate 10 in the device region R2 .

[0070] In summary, the boundary of the bonded semiconductor structure is prone to cracking after being cut with a cutter. Therefore, the present invention is characterized in that, in addition to cutting the boundary with a cutter, an additional boundary etching step is performed. The boundary etching step is performed chemically, so that a flatter boundary profile can be formed, which can greatly reduce the probability of wafer cracking in the subsequent manufacturing process, which is beneficial to improving the overall manufacturing process yield.

[0071] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor wafer boundary structure, comprising: A first substrate, wherein a boundary region and a device region are defined on the first substrate; A first material layer covers the first surface and side surfaces of the boundary area; as well as The second material layer covers the first material layer, wherein the cross-sectional structure of the second material layer shows a gentle decline from the device region to the boundary region. 2 . The semiconductor wafer boundary structure as claimed in claim 1 , wherein a cross-sectional structure of the first material layer on the first surface is flat in the direction from the device region to the boundary region. 3 . The semiconductor wafer boundary structure as claimed in claim 1 , further comprising a device layer located in the device region on the first substrate. 4 . The semiconductor wafer boundary structure as claimed in claim 3 , further comprising a second substrate located on the device layer. 5 . The semiconductor wafer boundary structure as claimed in claim 4 , wherein the first substrate and the second substrate are both made of silicon. 6 . The semiconductor wafer boundary structure as claimed in claim 4 , wherein a thickness of the second substrate is smaller than a thickness of the first substrate. 7 . The semiconductor wafer boundary structure as claimed in claim 3 , wherein the first material layer directly contacts a portion of a side edge of the device layer. 8 . The semiconductor wafer boundary structure as claimed in claim 1 , wherein the second material layer further covers the second substrate in the device region. 9 . The semiconductor wafer boundary structure as claimed in claim 1 , wherein a top surface of the first substrate in the boundary region is lower than a top surface of the first substrate in the device region. 10 . The semiconductor wafer boundary structure as claimed in claim 1 , wherein the first material layer comprises a tetraethoxysilane (TEOS) layer, and the second material layer comprises silicon nitride.

11. A method for manufacturing a semiconductor wafer boundary structure, comprising: Providing a first substrate, wherein a device region and a boundary region are defined on the first substrate, and the first substrate includes a first device layer; Providing a second substrate, wherein the second substrate comprises a second element layer; Placing the first component layer in face-to-face contact with the second component layer; Performing a boundary cutting step on the boundary area to remove a portion of the second substrate and form a first surface in the boundary area of ​​the first substrate; forming a first material layer and a second material layer on the first surface; as well as A boundary etching step is performed to remove a portion of the second material layer.

12. The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 11, wherein the boundary etching step comprises first etching with sulfur hexafluoride (SF 6 ) for etching and then cleaning with diluted hydrofluoric acid (DHF). 13 . The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 11 , wherein after the boundary etching step, a cross-sectional structure of the second material layer shows a gentle decline from the device region to the boundary region. 14 . The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 11 , wherein the boundary cutting step is performed by physically cutting with a cutter to remove a portion of the first substrate, a portion of the first device layer and a portion of the second device layer to form the first surface.

15. The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 11, wherein after the first device layer and the second device layer are brought into face-to-face contact and before the boundary cutting step, a grinding step is further performed to reduce the thickness of the second substrate. 16 . The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 11 , wherein the first material layer comprises a tetraethoxysilane (TEOS) layer, and the second material layer comprises silicon nitride. 17 . The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 11 , wherein after the boundary etching step, it further comprises forming a back contact, penetrating through the second material layer and the second substrate, and electrically connecting to the second device layer. 18 . The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 17 , further comprising forming a circuit layer on the second material layer and electrically connecting the circuit layer to the back contact. 19 . The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 11 , wherein the first material layer directly contacts a portion of a side edge of the first device layer. 20 . The method for manufacturing a semiconductor wafer boundary structure as claimed in claim 11 , wherein a top surface of the first surface is lower than a top surface of the first substrate in the device region.

Images