Integrated circuit packaging structure

Abstract

The invention discloses an integrated circuit package structure. The integrated circuit packaging structure comprises a circuit substrate. The circuit substrate comprises a core board, a first inorganic dielectric layer, an organic dielectric layer and a solder mask layer. The core board has a first surface and a second surface opposite to each other. The first inorganic dielectric layer is disposed on the first surface of the core board. The organic dielectric layer is disposed on the second surface of the core board. The solder mask layer is disposed on the organic dielectric layer. The solder mask layer is separated from the first inorganic dielectric layer through the organic dielectric layer and the core board.

Description

Technical Field

[0001] The invention relates to an integrated circuit packaging structure, in particular to a circuit substrate of the integrated circuit packaging structure. Background Art

[0002] In the current semiconductor packaging technology, in order to cope with the continuous increase in the operating frequency and power consumption of integrated circuit chips, as well as the requirements of multi-chip integrated packaging and multi-input / output (I / O) end chips, the operating frequency and wiring density of the packaging substrate must be increased accordingly. However, in the application of high-speed transmission (High Performance Computing, HPC) printed circuit boards, maintaining good reliability is becoming increasingly important.

[0003] Therefore, in this technical field, an improved packaging substrate is needed. Summary of the invention

[0004] The embodiment of the present invention provides an integrated circuit packaging structure. The integrated circuit packaging structure includes a circuit substrate. The circuit substrate includes a core board, a first inorganic dielectric layer, an organic dielectric layer and a solder mask. The core board has a first surface and a second surface opposite to each other. The first inorganic dielectric layer is arranged on the first surface of the core board. The organic dielectric layer is arranged on the second surface of the core board. The solder mask is arranged on the organic dielectric layer. The solder mask is separated from the first inorganic dielectric layer by the organic dielectric layer and the core board. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In order to make the features and advantages of the present invention more clearly understood, different embodiments are described in detail below with reference to the accompanying drawings:

[0006] Figure 1 A schematic cross-sectional view of a circuit substrate of an integrated circuit packaging structure according to some embodiments of the present invention;

[0007] Figure 2 A schematic cross-sectional view of a circuit substrate of an integrated circuit packaging structure according to some embodiments of the present invention;

[0008] Figure 3 A schematic cross-sectional view of a circuit substrate of an integrated circuit packaging structure according to some embodiments of the present invention;

[0009] Figure 4 A schematic cross-sectional view of a circuit substrate of an integrated circuit packaging structure according to some embodiments of the present invention;

[0010] Figure 5 Schematic cross-sectional view of integrated circuit packaging structures according to some embodiments of the present invention;

[0011] Figure 6 Schematic cross-sectional view of integrated circuit packaging structures according to some embodiments of the present invention;

[0012] Figure 7 Cross-sectional schematic diagram of an integrated circuit package structure according to some embodiments of the present invention;

[0013] Figure 8 Cross-sectional schematic diagram of an integrated circuit package structure according to some embodiments of the present invention;

[0014] Fig. 9 Cross-sectional schematic diagram of an integrated circuit package structure according to some embodiments of the present invention;

[0015] Fig.10 Cross-sectional schematic diagram of an integrated circuit package structure according to some embodiments of the present invention.

[0016] Symbol description

[0017] 100, 100-1, 100-2: Chip

[0018] 100a, 100-1a, 100-2a: Active surface

[0019] 102, 102-1, 102-2, 102-1A, 102-2A: Chip pad

[0020] 200: Core board

[0021] 200T: First surface

[0022] 200B: Second surface

[0023] 200V: Core conductive via

[0024] 210T, 210B: Inorganic dielectric layer

[0025] 212T, 212T’, 212B, 222, 262: Conductor

[0026] 214A: Conductive structure

[0027] 214T, 214B, 224, 264: Conductive via

[0028] 216, 216T’, 226: Pad

[0029] 220: Organic dielectric layer

[0030] 230, 240, 340, 440, 540: Redistribution structure

[0031] 250: Solder mask

[0032] 260: Stress relief dielectric layer

[0033] 280: Conductive bump

[0034] 290: Bridge element

[0035] 292:Bridge pad

[0036] 400A, 400B, 400C, 400D: Circuit board

[0037] 500,500A,500B,500C,500D,500E,500F: Integrated circuit packaging structure

[0038] D100,D120: Direction

[0039] T200, T210T, T210B, T220, T260: Thickness DETAILED DESCRIPTION

[0040] The present invention is described more fully below with reference to the accompanying drawings of embodiments of the present invention. However, the present invention may also be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the accompanying drawings may be exaggerated for clarity, and the same or similar reference numbers in the various drawings represent the same or similar elements.

[0041] 2.5D integrated circuit (IC) packaging usually uses an organic flip chip buildup substrate, and uses an interposer to connect the chip downward to the flip chip buildup substrate. The interposer is bonded to the chip through microbumps. The redistribution layout (RDL) lines and through holes of the interposer serve as the interconnect structure between the chip and the interposer. In addition, an underfill is used to fill the bottom of the bonded chip. In addition, the above structure is protected by a molding compound through a molding process. The protected structure is bonded to the flip chip buildup substrate through bumps, and the underfill is used again to fill the gap between the interposer and the flip chip buildup substrate to complete the 2.5D integrated circuit packaging.

[0042] There are many disadvantages in existing 2.5D integrated circuit (IC) packaging. For example, the manufacturing process of existing 2.5D integrated circuit (IC) packaging is very complicated, such as the need to perform a micro-bump manufacturing process for the chip. The bump manufacturing process for the interposer. The bottom glue filling manufacturing process for bonding the chip and the interposer, etc. In addition, it is necessary to reduce the parasitic capacitance and resistance caused by the bump effect as much as possible. Furthermore, there is still a large gap between the bumps of the organic build-up layer substrate, which cannot meet the chip miniaturization requirements. Even if the chip is placed accurately, problems such as chip shifting during the molding manufacturing process and wafer / panel stress caused during the thermal curing process will still occur. Therefore, in this technical field, an improved circuit substrate is needed to solve the aforementioned problems.

[0043] Figure 1 Schematic cross-sectional view of a circuit substrate 400A of an integrated circuit package structure 500 according to some embodiments of the present invention. In some embodiments, the circuit substrate 400A may include multiple layers of packaging substrates or interposers, the top and bottom surfaces of which may provide integrated circuit chips and conductive bumps mounted thereon, respectively. In the circuit substrate 400A, each layer of conductive layers may include a conductor, a ground layer, a power layer, or a combination thereof. The number of conductive layers of the circuit substrate 400A of the present invention may be determined according to settings and is not limited to the disclosed embodiments. Furthermore, Figure 1 The direction D100 indicated in the subsequent figures is defined as the horizontal direction (also regarded as the extending direction of the conductive wire / transmission line), and the direction D120 is defined as the vertical direction (also regarded as the extending direction of the via hole).

[0044] like Figure 1 As shown, the circuit substrate 400A may include a core board 200 , an inorganic dielectric layer 210T, an organic dielectric layer 220 and a solder mask 250 .

[0045] The core board 200 has a first surface 200T and a second surface 200B opposite to each other. In some embodiments, the first surface 200T may be a chip side surface, and the second surface 200B may be a conductive bump side (or solder ball side) surface. In some embodiments, the material of the core board 200 may include glass, ceramic, or glass ceramic. In an embodiment where the material of the core board 200 is glass, the coefficient of thermal expansion (CTE) of the core board 200 is between 3 ppm / ℃ and 9 ppm / ℃.

[0046] The core board 200 also has a core conductive through hole 200V. The core conductive through hole 200V runs through the core board 200, and the two ends of the core conductive through hole 200V can be aligned with the first surface 200T and the second surface 200B of the core board 200, respectively. In some embodiments, the core conductive through hole 200V can be a solid column or a hollow column. In some embodiments, the material of the core conductive through hole 200V can be a conductive metal such as copper or a copper alloy, and the core conductive through hole 200V can be formed using a drilling process and an electroplating process. In some embodiments, the core conductive through hole 200V can be a solid cylinder or a hollow cylinder filled with a plugging material. The plugging material includes a resin, silver glue, or ink.

[0047] In the embodiment where the core board 200 is made of glass, the core conductive via 200V may also be referred to as a through glass via (TGV) 200V. The through glass via 200V may be formed by a drilling process including laser drilling, ultrasonic drilling, micro electrical discharge machining (μ-EDM), micro powder blasting, or inductively coupled plasma reactive ion etching (ICP-RIE), a wet etching process, and a subsequent electroplating process.

[0048] like Figure 1 As shown, a plurality of inorganic dielectric layers 210T stacked on each other are disposed on the first surface 200T of the core board 200. In some embodiments, the inorganic dielectric layer 210T closest to the core board 200 is directly connected to the first surface 200T of the core board 200. In other words, there is no organic dielectric layer between the inorganic dielectric layer 210T and the first surface 200T of the core board 200.

[0049] In some embodiments, the thermal expansion coefficient of the inorganic dielectric layer 210T is similar to the thermal expansion coefficient of the integrated circuit chip (not shown) mounted on the circuit substrate 400A. For example, when the integrated circuit chip is a silicon chip (the thermal expansion coefficient of silicon is between 3 ppm / °C and 5 ppm / °C), the thermal expansion coefficient of the inorganic dielectric layer 210T may be between 3 ppm / °C and 5 ppm / °C. In some embodiments, the material of the inorganic dielectric layer 210T includes a silicon-containing inorganic dielectric material, such as silicon oxide (SiO x ), silicon nitride (SiN x), silicon carbide (SiCN), silicon oxynitride (SiON), silicon carbide (SiC), or a combination thereof. In addition, the inorganic dielectric layer 210T may be formed using a deposition process such as plasma assisted chemical vapor deposition (PECVD). Corresponding to the material and manufacturing process characteristics of the inorganic dielectric layer 210T, the thickness T210T of a single inorganic dielectric layer 210T may be less than or equal to 1% of the thickness T200 of the core board 200.

[0050] like Figure 1 As shown, a plurality of organic dielectric layers 220 stacked on each other are disposed on the second surface 200B of the core board 200. In this embodiment, the organic dielectric layer 220 closest to the core board 200 is directly connected to the second surface 200B of the core board 200. In other words, there is no inorganic dielectric layer between the organic dielectric layer 220 and the second surface 200B of the core board 200.

[0051] In some embodiments, the thermal expansion coefficient of the organic dielectric layer 220 is between the thermal expansion coefficient of the printed circuit board (PCB) (not shown) mounted on the circuit substrate 400A and the thermal expansion coefficient of the core board 200. For example, when the core board 200 is made of glass (the thermal expansion coefficient of glass is between 3 ppm / °C and 9 ppm / °C), the thermal expansion coefficient of the printed circuit board is between 15 ppm / °C and 30 ppm / °C, and the thermal expansion coefficient of the organic dielectric layer 220 may be between 9 ppm / °C and 25 ppm / °C. In some embodiments, the material of the organic dielectric layer 220 includes BT resin, epoxy resin, phenolic resin, CE resin, polycarbonate (PC), silicone elastomer, or a combination thereof. In addition, the organic dielectric layer 220 may be formed using a coating or lamination process. Corresponding to the material and manufacturing process characteristics of the organic dielectric layer 220 , the thickness T220 of a single organic dielectric layer 220 may be between 1% and 15% of the thickness T200 of the core board 200 .

[0052] In some embodiments, the inorganic dielectric layer 210T and the organic dielectric layer 220 may have the same number of layers or different numbers of layers, and are not limited to the disclosed embodiments.

[0053] The circuit substrate 400A further includes a plurality of conductive wires 212T alternately arranged with the inorganic dielectric layer 210T, a plurality of conductive holes 214T penetrating the inorganic dielectric layer 210T, and pads 216 arranged on the outermost conductive wires 212T (the conductive wires 212T farthest from the core board 200). Figure 1 As shown, the corresponding wires 212T, conductive vias 214T and pads 216 are connected to each other and to the corresponding core conductive vias 200V. In addition, the circuit substrate 400A further includes a ground layer and a power layer (not shown) surrounding each layer of the wires 212T and conductive vias (not shown) connecting different layers of the ground layer and the power layer. In some embodiments, the inorganic dielectric layer 210T, the wires 212T alternately arranged with the inorganic dielectric layer 210T, the conductive vias 214T penetrating the inorganic dielectric layer 210T and the pads 216 arranged on the outermost wire 212T form a rewiring structure 230.

[0054] Similarly, the circuit substrate 400A further includes a plurality of conductive wires 222 alternately arranged with the organic dielectric layer 220, a plurality of conductive holes 224 penetrating the organic dielectric layer 220, and pads 226 arranged on the outermost conductive wires 222 (the conductive wires 222 farthest from the core board 200). Figure 1 As shown, the corresponding wires 222, conductive holes 224 and pads 226 are connected to each other and connected to the core conductive through hole 200V. In addition, the circuit substrate 400A also includes a ground layer and a power layer (not shown) surrounding the wires 222 of each layer and a conductive hole (not shown) connecting the ground layers and power layers of different layers. In some embodiments, the organic dielectric layer 220, the wires 222 alternately arranged with the organic dielectric layer 220, the conductive holes 224 penetrating the organic dielectric layer 220, and the pads 226 arranged on the outermost wires 222 form a rewiring structure 240. The rewiring structure 240 is connected to the rewiring structure 230 through the core conductive through hole 200V.

[0055] In some embodiments, corresponding to the material and manufacturing process characteristics of the inorganic dielectric layer 210T and the organic dielectric layer 220, the wiring density of the redistribution structure 230 is greater than the wiring density of the redistribution structure 240. In addition, the line width and spacing of the conductive lines 222 of the redistribution structure 240 are greater than the line width and spacing of the conductive lines 212T of the redistribution structure 230. For example, the ratio of the line width of the conductive lines 222 to the line width of the conductive lines 212T may be between 2.5 and 100.

[0056] like Figure 1As shown, the solder mask 250 of the circuit substrate 400A is disposed on the organic dielectric layer 220 and covers a portion of the redistribution structure 240. In addition, the solder mask 250 is separated from the inorganic dielectric layer 210T by the organic dielectric layer 220 and the core board 200. The solder mask 250 may have one or more openings, which expose a portion of the pads 226 and may provide a location for forming subsequent conductive bumps or solder balls (not shown).

[0057] In some embodiments, the solder mask 250 is not symmetrically formed on the first surface 200T and the second surface 200B of the core board 200. Figure 1 As shown, the solder mask of the circuit substrate 400A is a single solder mask 250, which is only formed on the second surface 200B of the core board 200. The redistribution structure 230 is not covered by any solder mask. In other words, the redistribution structure 230 is not arranged between the solder mask and the core board 200, and the surface of the pad 216 arranged on the outermost conductor 212T is coplanar with the surface of the outermost inorganic dielectric layer 210T.

[0058] In some embodiments, the solder mask 250 may include a solder mask material such as green paint, or may be an insulating material including polyimide, ABF film (ajinomoto build-up film), epoxy resin or acrylic resin or a composite of the two or polypropylene (PP). The solder mask 250 may be formed by coating, printing, laminating, laminating, etc.

[0059] Figure 2 FIG. 4 is a cross-sectional schematic diagram of a circuit substrate 400B of an integrated circuit package structure 500 (including integrated circuit package structures 500A, 500B, 500C, 500D, 500E, and 500F in subsequent figures) according to some embodiments of the present invention. Figure 1 The same or similar reference numerals represent the same or similar components. Figure 1 ) and the circuit substrate 400B( Figure 1 ) is that the inorganic dielectric layer of the circuit substrate 400B is formed on the opposite surface of the core board.

[0060] like Figure 2As shown, the circuit substrate 400B also includes an inorganic dielectric layer 210B. The inorganic dielectric layer 210B is disposed on the second surface 200B of the core board 200 and is disposed between the core board 200 and the organic dielectric layer 220. In the present embodiment, the top surface and the bottom surface of the inorganic dielectric layer 210B are directly connected to the second surface 200B of the core board 200 and the organic dielectric layer 220, respectively. In some embodiments, the thermal expansion coefficient of the inorganic dielectric layer 210B may be between 3 ppm / °C and 5 ppm / °C. The inorganic dielectric layer 210T and the inorganic dielectric layer 210B may include the same or similar materials. In some embodiments, the thickness T210B of a single inorganic dielectric layer 210B may be less than or equal to 1% of the thickness T200 of the core board 200. The thickness T210T of a single inorganic dielectric layer 210T may be the same as the thickness T210B of a single inorganic dielectric layer 210B. Alternatively, the thickness T210T of a single inorganic dielectric layer 210T may be different from the thickness T210B of a single inorganic dielectric layer 210B. In some embodiments, a multi-pass build-up process may be used to simultaneously form the same number of symmetrical inorganic dielectric layers 210T and inorganic dielectric layers 210B on both sides of the core board 200. Alternatively, a multi-pass build-up process may be used to form different numbers of inorganic dielectric layers 210T and inorganic dielectric layers 210B on both sides of the core board 200.

[0061] The circuit substrate 400B also includes a plurality of conductive wires 212B disposed between the core board 200 and the inorganic dielectric layer 210B and a plurality of conductive holes 214B penetrating the inorganic dielectric layer 210B. In some embodiments, the conductive wires 212T disposed on the inorganic dielectric layer 210T and 212B disposed on the inorganic dielectric layer 210B may have the same line width and spacing. The ratio of the line width of the conductive wire 222 disposed on the organic dielectric layer 220 to the line width of the conductive wire 212B may be between 2.5 and 100.

[0062] like Figure 2 As shown, the corresponding wire 212B and the conductive hole 214B are connected to each other, and are connected to the corresponding core conductive through hole 200V, the wire 222, the conductive hole 224 and the pad 226. In the present embodiment, the inorganic dielectric layer 210B, the wire 212B, the conductive hole 214B, the organic dielectric layer 220, the wire 222, the conductive hole 224 and the pad 226 disposed on the second surface 200B of the core board 200 can form a rewiring structure 340 together. The rewiring structure 340 can be connected to the rewiring structure 230 through the core conductive through hole 200V. In some embodiments, the wiring density of the rewiring structure 230 is greater than the wiring density of the rewiring structure 340.

[0063] The circuit substrates 400A and 400B of the integrated circuit package structure 500 can use a glass substrate with a thermal expansion coefficient close to that of silicon as the core board 200. In addition, the dielectric layer of the chip side redistribution structure (redistribution structure 230) and the conductive bump side (or solder ball side) redistribution structure ( Figure 1 Rewiring structure 240, Figure 2 The dielectric layer on the outside of the rewiring structure 340) has a different thermal expansion coefficient. For example, the dielectric layer of the chip side rewiring structure (rewiring structure 230) is an inorganic dielectric layer (inorganic dielectric layer 210T), and the thermal expansion coefficient of the inorganic dielectric layer is similar to the thermal expansion coefficient of the integrated circuit chip (not shown) installed on the circuit substrate, and can be more matched with the thermal expansion coefficient of the integrated circuit chip. In addition, the dielectric layer on the outside of the conductive bump side (or solder ball side) rewiring structure (rewiring structure 240, 340) is an organic dielectric layer (organic dielectric layer 220), and the thermal expansion coefficient of the organic dielectric layer is between the thermal expansion coefficient of the core board 200 and the thermal expansion coefficient of the printed circuit board, so as to serve as a thermal expansion coefficient buffer layer (CTE buffer layer) between the integrated circuit chip and the printed circuit board. When the integrated circuit package structure 500 is installed on the printed circuit board, the reliability problem caused by the mismatch of the thermal expansion coefficients (CTE mismatch) between the two can be avoided. Furthermore, the chip side redistribution structure (redistribution structure 230) may have a denser wiring density (similar to that of an integrated circuit chip), and the conductive bump side (or solder ball side) redistribution structure (redistribution structures 240, 340) may have a sparser wiring density (similar to that of a printed circuit board).

[0064] In the embodiment of the circuit substrate 400B, an inorganic dielectric layer (inorganic dielectric layer 210T, 210B) can be provided on both the chip side surface (first surface 200T) and the conductive bump side (or solder ball side) surface (second surface 200B) of the core board 200. Therefore, the dielectric layer of the conductive bump side (or solder ball side) redistribution structure (redistribution structure 340) includes an inorganic dielectric layer 210B close to the core board 200 and an organic dielectric layer (organic dielectric layer 220) close to the solder mask 250.

[0065] Figure 3 FIG. 4 is a cross-sectional view of a circuit substrate 400C of an integrated circuit packaging structure 500 according to some embodiments of the present invention. Figure 1 The same or similar reference numerals represent the same or similar components. Figure 1 ) and the circuit substrate 400C( Figure 3 ) is that the circuit substrate 400C further includes a stress release dielectric layer 260.

[0066] like Figure 3As shown, the stress release dielectric layer 260 is disposed on the second surface 200B of the core board 200 and is disposed between the core board 200 and the organic dielectric layer 220. In the present embodiment, the stress release dielectric layer 260 is directly connected to the second surface 200B of the core board 200. The stress release dielectric layer 260 is used to resist the stress and degradation generated by the circuit substrate 400C during use (in-service) (for example, bonding chips and / or printed circuit boards). In some embodiments, the material of the stress release dielectric layer 260 may include a hybrid organic-inorganic polymer (HOIP) material. In some embodiments, the above-mentioned hybrid organic-inorganic polymer material has an inorganic part including, for example, a silicon oxygen chain, and also includes an organic polymer part such as a carbon chain. For example, the material of the stress release dielectric layer 260 may include polycarbonate (PC), silicone elastomer, layered silicate, nanoparticles, other appropriate hybrid organic-inorganic polymer materials, or a combination of the above. In some embodiments, the thermal expansion coefficient of the stress release dielectric layer 260 may be between the thermal expansion coefficient of the inorganic dielectric layer 210T and the thermal expansion coefficient of the organic dielectric layer 220. In addition, the thermal expansion coefficient of the stress release dielectric layer 260 mainly depends on the thermal expansion coefficient of the organic polymer part. For example, the thermal expansion coefficient of the stress release dielectric layer 260 may be between 9 ppm / °C and 25 ppm / °C. In addition, the stress release dielectric layer 260 may be formed using a deposition process. In some embodiments, corresponding to the material and manufacturing process characteristics of the stress release dielectric layer 260, the thickness T260 of a single stress release dielectric layer 260 may be between 1% and 15% of the thickness T200 of the core board 200. The thickness T260 of a single stress release dielectric layer 260 may be the same as the thickness T220 of a single organic dielectric layer 220. Alternatively, the thickness T260 of a single stress release dielectric layer 260 may be different from the thickness T220 of a single organic dielectric layer 220.

[0067] The circuit substrate 400C also includes a plurality of conductive wires 262 disposed between the core board 200 and the stress release dielectric layer 260 and a plurality of conductive holes 264 penetrating the stress release dielectric layer 260. In some embodiments, corresponding to the material and manufacturing process characteristics of the stress release dielectric layer 260, the conductive wires 262 disposed on the stress release dielectric layer 260 and the conductive wires 222 disposed on the organic dielectric layer 220 may have the same line width and spacing. In addition, the line width and spacing of the conductive wires 262 are greater than the line width and spacing of the conductive wires 212T disposed on the inorganic dielectric layer 210T. For example, the ratio of the line width of the conductive wire 262 to the line width of the conductive wire 212T may be between 2.5 and 100.

[0068] like Figure 3 As shown, the corresponding wires 262 and the conductive holes 264 are connected to each other and to the corresponding core conductive vias 200V, wires 222, conductive holes 224 and pads 226. In the present embodiment, the stress relief dielectric layer 260, wires 262, conductive holes 264, organic dielectric layer 220, wires 222, conductive holes 224 and pads 226 disposed on the second surface 200B of the core board 200 can together form a rewiring structure 440. The rewiring structure 440 can be connected to the rewiring structure 230 through the core conductive vias 200V. In some embodiments, the wiring density of the rewiring structure 230 is greater than the overall wiring density of the rewiring structure 440.

[0069] Figure 4 FIG. 4 is a cross-sectional view of a circuit substrate 400D of an integrated circuit package structure 500 according to some embodiments of the present invention. Figures 1 to 3 The same or similar reference numerals represent the same or similar elements. Figure 2 ) and the circuit substrate 400D( Figure 4 ) is that the circuit substrate 400D further includes a stress release dielectric layer 260.

[0070] like Figure 4 As shown, the inorganic dielectric layer 210B is disposed on the second surface 200B of the core board 200, and the stress release dielectric layer 260 is disposed between the inorganic dielectric layer 210B and the organic dielectric layer 220. In this embodiment, the top surface and the bottom surface of the stress release dielectric layer 260 are directly connected to the inorganic dielectric layer 210B and the organic dielectric layer 220, respectively.

[0071] like Figure 4 As shown, the wire 262 covered by the stress release dielectric layer 260 is connected to the corresponding conductive hole 264 passing through the stress release dielectric layer 260, and is connected to the corresponding core conductive through hole 200V, the wire 212B, the conductive hole 214B, the wire 222, the conductive hole 224 and the pad 226. In the present embodiment, the inorganic dielectric layer 210B, the wire 212B, the conductive hole 214B, the stress release dielectric layer 260, the wire 262, the conductive hole 264, the organic dielectric layer 220, the wire 222, the conductive hole 224 and the pad 226 disposed on the second surface 200B of the core board 200 can form a rewiring structure 540 together. The rewiring structure 540 can be connected to the rewiring structure 230 through the core conductive through hole 200V. In some embodiments, the wiring density of the rewiring structure 230 is greater than the wiring density of the rewiring structure 540.

[0072] The circuit substrates 400C and 400D of the integrated circuit package structure 500 further have a stress release dielectric layer 260 disposed on the surface (second surface 200B) on the conductive bump side (or solder ball side), and the stress release dielectric layer 260 is disposed between the core board 200 and the organic dielectric layer 220. When the circuit substrates 400C and 400D are bonded to the chip and / or printed circuit board, the stress release dielectric layer 260 can serve as a buffer layer between the core board 200 and the organic dielectric layer 220, and absorb the above-mentioned bonding stress, so as to further enhance the reliability of the integrated circuit package structure 500.

[0073] Figure 5 FIG. 5 is a cross-sectional view of an integrated circuit package structure 500A according to some embodiments of the present invention. Figures 1 to 4 The same or similar reference numbers represent the same or similar elements.

[0074] like Figure 5 As shown, the integrated circuit package structure 500A includes a circuit substrate 400A, a chip 100 and a conductive bump (or solder ball) 280 .

[0075] The chip 100 is disposed on the inorganic dielectric layer 210T of the rewiring structure 230. In some embodiments, the chip 100 may include a single die of a central processing unit chip, a logic chip, a graphics processing chip, an input / output chip, a memory chip, a baseband chip, a radio frequency chip, or a special function integrated circuit chip. Alternatively, the chip 100 may also include a chiplet composed of the above single chip. In some embodiments, the active surface 100a of the chip 100 has a plurality of chip pads 102 and a dielectric layer (not shown) surrounding the chip pads 102, and the surfaces of these chip pads 102 and the surfaces of the dielectric layer surrounding the chip pads 102 are coplanar with each other. In some embodiments, the material of the chip pads 102 may include a conductive metal or alloy such as copper.

[0076] When the dielectric layer of the chip-side rewiring structure (rewiring structure 230) of the circuit substrate is formed by an inorganic dielectric layer (inorganic dielectric layer 210T), and the pads 216 of the rewiring structure 230 are formed by copper, a hybrid bonding method can be used to directly bond the chip-side rewiring structure (rewiring structure 230) to the chip. In detail, the chip pads 102 of the chip 100 are directly bonded to the corresponding pads 216 of the rewiring structure 230, and the dielectric layer surrounding the chip pads 102 is directly bonded to the outermost inorganic dielectric layer 210T of the rewiring structure 230. In the present embodiment, there are no solder mask layers, conductive bumps (such as solder bumps) and underfill between the chip 100 and the rewiring structure 230, and the chip pads 102 are not covered by the underfill.

[0077] A conductive bump (or solder ball) 280 is located above the second surface 200B of the circuit board 400A, and is disposed on the organic dielectric layer 220, and passes through the solder mask layer 250 to connect to the pad 226 of the redistribution structure 240. The chip pads 102 of the chip 100 can be coupled to the corresponding conductive bumps (or solder balls) 280 through the redistribution structure 230, the core conductive vias 200V, and the redistribution structure 240.

[0078] The integrated circuit package structure 500A further includes a dielectric layer 110. The dielectric layer 110 is disposed on the redistribution structure 230 and covers the side surfaces of the chip 100. The dielectric layer 110 can be used to protect the chip 100. In some embodiments, the coefficient of thermal expansion of the dielectric layer 110 can be similar to that of silicon, for example, between about 3 ppm / °C and 5 ppm / °C.

[0079] Figure 6 A cross-sectional schematic diagram of an integrated circuit package structure 500B according to some embodiments of the present invention. Elements having the same or similar reference numerals in the figure represent the same or similar elements. Figures 1 to 5 Same or similar reference numerals represent the same or similar elements.

[0080] As Figure 6 shown, the integrated circuit package structure 500B includes a circuit board 400B, a chip 100, and conductive bumps (or solder balls) 280. The chip 100 can be hybrid bonded to the redistribution structure 230 of the circuit board 400B, and the chip pads 102 of the chip 100 are directly bonded to the corresponding pads 216 of the redistribution structure 230. Therefore, the chip pads 102 of the chip 100 can be coupled to the corresponding conductive bumps (or solder balls) 280 through the redistribution structure 230, the core conductive vias 200V, and the redistribution structure 340.

[0081] In other embodiments, the chip 100 can also be hybrid bonded to the redistribution structure 230 of the circuit board 400C ( Figure 3 ) or the circuit board 400D ( Figure 4 ). The conductive bumps (or solder balls) 280 can be connected to the pads 226 of the redistribution structure 240 of the circuit board 400C ( Figure 3 ) or the circuit board 400D ( Figure 4 ).

[0082] Figure 7 A cross-sectional schematic diagram of an integrated circuit package structure 500C according to some embodiments of the present invention. Elements having the same or similar reference numerals in the figure represent the same or similar elements. At least one difference between the integrated circuit package structure 500A ( Figures 1 to 6 ) and the integrated circuit package structure 500C is that the integrated circuit package structure 500C includes a plurality of chips 100-1, 100-2. Figure 5 ) and the integrated circuit package structure 500C is that the integrated circuit package structure 500C includes a plurality of chips 100-1, 100-2.

[0083] like Figure 7 As shown, the integrated circuit package structure 500C includes a circuit substrate 400A, a chip 100-1, a chip 100-2, and a conductive bump (or solder ball side) 280. The chip 100-1 and the chip 100-2 are arranged side by side on the inorganic dielectric layer 210T of the redistribution structure 230 along the direction D100. In some embodiments, the active surfaces 100-1a and 100-2a of the chips 100-1 and 100-2 have a plurality of chip pads 102-1 and 102-2 and a dielectric layer (not shown) surrounding the chip pads 102-1 and 102-2. In this embodiment, the chips 100-1 and 100-2 are hybrid-bonded with the redistribution structure 230. Specifically, the chip pads 102-1 and 102-2 of the chips 100-1 and 100-2 are directly bonded to different pads 216 of the redistribution structure 230, respectively, and the dielectric layer surrounding the chip pads 102-1 and 102-2 is directly bonded to the outermost inorganic dielectric layer 210T of the redistribution structure 230. In the present embodiment, there are no solder mask layers, conductive bumps (such as solder bumps) and underfill between the chips 100-1 and 100-2 and the redistribution structure 230, and the chip pads 102-1 and 102-2 are not covered by the underfill.

[0084] According to the aforementioned connection method, the chip pads 102 - 1 and 102 - 2 of the chips 100 - 1 and 100 - 2 can be coupled to different conductive bumps (or solder balls) 280 through the redistribution structure 230 , the core conductive via 200V, and the redistribution structure 240 , respectively.

[0085] In addition, in the present embodiment, the chip 100-1 is coupled to the chip 100-2 through the rewiring structure 230. In detail, the chip pads 102-1 and 102-2 in the chips 100-1 and 100-2 that are close to each other can be coupled to each other through the wire 212T' and the pad 216T'. The two ends of the wire 212T' can be connected to the corresponding pads 216T' respectively. In addition, the wire 212T' and the pad 216T' will not be coupled to the conductive bump 280 through the core conductive via 200V and the rewiring structure 240.

[0086] like Figure 7 As shown, the dielectric layer 110 of the integrated circuit package structure 500C covers the side surfaces of the chips 100 - 1 and 100 - 2 and fills the gap between the chips 100 - 1 and 100 - 2 .

[0087] Figure 8 FIG. 5 is a cross-sectional view of an integrated circuit package structure 500D according to some embodiments of the present invention. Figures 1 to 7 The same or similar reference numerals represent the same or similar elements. Figure 6) and the integrated circuit package structure 500D is that the integrated circuit package structure 500D includes a plurality of chips 100 - 1 and 100 - 2.

[0088] In this embodiment, the chips 100-1 and 100-2 are hybrid-bonded to the redistribution structure 230. The chip pads 102-1 and 102-2 of the chips 100-1 and 100-2 are directly bonded to different pads 216 of the redistribution structure 230. Therefore, the chip pads 102-1 and 102-2 of the chips 100-1 and 100-2 can be coupled to different conductive bumps (or solder balls) 280 through the redistribution structure 230, the core conductive vias 200V, and the redistribution structure 340, respectively.

[0089] In addition, in this embodiment, the chip pad 102-1 of the chip 100-1 is coupled to the adjacent chip pad 102-2 of the chip 100-2 through the conductive wire 212T′ and the pad 216T′ of the redistribution structure 230. The conductive wire 212T′ and the pad 216′ are not coupled to the conductive bump (or solder ball) 280 through the core conductive via 200V and the redistribution structure 240.

[0090] In other embodiments, the chip pads 102-1 and 102-2 of the chips 100-1 and 100-2 may also be connected to the circuit substrate 400C ( Figure 3 ) or circuit substrate 400D( Figure 4 ) are hybridly bonded to different pads 216 of the redistribution structure 230 to couple to different conductive bumps (or solder balls) 280. The chip pads 102-1 and 102-2 of the chips 100-1 and 100-2 can be coupled to each other through the conductive wires 212T' and pads 216T' of the redistribution structure 230.

[0091] Fig. 9 FIG. 5 is a cross-sectional schematic diagram of an integrated circuit package structure 500E according to some embodiments of the present invention. Figures 1 to 8 The same or similar reference numerals represent the same or similar elements. Figure 7 ) and the integrated circuit package structure 500E is that the integrated circuit package structure 500E further includes a bridge element 290.

[0092] like Fig. 9 As shown, the integrated circuit package structure 500E includes a circuit substrate 400A, a chip 100 - 1 , a chip 100 - 2 , a bridge element 290 , a dielectric layer 110 , and a conductive bump (or solder ball) 280 .

[0093] The chip 100-1 and the chip 100-2 are arranged side by side on the inorganic dielectric layer 210T of the redistribution structure 230. The active surface 100-1a of the chip 100-1 has a plurality of chip pads 102-1 and 102-1A and a dielectric layer (not shown) surrounding the chip pads 102-1 and 102-1A. In the present embodiment, the chip pads 102-1 and 102-1A have different pitches. For example, the pitch of the chip pads 102-1A close to the chip 100-2 is smaller than the pitch of the chip pads 102-1 far from the chip 100-2.

[0094] Similarly, the active surface 100-2a of the chip 100-2 has a plurality of chip pads 102-2, 102-2A and a dielectric layer (not shown) surrounding the chip pads 102-2, 102-2A. In the present embodiment, the chip pads 102-2, 102-2A have different pitches. For example, the pitch of the chip pads 102-2A close to the chip 100-1 is smaller than the pitch of the chip pads 102-2 far from the chip 100-1. The chip pads 102-1A, 102-2A may have the same pitch.

[0095] The bridge element 290 is disposed in the inorganic dielectric layer 210T of the redistribution structure 230. In addition, in the direction D120, the bridge element 290 may partially overlap with the chips 100-1 and 100-2. For example, the thickness of the bridge element 290 may be smaller than the thickness of the chips 100-1 and 100-2, and the outermost inorganic dielectric layer 210T of the redistribution structure 230 may have a thicker thickness so that the bridge element 290 can be buried therein and the top surface 230T of the redistribution structure 230 can maintain a flat surface to facilitate bonding with the chips 100-1 and 100-2.

[0096] like Fig. 9 As shown, the bridge element 290 has a plurality of bridge pads 292. In some embodiments, the spacing of the bridge pads 292 may be equal to the spacing of the chip pads 102-1A and 102-2A. The chip pads 102-1A and 102-2A may be located directly above the corresponding bridge pads 292. In this embodiment, the bridge pad 292 may be connected to the conductive structure 214A of the redistribution structure 230. The conductive structure 214A is disposed in the outermost inorganic dielectric layer 210T and is located between the chip pads 102-1A and 102-2A and the corresponding bridge pads 292. In some embodiments, the bridge element 290 may include an active element or a passive element.

[0097] In this embodiment, the chips 100 - 1 and 100 - 2 are hybrid-bonded with the redistribution structure 230 . Specifically, the chip pads 102 - 1 and 102 - 2 of the chips 100 - 1 and 100 - 2 are directly bonded with different pads 216 of the redistribution structure 230 .

[0098] According to the aforementioned connection method, the chip pads 102 - 1 and 102 - 2 of the chips 100 - 1 and 100 - 2 can be coupled to different conductive bumps (or solder balls) 280 through the redistribution structure 230 , the core conductive via 200V, and the redistribution structure 240 , respectively.

[0099] In addition, in this embodiment, the chip 100-1 is coupled to the chip 100-2 through the bridge element 290. Specifically, the chip pads 102-1A and 102-2A close to each other in the chips 100-1 and 100-2 are directly bonded (hybrid bonded) to different conductive structures 214A of the redistribution structure 230. Moreover, different conductive structures 214A are directly bonded (hybrid bonded) to corresponding bridge pads 292. Moreover, the bridge element 290 and the conductive structure 214A are not coupled to the conductive bump 280 through the core conductive via 200V and the redistribution structure 240.

[0100] Furthermore, the dielectric layer surrounding the chip pads 102-1, 102-1A and the dielectric layer surrounding the chip pads 102-2, 102-2A are directly bonded to the outermost inorganic dielectric layer 210T of the redistribution structure 230. In the present embodiment, there is no solder mask, conductive bump (e.g., solder bump) and underfill between the chip pads 102-1, 102-2, 102-1A, 102-2A and the redistribution structure 230, and the chip pads 102-1, 102-2, 102-1A, 102-2A are not covered by the underfill.

[0101] Fig.10 FIG. 5 is a cross-sectional schematic diagram of an integrated circuit package structure 500F according to some embodiments of the present invention. Figures 1 to 9 The same or similar reference numerals represent the same or similar elements. Figure 8 ) and the integrated circuit package structure 500F is that the integrated circuit package structure 500F further includes a bridge element 290.

[0102] like Fig.10 As shown, the integrated circuit package structure 500F includes a circuit substrate 400B, a chip 100 - 1 , a chip 100 - 2 , a bridge element 290 , a dielectric layer 110 , and a conductive bump (or solder ball) 280 .

[0103] In this embodiment, the chips 100 - 1 and 100 - 2 are hybrid-bonded with the redistribution structure 230 . Specifically, the chip pads 102 - 1 and 102 - 2 of the chips 100 - 1 and 100 - 2 are directly bonded with different pads 216 of the redistribution structure 230 .

[0104] According to the aforementioned connection method, the chip pads 102 - 1 and 102 - 2 of the chips 100 - 1 and 100 - 2 can be coupled to different conductive bumps (or solder balls) 280 through the redistribution structure 230 , the core conductive via 200V, and the redistribution structure 340 , respectively.

[0105] In addition, in this embodiment, the chip 100-1 is coupled to the chip 100-2 through the bridge element 290. In detail, the chip pads 102-1A and 102-2A close to each other in the chips 100-1 and 100-2 are directly bonded (hybrid bonded) to different conductive structures 214A of the redistribution structure 230. Moreover, different conductive structures 214A are directly bonded (hybrid bonded) to corresponding bridge pads 292. Moreover, the bridge element 290 and the conductive structure 214A are not coupled to the conductive bump (or solder ball) 280 through the core conductive via 200V and the redistribution structure 340.

[0106] Furthermore, the dielectric layer surrounding the chip pads 102-1, 102-1A and the dielectric layer surrounding the chip pads 102-2, 102-2A are directly bonded (hybrid bonded) to the outermost inorganic dielectric layer 210T of the redistribution structure 230. In the present embodiment, there are no solder mask layers, conductive bumps (e.g., solder bumps) and underfill between the chip pads 102-1, 102-2, 102-1A, 102-2A and the redistribution structure 230, and the chip pads 102-1, 102-2, 102-1A, 102-2A are not covered by the underfill.

[0107] In other embodiments, the chip pads 102-1 and 102-2 of the chips 100-1 and 100-2 may also be connected to the circuit substrate 400C ( Figure 3 ) or circuit substrate 400D( Figure 4 ) are hybridly bonded to different pads 216 of the redistribution structure 230 to couple to different conductive bumps (or solder balls) 280. In addition, the chip pads 102-1A and 102-2A of the chips 100-1 and 100-2 can be coupled to each other via a bridge element 290 embedded in the redistribution structure 230.

[0108] The integrated circuit packaging structure 500A~500F of the embodiment of the present invention uses a hybrid bonding method to directly bond the chip side rewiring structure (rewiring structure 230) to the chip. The contact size can be greatly miniaturized and the thickness of the packaging structure can be reduced. In addition, it can avoid the problems of adjacent conductive bumps bridging short circuits and the inability to fill the bottom glue when the contact size is miniaturized in the existing flip-chip packaging technology. In addition, compared with the bump reflow manufacturing process (manufacturing process temperature is about 240°C to 250°C) used in the existing integrated circuit packaging structure, the hybrid bonding manufacturing process temperature is lower (for example, less than or equal to 200°C), which can greatly reduce the stress on the circuit substrate during chip bonding.

[0109] The integrated circuit packaging structure of the embodiment of the present invention has the following advantages: during the molding process after the chip is installed, the chip alignment accuracy can be maintained without causing the problem of chip displacement. The thermal expansion coefficient of the inorganic dielectric layer of the chip side rewiring structure is similar to that of silicon, which can improve the matching degree of the thermal expansion coefficient between the chip side rewiring structure and the chip. The circuit substrate packaged by the integrated circuit packaging structure can be hybrid-bonded with the chip through a fine-pitch bridge element without using solder to achieve a strong structure with a high-density input / output interface, and an extremely short interconnection structure can be achieved between different chips.

[0110] In the integrated circuit packaging structure of the embodiment of the present invention, the chip-side rewiring structure has a high-density and solder-free interface interconnection structure, which helps to reduce the required circuit power consumption and realize high-performance computing applications. The cost of the bridge element used to couple different chips is lower than the interposer of the wafer-level manufacturing process, which can reduce the cost of the integrated circuit packaging structure. Compared with the solder joints between the existing chip and the substrate, the integrated circuit packaging structure of the embodiment of the present invention can significantly reduce parasitic capacitance and resistance. The connection structure between the chip and the substrate does not use solder bumps at all, so there is no need for under-bump metal (UBM) and micro-bump or bump manufacturing process. In addition, there is no need for a reflow manufacturing process for bonding the chip to the substrate. The inorganic dielectric layer of the chip-side rewiring structure is hybrid-bonded (directly bonded) with the dielectric layer of the chip. Therefore, there is no need to fill the bottom glue between the circuit substrate and the chip. Therefore, the 2.5D integrated circuit packaging process can be greatly simplified.

[0111] The integrated circuit packaging structure of the embodiment of the present invention can use a panel-level glass core board, which can keep the surface flat in the thin film deposition process of forming an inorganic dielectric layer, and can reduce costs. Compared with the micro-bump and solder bump connection structure used in the existing integrated circuit packaging structure, the integrated circuit packaging structure of the embodiment of the present invention has a smaller number of manufacturing processes and a lower yield risk. The integrated circuit packaging structure of the embodiment of the present invention can use glass with a low thermal expansion coefficient, as well as low dielectric constant (dk) and loss factor (df) glass as a core board, which is more suitable for high-speed transmission applications. When the core board is made of glass, the flat and hard glass surface helps to control the substrate warping and perform a hybrid bonding process. The hybrid bonding process may include a low-temperature process such as a homogenized laser, and the laser focus can be controlled at the interface between the circuit substrate and the chip for local heating, and with an optional low-temperature annealing process to reduce the stress of the entire chip on the substrate.

[0112] An embodiment of the present invention provides an integrated circuit packaging structure. It includes a circuit substrate. The circuit substrate includes a core board, a first inorganic dielectric layer, an organic dielectric layer and a solder mask. The core board has a first surface and a second surface opposite to each other. The first inorganic dielectric layer is arranged on the first surface of the core board. The organic dielectric layer is arranged on the second surface of the core board. The solder mask is arranged on the organic dielectric layer. The solder mask is separated from the first inorganic dielectric layer by the organic dielectric layer and the core board.

[0113] In some embodiments, the material of the core board includes glass, ceramic or glass ceramic, and the thermal expansion coefficient of the core board can be selected between 3 ppm / ℃ and 9 ppm / ℃. The thermal expansion coefficient of the inorganic dielectric layer can be selected between 3 ppm / ℃ and 5 ppm / ℃, and its thickness is less than or equal to 1% of the thickness of the core board. The thermal expansion coefficient of the organic dielectric layer can be selected between 9ppm / ℃ and 25ppm / ℃, and its thickness is between 1% and 15% of the thickness of the core board. In addition, the ratio of the line width of the wire placed on the organic dielectric layer to the line width of the wire placed on the inorganic dielectric layer can be between 2.5 and 100.

[0114] Although the present invention is disclosed as above by the aforementioned embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the definition of the attached claims.

Claims

1. An integrated circuit packaging structure, comprising: Circuit substrate, including: A core board having a first surface and a second surface opposite to each other; A first inorganic dielectric layer is disposed on the first surface of the core board; an organic dielectric layer, disposed on the second surface of the core board, wherein the material of the organic dielectric layer is different from the material of the first inorganic dielectric layer; and The solder resist layer is disposed on the organic dielectric layer, wherein the solder resist layer is separated from the first inorganic dielectric layer by the organic dielectric layer and the core board. 2 . The integrated circuit package structure as claimed in claim 1 , wherein a coefficient of thermal expansion of the core board is between 3 ppm / ° C. and 9 ppm / ° C. 3 . The integrated circuit packaging structure as claimed in claim 1 , wherein the material of the core board comprises glass, ceramic or glass ceramic. 4 . The integrated circuit package structure as claimed in claim 1 , wherein a coefficient of thermal expansion of the first inorganic dielectric layer is between 3 ppm / ° C. and 5 ppm / ° C. 5 . The integrated circuit package structure as claimed in claim 1 , wherein a material of the first inorganic dielectric layer comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbide, or a combination thereof. 6 . The integrated circuit package structure as claimed in claim 1 , wherein a coefficient of thermal expansion of the organic dielectric layer is between 9 ppm / ° C. and 25 ppm / ° C. 7 . The integrated circuit package structure as claimed in claim 1 , wherein a material of the organic dielectric layer comprises maleimide triazine resin, epoxy resin, phenolic resin, cyanate resin, polycarbonate, polysilicone elastomer, or a combination thereof. 8 . The integrated circuit package structure as claimed in claim 1 , wherein a thickness of the first inorganic dielectric layer is less than or equal to 1% of a thickness of the core board. 9 . The integrated circuit package structure as claimed in claim 1 , wherein the thickness of the organic dielectric layer is between 1% and 15% of the thickness of the core board.

10. The integrated circuit package structure as claimed in claim 1, wherein the circuit substrate further comprises: A first redistribution structure is disposed on the first surface of the core board, wherein the first redistribution structure includes the first inorganic dielectric layer and a first conductive line disposed on the first inorganic dielectric layer; as well as A second redistribution structure is disposed on the second surface of the core board, wherein the second redistribution structure includes the organic dielectric layer and a second wire disposed on the organic dielectric layer. The first conductive line has a first line width, the second conductive line has a second line width, and the second line width is greater than the first line width. 11 . The integrated circuit package structure as claimed in claim 10 , wherein a ratio of the second line width to the first line width is between 2.5 and 100.

12. The integrated circuit package structure as claimed in claim 10, wherein the second redistribution structure further comprises: A second inorganic dielectric layer is disposed between the core board and the organic dielectric layer; as well as A third conductive line is disposed on the second inorganic dielectric layer. The first inorganic dielectric layer and the second inorganic dielectric layer include the same material. 13 . The integrated circuit package structure as claimed in claim 12 , wherein the third conductive line has a third line width, and the first line width is equal to the third line width. 14 . The integrated circuit package structure as claimed in claim 13 , wherein a ratio of the second line width to the third line width is between 2.5 and 100.

15. The integrated circuit package structure as claimed in claim 10, wherein the second redistribution structure further comprises: A stress release dielectric layer is disposed between the core board and the organic dielectric layer; as well as The fourth wire is disposed on the stress release dielectric layer. 16 . The integrated circuit package structure as claimed in claim 15 , wherein the fourth conductive line has a fourth line width, and the second line width is equal to the fourth line width. 17 . The integrated circuit package structure of claim 15 , wherein a coefficient of thermal expansion of the stress relief dielectric layer is between 9 ppm / ° C. and 25 ppm / ° C.

18. The integrated circuit package structure according to claim 10, further comprising: A first chip is disposed on the first inorganic dielectric layer, wherein a first chip pad of the first chip is directly connected to a first redistribution structure pad of the first redistribution structure; as well as The conductive bump is disposed on the organic dielectric layer and passes through the solder mask layer to connect to the second redistribution structure pad of the second redistribution structure.

19. The integrated circuit package structure according to claim 18, further comprising: The second chip is arranged side by side with the first chip on the first inorganic dielectric layer, wherein the second chip pad of the second chip is directly connected to the second redistribution structure pad of the first redistribution structure, and the first chip is coupled to the second chip through the first redistribution structure.

20. The integrated circuit package structure according to claim 19, further comprising: The bridge element is disposed in the first inorganic dielectric layer and partially overlaps the first chip and the second chip respectively, wherein the first chip is coupled to the second chip through the bridge element.

Images