A compact high-power high-efficiency GaN power amplifier chip

Abstract

The application discloses a compact high-power high-efficiency GaN power amplifier chip, and belongs to the technical field of radio frequency and microwave integrated circuits. The two-stage cascade amplification structure comprises an input end, an input matching network, a first-stage amplification network, an inter-stage matching network, a second-stage amplification network, an output matching network, an output end and a biasing and stabilizing circuit. The inter-stage matching network integrates power synthesis, gate bias feeding, stability design and inter-stage impedance matching functions, the output matching network integrates power synthesis, drain bias feeding and output impedance matching functions, and the second-stage amplification network adopts a plurality of GaN dies in parallel. The function integration reduces independent elements and wiring space, significantly reduces the chip size, optimizes the signal amplification link and energy transmission path, improves the output power and efficiency in a wide frequency band, enhances the stability and reliability of the chip in a wide working frequency band by combining the stabilizing circuit and the symmetrical layout design, and meets the demand of a communication system on a high-integration high-performance power amplifier.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency and microwave integrated circuit technology, in particular to a compact high-power high-efficiency GaN power amplifier chip. BACKGROUND

[0002] The current communication system develops rapidly, the system integration is higher and higher, the signal transmission bandwidth is also wider and wider, and higher requirements are put forward to the miniaturization and high integration of electronic components in the system. Higher frequency, higher voltage and higher output power semiconductor devices also emerge as the times require. The third generation semiconductor material represented by GaN material has become the research focus of global communication field semiconductor devices. Compared with the previous two generations of semiconductor materials, GaN material has higher breakdown voltage, higher power density, high thermal conductivity and higher electron mobility, which makes it very suitable for the design and production of power amplifiers in the field of radio frequency and microwave. As the core device of the transmitter in the communication system, the power amplifier is a key component that restricts the performance and technical level of the system.

[0003] Using GaN material to design and produce radio frequency and microwave power amplifiers can more effectively improve the output power and efficiency, and the wider bandwidth can better meet the needs of miniaturization and high integration of communication systems. The topological structure of the power amplifier is various, and different topological structures determine the final size area and output power and efficiency of the power amplifier. The two commonly used topological structures of wideband power amplifier are distributed matching structure and reactive matching structure. The advantages of the distributed matching structure are wide bandwidth and better input and output standing wave; the disadvantages are low gain, low output power and low efficiency. The advantages of the reactive matching structure are wide bandwidth, and high gain can be achieved by multi-stage cascade, and the output power and efficiency are also high; the disadvantage is that the bandwidth is not as wide as the distributed structure.

[0004] The design of the power amplifier needs to consider various indicators, such as working bandwidth, output power, efficiency, gain, gain flatness, stability, etc., and from the cost and miniaturization integration point of view, the chip area also needs to be considered. How to design a power amplifier chip with higher output power and efficiency and stable work in a smaller size space is the difficulty of power amplifier design. SUMMARY

[0005] The purpose of the present application is to overcome one or more shortcomings of the existing GaN power amplifier chip and provide a compact high-power high-efficiency GaN power amplifier chip.

[0006] The purpose of the present application is achieved by the following technical solutions:

[0007] A compact high-power high-efficiency GaN power amplifier chip includes a two-stage cascade amplification structure, and the specific components are:

[0008] an input terminal for inputting a radio frequency signal;

[0009] an input matching network connected between the input terminal and the first stage amplification network for matching the input impedance of the first stage GaN die to a 50Ω source impedance;

[0010] a first stage amplification network comprising a single GaN die for first amplifying the input signal;

[0011] an inter-stage matching network connected between the first stage amplification network and the second stage amplification network for matching the output impedance of the first stage die to the input impedance of the second stage die;

[0012] a second stage amplification network comprising a plurality of parallel connected GaN dies for second amplifying the signal;

[0013] an output matching network connected between the second stage amplification network and the output terminal for matching the output impedance of the second stage die to a 50Ω load impedance;

[0014] a gate biasing circuit connected to the gate of the GaN dies of the first stage amplification network and the second stage amplification network for providing gate DC feed;

[0015] a drain biasing circuit connected to the drain of the GaN dies of the first stage amplification network and the second stage amplification network for providing drain DC feed;

[0016] a stabilization circuit connected in series between the input matching network and the first stage amplification network.

[0017] Further, the inter-stage matching network comprises:

[0018] a power dividing structure for dividing the output signal of the first stage die into a plurality of signals corresponding to the number of the second stage dies;

[0019] a plurality of matching units, each of which comprises a first microstrip line and a matching capacitor connected in series, and each of which is combined with the gate biasing, one end of the matching capacitor being connected to the input terminal of the corresponding second stage die and the other end being connected to the gate biasing of the second stage die;

[0020] a multi-stage matching structure for matching the plurality of combined signals to a required impedance value through a multi-stage LC matching structure;

[0021] a first resistor and a second resistor connected in series in the signal path of the plurality of matching units, the first resistor being close to the input terminal of the second stage die and the second resistor being close to the gate biasing of the second stage die.

[0022] Further, the output matching network comprises:

[0023] a power combining structure for combining the output signals of the multiple parallel GaN dies of the second-stage amplification network into a single signal;

[0024] a drain bias LC unit comprising a series inductor and a capacitor, one end of the inductor being connected to a DC power supply, the other end of the inductor being connected to an output end of the power combining structure, and the capacitor being connected in parallel between the output end of the power combining structure and the ground.

[0025] Further, the stabilizing circuit is an RC parallel network comprising:

[0026] a resistor and a capacitor connected in parallel in a signal path, one end of the resistor being connected to an output end of an input matching network, the other end of the resistor being connected to an input end of a first-stage die, and the capacitor being connected in parallel with the resistor for reducing the input capacitance of the first-stage die.

[0027] Further, the gate bias circuit comprises:

[0028] a quarter-wavelength second microstrip line, one end of the second microstrip line being connected to a matching capacitor, the other end of the second microstrip line being connected to a bypass capacitor;

[0029] the bypass capacitor C2 being connected in parallel between an output end of the second microstrip line and the ground, and the output end of the second microstrip line being connected to a gate of a second-stage die through a matching capacitor of the inter-stage matching network.

[0030] Further, the second-stage amplification network comprises four parallel GaN dies, a power dividing structure of the inter-stage matching network divides the signal into four paths, each path being connected to a corresponding gate of a second-stage die through an independent matching unit (a first microstrip line, a first resistor, a matching capacitor, and a second resistor), and a power combining structure of the output matching network combines the four output signals into a single signal through a symmetric LC network.

[0031] The present application has the following advantages:

[0032] (1) The multi-stage matching, bias feeding, and stability design are combined through functional integration, the number of independent elements and the wiring space are reduced, the chip area is significantly reduced, and the high integration requirement is met.

[0033] (2) The signal amplification link and the energy transmission path are optimized, the signal loss is reduced, the power combining capability is enhanced, and the synchronous improvement of the output power and the efficiency in a wide frequency band is realized.

[0034] (3) The abnormal oscillation is suppressed, the frequency response is improved, the power amplifier chip is ensured to operate stably and reliably in a wide working frequency range, and the system-level performance safety is improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1A structure schematic diagram of a compact high-power high-efficiency GaN power amplifier chip provided for the embodiment is shown in the figure.

[0036] Figure 2 A structure schematic diagram of an inter-stage matching and gate bias circuit provided for the embodiment is shown in the figure.

[0037] Figure 3 A structure schematic diagram of an inter-stage matching and gate bias circuit of a conventional power amplifier is shown in the figure.

[0038] Figure 4 A structure schematic diagram of an output matching network provided for the embodiment is shown in the figure.

[0039] Figure 5 A layout structure schematic diagram of an inter-stage matching and bias circuit provided for the embodiment is shown in the figure.

[0040] Figure 6 A layout structure schematic diagram of an inter-stage matching and bias circuit of a conventional power amplifier is shown in the figure.

[0041] Figure 7 A simulation result diagram of the saturated output power and power-added efficiency of the chip provided for the embodiment is shown in the figure. DETAILED DESCRIPTION

[0042] The technical solutions of the present application will be described clearly and completely in the embodiments combined with the embodiments, obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor are within the protection scope of the present application.

[0043] As Figure 1 A structure schematic diagram of a compact high-power high-efficiency GaN power amplifier chip provided for the embodiment is shown in the figure, and the power amplifier comprises:

[0044] Input end: for inputting the radio frequency signal from the source end to the power amplifier chip, and transmitting the input radio frequency signal to the input matching network. In the embodiment, the frequency range of the input radio frequency signal is set to 2.7-3.5GHz,

[0045] Input matching network: for matching the input impedance of the first-stage die to the 50Ω source impedance. Here, a multi-stage LC matching structure is adopted, and the input impedance of the first-stage die is matched to the 50Ω source impedance through multi-stage impedance transformation. At the same time, the matching network and the stabilization circuit are combined, as shown in Figure 1 The stabilization circuit participates in the input matching, which can reduce the matching elements, reduce the loss, and improve the circuit output power and efficiency and stability;

[0046] The first-stage amplification network: a GaN die is used to complete the first amplification of the input signal. The GaN die selected here is a certain high electron mobility transistor (HEMT) with a gate width of 2.5 mm. Under suitable bias conditions, the die performs the first amplification of the input signal.

[0047] The inter-stage matching network: used to match the output impedance of the first-stage die to the input impedance of the final-stage die, while also having the functions of power division, gate bias feeding, stability design, and inter-stage impedance matching. A multi-stage LC matching structure is also used to ensure a suitable operating bandwidth. As shown in FIG. 1C, the inter-stage matching network integrates multiple circuit functions, reducing the chip area. Figure 2

[0048] The second-stage amplification network: four GaN dies are connected in parallel to complete the second amplification of the signal. Each die here is the same as the first-stage die, with a gate width of 2.5 mm, to achieve higher output power and efficiency. The four dies work in parallel to amplify the four signals distributed by the inter-stage matching network.

[0049] The output matching network: used to match the output impedance of the second-stage die to the 50Ω load impedance. As shown in FIG. 1D, the output matching network also has the functions of power combining, drain bias feeding, and impedance matching from the die output to the load end, reducing the number of matching elements, lowering losses, improving output power and efficiency, and reducing the chip area. Figure 4

[0050] The output end: used to transmit the RF signal amplified by the power amplifier chip from the output matching network to the load end.

[0051] The gate bias circuit: used to feed the gate of the transistor in the power amplifier, while also having a stability circuit design to improve the stability of the chip.

[0052] The drain bias circuit: used to feed the drain of the transistor in the power amplifier, while also having an output impedance matching function.

[0053] The stability circuit: used to ensure stable and reliable operation of the power amplifier.

[0054] Specifically, when the power amplifier chip is working, the RF signal enters the chip through the input end. The input end is connected with a DC blocking capacitor, which allows the RF signal to enter the chip while blocking the flow of DC signals from the previous stage and the flow of gate DC signals from the power amplifier chip. The input matching network uses a multi-stage reactance matching method to ensure sufficient operating bandwidth of the chip.

[0055] ​​A stabilizing circuit is connected in series before the input of the first stage. The stabilizing circuit is composed of a parallel RC network. The parallel capacitor in the stabilizing network can reduce the input capacitance of the chip, increase the cutoff frequency of the whole circuit, and improve the high frequency response. The parallel resistor can reduce the low frequency gain, improve the stability of the circuit, and improve the gain flatness of the circuit.

[0056] The gate bias circuit provides appropriate DC gate bias voltage for each stage of transistor, and prevents RF signals in the circuit from leaking to the DC power supply. In addition, in the embodiment, two small resistors are connected in series with the gate bias circuit, which can reduce the instability caused by the high low frequency gain, and effectively isolate the signal loop between the gates of each stage of circuit, to avoid causing unstable points and improve the stability of the circuit. The gate bias circuit is mainly composed of a quarter wavelength microstrip line and a bypass capacitor. For RF signals within a specific frequency band, the gate bias circuit is high impedance, and RF signals cannot pass through, achieving the purpose of suppressing RF signals from flowing to the power supply. For DC signals, the bias circuit can directly flow through, thereby achieving the purpose of passing DC.

[0057] In the embodiment, the inter-stage matching circuit and the gate bias circuit are combined to further reduce the size of the chip. As shown in the following formula, the matching capacitor C1 participates in the inter-stage matching, and is combined with the gate bias circuit. In this way, the capacitor C3 in the conventional matching circuit as shown in the following formula can be removed, reducing the area of the inter-stage matching. At the same time, to ensure symmetry, the input end of each chip is matched with a matching circuit composed of a first microstrip line L1, a first resistor R1, and a matching capacitor C1. To avoid mutual crosstalk between the four chips, a first resistor R1 and a second resistor R2 are connected in series, to enhance the stability of the circuit and eliminate oscillation. In the embodiment, as shown in the following formula, the matching capacitor C1 is connected in series with the gate bias circuit, and the capacitor C3 in the conventional matching circuit is removed. Figure 2 Figure 3 Figure 2 ​​The inter-stage matching circuit is shown, the area of the matching capacitor C1 is small, and the length of the first microstrip line L1 is also small; the area of the bypass capacitor C2 in the gate bias circuit is large, and the length of the second microstrip line L2 of the quarter-wave bias line is also large. After the matching capacitor C1 and the gate bias circuit are combined, only the LRC matching network with matching and stabilizing functions composed of the first microstrip line L1, the first resistor R1 and the matching capacitor C1 is reserved between the four dies, and the second microstrip line L2 with a long size and the bypass capacitor C2 with a large area are removed, so that the matching bandwidth and the stability of the circuit are ensured, the area of the chip inter-stage matching is reduced, the area of the whole chip is reduced, the insertion loss is reduced, and the output power and the efficiency are improved. The four dies are used as the second-stage amplification circuit as a whole, the gate bias circuit is distributed on the upper and lower ends, and is composed of the quarter-wave second microstrip line L2 and the bypass capacitor C2. The layout schematic diagram of the inter-stage matching scheme and the conventional matching circuit layout schematic diagram are shown in Figure 5 and Figure 6 It can be seen that the inter-stage matching scheme can effectively reduce the chip area.

[0058] The inter-stage matching network integrates the impedance conversion and the power division network, matches the output impedance of the first-stage die to the input impedance of the last-stage die, and divides the output power of the first-stage die into multiple signals with the same amplitude and phase to input into the second-stage amplification circuit. Because the second-stage amplification circuit has four dies in parallel, the matching circuit between the first-stage and the second-stage divides the output power of the first-stage die into four signals, and the four signals need to be as symmetrical as possible in amplitude and phase. As described above, the inter-stage matching network, the gate bias circuit and the stabilizing circuit are combined, the impedance matching is completed, the power distribution, the gate power supply and the stability improvement are achieved, the chip size is effectively reduced, the insertion loss is reduced, and the output power and the efficiency of the chip are improved.

[0059] The output matching network and the drain bias circuit are combined, and the output impedance of the second-stage die is matched to the 50Ω load impedance. As shown in Figure 4 The inductor L5 and the capacitor C5 are used as the drain bias circuit to provide appropriate DC bias for the second-stage amplification circuit, and are also used as part of the output matching network to participate in impedance matching, so that the matching elements are reduced, the chip area is reduced, the insertion loss is reduced, and the output power and the efficiency are improved.

[0060] In addition, it should be noted that the input matching network, inter-stage matching network, gate bias network, stabilizing circuit and output matching network in the power amplifier described in the specification are not limited to the structures specifically shown in the present application, and the present application does not make any specific limitation thereto. Figure 1

[0061] The working frequency of the present embodiment is 2.7-3.5 GHz, and the saturation output power (POD) is ≥47.2 dBm in the frequency band and the power added efficiency (PAE) is ≥70% in the frequency band by using the design method described in the present application, as shown in Figure 7 Figure 7 (a) is a chip saturation output power simulation diagram, Figure 7 (b) is a simulation result diagram of the chip power added efficiency. The chip area is 3.2 mm*2.3 mm, and compared with the power amplifier chip of this frequency band and power level, the chip designed in the present embodiment has a smaller chip area and higher output power and efficiency.

[0062] Compared with the prior art, the inter-stage matching structure of the power amplifier chip in the present application combines impedance matching, gate feeding and stability circuit, which can greatly reduce the chip size, and improve the output power and efficiency and the stability of the chip. Specifically, the input end is used for inputting a radio frequency signal; the input matching network is used for matching the input impedance of the first-stage die to 50Ω source impedance, and is combined with the gate bias circuit and the stability circuit to complete impedance matching while having gate feeding and stability design, thereby reducing the chip area; the first-stage amplification network uses a GaN die to complete the first amplification of the input signal and provide appropriate input power for the second-stage die; the inter-stage matching network is used for matching the output impedance of the first-stage die to the input impedance of the second-stage die, and has the functions of power division, gate bias feeding, stability design and inter-stage impedance matching, thereby reducing matching elements, reducing insertion loss, improving output power and efficiency and reducing chip area; the second-stage amplification network completes the second amplification of the signal; the output matching network is used for matching the output impedance of the second-stage die to 50Ω load impedance, and has the functions of power combining, drain bias feeding and impedance matching of the die output to the load end, thereby improving output power and efficiency and reducing chip area; the gate bias circuit is used for feeding the transistor gate in the power amplifier, and is combined with the impedance matching function to further reduce the chip area; the drain bias circuit is used for feeding the transistor drain in the power amplifier, and is combined with the impedance matching function to further reduce the chip area; the stability circuit is used for keeping the power amplifier in a stable working state and improving the reliability of the power amplifier. ​​

[0063] The foregoing is considered as illustrative only of the principles of the application. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the application to the exact construction and operation described. Accordingly, all such variations are intended to be included within the scope of the present application as defined in the claims below and their equivalents.

Claims

1. A compact high-power high-efficiency GaN power amplifier chip, characterized in that, The application relates to a two-stage cascade amplification structure, which comprises the following components: an input end for inputting a radio frequency signal; an input matching network connected between the input end and a first-stage amplification network, used for matching the input impedance of a first-stage GaN die to a 50-ohm source impedance; the first-stage amplification network containing a single GaN die, used for performing first-stage amplification on the input signal; an inter-stage matching network connected between the first-stage amplification network and a second-stage amplification network, used for matching the output impedance of the first-stage die to the input impedance of a second-stage die; the second-stage amplification network containing a plurality of parallelly-connected GaN dies, used for performing second-stage amplification on the signal; an output matching network connected between the second-stage amplification network and an output end, used for matching the output impedance of the second-stage die to a 50-ohm load impedance; a gate bias circuit connected to the gate of the GaN die of the first-stage amplification network and the second-stage amplification network, used for providing gate DC power supply; a drain bias circuit connected to the drain of the GaN die of the first-stage amplification network and the second-stage amplification network, used for providing drain DC power supply; a stabilizing circuit connected in series between the input matching network and the first-stage amplification network; the inter-stage matching network comprises a power division structure, a plurality of matching units and two second resistors R2; each matching unit comprises a first microstrip line L1, a first resistor R1 and a matching capacitor C1; the power division structure is connected to the output end of the first-stage amplification network, each output end is connected to a matching unit and the gate of a GaN die in the second-stage amplification network, and the power division structure is used for dividing the output signal of the first-stage GaN die into a plurality of signals corresponding to the number of GaN dies in the second-stage amplification network; each matching unit is arranged in the vertical direction of the output end of the power division structure, one end of the first microstrip line L1 in each matching unit is connected to the gate of a GaN die in the second-stage amplification network, the other end of the first microstrip line L1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the matching capacitor C1, and the other end of the matching capacitor C1 is grounded; when a certain matching unit is the matching unit corresponding to the first GaN die from top to bottom or the last GaN die in the second-stage amplification network, the other end of the first resistor R1 is further connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the gate bias circuit corresponding to the second-stage amplification network; the gate bias circuit corresponding to the second-stage amplification network comprises a second microstrip line L2 and a bypass capacitor C2; one end of the second microstrip line L2 is connected to the other end of the second resistor R2, the other end of the second microstrip line L2 is connected to one end of the bypass capacitor C2, and the other end of the bypass capacitor C2 is grounded. the output matching network comprises:

2. The GaN power amplifier chip of claim 1, wherein, a power combination structure for combining the output signals of the plurality of parallelly-connected GaN dies in the second-stage amplification network into a single signal; ​ The drain bias LC unit comprises an inductor and a capacitor in series, one end of the inductor is connected to a DC power supply, and the other end is connected to an output end of the power combining structure, and the capacitor is connected in parallel between the output end of the power combining structure and the ground.

3. The GaN power amplifier chip of claim 1, wherein, The stabilizing circuit is an RC parallel network, comprising: The resistance and the capacitor parallel structure are connected in series in the signal path, one end of the resistance is connected to an output end of an input matching network, and the other end is connected to an input end of a first-stage die; the capacitor is connected in parallel with the resistance and is used for reducing the input capacitance of the first-stage die.

4. The GaN power amplifier chip of any one of claims 1-3, wherein, The second-stage amplification network comprises four parallel GaN dies, a power dividing structure of the inter-stage matching network divides the signal into four paths, each path is connected to a corresponding second-stage die gate through an independent matching unit, and the matching structure is combined with the gate bias, and a power combining structure of the output matching network combines the four-path output signals into a single-path signal through a symmetric LC network.

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