Diode device and forming method thereof

Abstract

The invention discloses a diode device and a forming method thereof. The method comprises the following steps: providing a substrate; forming a well region in the substrate; forming a first doped region in the well region, wherein a first distance d1 is formed between the bottom of the first doped region and the surface of the substrate; a second doped region is formed in the well region, a second distance d2 exists between the bottom of the second doped region and the surface of the substrate, and the second distance d2 is smaller than the first distance d1. The whole well region is filled with the first doped region in the direction perpendicular to the surface of the substrate, and the whole well region is not filled with the second doped region in the direction perpendicular to the surface of the substrate, so that when the diode device releases charges, the charges flowing out of the second doped region can flow in the well region between the first doped region and the second doped region; and the charge can flow in the well region below the second doped region, so that the flow area of the charge is increased, the release efficiency of the charge in unit time is improved, and the performance of the diode device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a diode device and a method for forming the same. Background Art

[0002] Diode devices have advantages such as low leakage current, simple structure, and simple manufacturing process. An electrostatic discharge (ESD) diode is a device used to protect electronic circuits, devices, and equipment from electrostatic damage. It can provide rapid voltage protection when an electrostatic discharge event occurs. Electrostatic discharge is an instantaneous high-voltage event caused by the continuous accumulation and release of electrostatic charges. This voltage causes device damage, resulting in circuit failures and equipment damage. The electrostatic protection diode can quickly respond and conduct current during an electrostatic event, thereby protecting the circuit and device from damage.

[0003] However, there are still many problems with current electrostatic protection diodes. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a diode device and a method for forming the same to improve the robustness of the electrostatic protection diode.

[0005] To solve the above technical problem, an embodiment of the present invention provides a method for forming a diode device, including: providing a substrate; forming a well region in the substrate; forming a first doped region in the well region, the bottom of the first doped region having a first distance d from the surface of the substrate 1 ; forming a second doped region in the well region, the bottom of the second doped region having a second distance d from the surface of the substrate 2 , the second distance d 2 being less than the first distance d 1 .

[0006] Optionally, the first doped region extends along a second direction and is arranged parallel to a first direction, the second doped region extends along the second direction and is located between two adjacent first doped regions in the first direction, and the second direction is perpendicular to the first direction.

[0007] Optionally, the substrate includes a first semiconductor layer, an insulating layer on the surface of the first semiconductor layer, and a second semiconductor layer on the surface of the insulating layer.

[0008] Optionally, the material of the second semiconductor layer includes silicon, silicon germanide, and germanium; the second semiconductor layer is a stack of one or more layers.

[0009] Optionally, the thickness of the second semiconductor layer is the same as the thickness of the well region.

[0010] Optionally, the depth of the first doped region is the same as the depth of the well region; the depth of the second doped region is less than the depth of the well region.

[0011] Optionally, the method for forming the well region includes: performing a first ion implantation process on the substrate to form the well region.

[0012] Optionally, the parameters of the first ion implantation include: when the implanted ion type is N-type, the ion implantation energy is 10 keV to 100 keV, and the ion implantation dose is 1.0×10 12 atom / cm 2 to 1.0×10 13 atom / cm 2 ; when the implanted ion type is P-type, the ion implantation energy is 10 keV to 100 keV, and the ion implantation dose is 1.0×10 12 atom / cm 2 to 1.0×10 13 atom / cm 2 .

[0013] Optionally, before forming the well region, it further includes: forming a plurality of isolation structures in the substrate, the isolation structures penetrating through the second semiconductor layer, and the projection range of the isolation structures in the first direction is located outside the projection range of the well region in the first direction.

[0014] Optionally, the method for forming the isolation structures includes: forming a first mask layer on the surface of the substrate, the first mask layer exposing a part of the surface of the substrate; using the first mask layer as a mask to etch the substrate until the surface of the insulating layer is exposed to form a first opening; forming an initial isolation structure in the first opening; performing a planarization process on the initial isolation structure until the surface of the substrate is exposed to form the isolation structures.

[0015] Optionally, after forming the isolation structures and before forming the well region, it further includes: forming an active region between adjacent isolation structures; the size range of the active region in the second direction is 2 μm to 40 μm.

[0016] Optionally, after forming the well region and before forming the first doped region and the second doped region, it further includes: forming a gate layer on the surface of the well region, the gate layer exposing a part of the surface of the well region; the size range of the gate layer in the first direction is: 0.2 μm to 2 μm.

[0017] Optionally, after forming the well region and before forming the first doped region and the second doped region, it further includes: forming a blocking layer on the surface of the well region, the blocking layer exposing a part of the surface of the well region.

[0018] Optionally, the forming method of the first doping region and the second doping region includes: performing a second ion implantation process on the well region exposed by the gate layer to form the first doping region; performing a third ion implantation process on the well region exposed by the gate layer to form the second doping region.

[0019] Optionally, the forming method of the first doping region and the second doping region further includes: performing a second ion implantation process on the well region exposed by the blocking layer to form the first doping region; performing a third ion implantation process on the well region exposed by the blocking layer to form the second doping region.

[0020] Optionally, the size range of the first doping region and the second doping region in the first direction is: 0.2 μm to 2 μm; the first distance d 1 ranges from: 50 nm to 200 nm; the second distance d 2 ranges from: 0.4d 1 to 0.9d 1 .

[0021] Optionally, after forming the first doping region and the second doping region, it further includes: forming a contact layer on the surfaces of the first doping region and the second doping region; forming a conductive plug on the contact layer.

[0022] Correspondingly, the technical solution of the present invention also provides a diode device, including: a substrate; a well region located in the substrate; a first doping region located in the well region, the bottom of the first doping region having a first distance d from the surface of the substrate 1 ; a second doping region located in the well region, the bottom of the second doping region having a second distance d from the surface of the substrate 2 , the second distance d 2 being less than the first distance d 1 .

[0023] Optionally, the first doping region extends along a second direction and is arranged parallel to the first direction, the second doping region extends along the second direction and is located between two adjacent first doping regions in the first direction, and the second direction is perpendicular to the first direction.

[0024] Optionally, the substrate includes a first semiconductor layer, an insulating layer located on the surface of the first semiconductor layer, and a second semiconductor layer located on the surface of the insulating layer.

[0025] Optionally, the material of the second semiconductor layer includes silicon, silicon germanide, and germanium; the second semiconductor layer is a stack of one or more layers.

[0026] Optionally, the thickness of the second semiconductor layer is the same as the thickness of the well region.

[0027] Optionally, the depth of the first doped region is the same as the depth of the well region; the depth of the second doped region is less than the depth of the well region.

[0028] Optionally, it further includes: an isolation structure located in the substrate, the isolation structure penetrating the second semiconductor layer, and the projection range of the isolation structure in the first direction is located outside the projection range of the well region in the first direction.

[0029] Optionally, it further includes: a gate layer located on the surface of the well region, the gate layer exposing the surfaces of the first doped region, the second doped region, and the isolation structure; the size range of the gate layer in the first direction is: 0.2 μm to 2 μm.

[0030] Optionally, it further includes: a contact layer located on the surfaces of the first doped region and the second doped region; a conductive plug located on the surface of the contact layer.

[0031] Optionally, it further includes: an active region located between adjacent isolation structures; the size range of the active region in the second direction is 2 μm to 40 μm.

[0032] Optionally, the first distance d 1 has a range of: 50 nm to 200 nm; the second distance d 2 has a range of: 0.4d 1 to 0.9d 1 ; the size range of the first doped region and the second doped region in the first direction is: 0.2 μm to 2 μm.

[0033] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0034] In the diode device of the technical solution of the present invention, the second distance d 2 is less than the first distance d 1 . The first doped region fills the entire well region in the direction perpendicular to the surface of the substrate, while the second doped region does not fill the entire well region in the direction perpendicular to the surface of the substrate. When the diode device releases charge, the charge flowing out of the second doped region can not only flow in the well region between the first doped region and the second doped region, but also flow in the well region below the second doped region, increasing the charge flow area, improving the charge release efficiency per unit time, and improving the performance of the diode device.

[0035] Further, the first distance d 1 has a range of: 50 nm to 200 nm; the second distance d 2 has a range of: 0.4d 1 to 0.9d 1; The size range of the first doping region and the second doping region along the first direction is: 0.2 μm to 2 μm. The size of the second doping region along the first direction is much larger than the first distance d 1 and the second distance d 2 , when the diode device discharges charges, the charges flowing out of the second doping region can not only flow in the well region between the first doping region and the second doping region, but also flow in the well region below the second doping region, greatly increasing the charge flow area, improving the charge release efficiency per unit time, and improving the performance of the diode device.

[0036] Furthermore, the size range of the active region along the second direction is 2 μm to 40 μm. Only by controlling the second distance d 2 to be less than the first distance d 1 without increasing the size of the active region along the second direction, while increasing the charge flow area, the occupied area of the device will not be increased, saving costs while improving the electrostatic protection performance of the diode device.

[0037] In the method for forming the diode device of the technical solution of the present invention, the second distance d of the second doping region 2 is less than the first distance d of the first doping region 1 , the first doping region fills the entire well region in the direction perpendicular to the substrate surface while the second doping region does not fill the entire well region in the direction perpendicular to the substrate surface. When the diode device discharges charges, the charges flowing out of the second doping region can not only flow in the well region between the first doping region and the second doping region, but also flow in the well region below the second doping region, increasing the charge flow area, improving the charge release efficiency per unit time, and improving the performance of the diode device.

[0038] Furthermore, the range of the first distance d 1 is: 50 nm to 200 nm; the range of the second distance d 2 is: 0.4d 1 to 0.9d 1 ; The size range of the first doping region and the second doping region along the first direction is: 0.2 μm to 2 μm. The size of the second doping region along the first direction is much larger than the first distance d 1 and the second distance d 2 , when the diode device discharges charges, the charges flowing out of the second doping region can not only flow in the well region between the first doping region and the second doping region, but also flow in the well region below the second doping region, greatly increasing the charge flow area, improving the charge release efficiency per unit time, and improving the performance of the diode device.

[0039] Further, the size of the active region in the second direction ranges from 2 μm to 40 μm. Only by controlling the second distance d 2 is less than the first distance d 1 without increasing the size of the active region in the second direction, the charge flow area is increased while the occupied area of the device is not increased, saving costs while improving the electrostatic protection performance of the diode device. Description of the Drawings

[0040] Figure 1 is a schematic cross-sectional structure diagram of a diode device.

[0041] Figures 2 to 15 is a schematic structural diagram of each step of the method for forming the diode device according to the embodiment of the present invention. Detailed Embodiments

[0042] As described in the background art, there are still many problems with the electrostatic protection diodes in the prior art.

[0043] Figure 1 is a schematic cross-sectional structure diagram of an electrostatic protection diode.

[0044] Please refer to Figure 1 , the diode device includes: a substrate; a well region 100 located in the substrate, the well region 100 having a first depth d 1 ; two mutually separated first doping regions 101 located in the well region 100, each of the first doping regions 101 having a first depth d 1 , each of the first doping regions 101 extends in the second direction and is arranged parallel to the first direction, the second direction being perpendicular to the first direction; a second doping region 102 located in the well region 100, the second doping region 102 extends in the second direction and the second doping region 102 is located between two adjacent first doping regions 101 in the first direction, the doping type of the second doping region 102 being different from that of the first doping region 101, the second doping region 102 having a second depth d 2 , the second depth d 2 being the same as the first depth d 1 .

[0045] The diode device includes: a plurality of isolation structures 103 located in the substrate, the isolation structures 103 having a first depth d 1 .

[0046] The diode device includes: an active region located between adjacent isolation structures 103; the size of the active region in the second direction ranges from 2 μm to 40 μm.

[0047] The first doped region 101 and the second doped region 102 both fill the entire well region 100 in the direction perpendicular to the substrate surface. When the diode device releases charge, the charge flowing out of the second doped region 102 only flows within the well region 100 between the first doped region 101 and the second doped region 102. The flow area of the charge is small, and the charge release efficiency per unit time is low, which is not conducive to improving the performance of the diode device. Moreover, increasing the size of the active region in the second direction will increase the occupied area of the device and increase the cost.

[0048] To solve the above technical problems, the technical solution of the present invention provides a diode device and a method for forming the same, forming two mutually separated first doped regions within the well region and a second doped region located between two adjacent first doped regions in the first direction. The second distance d of the second doped region 2 is less than the first distance d of the first doped region 1 , the first doped region fills the entire well region in the direction perpendicular to the substrate surface while the second doped region does not fill the entire well region in the direction perpendicular to the substrate surface. When the diode device releases charge, the charge flowing out of the second doped region can not only flow within the well region between the first doped region and the second doped region, but also flow within the well region below the second doped region, increasing the flow area of the charge, improving the charge release efficiency per unit time, and improving the performance of the diode device.

[0049] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0050] Figures 2 to 15 is a schematic structural diagram of the formation process of the diode device according to the embodiment of the present invention.

[0051] Please refer to Figure 2 and Figure 3 , Figure 2 is Figure 3 a top view of Figure 3 is Figure 2 a schematic cross-sectional structure diagram along the XX' direction, providing a substrate 200.

[0052] The substrate 200 includes a first semiconductor layer 201, an insulating layer 202 located on the surface of the first semiconductor layer 201, and a second semiconductor layer 203 located on the surface of the insulating layer 202.

[0053] The second semiconductor layer 203 provides a structural basis for subsequently forming the well region 206.

[0054] The material of the second semiconductor layer 203 includes silicon, silicon germanide, and germanium.

[0055] The second semiconductor layer 203 is a stack of one or more layers. Specifically, in this embodiment, the second semiconductor layer 203 is a single layer.

[0056] In other embodiments, the second semiconductor layer 203 may be a stack of multiple layers.

[0057] The thickness range of the second semiconductor layer 203 is: 50 nm to 200 nm.

[0058] The material of the insulating layer 202 includes silicon oxide.

[0059] Please refer to Figure 4 and Figure 5 , Figure 4 is Figure 5 a top view of Figure 5 is Figure 4 a schematic cross-sectional structure diagram along the XX' direction. A plurality of isolation structures 204 are formed in the substrate 200, and the isolation structures 204 penetrate through the second semiconductor layer 203.

[0060] The projection range Ⅰ of the isolation structure 204 along the first direction XX' is located outside the projection range Ⅱ of the subsequently formed well region 206 along the first direction XX'.

[0061] The method for forming the isolation structure 204 includes: forming a first mask layer (not shown) on the surface of the substrate 200, and the first mask layer exposes a part of the surface of the substrate 200; using the first mask layer as a mask to etch the substrate 200 until the surface of the insulating layer 202 is exposed to form a first opening (not shown); forming an initial isolation structure (not shown) in the first opening; performing a planarization process on the initial isolation structure until the surface of the substrate 200 is exposed to form the isolation structure 204.

[0062] The methods for the planarization process include: mechanical polishing method, chemical polishing method, fluid polishing method, and chemical mechanical polishing method, etc.

[0063] In this embodiment, the method for the planarization process is the mechanical polishing method.

[0064] In this embodiment, the depth of the isolation structure 204 is the same as that of the second semiconductor layer 203.

[0065] The depth range of the isolation structure 204 is: 50 nm to 200 nm.

[0066] In another embodiment, the depth of the isolation structure is increased by 10 nanometers compared to the thickness of the second semiconductor layer, that is, ensuring 10 nanometers of over-etching of the isolation structure to achieve electrical isolation between different diode devices.

[0067] The isolation structure 204 is used to avoid electrical crosstalk between adjacent diode devices.

[0068] In this embodiment, the material of the isolation structure 204 includes silicon oxide.

[0069] Please refer to Figure 6 and Figure 7 , Figure 6 which is Figure 7 a top view of Figure 7 and Figure 6 is a schematic cross-sectional structure diagram along the XX' direction. After forming the isolation structure 204, an active region 205 is formed between adjacent isolation structures 204.

[0070] The second direction YY' is perpendicular to the first direction XX'. Specifically, in this embodiment, the size w 1 of the active region 205 along the second direction YY' ranges from 2 μm to 40 μm.

[0071] The size w 1 of the active region 205 along the second direction YY' is proportional to the charge flow area through which the charge flows out of the subsequently formed second doping region 209.

[0072] In this embodiment, only by controlling that the second distance d 2 of the subsequently formed second doping region 209 is less than the first distance d 1 of the first doping region 208 without increasing the size of the active region 205 along the second direction YY', while increasing the charge flow area, the occupied area of the device is not increased, and while improving the electrostatic protection performance of the diode device, the cost is saved.

[0073] Please refer to Figure 8 and Figure 9 , Figure 8 which is Figure 9 a top view of Figure 9 and Figure 8 is a schematic cross-sectional structure diagram along the XX' direction. A well region 206 is formed in the substrate 200.

[0074] The projection range Ⅰ of the isolation structure 204 along the first direction XX' is located outside the projection range Ⅱ of the well region 206 along the first direction XX'.

[0075] The well region 206 provides a structural basis for subsequently forming the first doping region 208 and the second doping region 209.

[0076] The formation method of the well region 206 includes: performing a first ion implantation process on the substrate 200 to form the well region 206.

[0077] In this embodiment, the parameters of the first ion implantation include: the implanted ion type is N-type, the ion implantation energy is 10 keV to 100 keV, and the ion implantation dose is 1.0×10 12 atom / cm 2 to 1.0×10 13 atom / cm 2 .

[0078] In another embodiment, the parameters of the first ion implantation include: when the implanted ion type is P-type, the ion implantation energy is 10 keV to 100 keV, and the ion implantation dose is 1.0×10 12 atom / cm 2 to 1×10 13 atom / cm 2 .

[0079] In this embodiment, the thickness of the second semiconductor layer 203 is the same as the thickness of the well region 206.

[0080] The depth range of the well region 206 is: 50 nm to 200 nm.

[0081] Please refer to Figure 10 and Figure 11 , Figure 10 which is Figure 11 the top view of Figure 11 and Figure 10 is the schematic cross-sectional structure diagram along the XX' direction. A gate layer 207 is formed on the surface of the well region 206, and the gate layer 207 exposes a part of the surface of the well region 206.

[0082] In another embodiment, it further includes: forming a blocking layer on the surface of the well region, and the blocking layer exposes a part of the surface of the well region.

[0083] In this embodiment, the material of the gate layer 207 includes polysilicon.

[0084] The forming method of the gate layer 207 includes: depositing an initial gate layer (not shown in the figure) on the surface of the well region 206, forming a second mask layer (not shown) on the surface of the initial gate layer, and the second mask layer exposes a part of the surface of the initial gate layer; using the second mask layer as a mask, etching the initial gate layer until the surface of the well region 206 is exposed to form the gate layer 207.

[0085] The process of etching the initial gate layer includes wet etching or dry etching. Wet etching is a technique in which the etching material is immersed in an etching solution for etching. It is a pure chemical etching with excellent selectivity. Wet etching is isotropic. Dry etching includes isotropic radial etching, reactive ion etching, sputter etching, ion milling, ion beam assisted etching, reactive ion beam etching, etc. Dry etching is anisotropic.

[0086] In this embodiment, the process of etching the initial gate layer is wet etching.

[0087] In this embodiment, the size range of the gate layer 207 along the first direction XX' is: 0.2 μm to 2 μm.

[0088] If the size of the gate layer 207 along the first direction XX' is too large, it will increase the area of the diode device; if the size of the gate layer 207 along the first direction XX' is too small, it will cause the ions of the subsequently formed first doped region 208 and second doped region 209 to diffuse, affecting the formation of the PN junction.

[0089] The size of the gate layer 207 along the first direction XX' is positively correlated with the resistance value of the well region below the gate layer 207. Therefore, the size of the gate layer 207 along the first direction XX' is positively correlated with the voltage value of the diode device. Specifically, in this embodiment, when the size of the gate layer 207 along the first direction XX' increases by 0.1 μm, the voltage value of the diode device increases by 0.4 V.

[0090] Please refer to Figure 12 and Figure 13 , Figure 12 is Figure 13 a top view of Figure 13 is Figure 12 a schematic cross-sectional structure diagram along the XX' direction. A first doped region 208 is formed in the well region 206, and the bottom of the first doped region 208 has a first distance d from the surface of the substrate 200 1 ; a second doped region 209 is formed in the well region 206, and the bottom of the second doped region 209 has a second distance d from the surface of the substrate 200 2 , and the second distance d 2 is less than the first distance d 1 .

[0091] The first doped region 208 extends along the second direction YY' and is arranged parallel to the first direction XX'. The second doped region 209 extends along the second direction YY' and is located between two adjacent first doped regions 208 in the first direction XX'. The second direction YY' is perpendicular to the first direction XX'.

[0092] The size w of the first doping region 208 and the second doping region 209 along the first direction XX' 2 ranges from 0.2 μm to 2 μm; the first distance d 1 ranges from 50 nm to 200 nm; the second distance d 2 ranges from 0.4d 1 to 0.9d 1 .

[0093] Specifically, in this embodiment, the charge flow area of the second doping region 209 for discharging charges is w 1 *(w 2 + 2d 2 ).

[0094] The size w of the first doping region 208 and the second doping region 209 along the first direction XX' 2 is positively correlated with the charge flow area of the second doping region 209 for discharging charges. Specifically, in this embodiment, when the size w of the first doping region 208 and the second doping region 209 along the first direction XX' 2 increases by 0.1 μm, the current value of the diode device increases by 100 mA.

[0095] The second distance d of the second doping region 209 2 is less than the first distance d of the first doping region 208 1 . The first doping region 208 fills the entire well region 206 in the direction perpendicular to the surface of the substrate 200, while the second doping region 209 does not fill the entire well region 206 in the direction perpendicular to the surface of the substrate 200. When the diode device discharges charges, on the one hand, the charges flowing out of the second doping region 209 can flow not only in the well region 206 between the first doping region 208 and the second doping region 209, but also in the well region 206 below the second doping region 209, increasing the charge flow area, improving the charge release efficiency per unit time, and enhancing the performance of the diode device.

[0096] The size w of the second doping region 209 along the direction parallel to the first direction 2 is much larger than the first distance d 1 and the second distance d 2 . When the diode device discharges charges, the charges flowing out of the second doping region 209 can flow not only in the well region 206 between the first doping region 208 and the second doping region 209, but also in the well region 206 below the second doping region 209, greatly increasing the charge flow area, improving the charge release efficiency per unit time, and enhancing the performance of the diode device.

[0097] The depth d of the first doping region 208 1is the same as the depth of the well region 206.

[0098] The depth d of the second doped region 209 2 is less than the depth of the well region 206.

[0099] In this embodiment, the forming methods of the first doped region 208 and the second doped region 209 include: performing a second ion implantation process on the well region 206 exposed by the gate layer 207 to form the first doped region 208; performing a third ion implantation process on the well region 206 exposed by the gate layer 207 to form the second doped region 209.

[0100] In this embodiment, the parameters of the second ion implantation include: the implanted ion type is N-type, the ion implantation energy is 5 KeV to 100 KeV, and the ion implantation dose is 1.0×10 13 atom / cm 2 to 9×10 15 atom / cm 2 .

[0101] In another embodiment, the parameters of the second ion implantation include: the implanted ion type is P-type, the ion implantation energy is 5 KeV to 100 KeV, and the ion implantation dose is 2.0×10 13 atom / cm 2 to 8×10 15 atom / cm 2 .

[0102] In this embodiment, the parameters of the third ion implantation include: the implanted ion type is P-type, the ion implantation energy is 5 KeV to 100 KeV, and the ion implantation dose is 2.0×10 13 atom / cm 2 to 8×10 15 atom / cm 2 .

[0103] In another embodiment, the parameters of the third ion implantation include: the implanted ion type is N-type, the ion implantation energy is 5 KeV to 100 KeV, and the ion implantation dose is 1.0×10 13 atom / cm 2 to 9×10 15 atom / cm 2 .

[0104] The depth d of the second doped region 209 2 is positively correlated with the energy of the third ion implantation. Specifically, in this embodiment, the doping concentration of the second doped region 209 is 0.4 times to 0.9 times that of the first doped region 208.

[0105] In another embodiment, the method for forming the first doped region and the second doped region further includes: performing a second ion implantation process on the well region exposed by the barrier layer to form the first doped region; performing a third ion implantation process on the well region exposed by the barrier layer to form the second doped region.

[0106] Please refer to Figure 14 and Figure 15 , Figure 14 is Figure 15 a top view of Figure 15 is Figure 14 a schematic cross-sectional structure diagram along the XX' direction. After forming the first doped region 208 and the second doped region 209, it further includes: forming a contact layer 210 on the surfaces of the first doped region 208 and the second doped region 209; forming a conductive plug 211 on the contact layer 210.

[0107] In this embodiment, the material of the contact layer 210 is metal silicide.

[0108] The metal silicide material includes titanium silicide, cobalt silicide, and nickel platinum silicide.

[0109] The material of the conductive plug 211 includes a metal conductive material.

[0110] In this embodiment, the material of the conductive plug 211 is aluminum.

[0111] In this embodiment, the first doped region 208 is electrically connected to the negative electrode terminal through the conductive plug 211, and the second doped region 209 is connected to the positive electrode terminal through the conductive plug 211.

[0112] Correspondingly, an embodiment of the present invention further provides a diode device. Please continue to refer to Figure 14 and Figure 15 , Figure 14 is Figure 15 a top view of Figure 15 is Figure 14 a schematic cross-sectional structure diagram along the XX' direction, including: a substrate 200; a well region 206 located in the substrate 200; a first doped region 208 located in the well region 206, the bottom of the first doped region 208 having a first distance d from the surface of the substrate 200 1 ; a second doped region 209 located in the well region 206, the bottom of the second doped region 209 having a second distance d from the surface of the substrate 200 2 , the second distance d 2 being less than the first distance d 1 .

[0113] The diode device includes: a substrate 200.

[0114] The substrate 200 includes a first semiconductor layer 201, an insulating layer 202 located on the surface of the first semiconductor layer 201, and a second semiconductor layer 203 located on the surface of the insulating layer 202.

[0115] The material of the second semiconductor layer 203 includes silicon, silicon germanide, and germanium.

[0116] The second semiconductor layer 203 is a stack of one or more layers. Specifically, in this embodiment, the second semiconductor layer 203 is a single layer.

[0117] In other embodiments, the second semiconductor layer 203 may be a stack of multiple layers.

[0118] The thickness of the second semiconductor layer 203 is the same as the thickness of the well region 206. The thickness range of the second semiconductor layer 203 is: 50 nm to 200 nm.

[0119] The material of the insulating layer 202 includes silicon oxide.

[0120] The diode device includes: an isolation structure 204 located in the substrate 200, the isolation structure 204 penetrating through the second semiconductor layer 203, and the projection range Ⅰ of the isolation structure 204 along the first direction XX' is located outside the projection range Ⅱ of the subsequently formed well region 206 along the first direction XX'.

[0121] In this embodiment, the depth of the isolation structure 204 is the same as the second semiconductor layer 203. The depth range of the isolation structure 204 is: 50 nm to 200 nm.

[0122] In another embodiment, the depth of the isolation structure is increased by 10 nanometers compared to the thickness of the second semiconductor layer, that is, ensuring 10 nanometers of over-etching of the isolation structure to achieve electrical isolation between different diode devices.

[0123] In this embodiment, the material of the isolation structure 204 includes silicon oxide.

[0124] The diode device includes: an active region 205 located between adjacent isolation structures 204.

[0125] The second direction YY' is perpendicular to the first direction XX'. Specifically, in this embodiment, the dimension w of the active region 205 along the second direction YY' 1 ranges from 2 μm to 40 μm.

[0126] The diode device includes: a well region 206 located in the substrate 200.

[0127] The projection range Ⅰ of the isolation structure 204 along the first direction XX’ is located outside the projection range Ⅱ of the well region 206 along the first direction XX’.

[0128] In this embodiment, the ion doping type of the well region 206 is N-type, and the ion doping concentration is 1.0×10 12 atom / cm 3 to 1.0×10 13 atom / cm 3 。

[0129] In another embodiment, the ion doping type of the well region 206 is P-type, and the ion doping concentration is 1.0×10 12 atom / cm 3 to 1.0×10 13 atom / cm 3 。

[0130] In this embodiment, the thickness of the second semiconductor layer 203 is the same as the thickness of the well region 206.

[0131] The diode device includes: a gate layer 207 located on the surface of the well region 206, and the gate layer 207 exposes the surfaces of the first doping region 208, the second doping region 209, and the isolation structure 204.

[0132] The size range of the gate layer 207 along the first direction is: 0.2μm to 2μm.

[0133] In this embodiment, the material of the gate layer 207 includes polysilicon.

[0134] The diode device includes: a first doping region 208 located in the well region 206, and the bottom of the first doping region 208 has a first distance d from the surface of the substrate 200 1 。

[0135] The depth d of the first doping region 208 1 is the same as the depth of the well region 206.

[0136] In this embodiment, the ion doping type of the first doping region 208 is N-type, and the ion doping concentration is 1.0×10 13 atom / cm 3 to 9×10 15 atom / cm 3 。

[0137] In another embodiment, the ion doping type of the first doping region is P-type, and the ion doping concentration is 2.0×10 13 atom / cm 3 to 8×1015 atom / cm 3 。

[0138] The diode device includes: a second doped region 209 located in the well region 206, and a second distance d from the bottom of the second doped region 209 to the surface of the substrate 200 2 , the second distance d 2 is less than the first distance d 1 。

[0139] The first distance d 1 ranges from 50 nm to 200 nm; the second distance d 2 ranges from 0.4d 1 to 0.9d 1 ; the dimensions of the first doped region 208 and the second doped region 209 in the first direction range from 0.2 μm to 2 μm.

[0140] The depth of the second doped region 209 is less than the depth of the well region 206.

[0141] In this embodiment, the ion doping type of the second doped region 209 is P-type, and the ion doping concentration is 2.0×10 13 atom / cm 3 to 8×10 15 atom / cm 3 。

[0142] In another embodiment, the ion doping type of the second doped region is N-type, and the ion doping concentration is 1.0×10 13 atom / cm 3 to 9×10 15 atom / cm 3 。

[0143] The first doped region 208 extends along the second direction YY' and is arranged parallel to the first direction XX', the second doped region 209 extends along the second direction YY' and is located between two adjacent first doped regions 208 in the first direction XX', and the second direction YY' is perpendicular to the first direction XX'.

[0144] The diode device includes: a contact layer 210 located on the surfaces of the first doped region 208 and the second doped region 209; a conductive plug 211 located on the surface of the contact layer 210.

[0145] In this embodiment, the material of the contact layer 210 is metal silicide.

[0146] The metal silicide materials include titanium silicide, cobalt silicide, and nickel platinum silicide.

[0147] The material of the conductive plug 211 includes a metal conductive material.

[0148] In this embodiment, the material of the conductive plug 211 is aluminum.

[0149] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A diode device, It is characterized in that include: substrate; a well region located in the substrate; A first doped region is located in the well region, and a first distance d is formed between the bottom of the first doped region and the surface of the substrate 1 ; A second doped region is located in the well region, and a second distance d is formed between the bottom of the second doped region and the surface of the substrate 2 , the second distance d 2 Less than the first distance d 1 .

2. The diode device according to claim 1, It is characterized in that The first doped region extends along a second direction and is arranged parallel to the first direction, the second doped region extends along the second direction and is located between two adjacent first doped regions in the first direction, and the second direction is perpendicular to the first direction.

3. The diode device according to claim 2, It is characterized in that The substrate includes a first semiconductor layer, an insulating layer located on a surface of the first semiconductor layer, and a second semiconductor layer located on a surface of the insulating layer.

4. The diode device according to claim 3, It is characterized in that The material of the second semiconductor layer includes silicon, silicon germanium and germanium; the second semiconductor layer is a stack of one or more layers.

5. The diode device according to claim 3, It is characterized in that The thickness of the second semiconductor layer is the same as the thickness of the well region.

6. The diode device according to claim 1, It is characterized in that The depth of the first doping region is the same as the depth of the well region; the depth of the second doping region is less than the depth of the well region.

7. The diode device according to claim 3, It is characterized in that Also includes: An isolation structure is located in the substrate, the isolation structure penetrates the second semiconductor layer, and a projection range of the isolation structure along the first direction is outside a projection range of the well region along the first direction.

8. The diode device according to claim 7, It is characterized in that Also includes: A gate layer located on the surface of the well region, wherein the gate layer exposes the surfaces of the first doped region, the second doped region and the isolation structure; The size of the gate layer along the first direction ranges from 0.2 μm to 2 μm.

9. The diode device according to claim 1, It is characterized in that Also includes: a contact layer located on surfaces of the first doping region and the second doping region; A conductive plug is located on the surface of the contact layer.

10. The diode device according to claim 7, It is characterized in that Also includes: an active region located between adjacent isolation structures; The size of the active region along the second direction ranges from 2 μm to 40 μm.

11. The diode device according to claim 2, It is characterized in that The first distance d 1 The range of the second distance d is: 50nm~200nm; 2 The range is: 0.4d 1 ~0.9d 1 ; The size range of the first doping region and the second doping region along the first direction is: 0.2μm~2μm.

12. A method for forming a diode device, It is characterized in that include: providing a substrate; forming a well region in the substrate; A first doped region is formed in the well region, and a first distance d is formed between the bottom of the first doped region and the surface of the substrate 1 ; A second doped region is formed in the well region, and a second distance d is formed between the bottom of the second doped region and the surface of the substrate. 2 , the second distance d 2 Less than the first distance d 1 .

13. The method for forming a diode device according to claim 12, It is characterized in that The first doped region extends along a second direction and is arranged parallel to the first direction, the second doped region extends along the second direction and is located between two adjacent first doped regions in the first direction, and the second direction is perpendicular to the first direction.

14. The method for forming a diode device according to claim 13, It is characterized in that The substrate includes a first semiconductor layer, an insulating layer located on a surface of the first semiconductor layer, and a second semiconductor layer located on a surface of the insulating layer.

15. The method for forming a diode device according to claim 14, It is characterized in that The material of the second semiconductor layer includes silicon, silicon germanium and germanium; the second semiconductor layer is a stack of one or more layers.

16. The method for forming a diode device according to claim 14, It is characterized in that The thickness of the second semiconductor layer is the same as the thickness of the well region.

17. The method for forming a diode device according to claim 12, It is characterized in that The depth of the first doping region is the same as the depth of the well region; the depth of the second doping region is less than the depth of the well region.

18. The method for forming a diode device according to claim 12, It is characterized in that The method for forming the well region includes: performing a first ion implantation process on the substrate to form the well region.

19. The method for forming a diode device according to claim 18, It is characterized in that The parameters of the first ion implantation include: when the implanted ion type is N-type, the ion implantation energy is 10KeV to 100KeV, and the ion implantation dose is 1.0×10 12 atom / cm 2 to 1.0×10 13 atom / cm 2 When the implanted ion type is P type, the ion implantation energy is 10KeV~100KeV, and the ion implantation dose is 1.0×10 12 atom / cm 2 to 1.0×10 13 atom / cm 2 .

20. The method for forming a diode device according to claim 14, It is characterized in that Before forming the well region, the method further includes: forming a plurality of isolation structures in the substrate, wherein the isolation structures penetrate the second semiconductor layer, and the projection range of the isolation structures along the first direction is outside the projection range of the well region along the first direction.

21. The method for forming a diode device according to claim 20, It is characterized in that The method for forming the isolation structure includes: forming a first mask layer on the surface of the substrate, the first mask layer exposing a portion of the surface of the substrate; using the first mask layer as a mask, etching the substrate until the surface of the insulating layer is exposed to form a first opening; forming an initial isolation structure in the first opening; and flattening the initial isolation structure until the surface of the substrate is exposed to form an isolation structure.

22. The method for forming a diode device according to claim 20, It is characterized in that After forming the isolation structure and before forming the well region, the method further includes: forming an active region between adjacent isolation structures; the size of the active region along the second direction ranges from 2 μm to 40 μm.

23. The method for forming a diode device according to claim 13, It is characterized in that After forming the well region and before forming the first doping region and the second doping region, the method further includes: forming a gate layer on the surface of the well region, wherein the gate layer exposes a portion of the surface of the well region; and the size of the gate layer along the first direction ranges from 0.2 μm to 2 μm.

24. The method for forming a diode device according to claim 13, It is characterized in that After forming the well region and before forming the first doping region and the second doping region, the method further includes: forming a barrier layer on the surface of the well region, wherein the barrier layer exposes a portion of the surface of the well region.

25. The method for forming a diode device according to claim 23, It is characterized in that The method for forming the first doping region and the second doping region includes: performing a second ion implantation process on the well region exposed by the gate layer to form the first doping region; and performing a third ion implantation process on the well region exposed by the gate layer to form the second doping region.

26. The method for forming a diode device according to claim 24, It is characterized in that The method for forming the first doping region and the second doping region further includes: performing a second ion implantation process on the well region exposed by the barrier layer to form the first doping region; and performing a third ion implantation process on the well region exposed by the barrier layer to form the second doping region.

27. The method for forming a diode device according to claim 13, It is characterized in that The size range of the first doping region and the second doping region along the first direction is: 0.2 μm to 2 μm; the first distance d 1 The range of the second distance d is: 50nm~200nm; 2 The range is: 0.4d 1 ~0.9d 1 .

28. The method for forming a diode device according to claim 12, It is characterized in that After forming the first doping region and the second doping region, the method further includes: forming a contact layer on surfaces of the first doping region and the second doping region; and forming a conductive plug on the contact layer.

Images