Buffer layer for dielectric protection in physical vapor deposition metal liner applications

Abstract

Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes depositing a metal buffer layer on a substrate and within a feature disposed in a dielectric layer of the substrate. The buffer layer is deposited using a first physical vapor deposition (PVD) process at a chamber pressure of less than 500 mTorr while applying an RF bias power of less than or equal to 0.08 W / cm2 to the substrate if the chamber pressure is less than or equal to 3 mTorr, and applying an RF bias power of less than or equal to 0.8 W / cm2 to the substrate if the chamber pressure is greater than 3 mTorr. A metal liner layer is deposited atop the buffer layer using a second PVD process at a chamber pressure less than or equal to 3 mTorr while applying an RF bias power greater than 0.08 W / cm2 to the substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to thin film manufacturing techniques. Background Art

[0002] The fabrication of integrated circuits and other microelectronic devices includes processes for filling features formed in or on a substrate. The dimensions of contacts to source and drain regions, as well as contacts to metal gates, have decreased dramatically over time and continue to decrease. The inventors have observed that the contact resistance in semiconductor devices increases dramatically as the contact and feature sizes decrease, and conventional methods of filling such features may result in unacceptably high resistance.

[0003] The inventors have further observed that metal liners deposited in features by physical vapor deposition (PVD) can result in very low contact resistance in the completed features, such as trenches or vias. However, depositing a metal liner within a feature typically requires energetic species from a target, which are often further accelerated by a bias voltage on the substrate. The inventors have observed that such processing may undesirably cause the metal species to impregnate the surrounding dielectric layer in which the feature is formed, which may result in electrical leakage among or between device structures. The inventors have also observed that such processing may undesirably cause a change in the critical dimension (CD) in the feature due to the bombardment of the substrate by the metal species, which may further result in downstream processing issues, such as due to a change in the overlap margin used for design.

[0004] Accordingly, the inventors have developed improved techniques for filling features with a conductive material. Summary of the Invention

[0005] Methods and apparatuses for processing a substrate are provided herein. In some embodiments, a method includes: depositing a metal buffer layer on a substrate and within a feature disposed in a dielectric layer of the substrate, wherein the buffer layer is deposited using a first physical vapor deposition (PVD) process at a chamber pressure of less than 500 mTorr, wherein during the first PVD process: if the chamber pressure is less than or equal to 3 mTorr, then applying an RF bias power of less than or equal to 0.08 W / cm 2 to the substrate; or if the chamber pressure is greater than 3 mTorr and less than or equal to 500 mTorr, then applying an RF bias power of less than or equal to 0.8 W / cm 2 to the substrate; and depositing a metal liner layer on top of the buffer layer, wherein the liner layer is deposited using a second PVD process at a chamber pressure of less than or equal to 3 mTorr while applying an RF bias power greater than 0.08 W / cm2 RF bias power.

[0006] In some embodiments, a non - transitory computer - readable medium stores instructions that, when executed, cause a method to be performed. The method includes: depositing a metal buffer layer on the substrate and within features disposed in a dielectric layer of the substrate using a first physical vapor deposition (PVD) process at a chamber pressure less than 500 mTorr, and applying an RF bias power less than or equal to 0.08 watts / cm 2 to the substrate if the chamber pressure is less than or equal to 3 mTorr, and applying an RF bias power less than or equal to 0.8 watts / cm 2 to the substrate if the chamber pressure is greater than 3 mTorr; and depositing a metal liner layer on top of the buffer layer, wherein the liner layer is deposited using a second PVD process at a chamber pressure less than or equal to 3 mTorr while applying an RF bias power greater than 0.08 watts / cm 2 to the substrate.

[0007] In some embodiments, a system for processing a substrate includes: a first PVD chamber configured to deposit a metal buffer layer on the substrate and within features disposed in a dielectric layer of the substrate, wherein the first PVD chamber is configured to deposit the buffer layer using a first physical vapor deposition (PVD) process at a chamber pressure less than 500 mTorr, and applying an RF bias power less than or equal to 0.08 watts / cm 2 to the substrate if the chamber pressure is less than or equal to 3 mTorr, and applying an RF bias power less than or equal to 0.8 watts / cm 2 to the substrate if the chamber pressure is greater than 3 mTorr; and a second PVD chamber configured to deposit a metal liner layer on top of the buffer layer, wherein the second PVD chamber is configured to deposit the liner layer using a second PVD process at a chamber pressure less than or equal to 3 mTorr while applying an RF bias power greater than 0.08 watts / cm 2 to the substrate.

[0008] Other and further embodiments of the present disclosure are described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, may be understood by reference to the illustrative embodiments depicted in the accompanying drawings. However, the drawings illustrate only typical embodiments of the present disclosure and should not be considered limiting of the scope as the present disclosure may admit other equally effective embodiments.

[0010] Figure 1 is a flowchart of a method of depositing a liner in a feature according to an embodiment of the present disclosure.

[0011] Figures 2A to 2D Each stage of processing a substrate according to an embodiment of the present disclosure is depicted respectively.

[0012] Figure 3 A schematic side view of a physical vapor deposition (PVD) chamber suitable for processing a substrate according to an embodiment of the present disclosure is depicted.

[0013] Figure 4 A schematic plan view of an integration tool (e.g., a cluster tool) suitable for processing a substrate according to an embodiment of the present disclosure is depicted.

[0014] For the sake of facilitating understanding, where possible, the same reference numerals are used to denote elements common to the drawings. The drawings are not drawn to scale and may be simplified for clarity. The elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0015] Embodiments of a method of filling features on a substrate with a conductive material are provided herein. Embodiments of the method of the present invention include depositing a conductive low-energy buffer layer on top of the substrate and within features disposed in or on the substrate, and depositing a conductive high-energy liner layer on top of the low-energy buffer layer. The low-energy buffer layer advantageously provides a buffer layer on top of the substrate and within the features that protects the bottom of the features and the top surface of the substrate from high-energy metal ions during subsequent deposition of the high-energy liner layer. Thus, good coverage within the features can be obtained without substantial damage due to high-energy processes.

[0016] Figure 1 is a flowchart of a method 100 of depositing a liner in a feature according to an embodiment of the present disclosure. Figures 2A to 2D Each stage of processing a substrate according to an embodiment of the present disclosure is depicted respectively.

[0017] Method 100 may be performed on a substrate having features formed in or on the substrate. For example, as Figure 2AAs depicted, substrate 200 includes features 202 formed in a dielectric layer 204, such as an interlayer dielectric of an electronic device or structure being fabricated. The features 202 can be trenches, vias, or dual damascene structures including one or more trenches and one or more vias. In some embodiments, the features can have an opening size (e.g., width) of from about 5 nm to about 300 nm. The substrate 200 can include additional layers, such as another dielectric layer 206 disposed below the dielectric layer 204. A conductive layer 208 can be disposed within the dielectric layer of the substrate, such as within the dielectric layer 206 as Figure 2A depicted. In some embodiments, the conductive layer 208 can have an upper surface that at least partially defines the bottom of the feature 202. For example, the conductive layer 208 can be a contact pad, a conductive line, part of an electronic device (such as a transistor), or some other component that will make electrical contact via the feature 202 once filled. Other optional layers can include, for example, an etch stop layer 210 (illustrated in dashed lines) for fabricating the features during a previous process of the substrate 200. The feature 202 can be formed in a conventional manner, and optionally, a pre-clean process can be provided if needed before starting method 100.

[0018] Method 100 generally begins at block 110, in which a low-energy buffer layer is deposited on the substrate and within the features disposed in the dielectric layer of the substrate. For example, as Figure 2B depicted, a low-energy buffer layer 212 is deposited on the substrate 200, specifically on top of the upper surface 214 of the substrate 200 (e.g., on top of the dielectric layer 204) and within the features 202, including on the bottom 216 of the feature 202 (e.g., on top of the conductive layer 208) and on the sidewalls 218 (e.g., on top of the dielectric layer 204).

[0019] The low-energy buffer layer is a metal layer (e.g., a first metal layer). Examples of suitable metals for forming the low-energy buffer layer include, but are not limited to, cobalt, copper, molybdenum, ruthenium, tantalum, titanium, tungsten, nitrides of the foregoing, and combinations of the foregoing. For example, the low-energy buffer layer can consist of or can be substantially composed of cobalt, copper, molybdenum, ruthenium, tantalum, titanium, tungsten, nitrides of the foregoing, and combinations of the foregoing.

[0020] The low-energy buffer layer is deposited using a low-energy physical vapor deposition (PVD) process (e.g., a first PVD process) at a chamber pressure less than or equal to 500 mTorr with little or no substrate bias. The substrate bias can be provided by an RF power source that provides, for example, RF energy at 13.56 MHz (but other frequencies can also be used). The amount of substrate bias power applied depends on the chamber pressure. If the pressure within the PVD chamber is less than or equal to 3 mTorr, the RF bias power density applied to the substrate is less than or equal to 0.08 watts / cm 2, including zero watts or no RF bias power (as shown in block 112). If the pressure in the PVD chamber is greater than 3 mTorr, the applied RF bias power density is less than or equal to 0.8 watts / cm 2 , including zero watts or no RF bias power (as shown in block 114).

[0021] Additional parameters of the low-energy PVD process can include, for example, providing continuous or pulsed DC power of about 10 watts to about 50 kilowatts to a target containing the metal to be deposited on the substrate, while supplying an inert gas sufficient to maintain the desired chamber pressure. The low-energy PVD process can be performed at a substrate temperature of about room temperature (e.g., about 25 degrees Celsius to about 500 degrees Celsius).

[0022] In some embodiments, the low-energy PVD process can be performed for a sufficient duration to deposit a low-energy buffer layer to a thickness of at least about 5 angstroms as measured on the field of the substrate (e.g., the upper surface 214). In some embodiments, the thickness of the low-energy buffer layer is equal to about 5 angstroms to about 50% of the width of the feature at the top (e.g., a feature width of about 5 nm to about 300 nm).

[0023] Next, at block 120, a high-energy liner layer is deposited on the low-energy buffer layer, on top of the substrate, and within features disposed in the dielectric layer of the substrate. For example, as Figure 2B shown, a high-energy liner layer 220 can be deposited on the substrate 200, particularly on top of the upper surface 214 of the substrate and within the features 202, including on the bottom 216 and sidewalls 218 of the features 202 (e.g., on top of the low-energy buffer layer 212).

[0024] The high-energy liner layer is a metal layer (e.g., a second metal layer). Examples of suitable metals for forming the high-energy liner layer include, but are not limited to, cobalt, copper, molybdenum, ruthenium, tantalum, titanium, tungsten, nitrides of the foregoing, and combinations of the foregoing. For example, the high-energy liner layer can consist of or can be substantially composed of cobalt, copper, molybdenum, ruthenium, tantalum, titanium, tungsten, nitrides of the foregoing, and combinations of the foregoing. The high-energy liner layer can be the same metal as the low-energy buffer layer or a different metal from the low-energy buffer layer. The high-energy liner layer is a metal that is compatible with the material to be deposited to fill the features. The material for filling the features can be a metal, such as cobalt, copper, molybdenum, or tungsten.

[0025] The high-energy liner layer is deposited using a process with higher energy than the low-energy buffer layer. For example, the high-energy liner layer is deposited using a high-energy PVD process (e.g., a second PVD process) at a chamber pressure of less than or equal to 3 mTorr. The substrate bias is provided by an RF power source that provides, for example, RF energy at 13.56 MHz (although other frequencies can also be used). At greater than 0.08 watts / cm 2Apply a substrate bias at the power density shown in block 122.

[0026] Additional parameters of the high-energy PVD process can include, for example, providing continuous or pulsed DC power of about 10 watts to about 50 kilowatts to a target containing the metal to be deposited on the substrate, while supplying an inert gas sufficient to maintain the desired chamber pressure. The low-energy PVD process can be performed at a substrate temperature of about room temperature (e.g., about 25 degrees Celsius to about 500 degrees Celsius).

[0027] In some embodiments, the high-energy PVD process can be performed for a sufficient duration to deposit a high-energy liner layer to a thickness of at least about 5 angstroms as measured on the field of the substrate (e.g., the upper surface 214). In some embodiments, the thickness of the high-energy buffer layer is equal to about 5 angstroms to about 50% of the width of the feature at the top (e.g., a feature width of about 5 nm to about 300 nm). In some embodiments, the maximum combined thickness of the low-energy buffer layer and the high-energy liner layer is about the depth of the feature to be filled. In some embodiments, the maximum combined thickness of the low-energy buffer layer and the high-energy liner layer is specified by the amount of thickness of the opening of the feature that will be pinched off due to the PVD process, which can be determined empirically for any particular process being performed.

[0028] In some embodiments, the high-energy liner layer is deposited in the same PVD chamber (e.g., the first PVD chamber) as the low-energy buffer layer. In some embodiments, the low-energy PVD process continues until the low-energy buffer layer is deposited to the desired thickness. When the process terminates, the PVD chamber can be controlled to prepare and perform the high-energy PVD process and deposit the high-energy liner layer. The first PVD chamber can be a standalone chamber or part of an integrated tool (e.g., a cluster tool).

[0029] In some embodiments, the high-energy liner layer is deposited in a PVD chamber different from the low-energy buffer layer. In some embodiments, the low-energy PVD process is performed in the first PVD chamber until the low-energy buffer layer is deposited to the desired thickness. When the process terminates, the substrate can be transferred to a second PVD chamber to perform the high-energy PVD process to deposit the high-energy liner layer. In some embodiments, the transfer can be performed without breaking the vacuum. The first PVD chamber and the second PVD chamber can each be a standalone chamber or part of an integrated tool (e.g., a cluster tool).

[0030] For example, in some embodiments, a low energy buffer layer can be deposited and then, in the same PVD chamber, a high energy liner layer can be deposited without transferring the substrate and without a vacuum break. In some embodiments, the low energy buffer layer can be deposited in a first PVD chamber and then the high energy liner layer can be deposited in a different second PVD chamber. Transfer from the first PVD chamber to the second PVD chamber can be done with or without a vacuum break. However, if a vacuum break occurs, a pre-clean process may be required before depositing the high energy liner layer.

[0031] Once the deposition of the high energy liner layer is complete, method 100 generally ends. However, the substrate can continue with additional processing, such as depositing a conductive material on top of the high energy liner layer to fill features (e.g., on top of the substrate and within features disposed in a dielectric layer of the substrate). For example, as Figure 2D shown, a fill layer 222 can be deposited on substrate 200, particularly on top of the upper surface 214 of the substrate and within features 202, including on the bottom 216 and sidewalls 218 of features 202 (e.g., on top of the high energy liner layer 220). In some embodiments, the conductive material for filling the features is a metal, such as at least one of cobalt, copper, molybdenum, or tungsten.

[0032] In some embodiments, the fill process is a chemical vapor deposition (CVD) process. In some embodiments, the conductive material is a metal, such as tungsten or molybdenum. In some embodiments, the CVD chamber can be a part of an integrated tool that includes the PVD chamber configured to deposit both the low energy buffer layer and the high energy liner layer. In some embodiments, the CVD chamber can be a part of an integrated tool that includes a first PVD chamber configured to deposit the low energy buffer layer and a second PVD chamber configured to deposit the high energy liner layer. In some embodiments, the CVD chamber can be separate from one or more PVD chambers used to deposit the low energy buffer layer and the high energy liner layer.

[0033] Figure 3 FIG. 12 depicts a schematic side view of a physical vapor deposition (PVD) chamber 300 configured for substrate processing in accordance with an embodiment of the present disclosure. PVD chamber 300 is a vacuum chamber that is suitably adapted to maintain a sub-atmospheric pressure within an internal volume 320 during substrate processing. PVD chamber 300 includes a chamber body 306 covered by a lid assembly 304 that encloses a processing volume 319 located in an upper portion of the internal volume 320. Chamber body 306 and lid assembly 304 can be made of a metal, such as aluminum. Chamber body 306 can be grounded via a coupling to ground 314.

[0034] A substrate support 324 is disposed within the interior volume 320 to support and hold a substrate 322, such as a semiconductor wafer, e.g., substrate 200, during method 100. The substrate support 324 generally may include an electrostatic chuck 350 disposed on a pedestal 336 and a hollow support shaft 312 for supporting the pedestal 336 and the electrostatic chuck 350. The electrostatic chuck 350 includes a dielectric plate in which one or more electrodes 354 are disposed.

[0035] The hollow support shaft 312 provides conduits for supplying, e.g., backside gas, process gas, fluid, coolant, electricity, etc., to the electrostatic chuck 350. In some embodiments, the hollow support shaft 312 is coupled to a lift mechanism 313, such as an actuator or a motor, that provides vertical movement of the electrostatic chuck 350 between an upper processing position (as Figure 3 shown) and a lower transfer position (not illustrated).

[0036] The hollow support shaft 312 provides conduits for coupling a chuck power supply 310 and an RF bias power supply 317 to the electrostatic chuck 350. In some embodiments, the RF bias power supply 317 is coupled to the electrostatic chuck 350 via an RF matching network 316. In some embodiments, the substrate support 324 may alternatively or additionally include a DC bias power.

[0037] A substrate lifter 330 may include a lift rod 309 that is coupled to a second lift mechanism 332 to raise and lower the substrate lifter 330 such that the substrate 322 can be placed on or removed from the electrostatic chuck 350. The electrostatic chuck 350 may include a through hole to receive the lift rod 309.

[0038] A target 308 that acts as a cathode during processing is disposed in the processing volume 319 opposite the substrate support 324. The substrate support 324 has a support surface that has a plane that is substantially parallel to the sputtering surface of the target 308. The target 308 is connected to a DC power supply 390. The DC power supply 390 may apply continuous or pulsed power to the target 308.

[0039] The target 308 generally includes a sputtering plate mounted to a backing plate, but an integral target (e.g., a sputtering plate without a backing plate) may also be used. The target 308 includes a material to be sputtered onto the substrate 322, such as the materials disclosed herein with respect to method 100. In some embodiments, the PVD chamber 300 includes a magnetic field generator 356 (e.g., a magnetron) to shape the magnetic field around the target 308 to improve sputtering of the target 308.

[0040] The PVD chamber 300 includes a process kit 302 that surrounds various chamber components to prevent unwanted reactions between these components and the ionized process materials. The process kit 302 may include a process shield 305 that surrounds the substrate support 324 and the target 308 to at least partially define a processing volume 319. For example, the process shield 305 may define the outer boundary of the processing volume 319. In some embodiments, the process shield 305 is made of a metal such as aluminum. The process shield 305 may include an outer flange that rests on the chamber body 306 to support the process shield in place.

[0041] In some embodiments, the process kit 302 includes a deposition ring 370 that rests on the outer edge of the electrostatic chuck 350. In some embodiments, the process kit 302 includes a cover ring 380 that is disposed on the process shield 305 to protect the substrate support 324.

[0042] The PVD chamber 300 is coupled to and in fluid communication with a vacuum system 384 that includes a gate valve or throttle valve and a vacuum pump for evacuating the PVD chamber 300. The pressure within the PVD chamber 300 can be adjusted by regulating the throttle valve, the vacuum pump, and / or the flow rate of the gas provided to the PVD chamber 300. The PVD chamber 300 is also coupled to and in fluid communication with a process gas supply 318 that can supply one or more process gases to the PVD chamber 300 for processing a substrate 322 disposed within the PVD chamber. A slit valve 348 may be coupled to the chamber body 306 and aligned with an opening in the sidewall of the chamber body 306 to facilitate transfer of the substrate 322 into and out of the chamber body 306.

[0043] The controller 340 controls the operation of the PVD chamber 300 using direct control of the PVD chamber 300 or alternatively by controlling a computer (or controller) associated with the PVD chamber 300. In operation, the controller 340 enables data collection and feedback from the respective systems to control the performance of the PVD chamber 300. The controller 340 generally includes a central processing unit (CPU) 342, a memory 344, and support circuitry 346. The CPU 342 can be any form of general-purpose computer processor that can be used in an industrial environment. The support circuitry 636 is generally coupled to the CPU 342 and can include a cache, a clock circuit, an input / output subsystem, a power supply, and the like. Software routines such as the methods described herein can be stored in the memory 344 and, when executed by the CPU 342, transform the CPU 342 into a special-purpose computer (controller 340). The software routines can also be stored and / or executed by a second controller (not shown) located remote from the PVD chamber 300.

[0044] The memory 344 is in the form of a computer-readable storage medium containing instructions that, when executed by the CPU 342, facilitate the operation of semiconductor processes and devices. The instructions in the memory 344 are in the form of a program product, such as a program implementing the methods of the present principles. The program code can conform to any one of a variety of different programming languages. In one example, the present disclosure can be implemented as a program product stored on a computer-readable storage medium for use by a computer system. The program of the program product defines the functionality of aspects, including the methods described herein. Illustrative computer-readable storage media include, but are not limited to: non-writable storage media (e.g., read-only memory devices within a computer, such as a CD-ROM disk readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory) that permanently store information; and writable storage media (e.g., a floppy disk in a disk drive or a hard disk drive or any type of solid-state random-access semiconductor memory) that store variable information. Such a computer-readable storage medium, when carrying computer-readable instructions that direct the functionality of the methods described herein, is an aspect of the present principles.

[0045] The PVD chamber described above Figure 3 can be in a stand-alone configuration or as part of a cluster tool (e.g., as described below with reference to Figure 4Provided as part of the described integration tool 400 (e.g., a cluster tool). An advantage of using the integration tool 400 is that there is no vacuum break between chambers, and thus there is no need to degas and pre-clean the substrate before further processing. For example, in some embodiments, the method of the present invention discussed above can advantageously be performed in an integration tool such that there is a limited or no vacuum interruption between processes, thereby limiting or preventing contamination (such as oxidation, etc.) of the substrate. The integration tool 400 includes a vacuum-sealed processing platform 401, a factory interface 404, and a system controller 402. The processing platform 401 includes a plurality of processing chambers operably coupled to a vacuum substrate transfer chamber (transfer chambers 403A, 403B), such as 414A, 413B, 414C, 414D, 414E, and 414F. The factory interface 404 is operably coupled to the transfer chamber 403A through one or more load lock chambers (two load lock chambers, such as Figure 4 406A and 406B as shown in

[0046] In some embodiments, the factory interface 404 includes at least one docking station 407 and at least one factory interface robot 438 to facilitate the transfer of semiconductor substrates. The docking station 407 is configured to receive one or more front opening unified pods (FOUPs). Four FOUPs, such as 405A, 405B, 405C, and 405D, are illustrated in the Figure 4 embodiment. The factory interface robot 438 is configured to transfer substrates from the factory interface 404 to the processing platform 401 via load lock chambers (such as 406A and 406B). Each of the load lock chambers 406A and 406B has a first port coupled to the factory interface 404 and a second port coupled to the transfer chamber 403A. The load lock chambers 406A and 406B are coupled to a pressure control system (not shown) that evacuates and vents the load lock chambers 406A and 406B to facilitate the transfer of substrates between the vacuum environment of the transfer chamber 403A and the substantially ambient (e.g., atmospheric) environment of the factory interface 404. The transfer chambers 403A, 403B have vacuum robots 442A, 442B disposed in the respective transfer chambers 403A, 403B. The vacuum robot 442A is capable of transferring the substrate 421 (e.g., the substrate 200 during the execution of method 100) between the load lock chambers 406A, 406B, the processing chambers 414A and 414F, and the cooling station 440 or the pre-cleaning station 444. The vacuum robot 442B is capable of transferring the substrate 421 between the cooling station 440 or the pre-cleaning station 444 and the processing chambers 414B, 414C, 414D, and 414E.

[0047] In some embodiments, processing chambers 414A, 414B, 414C, 414D, 414E, and 414F are coupled to transfer chambers 403A, 403B. The processing chambers 414A, 414B, 414C, 414D, 414E, and 414F can include, for example, a substrate soak chamber, an atomic layer deposition (ALD) processing chamber, a physical vapor deposition (PVD) processing chamber, a remote plasma chamber, a chemical vapor deposition (CVD) chamber, an annealing chamber, and the like. These chambers can include any chamber suitable for performing all or part of the methods described herein, as discussed above, such as one or more PVD chambers configured to deposit a low-energy buffer layer and a high-energy liner layer, one or more CVD chambers configured to deposit a conductive fill, and the like. In some embodiments, one or more optional service chambers (illustrated as 416A and 416B) can be coupled to transfer chamber 403A. Service chambers 416A and 416B can be configured to perform other substrate processing, such as degassing, orientation, substrate metrology, cooling, and the like.

[0048] System controller 402 controls the operation of tool 400 using direct control of processing chambers 414A, 414B, 414C, 414D, 414E, and 414F or alternatively by controlling a computer (or controller) associated with processing chambers 414A, 414B, 414C, 414D, 414E, and 414F and tool 400. In operation, system controller 402 enables data collection and feedback from the respective chambers and systems to optimize the performance of tool 400. System controller 402 generally includes a central processing unit (CPU) 430, a memory 434, and support circuitry 432. System controller 402 can be configured similar to controller 340 described above. Software routines, such as those of the methods described above, can be stored in memory 434 and, when executed by CPU 430, transform CPU 430 into a dedicated computer (system controller) 402. The software routines can also be stored and / or executed by a second controller (not illustrated) located remote from tool 400.

[0049] Although the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure can be designed without departing from the basic scope of the present disclosure.

Claims

1. A method for processing a substrate, comprising: Deposit a metal buffer layer on the substrate and within features disposed in a dielectric layer of the substrate using a first physical vapor deposition (PVD) process at a chamber pressure of less than 500 mTorr, while applying an RF bias power of less than or equal to 0.08 watts / cm 2 to the substrate if the chamber pressure is less than or equal to 3 mTorr, and applying an RF bias power of less than or equal to 0.8 watts / cm 2 to the substrate if the chamber pressure is greater than 3 mTorr; and Deposit a metal buffer layer on top of the buffer layer, wherein the buffer layer is deposited using a second PVD process at a chamber pressure less than or equal to 3 mTorr while applying an RF bias power greater than 0.08 watts / cm 2 to the substrate.

2. The method according to claim 1, wherein the buffer layer and the liner layer are made of the same material.

3. The method according to claim 1, wherein the buffer layer and the liner layer are made of different materials.

4. The method according to claim 1, wherein the buffer layer is composed of cobalt, copper, molybdenum, ruthenium, tantalum, titanium, tungsten, nitrides of the foregoing items, and combinations of the foregoing items, and wherein the liner layer is composed of cobalt, copper, molybdenum, ruthenium, tantalum, titanium, tungsten, nitrides of the foregoing items, and combinations of the foregoing items.

5. The method according to claim 1, wherein the buffer layer is deposited to a thickness of at least about 5 angstroms.

6. The method according to claim 5, wherein the liner layer is deposited to a thickness of at least about 5 angstroms.

7. The method according to claim 1, wherein the buffer layer and the liner layer are deposited in the same PVD chamber without breaking vacuum.

8. The method according to claim 1, wherein the buffer layer and the liner layer are deposited in different PVD chambers.

9. The method according to claim 1, wherein the buffer layer and the liner layer are deposited in different PVD chambers without breaking vacuum.

10. The method according to any one of claims 1-9, further comprising: depositing a conductive layer on top of the liner layer to fill the feature.

11. The method according to claim 10, wherein the conductive layer is deposited via a chemical vapor deposition process.

12. The method according to claim 10, wherein the conductive layer is a metal layer.

13. The method according to claim 12, wherein the conductive layer is at least one of cobalt, copper, molybdenum, or tungsten.

14. A non-transitory computer-readable medium having instructions stored thereon that, when executed, cause a method to be performed, the method comprising: Deposit a metal buffer layer on the substrate and within features disposed in a dielectric layer of the substrate using a first physical vapor deposition (PVD) process at a chamber pressure less than 500 mTorr, and apply an RF bias power less than or equal to 0.08 watts / cm 2 to the substrate if the chamber pressure is less than or equal to 3 mTorr, and apply an RF bias power less than or equal to 0.8 watts / cm 2 to the substrate if the chamber pressure is greater than 3 mTorr; and Deposit a metal buffer layer on top of the buffer layer, where the buffer layer is deposited using a second PVD process at a chamber pressure less than or equal to 3 mTorr while applying an RF bias power greater than 0.08 watts / cm 2 to the substrate.

15. The non-transitory computer-readable medium according to claim 14, wherein the liner layer is deposited on top of the buffer layer without breaking vacuum.

16. A system for processing a substrate, comprising: A first PVD chamber configured to deposit a metal buffer layer on a substrate and within features disposed in a dielectric layer of the substrate, wherein the first PVD chamber is configured to deposit the buffer layer using a first physical vapor deposition (PVD) process at a chamber pressure less than 500 mTorr, while applying an RF bias power less than or equal to 0.08 watts / cm 2 to the substrate if the chamber pressure is less than or equal to 3 mTorr, and applying an RF bias power less than or equal to 0.8 watts / cm 2 to the substrate if the chamber pressure is greater than 3 mTorr; and A second PVD chamber, configured to deposit a metal liner layer on top of the buffer layer, wherein the second PVD chamber is configured to deposit the liner layer using a second PVD process at a chamber pressure less than or equal to 3 mTorr while applying an RF bias power greater than 0.08 watts / cm 2 to the substrate.

17. The system according to claim 16, wherein the first PVD chamber and the second PVD chamber are the same chamber.

18. The system according to claim 16, wherein the first PVD chamber and the second PVD chamber are different chambers.

19. The system according to any one of claims 16-18, further comprising: a vacuum substrate transfer chamber having the first PVD chamber and the second PVD chamber coupled thereto.

20. The system according to claim 19, further comprising a chemical vapor deposition chamber configured to deposit a metal layer on top of the liner layer to fill the feature.

Images