NOR memory and its programming and erasing method

Abstract

The application provides a NOR memory and a programming and erasing method thereof, comprising: N minimum data storage modules arranged in sequence along the row direction of the memory cells, and sharing a word line row driving circuit; each data storage module comprises an independent memory cell array, a switch selection unit, a common source, a well and a corresponding switching unit, the switch selection unit and the switching unit are arranged at the periphery of the memory cell array; the gate of the same row of memory cells in the memory cell array is connected to the same word line, and the drain of the same column of memory cells is connected to the same bit line; the switch selection unit connects every M bit lines in the memory cell array to a corresponding main bit line; the switching unit connects the common source and the well of the memory cell array, and provides the required driving voltage for the common source and the well. When a certain selected sector or block of the NOR memory is programmed and erased, the application avoids electrical crosstalk to other non-selected sectors or blocks, and the increase in area can also be better controlled.

Description

Technical Field

[0001] This invention relates to the field of memory array layout design, and in particular to a NOR memory and its programming and erasing methods. Background Technology

[0002] Memory, also known as RAM, is a hardware component in a computer system used to store data and programs. Its function is to temporarily or permanently store data and instructions so that the processor (CPU) or other hardware components can access and execute them.

[0003] Memory can be divided into two main categories: volatile memory and non-volatile memory. Volatile memory, such as random access memory (RAM), loses data when power is turned off; this includes dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory, such as hard disk drives (HDDs), solid-state drives (SSDs), and flash memory, retains data even when power is off. NOR flash memory is a type of non-volatile memory, consisting of a series of ordered storage cells, each with a unique address. Data can be read or written directly by accessing the address. NOR flash memory is widely used in many fields due to its fast random access capabilities.

[0004] Existing NOR flash memory arrays are generally divided into the following parts: the memory array, which is the core part of the NOR flash memory and is used to store data "0" or "1". The memory array is composed of a large number of memory cells connected in parallel in a horizontal and vertical interlacing manner of word lines (WL) and bit lines (BL) according to the NOR type arrangement. It is the most important part of the entire memory array. Its area, cost, performance and reliability are not only closely related to the manufacturing process, but also inseparable from the layout design of the entire array. Word line row drivers (WL DRVs), located on the left or right side of the memory matrix, are used to accurately address the gate of the memory cell being operated on and provide the correct voltage during read, write, and erase operations. Since these operations involve relatively high voltages, such as -10V to +10V, the components required for these driver circuits are often high-voltage resistant. Furthermore, different word lines require different output voltages depending on the operating state, making the situation complex. Therefore, this part of the circuit occupies a significant portion of the area in the entire NOR memory array. Word line rows, located inside the memory matrix, connect the corresponding word line driver and the gate of the memory cell at both ends of each row. During read, write, and erase operations, the word line driver uses the word lines to accurately address the gate of the memory cell being operated on and provide the correct voltage. The same word line continuously connects the gates of multiple memory cells on the same row; the number of memory cells is equal to the number of bit lines. Bit lines, located within the memory matrix, are used to accurately address the drain of memory cells during read, write, and erase operations, providing the necessary voltage or output current. A single bit line continuously connects the drains of multiple memory cells in the same column, with the number of memory cells equal to the number of word lines. Main Bit Line (MBL): The main bit line is the superior bit line to the bit lines. Typically, a main bit line connects to multiple bit lines through multiple switching transistors, and it is usually longer than the bit lines, covering a larger area. The select gate module (SG) is located on the top and bottom sides of the memory matrix. It is used to connect the main bit line and the corresponding multiple bit lines. Its number is the same as the number of bit lines. When performing read, write, erase and other operations on the memory cells inside the memory matrix, the chip controls the opening and closing of the select gate through the operation address decoding circuit, thereby determining whether to transmit the operation voltage into the bit line (write operation) or to output the current of the memory cell through the bit line to the sensitive amplifier connected to the main bit line (read operation).The block switch circuit, located around the periphery of the memory matrix, is used to address the common source line (SL) and memory well of the memory matrix sector when performing read, write, and erase operations on the memory cells inside the memory matrix, and provides the necessary voltage drive.

[0005] like Figure 1 and Figure 2 As shown, taking a block 1 of a 4Mb = 4096Kb NOR memory array as an example, this 4Mb block consists of eight storage sub-matrices 110-117 (forming storage matrix 11) from bottom to top, each storage sub-matrix having a capacity of 512Kb. To the left of storage matrix 11 are eight word line row driver units 120-127 (SECs) corresponding to each storage sub-matrix. <0> -SEC <7> The storage matrix 11 consists of a word line drive (12), comprising 256 word line drive circuits. The right side is a shared block switching circuit 14 (including common-source and well drive circuits). The upper and lower sides of the storage matrix 11 are bit line switch selection modules 131 and 132 (in this example, four switch control signals SG_0 to SG_3 are set, each controlling the selection of 4096 bit lines). Each major bit line MBL is connected to four lower-level bit lines BL (or 8, 16, 32, etc.). There are 4096 major bit lines MBL and 16384 bit lines BL. It is important to note that the entire block shares a set of upper and lower switch selection modules 13, and the sources and wells of all eight sectors are connected together. Each 512Kb sector contains 32 word lines and 16K (=16×1024=16384) bit lines, satisfying the condition that sector capacity = number of word lines per sector × number of bit lines; the left side is the row drive unit for each sector's 32 word lines, and the right side is the shared block switching circuit 14; there are no independent switching selection transistors on the top and bottom sides; such as Figure 3 and Figure 4 As shown, this is the lowest-order sector.

[0006] As can be seen from the above, this 4Mb memory array (Block) maximizes the saving of memory array area by sharing all the switch selection modules, common sources, and wells of each memory submatrix into a single group, making it the most compact array layout method. However, based on the erase and write operation conditions of this array, for any selected target memory cell A (denoted by SEC) within the Block... <0> The corresponding position is WL <0> BL <0> (taking a cell as an example) and a non-selected memory cell B (taking SEC) on the same bit line but belonging to a different sector. <7> The corresponding position is WL <255> BL <0> Taking the unit as an example, since they share the switch selection transistor SGa, when performing a write (programming) operation, the main bit line MBL... <0> The 4V programming voltage on the SG is passed through <0> The control turns on the switch selector transistor SGa, which in turn transmits the signal to the bit line BL. <0> This refers to all 256 connected memory cells, including both the selected target cell A and all other unselected cells, such as cell B. Similarly, since all sectors share the same well, the well potentials of the selected target cell A and unselected cell B are identical during an erase operation. (Refer to...) Figure 2 And see Table 1 below.

[0007]

[0008] Table 1

[0009] This results in the only difference in voltage conditions at each terminal of the selected target memory cell A and the unselected memory cell B on the same bit line BL, regardless of whether it's erasing or writing, being the word line WL. <0> and WL <255> The difference is that the other bit lines, source lines, and sink potentials are the same. This is due to the Block layout design method of this 4Mb memory array. The direct consequence is that during a write operation, the unselected memory cell on the same bit line has to endure a 4V bit line crosstalk. The longest total time of this crosstalk can be roughly estimated as: 10us (write time per row) × 32 (number of word lines per sector) × 100,000 (number of erase / write cycles per sector) × 7 (number of sectors) = 224 seconds. If the unselected memory cell B is in the data "0" state, it means that its floating gate stores a lot of negatively charged electrons. Since the bit line is positive at 4V, this creates a prolonged positive electric field between the bit line and the floating gate. The negatively charged electrons in the floating gate are easily caused by the weak FN tunneling effect due to this prolonged positive electric field, causing them to fall out of the floating gate, resulting in charge loss. This significantly affects the stability of the data "0", reduces the correct window for data "0", and can even lead to data errors; this is especially problematic when the unselected cell has also undergone repeated high-temperature erasures and writes. Similarly, during the erase operation, the unselected memory cell B in different sectors is subjected to a 9V well-to-word line crosstalk. The longest total time of this crosstalk can be estimated as: 50ms (erasure time per sector) × 100,000 (number of erase / write cycles per sector) × 7 (number of sectors) = 35,000 seconds. Similarly, for the data "0" state, the well crosstalk will also create a weak FN tunneling effect with a positive electric field from the well to the floating gate for an extremely long time. This causes negatively charged electrons in the floating gate to fall out, resulting in charge drop, which can eventually lead to data errors. Both of these types of data errors are unacceptable for NOR flash memory, which is primarily used for storing code.

[0010] Current solutions to the above problems generally involve large footprints. Therefore, how to improve the reliability of NOR memory while taking cost into account has become one of the urgent problems to be solved by those skilled in the art.

[0011] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0012] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a NOR memory and its programming and erasing methods to solve the problem that the reliability and cost of NOR memory cannot be balanced in the prior art.

[0013] To achieve the above and other related objectives, the present invention provides a NOR memory, the NOR memory comprising at least:

[0014] The N data storage modules are arranged sequentially along the row direction of the storage unit and share the word line drive circuit. The same row of the N data storage modules receives the same word line drive signal.

[0015] Each data storage module includes an independent memory cell array, a switch selection unit, a common source, a well, and a switching unit. The switch selection unit and the switching unit are located on the periphery of the memory cell array. In the memory cell array, the gates of memory cells in the same row are connected to the same word line, and the drains of memory cells in the same column are connected to the same bit line. All memory cells share a common source and have the same well potential. The switch selection unit connects every M bit lines in the memory cell array to a corresponding major bit line. The switching unit connects the common source and well of the memory cell array, providing the required drive voltage to the common source and well of each memory cell in the memory cell array.

[0016] Wherein, the data storage module is the smallest erase array unit, N is a natural number greater than or equal to 2, and M is a natural number greater than or equal to 2.

[0017] Optionally, the data storage module is a sector or a block.

[0018] Optionally, the word line row driving circuit is disposed on the periphery of the storage area composed of each data storage module, and is arranged sequentially with each data storage module along the row direction of the storage unit.

[0019] Optionally, the switching unit is located at one end of the word line in the corresponding memory cell array.

[0020] Alternatively, the structures of two adjacent data storage modules can be mirrored.

[0021] Optionally, the switch selection unit is located at at least one end of the bit line in the corresponding memory cell array.

[0022] Optionally, the storage cell is an N-type storage cell, a P-type storage cell, a floating gate storage cell, or a charge trap storage cell.

[0023] To achieve the above and other related objectives, the present invention also provides a method for programming a NOR memory, implemented using the aforementioned NOR memory, wherein the method for programming the NOR memory includes at least:

[0024] Each switching unit configures the common source voltage and sink voltage for the corresponding data storage module;

[0025] The row containing the memory cell to be programmed is selected based on the word line row driving circuit;

[0026] Based on the switch selection unit in the data storage module where the storage unit to be programmed is located, the bit line of the column where the storage unit to be programmed is located is selected, and data is written.

[0027] Optionally, the common source voltage of each data storage module is equal, and the sink voltage of each data storage module is equal.

[0028] Alternatively, when the storage cell in the data storage module is an N-type floating gate storage cell, the common source voltage and sink voltage of each data storage module are configured to 0V.

[0029] To achieve the above and other related objectives, the present invention also provides a method for erasing a NOR memory, which employs the aforementioned NOR memory. The method for erasing the NOR memory includes at least the following:

[0030] Based on the word line row driving circuit and each switch selection unit, the same word line voltage and bit line voltage are configured for each memory cell;

[0031] Based on the corresponding switching unit in the data storage module that does not need to be erased, the common source of the data storage module that does not need to be erased is floated, and the sink voltage is configured to be equal to the word line voltage.

[0032] Based on the switching unit in the data storage module to be erased, the common source voltage and sink voltage of the data storage module to be erased are set to a set voltage to achieve data erasure.

[0033] Optionally, when the storage unit in the data storage module is an N-type floating gate storage unit, the set voltage is 7V to 10V.

[0034] Optionally, when the storage unit in the data storage module is an N-type floating gate storage unit, the word line of each storage unit is configured with negative high voltage and the bit line is floating.

[0035] Alternatively, the negative high voltage is -8V to -10V.

[0036] As described above, the NOR memory and its programming and erasing methods of the present invention have the following beneficial effects:

[0037] The NOR memory and its programming and erasing method of the present invention isolate the bit lines, sources and wells of each sector or block, so as to avoid electrical crosstalk to other unselected sectors or blocks when programming and erasing a selected sector or block; at the same time, different sectors or blocks in the same row share the same set of word line row drive circuits, thereby greatly reducing the area occupied by the NOR memory; and taking into account both reliability and cost. Attached Figure Description

[0038] Figure 1 The diagram shows a 4Mb Block array consisting of eight sectors arranged vertically.

[0039] Figure 2 The diagram shows a 4Mb Block array composed of storage cells.

[0040] Figure 3 Displayed as Figure 1 A schematic diagram of a 512Kb sector array.

[0041] Figure 4 Displayed as Figure 1 A schematic diagram of a 512kb sector array composed of storage cells.

[0042] Figure 5 The diagram shows a 4Mb Block array consisting of 8 sectors arranged horizontally.

[0043] Figure 6 Displayed as Figure 5 A schematic diagram of the structure where two adjacent sectors are mirrored.

[0044] Figure 7 Displayed as Figure 5 A schematic diagram of a 512kb sector array composed of storage cells.

[0045] Figure 8 The diagram shown is a block diagram of the NOR memory of this invention.

[0046] Figure 9 The diagram shown is a block diagram of a sector of the present invention.

[0047] Figure 10 The diagram shown is a structural schematic of a 512kb sector array composed of storage cells according to the present invention.

[0048] Figure 11 The diagram shown is a block diagram of a 4Mb Block array consisting of eight sectors arranged horizontally according to the present invention.

[0049] Figure 12 The diagram shows a schematic representation of the mirrored distribution of two adjacent sectors in this invention.

[0050] Component designation explanation

[0051] 1 NOR type memory array

[0052] Storage submatrices 110, 111, 116, and 117

[0053] 11 Storage Matrix

[0054] Word line drive units 120, 121, 126, 127

[0055] 12-line drive

[0056] 131, 132 Switch Selection Transistor Module

[0057] 14 switching circuits

[0058] 2 NOR type memory array

[0059] Sectors 20, 21, 26, and 27

[0060] 201, 211 storage submatrices

[0061] 202, 212 Word Line Drive Unit

[0062] 203a, 203b, 213a, 213b, Switch Selection Transistor Module

[0063] 204, 214 sector switching circuit

[0064] 3 NOR memory

[0065] 31-line drive circuit

[0066] Data storage modules 320, 321, 326, 327, 32(N-2), 32(N-1)

[0067] 32 storage areas

[0068] 3a Memory Cell Array

[0069] 3b1, 3b2 switch selection unit

[0070] 3C switching unit Detailed Implementation

[0071] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] Please see Figures 5-12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0073] like Figure 5 As shown, a memory array layout is proposed where each sector has its own independent switch selection transistor module and well, taking a 4Mb = 4096Kb NOR memory array (Block 2) as an example. This 4Mb Block consists of 8 sectors 20-27 from left to right. <0> -SECTOR <7> Each sector (forming a block) has a capacity of 512Kb. Within a block, each sector has its own independent 256 word lines drive unit, as well as its own independent source and well drive circuitry. For example... Figure 6 As shown, sector 20 includes a storage submatrix 201, a word line row driver unit 202, switch selection transistor modules 203a and 203b, and a sector switching circuit 204; sector 21 includes a storage submatrix 211, a word line row driver unit 212, switch selection transistor modules 213a and 213b, and a sector switching circuit 214; other sectors have the same composition and will not be described in detail here. Each sector has switch selection transistors for bit lines on both the top and bottom sides, and each main bit line MBL is connected to four lower-level bit lines BL (or 8, 16, 32, etc.). The total number of main bit lines MBL in the entire block is still 4096, and the number of bit lines BL is 16384. For ease of layout and routing, the Mth sector and the (M+1)th sector (M=1, 2, 3) within the 4Mb Block array are mirror images in structural layout. For example... Figure 7 As shown (taking the least significant sector as an example), each 512Kb sector contains 256 word lines and 2×1024=2048=2K bit lines, satisfying the condition that sector capacity = number of word lines per sector × number of bit lines; the left side is the row drive unit for the 256 word lines of each sector, and the right side is the independent sector switching circuit (common source and well drive) for each sector; both the top and bottom sides have their own independent switching selection transistors for each sector.

[0074] As can be seen from the above, this type of 4Mb storage array Block, because it arranges the sectors horizontally, and each sector contains its own independent switch selection transistor module and well, as well as its own independent 256 word line row drive unit, is the most wasteful in terms of storage array Block area, but it is the safest array layout method. Based on the erase and write operation conditions of this array, for any selected target storage cell A (in Sec...) within the Block... <0> The corresponding position is WL <0> BL <0> Taking the cell as an example) and the non-selected memory cell B (taking Sec) in the same sector and on the same bit line (because each sector has an independent switch selection module, memory cells on the same bit line can only be located within the same sector). <0> The corresponding position is WL <255> BL <0> Taking a unit as an example, during a write operation, the major bit line MBL... <0> The 4V programming voltage is supplied via SG. <0> Turn on switch SGa and pass it to bit line BL. <0> This refers to all 256 connected memory cells, including both the selected target cell A and all other unselected cells, such as cell B. Similarly, since each sector has its own independent word line driver and sink, when performing an erase operation, the selected Sec... <0> Target cell A and unselected storage cell C (in Sec) <1> The corresponding position is WL <255> BL <4095> Taking a cell as an example, the word line and well potential can be different, such as... Figure 6 And as shown in Table 2 below.

[0075]

[0076]

[0077] Table 2

[0078] During the write operation, since target cell A and unselected cell B are in the same sector, there is no need to consider the additional 100,000 erase / write cycles; only the sector needs to be moved from the word line WL. <0> Continue writing up to the word line WL <254> The worst-case scenario is considered. During this process, although the unselected memory cell B on the same bit line will experience a 4V bit line crosstalk, the total time of this crosstalk can be roughly estimated as: 10µs (write time per row) × 255 (number of word lines per sector - 1) = 2.55 milliseconds, a significant reduction compared to the previous 224 seconds, making its bit line crosstalk effect almost negligible. For the target cell A and the unselected cell C in a different sector, as can be seen from Table 2's operating voltage, the BL of cell C at this time... <4095> and WL <255> Both are equal to 0V, with no voltage difference, therefore there is naturally no bit line crosstalk. During the erase operation, target cell A and cell B are in the same sector, and the smallest erase unit of NOR Flash is a sector, so these two cells are definitely erased simultaneously, without any so-called well-to-word line crosstalk. Target cell A and the unselected cell C, which is in a different sector, have their own independent wells, common-source terminals, and word line drives. As can be seen from the operating voltages in Table 2, the WL of cell C at this time... <255> Since both the sink and the word line are equal to 0V, there is no voltage difference, so there is naturally no crosstalk from the sink to the word line.

[0079] As can be seen from the above, the memory array block layout design scheme with completely independent word line drivers, switch selection transistor modules, traps and common source in each sector can solve and avoid the aforementioned bit line crosstalk and trap crosstalk. The cost is that the array area will become relatively large, and the difference can be more than 20%-50% depending on the different array block capacities.

[0080] To balance the reliability and footprint of NOR memory, this invention proposes a NOR memory 3, such as... Figure 8 As shown, the NOR memory 3 includes:

[0081] The word line drive circuit 31 and N data storage modules (320, 321, ..., 32(N-2), 32(N-1)) are arranged sequentially along the row direction of the storage cell and share the word line drive circuit 31. The same row of the N data storage modules receives the same word line drive signal.

[0082] like Figure 9 and Figure 10As shown, each data storage module (320, 321, ..., 32(N-2), 32(N-1)) includes an independent storage cell array 3a, switch selection units (3b1 and 3b2), a common source, a sink, and a switching unit 3c. The switch selection units (3b1 and 3b2) and the switching unit 3c are located around the storage cell array 3a. The storage cell array 3a (as an example, is configured with a 256-row, 2048-column array structure) Figure 9 and Figure 10 In this array, i is an integer satisfying the following conditions: (i = 0, 1, ..., N-1). The gates of memory cells in the same row are connected to the same word line WL, and the drains of memory cells in the same column are connected to the same bit line BL. All memory cells share a common source and have the same well potential. Switch selection units (3b1 and 3b2) connect every M bit lines BL in the memory cell array 3a to a corresponding major bit line MBL (for example, M is set to 4). The lower-level bit lines BL corresponding to the same major bit line MBL are isolated by the corresponding switch selection transistors. Switching unit 3c connects the common source and well of the memory cell array 3a and provides the required drive voltage to the common source and well of each memory cell in the memory cell array 3a. The wells of different memory cell arrays 3a are isolated by wells of opposite types. The data storage module 3a is the smallest erase array unit, including but not limited to sectors or blocks, where N is a natural number greater than or equal to 2, and M is a natural number greater than or equal to 2.

[0083] Specifically, such as Figure 8 As shown, the word line row driving circuit 31 is located on the periphery of the storage area 32 formed by the data storage modules (320, 321, ..., 32(N-2), 32(N-1)), and is arranged sequentially with the data storage modules (320, 321, ..., 32(N-2), 32(N-1)) along the row direction of the storage cells. That is, the word line row driving circuit 31 is located at one end of the storage area 32, providing word line driving signals corresponding to the row number of the storage cells in the data storage modules (320, 321, ..., 32(N-2), 32(N-1)). Each word line driving signal can simultaneously control one row of N data storage modules (320, 321, ..., 32(N-2), 32(N-1)) (i.e., storage cells in different data storage modules in the same row share the same set of word lines).

[0084] Specifically, such as Figure 9 and Figure 10As shown, in this embodiment, in each data storage module (320, 321, ..., 32(N-2), 32(N-1)), the switching unit 3c is disposed at one end (left or right) of the word line in the corresponding storage cell array 3a; that is, the storage cell array 3a and the switching unit 3c are arranged in the row direction of the storage cell. The switch selection units (3b1 and 3b2) are disposed at at least one end of the bit line in the corresponding storage cell array 3a; as an example, the switch selection unit is divided into two parts 3b1 and 3b2, and the two parts are respectively disposed at both ends (top and bottom) of the bit line of the storage cell array 3a.

[0085] It should be noted that, in this example, for ease of wiring, the switching unit 3c is positioned in the row direction of the memory cell array 3a, and the switch selection units (3b1 and 3b2) are positioned in the column direction of the memory cell array 3a. In actual use, the positions of the switching unit and the switch selection unit can be interchanged, or they can be positioned on the same side, and are not limited to this embodiment.

[0086] To facilitate wiring, adjacent data storage modules are further configured as mirror images (symmetrically distributed). Of course, in actual use, mirroring is not necessary.

[0087] Specifically, the memory cell is configured as an N-type memory cell, a P-type memory cell, a floating gate memory cell, or a charge trap memory cell. Any structure that can be used as a memory cell in a NOR memory is applicable to this invention, and will not be described in detail here.

[0088] The present invention will be described below using a 4Mb = 4096Kb NOR flash memory as an example, wherein the data storage module 3a is a sector; of course, the data storage module 3a can also be set as a block, in which case the block is the smallest erase unit in the memory, which will not be elaborated here.

[0089] like Figure 11 As shown in the example, this 4Mb block consists of eight sectors 320-327 arranged from left to right. <0> ~SECTOR <7> The block consists of 16 sectors, each with a capacity of 512Kb. Other configurations are also possible, including but not limited to 16 sectors with a capacity of 256Kb each. The block capacity must satisfy the condition: Block capacity = sector capacity × number of sectors. This embodiment is not limited to this specific example. Each sector has its own independent switching unit 3c (providing the common source and well drive voltages), but no independent word line drive. Instead, the entire block shares a set of word line drive circuits 31. This significantly reduces the area required, as adding seven more sets in this example would be necessary if each sector used a separate set of word line drive circuits. Figure 9 and Figure 10 As shown, the top and bottom sides of the sector are equipped with bit line switch selection transistors, and each major bit line MBL is connected to four lower-level bit lines BL. Therefore, the entire block has 4096 major bit lines MBL and 16384 bit lines BL. The number of lower-level bit lines corresponding to each major bit line MBL can be set according to actual needs, including but not limited to 8, 16, and 32, which will not be elaborated here. Each 512Kb sector contains 256 word lines and 2 × 1024 = 2048 = 2K bit lines, satisfying the condition that the sector capacity = number of word lines per sector × number of bit lines. The inner side of each sector no longer has an independent 256 word line row driver for each sector, but only a metal connection to the shared word line row driver circuit 31 on the outermost side of the block. The right side still has an independent switching unit 3c for each sector. The top and bottom sides each have their own independent switch selection transistor switch selection units (3b1 and 3b2).

[0090] Furthermore, such as Figure 12 As shown, data storage modules 320 and 321 are arranged adjacently and in a mirror image (symmetrical to each other); any two adjacent data storage modules are set in a mirror relationship, which will not be elaborated here.

[0091] As can be seen from the above, since the sectors in the 4Mb memory array Block of the present invention are arranged horizontally, and each sector contains its own independent switch selection unit and well, but does not have its own independent 256 word line drivers, the entire Block shares a set of word line row drive circuits. This can avoid bit line crosstalk and well crosstalk, and can also greatly reduce the area, which is a memory array layout scheme that achieves the best of both worlds.

[0092] The programming method of the NOR memory 3 of the present invention is as follows:

[0093] 11) Configure the common source voltage and sink voltage for the corresponding data storage module based on each switching unit.

[0094] Specifically, the common-source voltage SL of each data storage module is equal, and the well voltage Mwell of each data storage module is equal; in this embodiment, the common-source voltage and well voltage of each data storage module are configured to 0V. It should be noted that the common-source voltage and well voltage of each data storage module are provided by the corresponding internal switching unit 3c.

[0095] 12) Based on the word line row driving circuit 31, select the row where the memory cell to be programmed is located.

[0096] Specifically, the word line drive circuit 31 provides word line drive voltages corresponding to each row. Each row of each data storage module receives the same word line drive voltage. The gates of all memory cells in the selected row are turned on. The corresponding drive voltage value can be configured according to actual needs.

[0097] 13) Based on the switch selection unit in the data storage module where the storage cell to be programmed is located, select the bit line of the column where the storage cell to be programmed is located and write the data.

[0098] The erasure method of the NOR memory 3 of the present invention is as follows:

[0099] 21) Based on the word line row driving circuit and each switch selection unit, configure the same word line voltage and bit line voltage for each memory cell.

[0100] Specifically, in this embodiment, the word lines of each memory cell are configured with negative high voltage, and the bit lines are floating; wherein, the negative high voltage is set to -8V to -10V, including but not limited to -8.5V, -9V, and -9.5V, which will not be described in detail here.

[0101] 22) Based on the corresponding switching unit in the data storage module that does not need to be erased, the common source of the data storage module that does not need to be erased is floated, and the sink voltage is configured to be equal to the word line voltage.

[0102] Specifically, in this embodiment, the well voltage and word line voltage of each memory cell in the data storage module that does not need to be erased are both negative high voltage.

[0103] 23) Based on the switching unit in the data storage module to be erased, the common source voltage and sink voltage of the data storage module to be erased are set to a set voltage to achieve data erasure.

[0104] Specifically, in this embodiment, the voltage is set to 7V to 10V, including but not limited to 8V, 8.5V, 9V, and 9.5V, which will not be elaborated here. As an example, the common-source voltage and well voltage of the data storage module to be erased are the same.

[0105] It should be noted that, in this embodiment, the programming and erasing methods of the NOR memory 3 are based on the N-type floating gate memory cell, and voltage values ​​are set for each node. In actual use, for memory cells of different types and different processes, the corresponding voltage values ​​can be configured according to actual needs, and are not limited to this embodiment.

[0106] like Figure 12As shown, for any selected target storage unit A within the Block (using WL in data storage module 320) <0> BL <0> (Taking cell 320 as an example) and the unselected memory cell B in the same sector and bit line (taking WL in data storage module 320 as an example) <255> BL <0> Taking a unit as an example, during a write operation, the major bit line MBL... <0> The 4V programming voltage is transmitted to the bit line BL through the corresponding switch selection transistor. <0> This refers to all 256 connected storage units, including both the selected target unit A and all other non-selected units, such as unit B, as shown in Table 3 below. Similarly, since each sector has its own independent well, during the erase operation, target unit A and non-selected storage units C (as shown in WL in data storage module 321) are considered. <255> BL <4095> The trap potential of a single cell can be different, as shown in Table 3 below.

[0107]

[0108] Table 3

[0109] During the write operation, since target cell A and unselected cell B are in the same sector, there is no need to consider the additional 100,000 erase / write cycles; only the sector needs to be moved from WL. <0> Continue writing until WL <254> The worst-case scenario is acceptable. During this process, although the unselected memory cell B on the same bit line will experience a 4V bit-line crosstalk, the total time of this crosstalk can be roughly estimated as: 10µs (write time per row) × 255 (number of word lines per sector - 1) = 2.55 milliseconds. Figure 1 The 224-second time limit of the solution is significantly reduced, and the impact of bit line crosstalk is almost negligible. As can be seen from Table 3, the operating voltages of target cell A and the unselected cell C, which are in different sectors, are such that the BL of the unselected cell C is... <4095> and WL <255> Both are equal to 0V, with no voltage difference, therefore there is naturally no well-to-word line crosstalk. During the erase operation, consider two cases: Target cell A and unselected cell B are in the same sector, and the smallest erase unit of a NOR Flash is a sector; therefore, these two cells are erased simultaneously, with no well-to-word line crosstalk. Target cell A and unselected cell C are in different sectors. Since different sectors have their own independent Mwell,SL, as can be seen from the operating voltages in Table 3, the WL of unselected cell C is... <255> Since both the sink and the word line are equal to -9.5V and there is no voltage difference, there is naturally no crosstalk from the sink to the word line.

[0110] As shown in Table 4 below, the present invention can solve the crosstalk problem and effectively control the waste of array area, thus achieving both goals.

[0111]

[0112] Table 4

[0113] In summary, this invention provides a NOR memory and its programming and erasing methods, comprising: a word line row driving circuit and N data storage modules; the N data storage modules are arranged sequentially along the row direction of the memory cells and share the word line row driving circuit, and the same row of the N data storage modules receives the same word line driving signal; each data storage module includes an independent memory cell array, a switch selection unit, a common source, a well, and a switching unit, the switch selection unit and the switching unit being disposed on the periphery of the memory cell array; the gates of memory cells in the same row of the memory cell array are connected to the same word line, the drains of memory cells in the same column are connected to the same bit line, and all memory cells share the same source and have the same well potential; the switch selection unit connects every M bit lines in the memory cell array to a corresponding major bit line; the switching unit connects the common source and well of the memory cell array and provides the required driving voltage to the common source and well of each memory cell in the memory cell array; wherein, the data storage module is the smallest erasing array unit, N is a natural number greater than or equal to 2, and M is a natural number greater than or equal to 2. This invention avoids electrical crosstalk to other unselected sectors or blocks when programming and erasing a selected sector or block of a NOR memory, and the increase in area can also be well controlled. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A NOR memory, characterized in that, The NOR memory includes at least: The N data storage modules are arranged sequentially along the row direction of the storage unit and share the word line drive circuit. The same row of the N data storage modules receives the same word line drive signal. Each data storage module includes an independent memory cell array, a switch selection unit, a common source, a well, and a switching unit. The switch selection unit and the switching unit are located on the periphery of the memory cell array. In the memory cell array, the gates of memory cells in the same row are connected to the same word line, and the drains of memory cells in the same column are connected to the same bit line. All memory cells share a common source and have the same well potential. The switch selection unit connects every M bit lines in the memory cell array to a corresponding major bit line. The switching unit connects the common source and well of the memory cell array and provides the required drive voltage to the common source and well of each memory cell in the memory cell array. The data storage module is the smallest erase array unit, where N is a natural number greater than or equal to 2 and M is a natural number greater than or equal to 2; the structures of two adjacent smallest data storage modules are mirror images of each other.

2. The NOR memory according to claim 1, characterized in that: The data storage module is a sector or a block.

3. The NOR memory according to claim 1, characterized in that: The word line row driving circuit is located on the periphery of the storage area formed by each data storage module, and is arranged sequentially with each data storage module along the row direction of the storage unit.

4. The NOR memory according to claim 1, characterized in that: The switching unit is located at one end of the word line in the corresponding memory cell array.

5. The NOR memory according to claim 1, characterized in that: The switch selection unit is located at at least one end of the bit line in the corresponding memory cell array.

6. The NOR memory according to claim 1, characterized in that: The storage unit is an N-type storage unit, a P-type storage unit, a floating gate storage unit, or a charge trap storage unit.

7. A method for programming a NOR memory, implemented using the NOR memory as described in any one of claims 1-6, characterized in that, The programming method for the NOR memory includes at least the following: Each switching unit configures the common source voltage and sink voltage for the corresponding data storage module; The row containing the memory cell to be programmed is selected based on the word line row driving circuit; Based on the switch selection unit in the data storage module where the storage unit to be programmed is located, the bit line of the column where the storage unit to be programmed is located is selected, and data is written.

8. The programming method for NOR memory according to claim 7, characterized in that: The common-source voltage of each data storage module is equal, and the sink voltage of each data storage module is equal.

9. The programming method for NOR memory according to claim 8, characterized in that: When the storage cells in the data storage module are N-type floating gate storage cells, the common source voltage and sink voltage of each data storage module are configured to 0V.

10. A method for erasing a NOR memory, implemented using the NOR memory as described in any one of claims 1-6, characterized in that, The erasure method for the NOR memory includes at least the following: Based on the word line row driving circuit and each switch selection unit, the same word line voltage and bit line voltage are configured for each memory cell; Based on the corresponding switching unit in the data storage module that does not need to be erased, the common source of the data storage module that does not need to be erased is floated, and the sink voltage is configured to be equal to the word line voltage. Based on the switching unit in the data storage module to be erased, the common source voltage and sink voltage of the data storage module to be erased are set to a set voltage to achieve data erasure.

11. The method for erasing NOR memory according to claim 10, characterized in that: When the storage unit in the data storage module is an N-type floating gate storage unit, the set voltage is 7V~10V.

12. The method for erasing NOR memory according to claim 10, characterized in that: When the storage cell in the data storage module is an N-type floating gate storage cell, the word line of each storage cell is configured with negative high voltage and the bit line is floating.

13. The method for erasing NOR memory according to claim 12, characterized in that: The negative high voltage is -8V to -10V.

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