Interface circuit, conversion method, and integrated circuit for multi-phase data conversion

Abstract

The present application discloses an interface circuit, conversion method, and integrated circuit for multi-phase data conversion, comprising: a first conversion circuit connected between a first port and a register circuit, configured to convert first data into second data, the first data having a first phase number and a first indication signal, the second data having a second phase number and a second indication signal, and the first data amount being equal to the second data amount; a register circuit coupled to a second conversion circuit, transmitting the second data based on a preset register configuration, and converting the second indication signal into a third indication signal, the preset register configuration being determined based on a write clock signal of the first conversion circuit and a read clock signal of the second conversion circuit; a second conversion circuit configured to convert the second data into third data and output the third data through a second port, the third data having a third phase number and a fourth indication signal, and the third data amount being equal to the second data amount. The present application has the technical effect of improving the flexibility of cross-clock conversion in data transmission.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of circuit technology, and more particularly to an interface circuit, a conversion method, and an integrated circuit for multi-phase data conversion. Background Art

[0002] With the rapid development of wireless communication technology, including the continued popularization of fifth-generation (5G) communications, millimeter-wave communications, and carrier aggregation, the demand for signal bandwidth and data rates has increased significantly. This, in turn, has driven the rapid evolution of the sampling rate and data bandwidth of high-speed analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chips. Therefore, the issue of data conversion and transmission between different sampling rates deserves attention. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide an interface circuit, a conversion method, and an integrated circuit for multi-phase data conversion, in order to improve the flexibility of cross-clock conversion of data transmission. In a first aspect, an interface circuit for multi-phase data conversion is provided, comprising: a first conversion circuit, a register circuit, and a second conversion circuit; the first conversion circuit is connected between the first port and the register circuit, and is configured to convert first data into second data, wherein the first data has a first phase number and a first indication signal, and the second data has a second phase number and a second indication signal, wherein a first data amount of the first data is determined based on the first phase number, the first indication signal, and a write clock signal of the first conversion circuit, and a second data amount of the second data is determined based on the second phase number, the second indication signal, and the write clock signal, and the first data amount is equal to the second data amount; the register circuit is coupled to the second conversion circuit, and is configured to transmit the second data based on a preset register configuration, and convert the second indication signal into a third indication signal, and the preset register configuration is determined based on the write clock signal of the first conversion circuit and the read clock signal of the second conversion circuit; the second conversion circuit is coupled to the second port, and is configured to convert the second data into third data and output the third data through the second port, wherein the third data has a third phase number and a fourth indication signal, and wherein the third data amount of the third data is equal to the second data amount. Among them, the first indication signal is determined based on the data valid indication of the previous stage circuit of the interface circuit, the second indication signal is determined based on the first phase number, the third phase number and the first indication signal; the third indication signal is determined based on the preset registration configuration; the fourth indication signal is determined based on the third indication signal, the second phase number and the third phase number.

[0004] During the above data conversion process, there is no need to adjust the clock signal frequency of the data input end and the data output end. According to the number of phases required for data output, the first conversion circuit and the second conversion circuit adjust the phase number and the indication signal, and the data is transmitted in combination with the preset configuration parameters of the register circuit, which reduces the requirements for the user clock, ensures that the total amount of data remains unchanged, ensures the integrity of the data, and improves the convenience and flexibility of user interface data transmission.

[0005] Optionally, the data type of the first data includes one or all of in-phase data or orthogonal data, and the first conversion circuit includes: a first conversion module and an interleaving module; the first conversion module is connected between the first port and the interleaving module, and is configured to convert the first data into second data when the first data includes multiple data types; the interleaving module is coupled to the register circuit and is configured to adjust the in-phase data and the orthogonal data to a first data format.

[0006] Optionally, the first conversion circuit also includes: a second conversion module and a first selection module; the second conversion module is connected between the first port and the first selection module, and is configured to convert the first data into second data when the first data is in-phase data; the first selection module is connected between the interleaving module and the register circuit, and is configured to select one or more modules in the first conversion module, the second conversion module or the interleaving module based on a data type selection signal, wherein the data type selection signal is determined based on the data type of the first data.

[0007] Optionally, the second conversion circuit includes: a third conversion module, a deinterleaving module and a second selection module; the third conversion module is connected between the register circuit and the second selection module, and is configured to convert the second data into third data; the deinterleaving module is connected between the third conversion module and the second selection module, and is configured to adjust the first data format to the second data format; the second selection module is coupled to the second port, and is configured to select the deinterleaving module based on the data type selection signal.

[0008] Optionally, the signal frequencies of the read clock signal and the write clock signal are the same or different.

[0009] Optionally, the signal values ​​of the first indication signal, the second indication signal, the third indication signal and the fourth indication signal are less than or equal to 1.

[0010] Optionally, the preset registration configuration includes a valid number of signals and a number of cycles of the read clock signal, and the third indication signal is determined based on a ratio of the valid number of signals to the number of cycles of the read clock signal.

[0011] In a second aspect, a multi-phase data conversion method is provided, which is used for the interface circuit of the multi-phase data conversion provided in the first aspect. The multi-phase data conversion method includes: acquiring first data, the first data including a first phase number and a first indication signal, and the first indication signal is determined based on the application scenario of the previous circuit of the interface circuit; converting the first data into second data, the second data including a second phase number and a second indication signal; transmitting the second data based on a preset register configuration, and converting the second indication signal into a third indication signal based on a write clock signal and a read clock signal; converting the second data into third data, the third data including a third phase number and a fourth indication signal; outputting the third data; wherein the first data amount of the first data, the second data amount of the second data, and the third data amount of the third data are equal.

[0012] Optionally, the first method further includes: obtaining a data type selection signal of the first data; and selecting a first selection module or a second selection module of the interface circuit for multi-phase data conversion based on the data type selection signal.

[0013] In a third aspect, an integrated circuit is provided, comprising: the interface circuit for multi-phase data conversion in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following is a brief introduction to the drawings used in describing the embodiments of the present disclosure:

[0015] Figure 1 A schematic diagram of the connection structure between an ADC / DAC chip and a digital processing chip provided in some embodiments of the present application is shown;

[0016] Figure 2 A schematic diagram of the integrated structure of an ADC / DAC chip and a SoC chip provided in some embodiments of the present application is shown;

[0017] Figure 3 A schematic diagram showing six identical phase component data provided in some embodiments of the present application is shown;

[0018] Figure 4 A schematic diagram of the circuit structure of an interface circuit for multi-phase data conversion provided in some embodiments of the present application is shown;

[0019] Figure 5 A schematic diagram of the circuit structure of another multi-phase data conversion interface circuit provided in some embodiments of the present application is shown;

[0020] Figure 6 A schematic diagram showing the data format of I / Q data after conversion by the first conversion module provided in some embodiments of the present application is shown;

[0021] Figure 7A schematic diagram showing the data format of I / Q data after interleaving by an interleaving module provided in some embodiments of the present application is shown;

[0022] Figure 8 A schematic diagram showing the data format of I / Q data after conversion by the third conversion module provided in some embodiments of the present application is shown;

[0023] Figure 9 A schematic diagram showing the data format of I / Q data after deinterleaving by a deinterleaving module provided in some embodiments of the present application is shown;

[0024] Figure 10 A flow chart of a multi-phase conversion control method provided in some embodiments of the present application is shown. DETAILED DESCRIPTION

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, examples of implementation of the present disclosure will be described below with reference to the accompanying drawings. The drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings and other implementations can be obtained based on these drawings without inventive work. Adjustments and improvements made without departing from the concept of the present disclosure are all within the scope of protection of the present disclosure.

[0026] To simplify the drawings, the figures schematically illustrate only the portions relevant to the embodiments and do not represent the actual structure of the products. Furthermore, to simplify the drawings and facilitate understanding, in some figures, only a portion of components with the same structure or function are schematically depicted; in practice, more or fewer components with the same structure or function may exist.

[0027] In the present disclosure, unless otherwise expressly specified and limited, ordinal numbers such as "first" and "second" are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, for example, "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, for example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3" or "a1, a2 and a3".

[0028] With the rapid development of wireless communication technology, technologies such as the fifth-generation communication technology, millimeter wave communication and carrier aggregation continue to become popular, and the demand for signal bandwidth and data rate has increased significantly, which in turn has promoted the rapid evolution of the sampling rate and data bandwidth of high-speed analog-to-digital converters and digital-to-analog converter chips. Figure 1 Schematic diagram showing the connection structure of an ADC / DAC chip and a digital processing chip provided in some embodiments of the present application. Figure 1 ANA is the analog portion of the ADC / DAC chip, DIG LOGIC is the digital portion of the ADC / DAC chip, AXIS is a high-speed data stream interface, JESD is the transmission protocol, SDS TX / RX are the serial-to-parallel / parallel-to-serial transmit and receive modules, and USER LOGIC is the user digital signal processing logic within the SoC chip. The DIG LOGIC digital portion of the ADC / DAC chip primarily implements key functions in communication systems, such as the digital downconverter (DDC) and digital upconverter (DUC), for signal sampling rate conversion and frequency conversion. This reduces the user data rate, generates I / Q orthogonal signals, and improves subsequent processing efficiency. However, taking a 16-bit analog-to-digital conversion process at a 6GHz sampling rate as an example, the data volume per channel reaches 96Gb. Using 12Gbps transmit and receive modules requires at least eight lanes for transmission, and complex debugging of the JESD protocol or SDS is required. At the same time, the AXIS interface needs to perform operations such as data bit width and clock conversion with the JESD protocol and SDS, and a hardware path is required between the sending and receiving modules to ultimately convert the data received or sent by the user. The overall process is relatively complex.

[0029] On the other hand, with the development of advanced processes such as Chip on Wafer on Substrate (CoWoS) technology with silicon interposer, larger chip scale and more complex heterogeneous integration are easy to achieve. Such designs can greatly simplify interface and connection design. Figure 2 The integrated structure diagram of an ADC / DAC chip and a SoC chip provided in some embodiments of the present application is shown. Figure 2 In the integrated solution shown, the digital interface of the ADC / DAC chip is directly connected to the digital interface of the SoC chip, eliminating the need for protocol and SDS conversion. Therefore, the ADC / DAC chip only needs to implement AXIS interface conversion between it and the SoC. To reduce subsequent logic processing and facilitate user use, the interface conversion logic is generally implemented within the ADC / DAC chip.

[0030] However, the digital logic within high-speed ADC / DAC chips is limited by the digital circuit clock. This is typically achieved by increasing data parallelism and reducing the clock frequency. For example, if the chip processes a single sampling point for 3GSPS analog-to-digital conversion, a 3GHz digital clock is required, which cannot be met with current process technologies. However, if multiple sampling points are arranged sequentially as a data block, for example, including six sampling points, the digital clock requirement can be reduced to 500MHz, a clock frequency that can be achieved in hardware. Figure 3 A schematic diagram illustrating six identical phase component data provided in some embodiments of the present application is shown. Phases I0 through I5 are arranged sequentially from right to left, with each sampling point being referred to as a phase (samples). Therefore, "multi-phase" in this application may refer to data formed by arranging multiple sampled data together. In existing interface designs, for example, a scheme with a selectable number of phases is used to determine the data clock frequency. The data valid indicator signal is always high and cannot be configured by the user. For example, if the parallelism is selectable from 4 to 12, the user must provide a clock between CLK = FS / N (4 to 12). Changing the sampling rate may require changing the user's logical clock frequency. If the number of phases remains unchanged, the receiving logical clock frequency must be changed. If the number of phases is reconfigured, an appropriate logical clock must be set, and the user's received data bit width will change accordingly, requiring modifications to the receiving logic. Using independent I / Q interfaces and a configurable number of phases requires a large number of reserved interfaces, resulting in low interface utilization. There are relatively few configurable phase options, and the data valid signal is not used (always high). The user needs to provide a matching clock frequency based on the sampling rate and phase number, resulting in poor data interface flexibility. This application converts the high-speed data interface inside the ADC / DAC into a high-speed interface for the user, mainly including the phase number and clock domain. The interface circuit can efficiently complete the conversion of the in-phase component (I) or in-phase / quadrature component (I / Q) signal, and combined with the different data valid indications that can be generated by the register configuration parameters, it reduces the requirements for the user clock. Only one set of configurations is required to complete the sampling rate change and cross-clock conversion of the high-speed interface while retaining the user's original logic design to the greatest extent. Improve the convenience and flexibility of data transmission.

[0031] Figure 4The circuit structure diagram of an interface circuit for multi-phase data conversion provided in some embodiments of the present application is shown. The interface circuit 400 for multi-phase data conversion includes: a first conversion circuit 410, a register circuit 420, and a second conversion circuit 430; the first conversion circuit 410 is connected between the first port IN and the register circuit 420, and is configured to convert the first data into the second data, wherein the first data has a first phase number and a first indication signal, and the second data has a second phase number and a second indication signal, wherein the first data amount of the first data is determined based on the first phase number, the first indication signal, and the write clock signal of the first conversion circuit, and the second data amount of the second data is determined based on the second phase number, the second indication signal, and the write clock signal The first data amount is equal to the second data amount; the register circuit 420 is coupled to the second conversion circuit 430 and is configured to transmit the second data based on a preset register configuration and convert the second indication signal into a third indication signal, wherein the preset register configuration is determined based on the write clock signal of the first conversion circuit and the read clock signal of the second conversion circuit; the second conversion circuit 430 is coupled to the second port OUT and is configured to convert the second data into third data and output the third data through the second port, wherein the third data has a third phase number and a fourth indication signal, wherein the third data amount of the third data is equal to the second data amount. The first indication signal is determined based on the data valid indication of the previous stage circuit of the interface circuit, the second indication signal is determined based on the first phase number, the third phase number, and the first indication signal; the third indication signal is determined based on the preset register configuration; and the fourth indication signal is determined based on the third indication signal, the second phase number, and the third phase number.

[0032] In the above multi-phase data conversion interface circuit, the first data can be acquired from multiple sampling points and arranged in sequence. For example, if the data is determined using four sampling points, the first data can have four phases. The specific number of sampling points can be determined based on the hardware design of the interface circuit to reduce the requirements for the digital clock. For example, if eight sampling points are designed, the first data can have a number of phases less than or equal to eight, but this is not specifically limited here. The first conversion circuit 410 can adjust the first phase number of the first data to match the phase number, clock, and other parameters of the desired output data (e.g., the third data). For example, if the first data has four phases and the desired output third data has six phases, the first conversion circuit 410 can first adjust the first phase number of the first data to eight phases. During this process, the first indication signal is converted to a second indication signal. For example, if the valid indication of the first indication signal is 1, the conversion from four phases to eight phases generates a valid indication of half the second indication signal. While the write clock signal remains unchanged, the change in the indication signal ensures that the total amount of data remains unchanged, i.e., the second data amount remains equal to the first data amount. The indicator signal is used to indicate data validity. This indicator signal indicates whether the current data is valid, for example, if the data valid indicator is high. When the indicator signal is always high, it indicates that the data is continuously valid, that is, the data is valid at all clock trigger edges. For example, when the indicator signal is 1 / 2, it indicates that one clock trigger edge is valid (high level) every two clock cycles, and the corresponding data is also valid at this time. Other typical values ​​such as 1 / 3, 1 / 4, and 1 / 8 are also possible. The first indicator signal is determined by the preceding circuit of the interface circuit 400 in the user's usage scenario. For example, if the customer uses a decimation-by-2 processing method after ADC sampling, the data valid indicator is generally 1 / 2, 1 / 8 when decimating by 8, and always high when directly outputting without decimation. During data transmission, the write clock frequency may differ from the read clock frequency. To ensure complete transmission of the input data, the register circuit 420 can match the clock frequencies of the write and read clocks using a preset register configuration to temporarily store the second data. For example, under the action of the write clock signal, the selected 8-phase second data can be written to the register circuit 420, and then, under the action of the read clock signal, the 8-phase data can be read out according to the preset register configuration. The preset register configuration may include a valid number and a cycle number, i.e., a number of reads within a certain number of read clock cycles. For example, if the valid number is x and the cycle number is y, then x reads are performed within y read clock cycles. At this time, the valid indication of the second indicator signal changes to valid number / cycle number, i.e., x / y, forming a third indicator signal and continuing to transmit to the next stage. For example, to achieve complete data transmission, if the signal frequency of the write clock signal is 300 MHz and the valid value of the second indicator signal is 1 / 2, the second data volume can be expressed as 300 × 8 × 1 / 2 = 1200.To ensure a constant data transmission rate, when the read clock signal frequency is 200 MHz, a preset register configuration is used to convert the second indication signal into a third indication signal, with its effective value adjusted to 3 / 4. This ensures that the data transmission rate of 300 × 8 × 1 / 2 = 200 × 8 × 3 / 4 is matched, enabling complete transmission of the second data to the second conversion circuit 430. In the second conversion circuit 430, since it is necessary to output 6-phase third data while maintaining the total data volume, the clock signal in the second conversion circuit 430 remains unchanged, but the number of phases is adjusted from 8 to 6. Accordingly, the third indication signal needs to be adjusted to a fourth indication signal, for example, with its effective value set to a constant high (i.e., 1), meeting the data transmission rate of 200 × 8 × 3 / 4 = 200 × 6 × 1. This achieves the conversion from a 4-phase input to a 6-phase output, while ensuring a constant data volume during the conversion process. The fourth indication signal can be determined based on the third indication signal, the number of phases when the data is output, and the number of intermediate phases in the conversion process, but the effective value needs to be less than or equal to 1. For example, when the third indication signal is 3 / 4, the number of phases when output is 6, and the number of intermediate phases is 8, the effective value of the fourth indication signal is (3 / 4)×(8 / 6)=1. The register circuit of the present application can be a register circuit based on a first-in-first-out (FIFO) structure, which can support independent read and write clocks, automatically generate a read enable signal by configuring the effective number and cycle number, and synchronize the read enable signal with the read data before output (the synchronized read enable signal is the output third indication signal), so that the register circuit supports generating a read enable signal based on any effective number and cycle number. During the above data conversion process, there is no need to adjust the clock signal frequency of the data input and data output terminals. Based on the number of phases required for data output, the first conversion circuit and the second conversion circuit adjust the number of phases and the indication signal, and data transmission is performed in conjunction with preset configuration parameters of the register circuit. This reduces the requirements for the user clock, ensures that the total amount of data remains unchanged, ensures data integrity, and improves the convenience and flexibility of user interface data transmission. The above embodiments can reuse data interfaces. For example, when only an I signal is transmitted, the interface can be configured to output all phases as I. When simultaneously transmitting I / Q signals, the I / Q signals can be configured to each occupy half the transmission bit width, achieving 100% interface utilization. In some embodiments, the above data transmission method is not limited to inputting first data from the first port and outputting third data from the second port. It can also be configured to input first data from the second port and output third data from the first port, achieving bidirectional data transmission. This is not specifically limited here.

[0033] In some embodiments of the present application, the data type of the first data includes one or both of in-phase data and quadrature data. Figure 5A schematic diagram of the circuit structure of another multi-phase data conversion interface circuit provided in some embodiments of the present application is shown. The multi-phase data conversion interface circuit 500 includes a first conversion circuit 510, a register circuit 520, and a second conversion circuit 530. The first conversion circuit 510 includes: a first conversion module and an interleaving module; the first conversion module is connected between the first port and the interleaving module and coupled to a first indication signal, and is configured to convert the first data into second data when the first data includes multiple data types; the interleaving module is coupled to the register circuit and is configured to adjust the in-phase data and the quadrature data to a first data format.

[0034] In the above embodiment, an interleaving module can be provided in the first conversion circuit 510 of the multi-phase data conversion interface circuit 500 to interleave the input data, thereby ensuring data alignment. The interleaving module can make the in-phase data and the orthogonal data I / Q appear in pairs within each clock cycle, ensuring their synchronization in the entire signal processing chain. If not interleaved, when processing the in-phase data I and the orthogonal data Q, they may be processed separately in different clock cycles, resulting in phase misalignment. Interleaving can improve the parallelism of the data stream, so that the data is evenly distributed among multiple phases, which is conducive to subsequent parallel processing. The interleaved I / Q data can be stored and accessed in a fixed pattern, reducing the complexity of out-of-order access.

[0035] In some embodiments, the first conversion circuit also includes: a second conversion module and a first selection module; the second conversion module is connected between the first port and the first selection module and coupled to the first indication signal, and is configured to convert the first data into second data when the first data is in-phase data; the first selection module is connected between the interleaving module and the register circuit, and is configured to select one or more modules of the first conversion module, the second conversion module or the interleaving module based on the data type selection signal, wherein the data type selection signal is determined based on the data type of the first data.

[0036] The data type selection signal can instruct the first selection module to select outputs based on different types of input data, enabling the multi-phase data conversion interface circuit 500 to process either in-phase data I alone or simultaneously with in-phase data I and quadrature data Q. For example, when the data type selection signal indicates that the input signal is in-phase data I, the first selection module can enable the second conversion module to output the converted in-phase second data. Alternatively, when the data type selection signal indicates that the output signal contains both in-phase data I and quadrature data Q, the first selection module can enable the first conversion module and the interleaving module to output the converted second data with both in-phase and quadrature data, thereby increasing the versatility of data transmission applications.

[0037] In some embodiments, the second conversion circuit includes: a third conversion module, a deinterleaving module and a second selection module; the third conversion module is connected between the register circuit and the second selection module, and is configured to convert the second data into third data; the deinterleaving module is connected between the third conversion module and the second selection module, and is configured to adjust the first data format to the second data format; the second selection module is coupled to the second port, and is configured to select the deinterleaving module based on the data type selection signal.

[0038] The interface circuit 500 for multi-phase data conversion is provided with an interleaving module and a deinterleaving module, which can cooperate with each other. For example, when the number of phases of the converted output third data is not a multiple of the number of phases of the input first data, there may be multiple arrangement formats on the output side, making it impossible to correctly decode the I / Q two-way signal. Taking the input of 4 phases and the output of 6 phases as an example, Figure 6 A schematic diagram of the data format of I / Q data after conversion by the first conversion module provided in some embodiments of the present application is shown, where data I0 to data I3 are arranged from right to left, and data Q0 to data Q3 are arranged from right to left starting from data I3. Figure 7 This diagram shows the data format of I / Q data after interleaving by the interleaving module provided in some embodiments of the present application. After interleaving, the data In and Qn are interleaved. After the data is adjusted by the register circuit, the above data format is maintained, so that the in-phase data and the orthogonal data I / Q appear in pairs within each clock cycle, ensuring their synchronization throughout the entire signal processing chain. Figure 8 A schematic diagram of the data format of I / Q data after conversion by the third conversion module provided in some embodiments of the present application is shown. After conversion, 8-phase data is converted into 6-phase data, completing the data phase conversion, and the interleaving state continues to be maintained. Figure 9 A schematic diagram illustrates the data format of I / Q data after deinterleaving by the deinterleaving module provided in some embodiments of the present application. The deinterleaving module restores the order of data I0 to data I2 from right to left, and data Q0 to data Q2 and from data I2 onwards from right to left, completing deinterleaving. The reason for interleaving input and output is that during the conversion process of the multi-phase switching circuit, when the number of phases of the output data is not a multiple of the number of phases of the input data, multiple arrangement formats may be generated on the output side, making it impossible to correctly decode the I / Q signals.

[0039] In some embodiments, the read clock signal and the write clock signal may have the same or different signal frequencies. Depending on the clock requirements of the subsequent circuitry of the interface circuit, the read clock signal and the write clock signal may differ. For example, the operating clock of the ASIC circuit in the previous stage of the interface circuit may be faster (e.g., 300 MHz), while the operating clock of the ASIC circuit when converted to the SoC / FPGA circuit may be slower (e.g., 200 MHz). The solution of the present application can avoid adjusting the clock signal frequency of the subsequent circuitry during the phase conversion process, further avoiding the situation where, when the user changes the sampling rate, the number of phases remains unchanged and the receiving logic clock frequency needs to be changed. Furthermore, if the number of phases is reconfigured, a suitable clock is required, and the user's received data bit width will change, which still requires modifying the receiving logic.

[0040] Figure 10 A flow chart of a multi-phase conversion control method provided in some embodiments of the present application is shown. The method is used to control the interface circuit of the multi-phase data conversion provided in the above embodiments, and the control method includes:

[0041] S1010: Acquire first data, where the first data includes a first phase number and a first indication signal, where the first indication signal is determined based on an application scenario of a previous stage circuit of the interface circuit;

[0042] S1020: Convert the first data into second data, where the second data includes a second phase number and a second indication signal;

[0043] S1030: Transmitting second data based on the preset register configuration, and converting the second indication signal into a third indication signal based on the write clock signal and the read clock signal;

[0044] S1040: Convert the second data into third data, where the third data includes a third phase number and a fourth indication signal;

[0045] S1050: Output third data; wherein the first data amount of the first data, the second data amount of the second data, and the third data amount of the third data are equal.

[0046] Before data conversion is performed by the multi-phase data conversion interface circuit, the data amount Data1 of the first data can be expressed by Formula 1:

[0047]

[0048] Where WR_CLK represents the frequency of the write clock signal, NPH0 represents the number of input phases, and VLD0 represents the effective value of the first indicator signal of the input data. After adjustment by the first conversion circuit, the data volume of the second data Data2 can be expressed by Formula 2:

[0049]

[0050] Wherein, NPH1 represents the phase number after adjustment by the first conversion circuit, and VLD1 represents the effective value of the second indication signal. When writing into the register circuit, the data volume Data2 of the second data can also be expressed by Formula 3:

[0051]

[0052] Wherein, RD_CLK represents the signal frequency of the read clock signal, and VLD2 represents the effective value of the third indication signal. Moreover, after the phase conversion is performed by the second conversion circuit, the third data Data3 can be expressed by Formula 4:

[0053]

[0054] Wherein, NPH2 represents the phase number after adjustment by the second conversion circuit, and VLD3 represents the effective value of the fourth indicator signal. If the data amounts of the above formulas 1 to 4 are all equal, then there is formula 5:

[0055]

[0056] In particular, given the amount of first data Data0 and the number of phases NPH2 of the output third data, the read clock signal frequency RD_CLK and the effective value VLD3 of the fourth indicator signal can be arbitrarily matched, thereby achieving multi-phase data conversion and transmission. Through the above conversion method, without adjusting the user clock signal frequency, the indicator signal is determined based on the changes in the number of input and output phases and the read and write clock signals, and data transmission is performed in conjunction with the preset configuration parameters of the register circuit, reducing the requirements for the user clock and improving the convenience and flexibility of user interface data transmission.

[0057] In some embodiments, the method further includes: obtaining a data type selection signal of the first data; and selecting a first selection module or a second selection module of the interface circuit for multi-phase data conversion based on the data type selection signal.

[0058] According to the data type of the first data, for example, when the first data includes in-phase and quadrature data, the first selection module and the second selection module in the interface circuit for multi-phase data conversion are controlled by the data type selection signal to select the corresponding data transmission branch to complete data transmission.

[0059] Based on the same technical concept, the present application also provides an integrated circuit, including: an interface circuit for multi-phase data conversion provided in the above embodiments.

[0060] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. An interface circuit for multi-phase data conversion, characterized in that: include: a first conversion circuit, a register circuit, and a second conversion circuit; The first conversion circuit is connected between the first port and the register circuit, and is configured to convert first data into second data, wherein the first data has a first phase number and a first indication signal, and the second data has a second phase number and a second indication signal, wherein a first data amount of the first data is determined based on the first phase number, the first indication signal, and a write clock signal of the first conversion circuit, and a second data amount of the second data is determined based on the second phase number, the second indication signal, and the write clock signal, and the first data amount is equal to the second data amount; The register circuit is coupled to the second conversion circuit and is configured to transmit the second data based on a preset register configuration and convert the second indication signal into a third indication signal, wherein the preset register configuration is determined based on a write clock signal of the first conversion circuit and a read clock signal of the second conversion circuit; The second conversion circuit is coupled to the second port and configured to convert the second data into third data and output the third data through the second port, wherein the third data has a third phase number and a fourth indication signal, and wherein a third data amount of the third data is equal to the second data amount; The first indication signal is determined based on the valid indication of the previous stage circuit data of the interface circuit; the second indication signal is determined based on the first phase number, the second phase number, and the first indication signal; the third indication signal is determined based on the preset register configuration; and the fourth indication signal is determined based on the third indication signal, the second phase number, and the third phase number. The data type of the first data includes one or both of in-phase data and quadrature data, and the first conversion circuit includes: a first conversion module and an interleaving module; The first conversion module is connected between the first port and the interleaving module and is configured to convert the first data into the second data when the first data includes multiple data types; The interleaving module is coupled to the register circuit and is configured to adjust the in-phase data and the quadrature data into a first data format.

2. The multi-phase data conversion interface circuit according to claim 1, characterized in that: The first conversion circuit further includes: a second conversion module and a first selection module; The second conversion module is connected between the first port and the first selection module, and is configured to convert the first data into the second data when the first data is in-phase data; The first selection module is connected between the interleaving module and the register circuit, and is configured to select one or more modules among the first conversion module, the second conversion module or the interleaving module based on a data type selection signal, wherein the data type selection signal is determined based on the data type of the first data.

3. The multi-phase data conversion interface circuit according to claim 2, characterized in that: The second conversion circuit includes: a third conversion module, a deinterleaving module and a second selection module; The third conversion module is connected between the register circuit and the second selection module and is configured to convert the second data into the third data; The deinterleaving module is connected between the third conversion module and the second selection module, and is configured to adjust the first data format to a second data format; The second selection module, coupled to the second port, is configured to select the deinterleaving module based on the data type selection signal.

4. The multi-phase data conversion interface circuit according to any one of claims 1 to 3, characterized in that: The read clock signal and the write clock signal have the same or different signal frequencies.

5. The multi-phase data conversion interface circuit according to any one of claims 1 to 3, characterized in that: The signal values ​​of the first indication signal, the second indication signal, the third indication signal, and the fourth indication signal are less than or equal to 1.

6. The multi-phase data conversion interface circuit according to any one of claims 1 to 3, characterized in that: The preset registration configuration includes a signal validity number and a read clock signal cycle number, and the third indication signal is determined based on a ratio of the signal validity number to the read clock signal cycle number.

7. A multi-phase data conversion method, characterized in that: An interface circuit for multi-phase data conversion according to any one of claims 1 to 6, wherein the multi-phase data conversion method comprises: Acquire first data, where the first data includes a first phase number and a first indication signal, where the first indication signal is determined based on an application scenario of a preceding circuit of the interface circuit; converting the first data into second data, wherein the second data includes a second phase number and a second indication signal; transmitting the second data based on a preset register configuration, and converting the second indication signal into a third indication signal based on a write clock signal and a read clock signal; converting the second data into third data, wherein the third data includes a third phase number and a fourth indication signal; outputting the third data; The first data volume of the first data, the second data volume of the second data, and the third data volume of the third data are equal.

8. The multi-phase data conversion method according to claim 7, wherein: Also includes: obtaining a data type selection signal for the first data; The first selection module or the second selection module of the multi-phase data conversion interface circuit is selected based on the data type selection signal.

9. An integrated circuit, characterized in that: include: The interface circuit for multi-phase data conversion according to any one of claims 1 to 6.

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