Memory and manufacturing method thereof
By depositing a first dielectric layer with a high dielectric constant in the semiconductor memory and performing thinning treatment, combined with the second dielectric layer with a low dielectric constant, the short circuit problem caused by the dielectric layer pores is solved, and the RC delay effect and leakage problems are improved, thereby improving memory performance.
Patent Information
- Application Number
- CN202510159545.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-05-30
AI Technical Summary
In semiconductor process nodes below 40 nanometers, the traditional nonvolatile memory manufacturing process causes short circuit problems between adjacent memory structures due to the existence of pores in the dielectric layer, and the RC delay effect and leakage problems are more prominent, affecting memory performance.
After deposition of the first dielectric layer with a high dielectric constant, a planarization process is performed and a pressure is applied to thin the first dielectric layer, reduce its thickness and increase density, thereby reducing the occurrence of pores. Subsequently, a second dielectric layer with a lower dielectric constant is deposited to cover the surface of the first dielectric layer, reducing the RC delay effect and leakage problems of the memory.
It effectively reduces pores in the dielectric layer, avoids short circuit problems between adjacent memory structures, and improves the RC delay effect and leakage problems of the memory, thereby improving the overall performance of the memory.
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Figure CN120076338A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a memory and a manufacturing method thereof. Background Art
[0002] Traditional embedded non-volatile memory technology has reached its physical limit at the 40-nanometer semiconductor process node. And in the process nodes below 40 nanometers, the HKMG (High-K Metal Gate) technology cannot be applied to the manufacturing process of traditional non-volatile memories. Instead, the HKMG process needs to be carried out separately after the manufacturing process of the storage unit is completed, and the process is quite complex, resulting in a substantial increase in the manufacturing cost of the memory.
[0003] The new back-end capacitor process technology breaks the limitation that the embedded non-volatile memory is not applicable to the process nodes below 40 nanometers due to problems such as the device size of the traditional front-end process. The resistive random access memory (RRAM), as a relatively leading technology in the new type of embedded non-volatile memory, realizes the storage and erasure of data by changing the resistivity of the solid dielectric. For example, when the resistive random access memory stores data, the solid dielectric enters the low-resistance state under the action of an externally applied electric field; when the resistive random access memory erases data, the solid dielectric enters the high-resistance state by applying a reverse voltage. Since the resistive random access memory belongs to the back-end capacitor process, the trench filling ability of the low-dielectric-constant dielectric material is poor, resulting in pores in the filled dielectric layer. Subsequently, when etching the dielectric layer to form a lead-out structure electrically connected to the storage structure, the existence of the pores will not only affect the etching of the lead-out holes, but may also cause bridging between adjacent storage structures, ultimately leading to a short circuit between adjacent storage structures. However, although the trench filling ability of the high-dielectric-constant dielectric material is higher than that of the low-dielectric-constant dielectric material, it will still cause the appearance of pores in the filled dielectric layer, and will also cause an increase in the RC delay effect and an increase in leakage.
[0004] Therefore, how to reduce the pores in the dielectric layer, avoid the short-circuit problem between adjacent storage structures, and at the same time improve the RC delay effect and leakage problem of the memory, so as to improve the performance of the memory, is a technical problem that needs to be solved urgently at present. Summary of the Invention
[0005] The present invention provides a memory and a forming method thereof, which are used to reduce the pores in the dielectric layer, avoid the short-circuit problem between adjacent storage structures, and at the same time improve the RC delay effect and leakage problem of the memory, so as to improve the performance of the memory.
[0006] According to some embodiments, the present invention provides a method for manufacturing a memory, including the following steps:
[0007] Form a plurality of memory structures on the top surface of a substrate, the substrate including a top surface and a bottom surface that are oppositely distributed along a first direction, and the plurality of memory structures are arranged at intervals along a second direction, the second direction being perpendicular to and intersecting the first direction;
[0008] Deposit a first dielectric material on the top surface of the substrate to form a first dielectric layer that continuously covers the top surface of the substrate and the plurality of memory structures;
[0009] Perform a planarization process on the first dielectric layer and apply pressure to the first dielectric layer to reduce the thickness of the first dielectric layer;
[0010] Form a second dielectric layer on the surface of the first dielectric layer after the thickness reduction, and the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer.
[0011] In some embodiments, before forming a plurality of memory structures on the top surface of a substrate, the following steps are further included:
[0012] Form a bottom interconnect layer;
[0013] Form a first isolation layer covering the top surface of the bottom interconnect layer and a second isolation layer covering the surface of the first isolation layer facing away from the bottom interconnect layer;
[0014] Form a plurality of bottom contact structures that penetrate the first isolation layer and the second isolation layer along the first direction and are electrically connected to the bottom interconnect layer, and the plurality of bottom contact structures are arranged at intervals along the second direction to form the substrate including the bottom interconnect layer, the first isolation layer, the second isolation layer, and the bottom contact structures.
[0015] In some embodiments, the specific steps of forming a plurality of memory structures on the top surface of a substrate include:
[0016] Form a stack layer on the top surface of the substrate, the stack layer including a lower electrode material layer covering the top surface of the substrate, a variable resistance material layer covering the surface of the lower electrode material layer, and an upper electrode material layer covering the surface of the variable resistance material layer;
[0017] Form a plurality of isolation grooves that penetrate the stack layer along the first direction, and the plurality of isolation grooves divide the stack layer into a plurality of the memory structures that are electrically connected to the plurality of bottom contact structures one by one. Each memory structure includes a lower electrode layer, a variable resistance layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the variable resistance layer.
[0018] In some embodiments, before depositing a first dielectric material on the top surface of the substrate to form a first dielectric layer that continuously covers the top surface of the substrate and a plurality of the storage structures, the following steps are further included:
[0019] Form a protective layer that continuously covers the top surface of the substrate, as well as the sidewalls and top surface of the storage structures.
[0020] In some embodiments, the specific steps of depositing a first dielectric material on the top surface of the substrate to form a first dielectric layer that continuously covers the top surface of the substrate and a plurality of the storage structures include:
[0021] Deposit TEOS material on the substrate by chemical vapor deposition to form the first dielectric layer that continuously covers the top surface of the substrate, a plurality of the storage structures, and fills the isolation grooves.
[0022] In some embodiments, the specific steps of planarizing the first dielectric layer and applying pressure to the first dielectric layer to reduce the thickness of the first dielectric layer include:
[0023] Thin the first dielectric layer by chemical mechanical polishing.
[0024] In some embodiments, the specific steps of thinning the first dielectric layer by chemical mechanical polishing include:
[0025] Adjust either or both of the polishing time and polishing pressure of the chemical mechanical polishing process to thin the first dielectric layer to a preset thickness.
[0026] In some embodiments, the specific steps of thinning the first dielectric layer by chemical mechanical polishing include:
[0027] Adjust either or both of the polishing time and polishing pressure of the chemical mechanical polishing process to thin the first dielectric layer to be flush with the protective layer on the top surface of the storage structure.
[0028] In some embodiments, the specific steps of forming a second dielectric layer on the surface of the first dielectric layer with reduced thickness include:
[0029] Deposit BDⅡ material on the thinned first dielectric layer to form the second dielectric layer.
[0030] In some embodiments, after forming a second dielectric layer on the surface of the first dielectric layer with reduced thickness, the following steps are further included:
[0031] Form a lead-out structure that penetrates the second dielectric layer and the first dielectric layer along the first direction and is electrically connected to the storage structure.
[0032] According to some other embodiments, the present invention further provides a memory formed by using the manufacturing method of the memory as described above; the memory includes:
[0033] A substrate, the substrate includes a top surface and a bottom surface that are oppositely distributed along a first direction;
[0034] A plurality of memory structures, located on the top surface of the substrate, and the plurality of memory structures are arranged at intervals along a second direction, and the second direction is perpendicular to and intersects the first direction;
[0035] A first dielectric layer, at least covering the top surface of the substrate and the side surfaces of the plurality of memory structures, and the first dielectric layer fills the isolation grooves between adjacent memory structures;
[0036] A second dielectric layer, covering the surface of the first dielectric layer, and the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer.
[0037] In some embodiments, the material of the first dielectric layer is TEOS material, and the material of the second dielectric layer is BDⅡ material.
[0038] In some embodiments, the substrate includes a bottom interconnection layer, a first isolation layer covering the top surface of the bottom interconnection layer, a second isolation layer covering the surface of the first isolation layer facing away from the bottom interconnection layer, and a plurality of bottom contact structures that penetrate the first isolation layer and the second isolation layer along the first direction and are electrically connected to the bottom interconnection layer, and the plurality of bottom contact structures are arranged at intervals along the second direction, and the plurality of bottom contact structures are electrically connected to the plurality of memory structures in one-to-one correspondence;
[0039] The memory structure includes a lower electrode layer electrically connected to the bottom contact structure, a variable resistance layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the variable resistance layer.
[0040] In some embodiments, it further includes:
[0041] A protective layer, continuously covering the top surface of the substrate and the side walls and the top surface of the memory structure, and the first dielectric layer is flush with the protective layer on the top surface of the memory structure.
[0042] The memory and its manufacturing method provided by the present invention, after depositing a first dielectric layer with a relatively high dielectric constant (higher than that of the second dielectric layer) and relatively good filling ability, planarize the first dielectric layer and apply pressure to the first dielectric layer to thin the first dielectric layer, so as to improve the density of the thinned first dielectric layer, thereby reducing or even avoiding the generation of pores in the first dielectric layer, and further avoiding the problem of bridging short circuit between adjacent storage structures. By depositing a second dielectric layer with a relatively low dielectric constant (lower than that of the first dielectric layer) on the first dielectric layer, the RC delay effect of the memory can be reduced, and the leakage problem in the memory can be reduced, realizing further improvement of the performance of the memory. Description of the Drawings
[0043] Figure 1 is a flowchart of the manufacturing method of the memory in the specific embodiment of the present invention;
[0044] Figure 2 is a schematic structural diagram of the specific embodiment of the present invention after forming the first isolation layer and the second isolation layer;
[0045] Figure 3 is a schematic structural diagram of the specific embodiment of the present invention after forming the bottom contact hole;
[0046] Figure 4 is a schematic structural diagram of the specific embodiment of the present invention after forming the bottom contact structure;
[0047] Figure 5 is a schematic structural diagram of the specific embodiment of the present invention after forming the stacked layer;
[0048] Figure 6 is a schematic structural diagram of the specific embodiment of the present invention after forming the storage structure;
[0049] Figure 7 is a schematic structural diagram of the specific embodiment of the present invention after forming the protective layer;
[0050] Figure 8 is a schematic structural diagram of the specific embodiment of the present invention after thinning the protective layer;
[0051] Figure 9 is a schematic structural diagram of the specific embodiment of the present invention after depositing the first dielectric layer;
[0052] Figure 10 is a schematic structural diagram of the specific embodiment of the present invention after thinning the first dielectric layer;
[0053] Figure 11It is a schematic structural diagram of the specific embodiment of the present invention after forming the second dielectric layer;
[0054] Figure 12 It is a schematic structural diagram of the specific embodiment of the present invention after forming the top contact hole;
[0055] Figure 13 It is a schematic structural diagram of the specific embodiment of the present invention after forming the top contact structure and the top interconnect layer.
[0056] Description of Reference Numerals
[0057] 20 Bottom Interconnect Layer
[0058] 21 First Isolation Layer
[0059] 22 Second Isolation Layer
[0060] 30 Bottom Contact Hole
[0061] 40 Bottom Contact Structure
[0062] 50 Lower Electrode Material Layer
[0063] 51 Variable Resistance Material Layer
[0064] 52 Upper Electrode Material Layer
[0065] 501 Lower Electrode Layer
[0066] 511 Variable Resistance Layer
[0067] 521 Upper Electrode Layer
[0068] 60 Isolation Groove
[0069] 70 Protective Layer
[0070] 90 First Dielectric Layer
[0071] 91 Pore
[0072] 110 Second Dielectric Layer
[0073] 120 Top Contact Hole
[0074] 130 Top Contact Structure
[0075] 131 Top Interconnect Layer Specific Embodiment
[0076] The following will describe in detail the specific embodiments of the memory and its manufacturing method provided by the present invention with reference to the accompanying drawings.
[0077] This specific embodiment provides a manufacturing method of a memory, Figure 1It is a flowchart of a method for manufacturing a memory in a specific embodiment of the present invention. As Figure 1 shown, the method for manufacturing the memory includes the following steps:
[0078] Step S11, forming a plurality of memory structures on the top surface of a substrate, the substrate including a top surface and a bottom surface that are oppositely distributed along a first direction, and the plurality of memory structures are arranged at intervals along a second direction, the second direction being perpendicular to and intersecting the first direction;
[0079] Step S12, depositing a first dielectric material on the top surface of the substrate to form a first dielectric layer that continuously covers the top surface of the substrate and the plurality of memory structures;
[0080] Step S13, performing a planarization process on the first dielectric layer and applying pressure to the first dielectric layer to reduce the thickness of the first dielectric layer;
[0081] Step S14, forming a second dielectric layer on the surface of the first dielectric layer after reducing the thickness, and the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer.
[0082] Figure 2 It is a schematic structural diagram of a specific embodiment of the present invention after forming a first isolation layer and a second isolation layer. Figure 3 It is a schematic structural diagram of a specific embodiment of the present invention after forming a bottom contact hole. Figure 4 It is a schematic structural diagram of a specific embodiment of the present invention after forming a bottom contact structure. In some embodiments, as Figures 2 - 4 shown, before forming a plurality of memory structures on the top surface of a substrate, the following steps are further included:
[0083] Forming a bottom interconnect layer 20;
[0084] Forming a first isolation layer 21 covering the top surface of the bottom interconnect layer 20 and a second isolation layer 22 covering the surface of the first isolation layer 21 facing away from the bottom interconnect layer 20;
[0085] Forming a plurality of bottom contact structures 40 that penetrate the first isolation layer 21 and the second isolation layer 22 along the first direction D1 and are electrically connected to the bottom interconnect layer 20, and the plurality of bottom contact structures 40 are arranged at intervals along the second direction D2 to form the substrate including the bottom interconnect layer 20, the first isolation layer 21, the second isolation layer 22, and the bottom contact structures 40.
[0086] For example, the substrate includes a base substrate, and a conductive material such as metallic copper is deposited on the top surface of the base substrate to form the bottom interconnect layer 20. Then, a material such as carbon-doped silicon nitride is deposited on the surface of the bottom interconnect layer 20 facing away from the base substrate to form the first isolation layer 21 serving as an etch stop layer. A TEOS (Tetraethyl orthosilicate) material is deposited on the surface of the first isolation layer 21 facing away from the bottom interconnect layer 20 to form the second isolation layer 22, as shown in Figure 2 . After forming the second isolation layer 22, the surface of the second isolation layer 22 facing away from the first isolation layer 21 is used as the top surface of the substrate. An etching process is employed to etch the second isolation layer 22 and the first isolation layer 21 in sequence from the top surface of the substrate along the first direction D1, forming bottom contact holes 30 that continuously penetrate through the second isolation layer 22 and the first isolation layer 21 along the first direction D1 and expose the bottom interconnect layer 20. A plurality of the bottom contact holes 30 are arranged at least at intervals along the second direction D2, as shown in Figure 3 . Then, a material such as TiN can be deposited on the substrate by physical vapor deposition to form a conductive material that fills a plurality of the bottom contact holes 30 and covers the top surface of the substrate. After removing the conductive material layer on the top surface of the substrate by processes such as chemical mechanical polishing, the remaining conductive material in the bottom contact holes 30 is used as the bottom contact structure 40, as shown in Figure 4 . The bottom contact structure 40 is in electrical contact connection with the bottom interconnect layer 20.
[0087] Figure 5 FIG. 10 is a schematic structural diagram of a specific embodiment of the present invention after forming a stacked layer, and FIG. 6 is a schematic structural diagram of a specific embodiment of the present invention after forming a storage structure. In some embodiments, the specific steps of forming a plurality of storage structures on the top surface of a substrate include:
[0088] Forming a stacked layer on the top surface of the substrate, the stacked layer including a lower electrode material layer 50 covering the top surface of the substrate, a variable resistance material layer 51 covering the surface of the lower electrode material layer 50, and an upper electrode material layer 52 covering the surface of the variable resistance material layer 51, as shown in Figure 5 ;
[0089] Forming a plurality of isolation grooves 60 penetrating through the stacked layer along the first direction D1. The plurality of isolation grooves 60 divide the stacked layer into a plurality of the storage structures that are in one-to-one corresponding electrical connection with the plurality of the bottom contact structures 40. Each storage structure includes a lower electrode layer 501, a variable resistance layer 511 covering the surface of the lower electrode layer 501, and an upper electrode layer 521 covering the surface of the variable resistance layer 511.
[0090] Specifically, any one or a combination of two or more of metal materials such as Al, Ti, and W is deposited on the top surface of the substrate to form the lower electrode material layer 50. A metal oxide material containing any one or a combination of two or more of Hf, Fe, and Mg and having a resistive switching characteristic is deposited on the surface of the lower electrode material layer 50 facing away from the substrate to form the variable resistance material layer 51. Any one or a combination of two or more of metal materials such as Al, Ti, and W is deposited on the surface of the variable resistance material layer 51 facing away from the lower electrode material layer 50 to form the upper electrode material layer. The lower electrode material layer 50, the variable resistance material layer 51, and the upper electrode material layer 52 together constitute the stacked layer of the MIM (metal-insulator-metal) structure. The stacked layer is etched along the first direction D1 by a dry etching process to form a plurality of isolation grooves 60 that penetrate the stacked layer along the first direction D1 and expose the top surface of the substrate. The plurality of isolation grooves 60 divide the lower electrode material layer 50 into a plurality of lower electrode layers 501 arranged at intervals along the second direction D2, divide the variable resistance material layer 51 into a plurality of variable resistance layers 511 arranged at intervals along the second direction D2, and divide the upper electrode material layer 52 into a plurality of upper electrode layers 521 arranged at intervals along the second direction D2. As Figure 6 shown, each lower electrode layer 501, the variable resistance layer 511 covering the surface of the lower electrode layer 501, and the upper electrode layer 521 covering the surface of the variable resistance layer 511 together constitute one storage structure, and the plurality of storage structures are arranged in parallel on the top surface of the substrate to form a storage array.
[0091] Figure 7 is a schematic structural diagram of a specific embodiment of the present invention after forming a protective layer, Figure 8 is a schematic structural diagram of a specific embodiment of the present invention after thinning the protective layer. In some embodiments, before depositing a first dielectric material on the top surface of the substrate to form a first dielectric layer continuously covering the top surface of the substrate and the plurality of storage structures, the following steps are further included:
[0092] A protective layer 70 is formed that continuously covers the top surface of the substrate, the side walls, and the top surface of the storage structure.
[0093] For example, after forming the storage array, an insulating material such as carbon-doped silicon nitride is deposited on the substrate to form a protective layer 70 that continuously covers the top surface of the substrate, the side walls, and the top surface of the storage structure, as Figure 7As shown, it is used to protect the storage structure and prevent subsequent processes from damaging the storage structure. In one example, after depositing the protective layer 70, the protective layer 70 can also be thinned by an etching process to reduce the thickness of the protective layer 70, such as Figure 8 shown, so as to facilitate the subsequent filling of the first dielectric layer in the isolation groove 60 and reduce the generation of air gaps in the first dielectric layer due to the excessive thickness of the protective layer 70.
[0094] Figure 9 is a schematic structural diagram of the specific embodiment of the present invention after depositing the first dielectric layer. In some embodiments, such as Figure 9 shown, the specific steps of depositing the first dielectric material on the top surface of the substrate to form the first dielectric layer 90 that continuously covers the top surface of the substrate and multiple storage structures include:
[0095] Deposit TEOS material on the substrate by chemical vapor deposition to form the first dielectric layer 90 that continuously covers the top surface of the substrate and multiple storage structures and fills the isolation groove 60.
[0096] In this specific embodiment, the first dielectric layer 90 filling the isolation groove 60 is formed by depositing TEOS material by chemical vapor deposition. On the one hand, compared with other low dielectric constant materials, TEOS material has relatively good step coverage and can reduce the pores 91 in the formed first dielectric layer 90 after deposition; on the other hand, other materials with high step coverage have a higher temperature during the deposition process and a stronger plasma bombardment, while using TEOS material can reduce the process temperature and the plasma bombardment, thereby avoiding damaging the storage structure during the process of filling the isolation groove 60.
[0097] Figure 10 is a schematic structural diagram of the specific embodiment of the present invention after thinning the first dielectric layer. In some embodiments, the specific steps of planarizing the first dielectric layer 90 and applying pressure to the first dielectric layer 90 to reduce the thickness of the first dielectric layer 90 include:
[0098] Thin the first dielectric layer 90 by chemical mechanical polishing to obtain the structure as Figure 10 shown.
[0099] In this specific embodiment, by adopting a chemical mechanical polishing process, it is possible to flatten and thin the first dielectric layer 90. Through the polishing head used in the chemical mechanical polishing process, pressure is applied to the first dielectric layer 90, making the first dielectric layer 90 densify to reduce or even completely eliminate the pores 91 within the first dielectric layer 90. This specific embodiment uses the chemical mechanical polishing process to simultaneously achieve the effects of thinning and applying pressure, without the need for a separate pressure application operation, thereby helping to simplify the manufacturing process of the memory and improve the manufacturing efficiency of the memory.
[0100] In some embodiments, the specific steps of thinning the first dielectric layer 90 using a chemical mechanical polishing process include:
[0101] Adjust either one or a combination of the polishing time and polishing pressure of the chemical mechanical polishing process to thin the first dielectric layer 90 to a preset thickness.
[0102] Specifically, adjusting either one or a combination of the polishing time and polishing pressure of the chemical mechanical polishing process can not only adjust the thickness of the remaining first dielectric layer 90 after thinning, but also adjust the magnitude of the total pressure applied to the first dielectric layer 90, thereby realizing the adjustment of the density of the thinned first dielectric layer 90 to further reduce the pores 91 within the thinned first dielectric layer 90.
[0103] In some embodiments, the specific steps of thinning the first dielectric layer 90 using a chemical mechanical polishing process include:
[0104] Adjust either one or a combination of the polishing time and polishing pressure of the chemical mechanical polishing process to thin the first dielectric layer 90 to be flush with the protective layer 70 on the top surface of the storage structure.
[0105] Specifically, by adjusting either one or a combination of the polishing time and polishing pressure of the chemical mechanical polishing process, the top surface of the thinned first dielectric layer 90 (i.e., the surface of the first dielectric layer 90 facing away from the substrate) is made flush with the protective layer 70 covering the top surface of the storage structure, so as to be able to thin the first dielectric layer 90 to the greatest extent and achieve the greatest densification of the first dielectric layer 90, to minimize the pores within the thinned first dielectric layer 90.
[0106] Figure 11 It is a schematic structural diagram of the specific embodiment of the present invention after forming the second dielectric layer. In some embodiments, as Figure 11 shown, the specific steps of forming the second dielectric layer 110 to the surface of the first dielectric layer 90 after reducing the thickness include:
[0107] Deposit the BDⅡ (Black Diamond II) material on the thinned first dielectric layer 90 to form the second dielectric layer 110.
[0108] Specifically, the dielectric constant of the BDⅡ material is lower than that of the TEOS material. Depositing the second dielectric layer 110 composed of the BDⅡ material on the first dielectric layer 90 can reduce the dielectric constant of the overall stacked dielectric layer composed of the first dielectric layer 90 and the second dielectric layer 110, thereby reducing the RC delay effect of the memory and reducing the leakage current of the memory, improving the overall operation speed and reliability of the memory. Moreover, depositing the second dielectric layer 110 composed of the BDⅡ material on the first dielectric layer 90 can also improve the flatness of the overall stacked dielectric layer, increase the process window for forming the lead-out structure subsequently, and reduce the difficulty of the memory manufacturing process.
[0109] Figure 12 It is a schematic structural diagram of the specific embodiment of the present invention after forming the top contact hole. Figure 13 It is a schematic structural diagram of the specific embodiment of the present invention after forming the top contact structure and the top interconnect layer. In some embodiments, as Figure 12 and Figure 13 shown, after forming the second dielectric layer 110 to the surface of the thinned first dielectric layer 90, the following steps are further included:
[0110] Form a lead-out structure that penetrates the second dielectric layer 110 and the first dielectric layer 90 along the first direction D1 and is electrically connected to the storage structure.
[0111] For example, after forming the second dielectric layer 110, etch the second dielectric layer 110, the first dielectric layer 90, and the protective layer 70 to form a top contact hole 120 that continuously penetrates the second dielectric layer 110, the first dielectric layer 90, and the protective layer 70 along the first direction D1 and exposes the top of the upper electrode layer 521 in the storage structure, as Figure 12 shown. Then, deposit a conductive material such as copper metal on the substrate to form a top contact structure 130 that fills the top contact hole 120 and a top interconnect layer 131 that covers the second dielectric layer 110, as Figure 13 shown, and the top contact structure 130 and the top interconnect layer 131 together form the lead-out structure.
[0112] This specific embodiment also provides a memory formed by using the manufacturing method of the memory as described above. See Figures 1 - 13The structure of the memory can be referred to Figure 13 . As Figures 1 - 13 shown, the memory includes:
[0113] a substrate, the substrate including a top surface and a bottom surface that are oppositely distributed along a first direction D1;
[0114] a plurality of memory structures, located on the top surface of the substrate, and the plurality of memory structures are arranged at intervals along a second direction D2, the second direction D2 being perpendicular to and intersecting the first direction D1;
[0115] a first dielectric layer 90, covering at least the top surface of the substrate and the side surfaces of the plurality of memory structures, and the first dielectric layer 90 fills the isolation grooves 60 between adjacent memory structures;
[0116] a second dielectric layer 110, covering the surface of the first dielectric layer 90, and the dielectric constant of the second dielectric layer 110 is less than the dielectric constant of the first dielectric layer 90.
[0117] In some embodiments, the material of the first dielectric layer 90 is TEOS material, and the material of the second dielectric layer 110 is BDⅡ material.
[0118] In some embodiments, the substrate includes a bottom interconnection layer 20, a first isolation layer 21 covering the top surface of the bottom interconnection layer 20, a second isolation layer 22 covering the surface of the first isolation layer 21 facing away from the bottom interconnection layer 20, and a plurality of bottom contact structures 40 that penetrate the first isolation layer 21 and the second isolation layer 22 along the first direction D1 and are electrically connected to the bottom interconnection layer 20, and the plurality of bottom contact structures 40 are arranged at intervals along the second direction D2, and the plurality of bottom contact structures 40 are electrically connected to the plurality of memory structures in one-to-one correspondence;
[0119] The memory structure includes a lower electrode layer 501 electrically connected to the bottom contact structure 40, a variable resistance layer 511 covering the surface of the lower electrode layer 501, and an upper electrode layer 521 covering the surface of the variable resistance layer 511.
[0120] In some embodiments, the memory further includes:
[0121] a protective layer 70, continuously covering the top surface of the substrate and the side walls and top surfaces of the memory structures, and the first dielectric layer 90 is flush with the protective layer 70 on the top surface of the memory structures.
[0122] The memory and its manufacturing method provided by this specific embodiment, after depositing a first dielectric layer with a relatively high dielectric constant (higher than that of the second dielectric layer) and relatively good filling ability, planarize the first dielectric layer and apply pressure to the first dielectric layer to thin the first dielectric layer, so as to improve the density of the thinned first dielectric layer, thereby reducing or even avoiding the generation of pores in the first dielectric layer, and further avoiding the problem of bridging short circuits between adjacent storage structures. By depositing a second dielectric layer with a relatively low dielectric constant (lower than that of the first dielectric layer) on the first dielectric layer, the RC delay effect of the memory can be reduced, and the leakage problem in the memory can be reduced, realizing further improvement of the performance of the memory.
[0123] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.
Claims
1. A method for manufacturing a memory, characterized in that: The steps include: Forming a plurality of storage structures on a top surface of a substrate, the substrate comprising a top surface and a bottom surface relatively distributed along a first direction, the plurality of storage structures being arranged at intervals along a second direction, the second direction being perpendicular to the first direction; Depositing a first dielectric material on the top surface of the substrate to form a first dielectric layer continuously covering the top surface of the substrate and the plurality of storage structures; planarizing the first dielectric layer and applying pressure to the first dielectric layer to reduce the thickness of the first dielectric layer; A second dielectric layer is formed on the surface of the first dielectric layer after the thickness is reduced, and the dielectric constant of the second dielectric layer is smaller than the dielectric constant of the first dielectric layer.
2. The method for manufacturing a memory according to claim 1, characterized in that: Before forming a plurality of storage structures on the top surface of a substrate, the method further includes the following steps: forming a bottom interconnect layer; forming a first isolation layer covering the top surface of the bottom interconnect layer and a second isolation layer covering the surface of the first isolation layer facing away from the bottom interconnect layer; A plurality of bottom contact structures are formed along the first direction, penetrating the first isolation layer and the second isolation layer and electrically connected to the bottom interconnect layer, and the plurality of bottom contact structures are arranged at intervals along the second direction to form the substrate including the bottom interconnect layer, the first isolation layer, the second isolation layer and the bottom contact structures.
3. The method for manufacturing a memory according to claim 2, characterized in that: The specific steps of forming a plurality of storage structures on the top surface of a substrate include: forming a stacked layer on the top surface of the substrate, the stacked layer comprising a lower electrode material layer covering the top surface of the substrate, a variable resistance material layer covering the surface of the lower electrode material layer, and an upper electrode material layer covering the surface of the variable resistance material layer; A plurality of isolation grooves are formed along the first direction through the stacked layer, and the plurality of isolation grooves separate the stacked layer into a plurality of storage structures electrically connected to the plurality of bottom contact structures one by one, and each of the storage structures includes a lower electrode layer, a variable resistance layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the variable resistance layer.
4. The method for manufacturing a memory according to claim 3, characterized in that: Before depositing a first dielectric material on the top surface of the substrate to form a first dielectric layer continuously covering the top surface of the substrate and the plurality of storage structures, the method further includes the following steps: A protection layer is formed to continuously cover the top surface of the substrate and the sidewalls and top surface of the storage structure.
5. The method for manufacturing a memory according to claim 4, characterized in that: The specific steps of depositing a first dielectric material on the top surface of the substrate to form a first dielectric layer continuously covering the top surface of the substrate and the plurality of storage structures include: A TEOS material is deposited on the substrate using a chemical vapor deposition process to form the first dielectric layer which continuously covers the top surface of the substrate and the plurality of storage structures and fills the isolation grooves.
6. The method for manufacturing a memory according to claim 4, characterized in that: The specific steps of planarizing the first dielectric layer and applying pressure to the first dielectric layer to reduce the thickness of the first dielectric layer include: The first dielectric layer is thinned by a chemical mechanical polishing process.
7. The method for manufacturing a memory according to claim 6, characterized in that: The specific steps of thinning the first dielectric layer by using a chemical mechanical polishing process include: The first dielectric layer is thinned to a preset thickness by adjusting either or both of the polishing time and the polishing pressure of the chemical mechanical polishing process.
8. The method for manufacturing a memory according to claim 6, wherein: The specific steps of thinning the first dielectric layer by using a chemical mechanical polishing process include: The polishing time and the polishing pressure of the chemical mechanical polishing process are adjusted, or a combination of the two, to thin the first dielectric layer to be flush with the protective layer on the top surface of the storage structure.
9. The method for manufacturing a memory according to claim 1, wherein: The specific steps of forming the second dielectric layer on the surface of the first dielectric layer after the thickness is reduced include: Depositing BDⅡ material on the thinned first dielectric layer to form the second dielectric layer.
10. The method for manufacturing a memory according to claim 1, wherein: After forming a second dielectric layer on the surface of the first dielectric layer with reduced thickness, the following steps are also included: A lead-out structure is formed along the first direction, penetrating the second dielectric layer and the first dielectric layer and electrically connected to the storage structure.
11. A memory, characterized in that: The memory is formed by the manufacturing method of the memory as claimed in claim 1; the memory comprises: A substrate, the substrate comprising a top surface and a bottom surface that are relatively distributed along a first direction; A plurality of storage structures are located on the top surface of the substrate, and the plurality of storage structures are arranged at intervals along a second direction, and the second direction intersects the first direction perpendicularly; A first dielectric layer at least covers the top surface of the substrate and the side surfaces of the plurality of storage structures, and the first dielectric layer completely fills the isolation grooves between adjacent storage structures; The second dielectric layer covers the surface of the first dielectric layer, and the dielectric constant of the second dielectric layer is smaller than the dielectric constant of the first dielectric layer.
12. The memory according to claim 11, characterized in that: The material of the first dielectric layer is TEOS material, and the material of the second dielectric layer is BDⅡ material.
13. The memory according to claim 11, characterized in that: The substrate comprises a bottom interconnect layer, a first isolation layer covering the top surface of the bottom interconnect layer, a second isolation layer covering the surface of the first isolation layer away from the bottom interconnect layer, and a plurality of bottom contact structures penetrating the first isolation layer and the second isolation layer along the first direction and electrically connected to the bottom interconnect layer, wherein the plurality of bottom contact structures are arranged at intervals along the second direction, and the plurality of bottom contact structures are electrically connected to the plurality of storage structures in a one-to-one correspondence; The storage structure includes a lower electrode layer electrically connected to the bottom contact structure, a variable resistance layer covering a surface of the lower electrode layer, and an upper electrode layer covering a surface of the variable resistance layer.
14. The memory according to claim 11, characterized in that: Also includes: The protective layer continuously covers the top surface of the substrate and the sidewalls and top surface of the storage structure, and the first dielectric layer is flush with the protective layer on the top surface of the storage structure.