Diode manufacturing method and diode

Abstract

The embodiment of the invention provides a diode manufacturing method and a diode. The manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises a first side and a second side which are arranged oppositely; forming a first oxide layer on the first side of the substrate, and forming a second oxide layer on the second side of the substrate; and removing the first oxide layer in a preset doped region by adopting a dry etching mode and a wet etching mode in sequence. According to the embodiment of the invention, the process steps of the diode are simplified, the risk of introducing defects is reduced, and the performance of the diode is improved.

Description

Technical Field

[0001] This application belongs to the technical field of electronic components, and particularly relates to a manufacturing method of a diode and a diode. Background Art

[0002] As a commonly used basic electronic component, the fast recovery diode has the advantages of short reverse recovery time, good switching characteristics, and large operating current, and is widely used in devices such as AC motor variable frequency speed regulators, switching power supplies, and uninterruptible power supplies. Among them, the fast recovery diode with a PIN structure has the advantages of high breakdown voltage and high switching speed. The fast recovery diode with a PIN structure usually has a P-type highly doped region and an N-type highly doped region, and moreover, the P-type highly doped region and the N-type highly doped region have a high impurity concentration.

[0003] Currently, in the process of manufacturing existing fast recovery diodes, the wet etching process is usually used to remove the oxide layer. This process may etch all the back oxide layers, causing the precipitation of impurity ions, affecting the device stability and contaminating the machine tool in subsequent processes. In order to prevent the precipitation of impurity ions, SiN (silicon nitride) is usually used as the encapsulation layer on the back of the wafer. However, when using SiN as the back encapsulation during the manufacturing process, in order to reduce the stress between the substrate and SiN, it is also necessary to first grow Pad-oxide (pad oxide layer) on the substrate, and then deposit SiN on the Pad-oxide. In the subsequent manufacturing process, it is necessary to remove the SiN and Pad-oxide on the front of the substrate before the growth of the oxide layer can be carried out. That is, the existing fast recovery diodes introduce steps such as Pad-oxide growth, SiN growth, SiN removal, and Pad-oxide removal during the manufacturing process. The steps are cumbersome, the cost is higher, and defects may be introduced in these steps, affecting the performance of the fast recovery diode. Summary of the Invention

[0004] This application aims to provide a manufacturing method of a diode and a diode to solve the problems of cumbersome processing steps and easy introduction of defects in existing diodes.

[0005] To solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, this application discloses a manufacturing method of a diode, and the manufacturing method includes:

[0007] Provide a substrate, the substrate includes a first side and a second side arranged opposite to each other;

[0008] Form a first oxide layer on the first side of the substrate, and form a second oxide layer on the second side of the substrate;

[0009] Remove the first oxide layer in the preset doping region by using dry etching and wet etching in sequence.

[0010] Optionally, the step of sequentially removing the first oxide layer of the preset doping region by dry etching and wet etching includes:

[0011] Defining a preset doping region on the first oxide layer by using a first mask;

[0012] Etching the first oxide layer of the preset doping region by dry etching, and the etching depth of the dry etching is a first depth;

[0013] Etching the first oxide layer of the preset doping region by wet etching, the etching depth of the wet etching is a second depth, and the sum of the second depth and the first depth is the thickness of the first oxide layer.

[0014] Optionally, the first depth is greater than the second depth.

[0015] Optionally, the first depth is 0.7um - 1.3um, and the second depth is 0.1um - 0.2um.

[0016] Optionally, the thicknesses of the first oxide layer and the second oxide layer are 0.8 - 1.5um.

[0017] Optionally, after the step of sequentially removing the first oxide layer of the preset doping region by dry etching and wet etching, the following steps are further included:

[0018] Doping impurities into the preset doping region of the substrate to form a doping structure in the substrate;

[0019] Forming a first metal layer and a protective layer on the first oxide layer on the first side of the substrate in sequence.

[0020] Optionally, the step of doping impurities into the preset doping region of the substrate to form a doping structure in the substrate includes:

[0021] Defining the preset doping region on the first oxide layer by using a second mask;

[0022] Performing photoresist coating, exposure and development on the first oxide layer, and only retaining the photoresist outside the preset doping region;

[0023] Injecting impurities into the preset doping region in the substrate by ion implantation;

[0024] After removing the photoresist on the first oxide layer, performing high-temperature push-in to diffuse the implanted impurity ions in the substrate to form a doping structure in the substrate.

[0025] Optionally, the impurity includes at least one of boron or aluminum, and the doping dose of the impurity is 1e10 - 1e16 ea / cm 2 .

[0026] Optionally, the substrate is an N+-type substrate with a high doping concentration, the impurity is a P-type impurity, and the doping structure is a P+N structure.

[0027] Optionally, the step of sequentially forming a first metal layer and a protective layer on the first oxide layer on the first side of the substrate includes:

[0028] Forming a continuous metal layer on the first oxide layer on the first side of the substrate by sputtering;

[0029] Defining the pattern of the first metal layer on the continuous metal layer using a third mask plate, and forming the first metal layer on the continuous metal layer by photolithography and etching;

[0030] Forming an insulating layer on the first metal layer by deposition or coating;

[0031] Defining the pattern of the protective layer on the insulating layer using a fourth mask plate, and forming the protective layer on the insulating layer by photolithography and etching.

[0032] Optionally, after the step of sequentially forming a first metal layer and a protective layer on the first oxide layer on the first side of the substrate, the method further includes:

[0033] Removing the second oxide layer on the second side of the substrate;

[0034] Forming a second metal layer on the second side of the substrate.

[0035] Optionally, the material of the first metal layer includes at least one of aluminum, aluminum-silicon, aluminum-silicon-copper, titanium, and tungsten;

[0036] The material of the second metal layer includes at least one of a titanium-nickel-silver alloy, a nickel-silver alloy, and an aluminum-titanium-nickel-silver alloy.

[0037] Optionally, before the step of forming a first oxide layer on the first side of the substrate and a second oxide layer on the second side of the substrate, the method further includes:

[0038] Sequentially forming a buffer layer and an epitaxial layer on the first side of the substrate, and sequentially forming a first polysilicon layer, a third oxide layer, and a second polysilicon layer on the second side of the substrate.

[0039] Optionally, the step of doping an impurity into the preset doping region of the substrate to form a doping structure in the substrate includes:

[0040] Dope impurities into the preset doping region of the epitaxial layer to form a doping structure within the epitaxial layer.

[0041] Optionally, the step of removing the second oxide layer on the second side of the substrate includes:

[0042] Remove the second oxide layer, the second polysilicon layer, the third oxide layer, and the first polysilicon layer on the second side of the substrate in sequence.

[0043] In a second aspect, the present application also discloses a diode, which is manufactured by using the manufacturing method of the diode described in any one of the above.

[0044] In the embodiments of the present application, the first oxide layer can be removed by dry etching and wet etching in sequence. Since dry etching can only etch the first oxide layer on the first side of the substrate, the second oxide layer on the second side of the substrate can be kept thick enough to block the precipitation of impurity ions on the substrate. In this way, the operation of using SiN as a packaging layer on the second side of the substrate can be avoided. Thus, steps such as Pad-oxide growth, SiN growth, SiN removal, and Pad-oxide removal can be reduced. This not only simplifies the process steps of the diode, but also reduces the risk of introducing defects and improves the performance of the diode.

[0045] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0046] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:

[0047] Figure 1 is a flowchart of the steps of a manufacturing method of a diode according to an embodiment of the present application;

[0048] Figure 2 is one of the schematic structural diagrams in the manufacturing process of a diode according to an embodiment of the present application;

[0049] Figure 3 is another schematic structural diagram in the manufacturing process of a diode according to an embodiment of the present application;

[0050] Figure 4 is yet another schematic structural diagram in the manufacturing process of a diode according to an embodiment of the present application;

[0051] Figure 5 is a flowchart of the steps of another manufacturing method of a diode according to an embodiment of the present application;

[0052] Figure 6 is one of the schematic structural diagrams in the manufacturing process of another diode according to an embodiment of the present application;

[0053] Figure 7 is the second of the schematic structural diagrams in the manufacturing process of another diode according to an embodiment of the present application;

[0054] Figure 8 is the third of the schematic structural diagrams in the manufacturing process of another diode according to an embodiment of the present application;

[0055] Figure 9 is the fourth of the schematic structural diagrams in the manufacturing process of another diode according to an embodiment of the present application;

[0056] Figure 10 is the fifth of the schematic structural diagrams in the manufacturing process of another diode according to an embodiment of the present application;

[0057] Figure 11 is the sixth of the schematic structural diagrams in the manufacturing process of another diode according to an embodiment of the present application;

[0058] Figure 12 is the seventh of the schematic structural diagrams in the manufacturing process of another diode according to an embodiment of the present application;

[0059] Figure 13 is the eighth of the schematic structural diagrams in the manufacturing process of another diode according to an embodiment of the present application;

[0060] Reference numerals: 10 - substrate, 11 - buffer layer, 12 - epitaxial layer, 13 - first polysilicon layer, 14 - third oxide layer, 15 - second polysilicon layer, 16 - first oxide layer, 17 - second oxide layer, 18 - doping structure, 19 - first metal layer, 110 - protective layer, 111 - second metal layer. Detailed Description of the Invention

[0061] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for explaining the present invention and should not be construed as limiting the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0062] The terms "first" and "second" in the description and claims of this application may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally means an "or" relationship between the associated objects before and after.

[0063] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0064] In the description of the present invention, it should be noted that, unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0065] The embodiments of this application provide a method for manufacturing a diode, and the diode may specifically be a fast recovery diode.

[0066] Refer to Figure 1 , which shows a flowchart of the steps of a method for manufacturing a diode according to the embodiments of this application. As Figure 1 shown, the manufacturing method may specifically include:

[0067] Step 101: Provide a substrate, and the substrate includes a first side and a second side disposed opposite to each other.

[0068] In the embodiments of this application, Figure 2The substrate 10 shown, and the substrate 10 can specifically be a silicon substrate. The substrate 10 can include a first side and a second side arranged oppositely. The first side can be the front side of the substrate 10, and the second side can be the back side of the substrate 10; or, the first side can be the back side of the substrate 10, and the second side can be the front side of the substrate 10. In the embodiments of the present application, only the case where the first side is the front side of the substrate 10 and the second side is the back side of the substrate 10 is taken as an example for illustration.

[0069] Optionally, the substrate 10 can be an N+ substrate with <100> crystal orientation and high doping concentration of N type, and the doping resistivity of the N+ substrate is less than 0.005 Ω·cm.

[0070] Step 102: Form a first oxide layer on the first side of the substrate, and form a second oxide layer on the second side of the substrate.

[0071] In the embodiments of the present application, methods such as deposition or thermal growth can be used to form the Figure 3 shown first oxide layer 16 and second oxide layer 17 on both sides of the substrate 10. A furnace tube device can be used to form the first oxide layer 16 and the second oxide layer 17 on both sides of the substrate 10 simultaneously.

[0072] Step 103: Remove the first oxide layer in the preset doping area by dry etching and wet etching in sequence.

[0073] In the embodiments of the present application, the dry etching method can be used to first remove the first oxide layer 16 in the preset doping area. Since dry etching can etch the first oxide layer 16 only from the first side of the substrate 10, during the process of dry etching, the thickness of the second oxide layer 17 on the second side of the substrate 10 is not thinned. Then, wet etching is used to continue to remove the first oxide layer 16 in the preset doping area to obtain the Figure 4 shown structure. Since wet etching has a lower cost and can achieve uniform etching, therefore, using wet etching is beneficial to reducing the etching cost and achieving a more uniform etching effect.

[0074] In a specific application, since dry etching can only etch the first oxide layer 16 on the first side of the substrate 10, the second oxide layer 17 on the second side of the substrate 10 can be kept with a sufficient thickness to block the precipitation of impurity ions on the substrate 10. In this way, the operation of using SiN as a packaging layer on the second side of the substrate 10 can be avoided, thereby, steps such as Pad-oxide growth, SiN growth, SiN removal, and Pad-oxide removal can be reduced. This not only simplifies the process steps of the diode, but also reduces the risk of introducing defects and improves the performance of the diode.

[0075] Specifically, the dry etching is a technique for thin film etching using plasma. When the gas exists in the form of plasma, it has two characteristics: on the one hand, the chemical activity of these gases in the plasma is much stronger than that in the normal state. According to the different materials to be etched, by selecting the appropriate gas, it can react with the material faster to achieve the purpose of etching and removal; on the other hand, the plasma can also be guided and accelerated by an electric field to make it have a certain energy. When it bombards the surface of the object to be etched, it will knock out the atoms of the material of the object to be etched, so as to achieve the purpose of etching by using physical energy transfer. In the embodiments of the present application, the dry etching may include any one of physical etching, chemical etching, and physical-chemical etching. The embodiments of the present application do not make specific limitations on the manner of the dry etching.

[0076] Specifically, the wet etching is an etching method, which is a technique of immersing the material to be etched in the etching solution for corrosion.

[0077] In summary, the manufacturing method of the diode described in the embodiments of the present application may at least include the following advantages:

[0078] In the embodiments of the present application, the first oxide layer may be removed by sequentially adopting dry etching and wet etching. Since the dry etching can only etch the first oxide layer on the first side of the substrate, the second oxide layer on the second side of the substrate can be kept thick enough to block the precipitation of impurity ions on the substrate. In this way, the operation of using SiN as the encapsulation layer on the second side of the substrate can be avoided, thereby reducing steps such as Pad-oxide growth, SiN growth, SiN removal, and Pad-oxide removal. This not only simplifies the process steps of the diode, but also reduces the risk of introducing defects and improves the performance of the diode.

[0079] Refer to Figure 5 , which shows the step flowchart of another manufacturing method of the diode described in the embodiments of the present application. As Figure 5 shown, the manufacturing method may specifically include the following steps:

[0080] Step 501: Provide a substrate, where the substrate includes a first side and a second side that are disposed opposite to each other.

[0081] The specific implementation process of this step is similar to step 101 in the above embodiments and will not be elaborated here.

[0082] Step 502: Sequentially form a buffer layer and an epitaxial layer on the first side of the substrate, and sequentially form a first polysilicon layer, a third oxide layer, and a second polysilicon layer on the second side of the substrate.

[0083] In the embodiments of the present application, asFigure 6 As shown, a buffer layer 11 and an epitaxial layer 12 can be successively formed on the first side of the substrate 10 through an epitaxial process. Among them, the buffer layer 11 can play a buffering role, and the epitaxial layer 12 can play a role in protecting the first side of the substrate 10. In addition, a first polysilicon layer 13, a third oxide layer 14, and a second polysilicon layer 15 can be successively formed on the second side of the substrate 10, and the first polysilicon layer 13, the third oxide layer 14, and the second polysilicon layer 15 can be used to play the role of the second side of the substrate 10.

[0084] Specifically, when the substrate 10 is an N+ substrate, the buffer layer 11 can be an N-type doped N buffer layer, and the epitaxial layer 12 can be an N-epitaxial layer with a low N-type doping concentration.

[0085] Step 503: Form a first oxide layer on the epitaxial layer and a second oxide layer on the second polysilicon layer.

[0086] In the embodiments of the present application, the first oxide layer 16 and the second oxide layer 17 shown in the figure can be formed on both sides of the substrate 10 by means of deposition or thermal growth. Specifically, the first oxide layer 16 and the second oxide layer 17 can be respectively formed on both sides of the substrate 10 by using the deposition method, or the first oxide layer 16 and the second oxide layer 17 can be simultaneously formed on both sides of the substrate 10 by using a furnace tube device, so as to form the first oxide layer 16 on the epitaxial layer 12 and form the second oxide layer 17 on the second polysilicon layer 15. Figure 7 Optionally, the thickness of the first oxide layer 16 and the second oxide layer 17 is 0.8 - 1.5 μm, so that the first oxide layer 16 and the second oxide layer 17 have sufficient thickness to protect the substrate 10 from both sides, block the precipitation of impurity ions on the substrate 10, and avoid the precipitation of impurity ions from affecting the stability of the diode and contaminating the machine in subsequent processes.

[0087] For example, the thickness of the first oxide layer 16 and the second oxide layer 17 can include but is not limited to any one of 0.8 μm, 0.95 μm, 1.2 μm, and 1.5 μm. The embodiments of the present application do not make specific limitations on the thickness of the first oxide layer 16 and the second oxide layer 17.

[0088] For example, the thickness of the first oxide layer 16 and the second oxide layer 17 can include but is not limited to any one of 0.8 μm, 0.95 μm, 1.2 μm, and 1.5 μm. The embodiments of the present application do not make specific limitations on the thickness of the first oxide layer 16 and the second oxide layer 17.

[0089] Step 504: Remove the first oxide layer in the preset doping area by means of dry etching and wet etching in sequence.

[0090] In some optional embodiments of the present application, the step of removing the first oxide layer in the preset doping area by means of dry etching and wet etching in sequence may include the following sub-steps:

[0091] Sub-step S11: Define a preset doping region on the first oxide layer by using a first mask plate.

[0092] In the embodiment of the present application, a preset doping region can be defined on the first oxide layer 16 by using a first mask plate. Specifically, the first mask plate may have a pattern of the preset doping region. By transferring the pattern on the first mask plate to the first oxide layer 16, the pattern of the preset doping region can be formed on the first oxide layer 16. In practical applications, after the first mask plate completes the definition of the preset doping region on the first oxide layer 16, the region corresponding to the preset doping region on the first oxide layer 16 can be etched away, while the regions outside the preset doping region cannot be etched away.

[0093] Sub-step S12: Etch the first oxide layer of the preset doping region by using dry etching, and the etching depth of the dry etching is a first depth.

[0094] In the embodiment of the present application, the first oxide layer 16 of the preset doping region can be removed first by using dry etching. Since dry etching can etch the first oxide layer 16 only from the first side of the substrate 10, the thickness of the second oxide layer 17 on the second side of the substrate 10 is not thinned during the dry etching process. Wherein, the etching depth of the dry etching is a first depth, and the first depth can be less than the thickness of the first oxide layer 16.

[0095] Sub-step S13: Etch the first oxide layer of the preset doping region by using wet etching, the etching depth of the wet etching is a second depth, and the sum of the second depth and the first depth is the thickness of the first oxide layer.

[0096] In the embodiment of the present application, after the first oxide layer 16 is dry-etched to a first depth, wet etching can be used to continue removing the first oxide layer 16 of the preset doping region to obtain Figure 8 the structure shown. Since wet etching has a lower cost and can achieve uniform etching, therefore, using wet etching is beneficial to reducing the etching cost and achieving a relatively uniform etching effect. Wherein, the etching depth of the wet etching can be a second depth, and the sum of the second depth and the first depth is the thickness of the first oxide layer 16. In this way, by performing dry etching and wet etching successively, the first oxide layer 16 of the preset doping region can be completely removed, so that the epitaxial layer 12 of the preset doping region is exposed.

[0097] Optionally, the first depth is greater than the second depth, that is, the etching depth of the dry etching is greater than the depth of the wet etching. In this way, the influence on the second oxide layer 17 on the second side of the substrate 10 during the wet etching process can be reduced, so that the second oxide layer 17 on the second side of the substrate 10 maintains a sufficient thickness to block the precipitation of impurity ions on the substrate 10. In this way, the operation of using SiN as the encapsulation layer on the second side of the substrate 10 can be avoided. Thus, steps such as Pad-oxide growth, SiN growth, SiN removal, and Pad-oxide removal can be reduced, which not only simplifies the process steps of the diode, but also reduces the risk of introducing defects and improves the performance of the diode.

[0098] Optionally, the first depth is 0.7um - 1.3um, and the second depth is 0.1um - 0.2um. In this way, not only can the depth of the dry etching be greater than the depth of the wet etching, but also the total thickness of the dry etching and the wet etching can be equal to the thickness of the first oxide layer 16 to achieve precise etching.

[0099] Exemplarily, the first depth may include but is not limited to any one of 0.7um, 0.95um, 1.2um, and 1.3um, and the second depth may include but is not limited to any one of 0.1um, 0.12um, 1.6um, and 0.2um. The specific values of the first depth and the second depth in the embodiments of the present application may not be limited.

[0100] Step 505: Dope impurities into the preset doping region of the substrate to form a doping structure in the substrate.

[0101] In the embodiments of the present application, the impurities can be doped into the preset doping region of the substrate 10 by ion implantation. When there is an epitaxial layer 12 on the first side of the substrate 10, the impurities can be doped into the preset doping region of the epitaxial layer 12 to form Figure 9 the doping structure 18 shown, so that the finally obtained diode has the advantages of high breakdown voltage and high switching speed.

[0102] Optionally, the substrate 10 is an N+ substrate with a high N-type doping concentration, the impurity is a P-type impurity, and the doping structure is a P+N structure.

[0103] In some alternative embodiments of the present application, the step of doping impurities into the preset doping region of the substrate to form a doping structure in the substrate may include the following sub-steps:

[0104] Sub-step S21: Define the preset doping region on the first oxide layer using a second mask plate.

[0105] In the embodiment of the present application, a second mask plate may be used to define the preset doping region on the first oxide layer 16. Specifically, the second mask plate may have the pattern of the preset doping region, and by transferring the pattern on the second mask plate to the first oxide layer 16, the pattern of the preset doping region can be formed on the first oxide layer 16.

[0106] Sub-step S22: Apply photoresist, expose, and develop the first oxide layer, and only retain the photoresist outside the preset doping region.

[0107] In the embodiment of the present application, the first oxide layer 16 may be coated with photoresist, exposed, and developed to remove the photoresist in the region outside the preset doping region, and only retain the photoresist outside the preset doping region. In practical applications, the photoresist can be used to block light from entering.

[0108] Sub-step S23: Inject impurities into the preset doping region in the substrate by ion implantation.

[0109] In the embodiment of the present application, impurities may be injected into the preset doping region in the epitaxial layer 12 by ion implantation. Optionally, in order to have a better doping effect, the impurities may include at least one of boron or aluminum, and the doping dose of the impurities is 1e10 - 1e16 ea / cm2.

[0110] Sub-step S24: After removing the photoresist on the first oxide layer, perform high-temperature drive-in to diffuse the implanted impurity ions in the substrate and form a doping structure in the substrate.

[0111] In the embodiment of the present application, high-temperature drive-in may be performed after removing the photoresist on the first oxide layer 16 to diffuse the implanted impurity ions in the epitaxial layer 12 and form a doping structure in the epitaxial layer 12. Specifically, the high-temperature drive-in method may include but is not limited to at least one of high-temperature annealing, rapid annealing, and laser annealing. The embodiment of the present application does not make specific limitations on the high-temperature drive-in method.

[0112] Step 506: Sequentially form a first metal layer and a protective layer on the first oxide layer on the first side of the substrate.

[0113] In the embodiment of the present application, a first metal layer 19 and a protective layer 110 may be sequentially formed on the first oxide layer 16 on the first side of the substrate 10. Among them, the first metal layer 19 may be used as the front metal layer of the diode, and the protective layer 110 may be used to protect the first metal layer 19.

[0114] Exemplarily, the material of the first metal layer 19 may include but is not limited to one of aluminum, aluminum silicon, aluminum silicon copper, titanium, and tungsten. The embodiments of the present application do not specifically limit the material of the first metal layer 19. The protective layer 110 may be made of an insulating material such as silicon nitride.

[0115] Optionally, the step of sequentially forming the first metal layer and the protective layer on the first oxide layer on the first side of the substrate may specifically include the following sub-steps:

[0116] Sub-step S31: Form a continuous metal layer on the first oxide layer 16 on the first side of the substrate 10 by means of sputtering.

[0117] In the embodiments of the present application, a continuous metal layer may be formed on the first oxide layer 16 on the first side of the substrate 10 by means of sputtering, so as to obtain the Figure 10 shown first metal layer 19 in subsequent processes.

[0118] Sub-step S32: Define the pattern of the first metal layer on the continuous metal layer by using a third mask plate, and form the first metal layer on the continuous metal layer by means of photolithography and etching.

[0119] In the embodiments of the present application, the pattern of the first metal layer 19 may be defined on the continuous metal layer by using a third mask plate first. Specifically, the third mask plate may have the pattern of the first metal layer 19. By transferring the pattern on the third mask plate to the continuous metal layer, the pattern of the first metal layer 19 can be formed on the continuous metal layer.

[0120] Then, the continuous metal layer may be etched by means of photolithography and etching to form the Figure 10 shown first metal layer 19 on the continuous metal layer.

[0121] Sub-step S33: Form an insulating layer on the first metal layer by means of deposition or coating.

[0122] In the embodiments of the present application, an insulating layer may be formed on the first metal layer 19 by means of deposition or coating, and the insulating layer may be used to achieve the insulating protection of the first metal layer 19.

[0123] Sub-step S34: Define the pattern of the protective layer on the insulating layer by using a fourth mask plate, and form the protective layer on the insulating layer by means of photolithography and etching.

[0124] In the embodiments of the present application, a fourth mask plate may be first used to define the pattern of the protective layer 110 on the insulating layer. Specifically, the fourth mask plate may have the pattern of the protective layer 110, and by transferring the pattern on the fourth mask plate to the insulating layer, the pattern of the protective layer 110 can be formed on the insulating layer.

[0125] Then, the insulating layer may be etched by photolithography and etching to form Figure 11 the protective layer 110 as shown.

[0126] Step 507: Remove the second oxide layer, the second polysilicon layer, the third oxide layer, and the first polysilicon layer on the second side of the substrate.

[0127] In the embodiments of the present application, a thinning process may be used to remove the second oxide layer 17, the second polysilicon layer 15, the third oxide layer 14, and the first polysilicon layer 13 on the second side of the N substrate 10 to reduce the overall thickness of the diode.

[0128] Step 508: Form a second metal layer on the second side of the substrate.

[0129] Specifically, a second metal layer 111 as shown may be formed on the second side of the substrate 10 by using an evaporation process. Specifically, the evaporation process enables an ohmic contact to be formed between the metal structure and the silicon interface, reduces the back contact resistance, and forms a back lead. Figure 13 Specifically, the material of the second metal layer 111 may include but is not limited to one of titanium nickel silver alloy, nickel silver alloy, and aluminum titanium nickel silver alloy. The embodiments of the present application do not make specific limitations on the material of the second metal layer 111.

[0130] Optionally, the material of the second metal layer 111 may include but is not limited to one of titanium nickel silver alloy, nickel silver alloy, and aluminum titanium nickel silver alloy. The embodiments of the present application do not make specific limitations on the material of the second metal layer 111.

[0131] The embodiments of the present application also provide a diode, and the diode may be manufactured by using the above manufacturing method of the diode.

[0132] It should be noted that the diode in the embodiments of the present application may include any structure obtained in the above manufacturing method, and correspondingly has the beneficial effects in the above manufacturing method, which will not be elaborated herein.

[0133] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0134] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A manufacturing method of a diode, characterized in that, the manufacturing method includes: providing a substrate, the substrate including a first side and a second side disposed opposite to each other; forming a first oxide layer on the first side of the substrate and a second oxide layer on the second side of the substrate; removing the first oxide layer in a preset doping region by dry etching and wet etching in sequence.

2. The manufacturing method according to claim 1, characterized in that, the step of removing the first oxide layer in the preset doping region by dry etching and wet etching in sequence includes: defining a preset doping region on the first oxide layer by using a first mask plate; etching the first oxide layer in the preset doping region by dry etching, the etching depth of the dry etching being a first depth; etching the first oxide layer in the preset doping region by wet etching, the etching depth of the wet etching being a second depth, and the sum of the second depth and the first depth being the thickness of the first oxide layer.

3. The manufacturing method according to claim 2, characterized in that, the first depth is greater than the second depth.

4. The manufacturing method according to claim 3, characterized in that, the first depth is 0.7um - 1.3um, and the second depth is 0.1um - 0.2um.

5. The manufacturing method according to claim 1, characterized in that, the thicknesses of the first oxide layer and the second oxide layer are 0.8 - 1.5um.

6. The manufacturing method according to claim 1, characterized in that, after the step of removing the first oxide layer in the preset doping region by dry etching and wet etching in sequence, the method further includes: doping impurities into the preset doping region of the substrate to form a doping structure in the substrate; forming a first metal layer and a protective layer on the first oxide layer on the first side of the substrate in sequence.

7. The manufacturing method according to claim 6, characterized in that, the step of doping impurities into the preset doping region of the substrate to form a doping structure in the substrate includes: defining the preset doping region on the first oxide layer by using a second mask plate; performing photoresist coating, exposure and development on the first oxide layer, and only retaining the photoresist outside the preset doping region; injecting impurities into the preset doping region in the substrate by ion implantation; removing the photoresist on the first oxide layer and then performing high-temperature push trap to diffuse the implanted impurity ions in the substrate to form a doping structure in the substrate.

8. The manufacturing method according to claim 6, characterized in that, The impurities include at least one of boron or aluminum, and the doping dose of the impurities is 1e10 - 1e16 ea / cm 2 .

9. The manufacturing method according to claim 6, characterized in that, the substrate is an N+ substrate with a high N-type doping concentration, the impurity is a P-type impurity, and the doping structure is a P+N structure.

10. The manufacturing method according to claim 6, characterized in that, the step of forming a first metal layer and a protective layer on the first oxide layer on the first side of the substrate in sequence includes: forming a whole-surface metal layer on the first oxide layer on the first side of the substrate by using a sputtering process; Define the pattern of the first metal layer on the entire metal layer using a third mask, and form the first metal layer on the entire metal layer by means of photolithography and etching; Form an insulating layer on the first metal layer by means of deposition or coating; Define the pattern of the protective layer on the insulating layer using a fourth mask, and form the protective layer on the insulating layer by means of photolithography and etching.

11. The manufacturing method according to claim 6, wherein, after the steps of sequentially forming the first metal layer and the protective layer on the first oxide layer on the first side of the substrate, further comprising: Removing the second oxide layer on the second side of the substrate; Forming a second metal layer on the second side of the substrate.

12. The manufacturing method according to claim 11, wherein, the material of the first metal layer includes at least one of aluminum, aluminum silicon, aluminum silicon copper, titanium, and tungsten; the material of the second metal layer includes at least one of a titanium nickel silver alloy, a nickel silver alloy, and an aluminum titanium nickel silver alloy.

13. The manufacturing method according to claim 1, wherein, before the steps of forming the first oxide layer on the first side of the substrate and forming the second oxide layer on the second side of the substrate, further comprising: Sequentially forming a buffer layer and an epitaxial layer on the first side of the substrate, and sequentially forming a first polysilicon layer, a third oxide layer, and a second polysilicon layer on the second side of the substrate.

14. The manufacturing method according to claim 13, wherein, the step of doping impurities into the preset doping region of the substrate to form a doping structure in the substrate includes: Doping impurities into the preset doping region of the epitaxial layer to form a doping structure in the epitaxial layer.

15. The manufacturing method according to claim 13, wherein, the step of removing the second oxide layer on the second side of the substrate includes: Sequentially removing the second oxide layer, the second polysilicon layer, the third oxide layer, and the first polysilicon layer on the second side of the substrate.

16. A diode, wherein, the diode is manufactured by using the manufacturing method of the diode according to any one of claims 1 to 15.

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