Method for forming deep groove super junction
By forming deep trenches in the cellular region and scribed trenches of the substrate and forming a single crystal silicon layer inside and outside, combined with the filling of the hard mask layer and the formation of grooves, the problem of additional shallow trenches as alignment marks in the prior art is solved, and the material and process saving effect is achieved.
Patent Information
- Application Number
- CN202510174913.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-05-30
AI Technical Summary
In the prior art, since the single crystal silicon epitaxial layer and substrate silicon are the same material, there is no obvious physical boundary division after chemical mechanical polishing, the alignment layer formed by the second deep groove cannot be used for the rear-end process alignment, and additional shallow grooves are needed as alignment marks, which wastes materials and processes.
By forming the first deep trench and the second deep trench in the cell region and the scribed trench region of the substrate, a single crystal silicon layer is formed inside and outside, and then a hard mask layer is formed in the remaining trenches. The hard mask layer forms a groove at the second deep trench as an alignment mark, and then a shallow trench, a gate oxide layer and a gate electrode are formed on both sides of the trench.
This achieves no additional formation of shallow grooves as alignment marks, thus saving materials and process and improving process efficiency.
Smart Images
Figure CN120076384A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for forming a deep trench superjunction. Background Art
[0002] The method for forming an alignment mark in the prior art is as follows. Refer to Figure 1 and Figure 2 to provide a substrate 101. The substrate 101 includes an adjacent cell region 101A and a dicing saw region 101B. Etch a part of the thickness of the substrate 101, and form a first shallow trench 102 in the substrate 101 of the dicing saw region 101B. The depth of the first shallow trench 102 is 0.5 μm to 3 μm. Form a hard mask layer 103 on the inner wall of the first shallow trench 102 and the surface of the substrate 101. Etch the hard mask layer 103 and a part of the depth of the substrate 101 to simultaneously form a first deep trench 104 in the substrate 101 of the cell region 101A and a second deep trench 105 in the substrate 101 of the dicing saw region 101B. The first deep trench 104 and the second deep trench 105 are arranged at intervals, and the depths of the first deep trench 104 and the second deep trench 105 are the same. Epitaxially grow a single crystal silicon epitaxial layer 106 in both the first deep trench 104 and the second deep trench 105. Form a photoresist layer 107 on the surface of the hard mask layer 103, and use the first shallow trench 102 as an alignment mark to form two second shallow trenches 108 in the substrate 101 on both sides of the first deep trench 104 in the cell region 101A. At the same time, form a second shallow trench 108 in the substrate 101 of the dicing saw region 101B. The second shallow trench 108 and the first shallow trench 102 have a certain distance. Form a gate oxide layer 109 and a gate 110 in the second shallow trench 108. The gate 110 is separated from the inner wall of the second shallow trench 108 by the gate oxide layer 109.
[0003] However, in the prior art, since the single crystal silicon epitaxial layer and the substrate silicon are of the same material, there is no obvious physical boundary division after chemical mechanical polishing, and the alignment layer formed by the second deep trench 105 cannot be used for the alignment of the subsequent process. Therefore, a first shallow trench 102 needs to be separately formed as an alignment mark before forming the first deep trench 104 and the second deep trench 105, wasting materials and processes. Summary of the Invention
[0004] The purpose of the present invention is to provide a method for forming a deep trench superjunction, which can save materials and processes without forming an additional shallow trench as an alignment mark.
[0005] To achieve the above purpose, the present invention provides a method for forming a deep trench superjunction, including:
[0006] Provide a substrate, where the substrate includes an adjacent cell region and a dicing saw region;
[0007] A first deep trench and a second deep trench are respectively formed in the substrate of the cell region and the dicing groove region. The lengths of the first deep trench and the second deep trench both extend along a first direction, and the first deep trench and the second deep trench are arranged at intervals along a second direction. The first direction and the second direction are perpendicular. The width of the first deep trench in the second direction is smaller than the width of the second deep trench in the second direction.
[0008] A single-crystal silicon layer is formed in both the first deep trench at a partial depth and the second deep trench at a partial depth.
[0009] A first hard mask layer is formed in both the remaining first deep trench and the remaining second deep trench. The first hard mask layer simultaneously covers the surface of the substrate. The first hard mask layer fills the remaining first deep trench and forms a groove at the second deep trench.
[0010] Taking the groove as a first alignment mark, a first shallow trench is formed in the substrate of the cell region on both sides of the first deep trench, and a second shallow trench is formed in the substrate of the dicing groove region.
[0011] A first gate oxide layer and a first gate are sequentially formed in the first shallow trench. The first gate is separated from the inner wall of the first shallow trench by the first gate oxide layer. At the same time, a second gate oxide layer and a second gate are sequentially formed in the second shallow trench. The second gate is separated from the inner wall of the second shallow trench by the second gate oxide layer. The second gate and the second gate oxide layer serve as a second alignment mark.
[0012] Optionally, in the method for forming the deep trench superjunction, the method for respectively forming the first deep trench and the second deep trench in the substrate of the cell region and the dicing groove region includes:
[0013] A second hard mask layer is formed on the surface of the substrate, and the second hard mask layer and a partial thickness of the substrate are etched to respectively form the first deep trench and the second deep trench in the substrate of the cell region and the dicing groove region.
[0014] Optionally, in the method for forming the deep trench superjunction, the method for forming the single-crystal silicon layer in both the first deep trench at a partial depth and the second deep trench at a partial depth includes:
[0015] A single-crystal silicon material layer is epitaxially formed inside and outside the first deep trench and the second deep trench. The single-crystal silicon material layer simultaneously covers the surface of the second hard mask layer.
[0016] A partial thickness of the single-crystal silicon material layer is etched to expose the first deep trench and the second deep trench at a partial depth. The remaining single-crystal silicon material layer in the first deep trench and the second deep trench serves as the single-crystal silicon layer.
[0017] Optionally, in the method for forming the deep trench superjunction, after successively forming a first gate oxide layer and a first gate in the first shallow trench, and successively forming a second gate oxide layer and a second gate in the second shallow trench, the method further includes:
[0018] Removing the first hard mask layer on the surface of the substrate, and retaining the first hard mask layer in the first deep trench and the second deep trench.
[0019] Optionally, in the method for forming the deep trench superjunction, after removing the first hard mask layer on the surface of the substrate, the method further includes:
[0020] Aligning with the first alignment mark or the second alignment mark, and forming a well region, a source region, and a drain region in the substrate on both sides of the first gate in the cell region, where the well region is close to the surface of the substrate, and the source region and the drain region respectively penetrate through the well region.
[0021] Optionally, in the method for forming the deep trench superjunction, after forming a well region, a source region, and a drain region in the substrate on both sides of the first gate in the cell region, the method further includes:
[0022] Forming an interlayer dielectric layer on the surface of the substrate and the first hard mask layer;
[0023] Forming a plurality of contact holes in the interlayer dielectric layer, and the plurality of contact holes extend into the source region, the drain region, and the first hard mask layer.
[0024] Optionally, in the method for forming the deep trench superjunction, the thickness of the first hard mask layer is greater than half of the width of the first deep trench and less than half of the width of the second deep trench.
[0025] Optionally, in the method for forming the deep trench superjunction, the method for forming a first shallow trench in the substrate of the cell region on both sides of the first deep trench and a second shallow trench in the substrate of the dicing saw region with the groove as the first alignment mark includes:
[0026] Using the groove as the first alignment mark to form a patterned photoresist layer on the surface of the first hard mask layer;
[0027] Etching a part of the thickness of the substrate with the patterned photoresist layer to form a first shallow trench in the substrate of the cell region on both sides of the first deep trench and a second shallow trench in the substrate of the dicing saw region;
[0028] Removing the patterned photoresist layer.
[0029] Optionally, in the method for forming the deep trench superjunction, the substrate includes a wafer.
[0030] Optionally, in the method for forming the deep trench superjunction, the first hard mask layer includes silicon oxide.
[0031] In the method for forming the deep trench superjunction provided by the present invention, the groove formed by the first hard mask layer at the second deep trench serves as the first alignment mark, and the second gate and the second gate oxide layer serve as the second alignment mark. Therefore, there is no need to additionally form a shallow trench as an alignment mark, thus saving materials and processes. Description of the Drawings
[0032] Figure 1 and Figure 2 are schematic structural diagrams of forming a deep trench superjunction in the prior art;
[0033] Figure 3 is a flowchart of the method for forming the deep trench superjunction according to an embodiment of the present invention;
[0034] Figures 4 to 8 is a schematic structural diagram of forming a deep trench superjunction according to an embodiment of the invention;
[0035] In the figures: 101 - substrate, 101A - cell region, 101B - dicing channel region, 102 - first shallow trench, 103 - hard mask layer, 104 - first deep trench, 105 - second deep trench, 106 - single-crystalline silicon epitaxial layer, 107 - photoresist layer, 108 - second shallow trench, 109 - gate oxide layer, 110 - gate, 201 - substrate, 201A - cell region, 201B - dicing channel region, 202 - second hard mask layer, 203 - first deep trench, 204 - second deep trench, 205 - single-crystalline silicon material layer, 206 - first hard mask layer, 207 - photoresist layer, 208 - groove, 209 - first shallow trench, 210 - first gate oxide layer, 211 - first gate, 212 - second shallow trench, 213 - second gate oxide layer, 214 - second gate. Detailed Embodiments
[0036] The following will describe the specific embodiments of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise ratios, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.
[0037] In the following text, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It is understood that, where appropriate, these terms so used may be interchanged. Similarly, if the methods described herein include a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and / or some other steps not described herein may be added to the method.
[0038] Also, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it may be directly on another layer or substrate, and / or there may also be intervening layers. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it may be directly under another layer, and / or there may also be one or more intervening layers. Additionally, the references to "on" and "under" the respective layers may be based on the drawings.
[0039] Please refer to Figure 3 , the present invention provides a method for forming a deep trench superjunction, comprising:
[0040] S11: Providing a substrate, the substrate including adjacent cell regions and dicing slot regions;
[0041] S12: Respectively forming a first deep trench and a second deep trench in the substrate of the cell region and the dicing slot region, the lengths of the first deep trench and the second deep trench both extending along a first direction, and the first deep trench and the second deep trench being arranged at intervals along a second direction, the first direction and the second direction being perpendicular, and the width of the first deep trench in the second direction being less than the width of the second deep trench in the second direction;
[0042] S13: Forming a single crystal silicon layer in both the first deep trench at a partial depth and the second deep trench at a partial depth;
[0043] S14: Forming a first hard mask layer in both the remaining first deep trench and the remaining second deep trench, the first hard mask layer simultaneously covering the surface of the substrate, the first hard mask layer filling the remaining first deep trench and forming a groove at the second deep trench;
[0044] S15: Using the groove as a first alignment mark, forming a first shallow trench in the substrate of the cell region on both sides of the first deep trench, and forming a second shallow trench in the substrate of the dicing slot region;
[0045] S16: Form a first gate oxide layer and a first gate in the first shallow trench in sequence. The first gate is separated from the inner wall of the first shallow trench by the first gate oxide layer. At the same time, form a second gate oxide layer and a second gate in the second shallow trench in sequence. The second gate is separated from the inner wall of the second shallow trench by the second gate oxide layer. The second gate and the second gate oxide layer serve as the second alignment mark.
[0046] Specifically, please refer to Figure 4 , first provide a substrate 201. The substrate 201 can be a wafer. The substrate 201 is divided into an adjacent cell region 201A and a dicing saw region 201B. Form a second hard mask layer 202 on the surface of the substrate 201. Etch the second hard mask layer 202 and a part of the thickness of the substrate 201 to form a first deep trench 203 in the substrate 201 of the cell region 201A and a second deep trench 204 in the substrate 201 of the dicing saw region 201B. The lengths of the first deep trench 203 and the second deep trench 204 both extend along a first direction, and the first deep trench 203 and the second deep trench 204 are arranged at intervals along a second direction. The first direction and the second direction are perpendicular. The width of the first deep trench 203 in the second direction is less than the width of the second deep trench 204 in the second direction.
[0047] Next, please refer to Figure 5 , epitaxially grow a single crystal silicon material layer 205 inside and outside the first deep trench 203 and the second deep trench 204. The single crystal silicon material layer 205 fills the first deep trench 203 and the second deep trench 204 and covers the surface of the second hard mask layer 202.
[0048] Next, please refer to Figure 6 , etch a part of the thickness of the single crystal silicon material layer 205 to expose a part of the depth of the first deep trench and a part of the depth of the second deep trench. Then, remove the second hard mask layer 202.
[0049] Next, please refer to Figure 7 , fill and form a first hard mask layer 206 in the remaining first deep trench and the second deep trench with a part of the depth. The thickness of the first hard mask layer 206 is greater than half of the width of the first deep trench and less than half of the width of the second deep trench. The first hard mask layer 206 simultaneously covers the surface of the substrate 201. The first hard mask layer 206 fills the remaining first deep trench and forms a groove 208 at the second deep trench. Then, using the groove 208 as the first alignment mark, form a patterned photoresist layer 207 on the surface of the first hard mask layer 206. Form a first shallow trench 209 in the substrate 201 of the cell region 201A on both sides of the first deep trench and a second shallow trench 210 in the substrate 201 of the dicing saw region 201B. Remove the patterned photoresist layer 207.
[0050] Next, please refer to Figure 7 and Figure 8 , and a first gate oxide layer 211 and a first gate 212 are sequentially formed in the first shallow trench 209. The first gate 212 is separated from the inner wall of the first shallow trench 209 by the first gate oxide layer 211. At the same time, a second gate oxide layer 213 and a second gate 214 are sequentially formed in the second shallow trench 210. The second gate 214 is separated from the inner wall of the second shallow trench 210 by the second gate oxide layer 213. The second gate 214 and the second gate oxide layer 213 serve as a second alignment mark. When forming the first gate 212 and the second gate 214, a part of single-crystalline silicon is formed in the groove 208. Next, by aligning with the first alignment mark or the second alignment mark, a well region, a source region, and a drain region are formed in the substrate on both sides of the first gate in the cell region. The well region is close to the surface of the substrate, and the source region and the drain region respectively penetrate the well region. An interlayer dielectric layer is formed on the surfaces of the substrate and the first hard mask layer. A plurality of contact holes are formed in the interlayer dielectric layer, and the plurality of contact holes extend into the source region, the drain region, and the first hard mask layer.
[0051] In summary, in the method for forming a deep trench superjunction provided in the embodiment of the present invention, the groove formed by the first hard mask layer at the second deep trench serves as the first alignment mark, and the second gate and the second gate oxide layer serve as the second alignment mark. Therefore, there is no need to additionally form a shallow trench as an alignment mark, thereby saving materials and processes.
[0052] The above is only a preferred embodiment of the present invention and does not impose any limitation on the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed in the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.
Claims
1. A method for forming a deep trench super junction, characterized in that: include: Providing a substrate, the substrate comprising adjacent cell regions and scribe line regions; A first deep trench and a second deep trench are formed in the substrate of the cell region and the scribe line region, respectively, wherein the lengths of the first deep trench and the second deep trench both extend along a first direction, and the first deep trench and the second deep trench are arranged in an interval along a second direction, the first direction and the second direction are perpendicular, and the width of the first deep trench in the second direction is smaller than the width of the second deep trench in the second direction; forming a single crystal silicon layer in both the first deep trench of a part of the depth and the second deep trench of a part of the depth; forming a first hard mask layer in the remaining first deep trenches and the remaining second deep trenches, wherein the first hard mask layer covers the surface of the substrate at the same time, the first hard mask layer fills the remaining first deep trenches, and forms a groove in the second deep trench; Using the groove as a first alignment mark, forming a first shallow groove in the substrate of the cell region on both sides of the first deep groove, and forming a second shallow groove in the substrate of the scribe line region; A first gate oxide layer and a first gate electrode are sequentially formed in the first shallow trench, and the first gate electrode is separated from the inner wall of the first shallow trench by the first gate oxide layer. Meanwhile, a second gate oxide layer and a second gate electrode are sequentially formed in the second shallow trench, and the second gate electrode is separated from the inner wall of the second shallow trench by the second gate oxide layer. The second gate electrode and the second gate oxide layer serve as second alignment marks.
2. The method for forming a deep trench super junction according to claim 1, wherein: The method of forming a first deep trench and a second deep trench in the substrate of the cell region and the scribe line region respectively comprises: A second hard mask layer is formed on the surface of the substrate, and the second hard mask layer and a portion of the thickness of the substrate are etched to form a first deep trench and a second deep trench in the substrate in the cell region and the scribe line region, respectively.
3. The method for forming a deep trench super junction according to claim 2, wherein: The method of forming a single crystal silicon layer in both the first deep trench of a partial depth and the second deep trench of a partial depth comprises: epitaxially forming a single crystal silicon material layer in the first deep trench and the second deep trench, wherein the single crystal silicon material layer simultaneously covers the surface of the second hard mask layer; A partial thickness of the single crystal silicon material layer is etched to expose a first deep trench and a second deep trench of a partial depth, and the remaining single crystal silicon material layer in the first deep trench and the second deep trench serves as a single crystal silicon layer.
4. The method for forming a deep trench super junction according to claim 1, wherein: After sequentially forming a first gate oxide layer and a first gate electrode in the first shallow trench, and sequentially forming a second gate oxide layer and a second gate electrode in the second shallow trench, the method further includes: The first hard mask layer on the surface of the substrate is removed, and the first hard mask layer in the first deep trench and the second deep trench is retained.
5. The method for forming a deep trench super junction according to claim 4, characterized in that: After removing the first hard mask layer located on the surface of the substrate, the method further includes: The first alignment mark or the second alignment mark is aligned to form a well region, a source region and a drain region in the substrate on both sides of the first gate of the cell region, wherein the well region is close to the surface of the substrate, and the source region and the drain region respectively penetrate the well region.
6. The method for forming a deep trench super junction according to claim 5, characterized in that: After forming a well region, a source region and a drain region in the substrate on both sides of the first gate of the cell region, the method further includes: forming an interlayer dielectric layer on surfaces of the substrate and the first hard mask layer; A plurality of contact holes are formed in the interlayer dielectric layer, and the plurality of contact holes extend into the source region, the drain region and the first hard mask layer.
7. The method for forming a deep trench super junction according to claim 1, wherein: The thickness of the first hard mask layer is greater than half of the width of the first deep trench and less than half of the width of the second deep trench.
8. The method for forming a deep trench super junction according to claim 1, wherein: The method of forming a first shallow trench in the substrate of the cell area on both sides of the first deep trench using the groove as a first alignment mark, and forming a second shallow trench in the substrate of the scribe line area includes: Using the groove as a first alignment mark, forming a patterned photoresist layer on the surface of the first hard mask layer; Etching a portion of the thickness of the substrate with the patterned photoresist layer to form a first shallow trench in the substrate in the cell region on both sides of the first deep trench, and a second shallow trench in the substrate in the scribe line region; The patterned photoresist layer is removed.
9. The method for forming a deep trench super junction according to claim 1, wherein: The substrate includes a wafer.
10. The method for forming a deep trench super junction according to claim 1, wherein: The first hard mask layer includes silicon oxide.