Fractional frequency synthesizer with multi-phase divider circuitry

Abstract

Embodiments of the present disclosure relate to a fractional frequency synthesizer utilizing a multi-phase divider circuit arrangement. A fractional frequency synthesizer, a fractional PLL, and a method for generating a fractional frequency signal based on a reference signal are provided. An example fractional frequency synthesizer includes a multi-phase clock generator configured to generate a clock vector including a plurality of clock signals, each clock signal oscillating according to a fractional frequency relative to a reference frequency and offset by a phase offset. The fractional frequency synthesizer includes multi-phase divider circuitry configured to select a clock signal from a clock vector to generate a fractional frequency feedback signal. Also included is an accumulator configured to incrementally count and a flipping detector configured to determine a flipping value associated with a flipping event on the accumulator. A clock signal is selected based on the flipping value, and a fractional frequency feedback signal is generated based at least in part on the selected clock signal.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to fractional frequency synthesizers, and more particularly to fractional phase-locked loops (PLLs) based on fractional frequency synthesizers. Background Art

[0002] Many modern electronic devices utilize phase-locked loops to perform various operations of the electronic devices. A PLL is a control system that generates an output signal having a phase related to the phase of an input signal. A PLL can be used to generate a signal having a determined frequency, stabilize a signal, modulate or demodulate a signal, filter or recover a signal from a noisy communication channel, multiply or divide a frequency, etc. A fractional PLL is a PLL that can be used to generate a frequency at a non-integer interval based on a reference frequency. A fractional PLL is capable of generating an output signal having a smaller step size (e.g., higher resolution).

[0003] The applicant has identified many technical challenges and difficulties associated with generating a fractional frequency signal based on a reference signal. Through the efforts, wisdom, and innovation exerted, the applicant has solved the problems related to generating a fractional frequency signal by developing the solutions embodied in the present disclosure, which will be described in detail below. Summary of the Invention

[0004] Various embodiments relate to example fractional frequency synthesizers, fractional PLLs, and methods for generating a fractional frequency signal based on a reference frequency. In some embodiments, the fractional frequency synthesizer may include a multi-phase clock generator configured to generate a clock vector based on a reference signal having a reference frequency, where the clock vector includes a plurality of clock signals, each clock signal oscillates according to a fractional frequency relative to the reference frequency, and where each clock signal is offset by a phase offset. The fractional frequency synthesizer may further include a multi-phase divider circuit electrically connected to the multi-phase clock generator and configured to receive the clock vector and select a selected clock signal from the plurality of clock signals to generate a fractional frequency feedback signal. The multi-phase divider circuit includes an accumulator and a flip detector, the accumulator is configured to incrementally count according to the fractional frequency, and the flip detector is configured to determine a flip value associated with a flip event of the count on the accumulator. In some embodiments, the selected clock signal is selected based on the flip value, and the fractional frequency feedback signal is generated at least in part based on the selected clock signal.

[0005] In some embodiments, the multi-phase clock generator includes a voltage-controlled ring oscillator.

[0006] In some embodiments, a voltage-controlled ring oscillator includes a delay line that includes a plurality of delay elements, wherein a plurality of clock signals included in a clock vector are transmitted along the delay line from a plurality of contact points.

[0007] In some embodiments, an accumulator includes a counter that includes a least significant bit of counter bits, wherein the counter is configured to increment by a step value.

[0008] In some embodiments, a fractional frequency of the plurality of clock signals is determined at least in part based on the number of counter bits and the step value.

[0009] In some embodiments, a rollover value represents a count after a rollover event of the accumulator.

[0010] In some embodiments, a selected clock signal is determined at least in part based on a comparison of the rollover value and the step value.

[0011] In some embodiments, a comparison of the rollover value and the step value is determined using a division lookup table.

[0012] In some embodiments, a frequency offset is determined between a clock edge of the selected clock signal and an ideal clock edge of a fractional frequency signal, wherein a second selected clock signal corresponding to a next accumulator rollover event is determined at least in part based on the frequency offset.

[0013] In some embodiments, the selected clock signal is determined prior to a rollover event of the accumulator.

[0014] In some embodiments, a phase offset between each successive clock signal of a plurality of clock signals including a clock vector is equal.

[0015] In some embodiments, the clock vector includes at least four clock signals.

[0016] A method for generating a fractional frequency feedback signal is also provided. In some embodiments, the method includes receiving, at a multi-phase divider circuit, a clock vector including a plurality of clock signals from a multi-phase clock generator, each clock signal oscillating at a fractional frequency based at least in part on a reference frequency of a reference signal, and each clock signal being offset by a phase offset. The method also includes detecting, at the multi-phase divider circuit, a rollover event of an accumulator configured to increment by the fractional frequency. The method also includes determining a rollover value corresponding to the count at the rollover event. The method also includes selecting a selected clock signal from the plurality of clock signals based on the rollover value, and generating a fractional frequency feedback signal at least in part based on the selected clock signal.

[0017] In some embodiments, the accumulator includes a counter that includes a least significant bit of counter bits, wherein the counter is configured to increment by a step value at least in part based on the reference frequency.

[0018] In some embodiments, a fractional frequency of a plurality of clock signals is determined based at least in part on a counter bit number and a step value.

[0019] In some embodiments, a flip value represents a count after a flip event of an accumulator.

[0020] In some embodiments, the method further includes determining a relationship between the flip value and the step value, and selecting a selected clock signal based at least in part on the relationship.

[0021] In some embodiments, the method further includes determining a phase difference between a clock edge of the selected clock signal and an ideal clock edge of a reference signal, and determining a second selected clock signal corresponding to a next accumulator flip event based at least in part on a frequency difference.

[0022] In some embodiments, a phase offset between each subsequent clock signal of a plurality of clock signals including a clock vector is equal.

[0023] A fractional phase-locked loop is also provided. In some embodiments, the fractional phase-locked loop includes a phase detector module, a loop filter, and a fractional frequency synthesizer. The phase detector module is configured to generate a difference signal corresponding to a difference between a phase of a reference signal and a phase of a fractional frequency feedback signal. The loop filter is configured to generate a filtered difference signal based at least in part on the difference signal. The fractional frequency synthesizer is configured to generate a fractional frequency feedback signal. The fractional frequency synthesizer may include a multi-phase clock generator configured to generate a clock vector based on the filtered difference signal. The clock vector includes a plurality of clock signals, each clock signal oscillating at a fractional frequency based at least in part on a reference frequency of the reference signal, and each clock signal being offset by a phase offset. The fractional frequency synthesizer may further include a multi-phase divider circuitry electrically connected to the multi-phase clock generator and configured to receive the clock vector and select a selected clock signal from the clock vector to generate the fractional frequency feedback signal. The multi-phase divider circuitry includes an accumulator configured to increment a count according to the fractional frequency, and a flip detector configured to detect a flip value associated with a flip event of the accumulator, wherein the selected clock signal is selected based on the flip value, and wherein the fractional frequency feedback signal is generated based at least in part on the selected clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Reference is now made to the drawings. In certain embodiments described herein, the components illustrated in the drawings may or may not be present. According to example embodiments of the present disclosure, some embodiments may include fewer (or more) components than those shown in the drawings.

[0025] Figure 1 The block diagram of an example fractional frequency synthesizer using a clock vector and a multi-phase divider block according to an example embodiment of the present disclosure is illustrated.

[0026] Figure 2 The block diagram of an example embodiment of a multi-phase clock generator according to an example embodiment of the present disclosure is illustrated.

[0027] Figure 3 The example signal diagram depicting multiple clock signals of a clock vector according to an example embodiment of the present disclosure is illustrated.

[0028] Figure 4 The example block diagram of a multi-phase divider block according to an example embodiment of the present disclosure is illustrated.

[0029] Figure 5 The example circuit-level diagram of an example embodiment of a multi-phase divider block according to an example embodiment of the present disclosure is illustrated.

[0030] Figure 6 The example signal diagram depicting a selected clock signal according to an example embodiment of the present disclosure is illustrated.

[0031] Figure 7 The example accumulator count compared with an example ideal count according to an example embodiment of the present disclosure is illustrated.

[0032] Figure 8A and Figure 8B The example accumulator flip event according to an example embodiment of the present disclosure is illustrated.

[0033] Figure 9 The example flowchart depicting an example method for determining a fractional frequency signal based on a reference signal according to an example embodiment of the present disclosure is depicted.

[0034] Figure 10 The example embodiment of a method for determining a fractional frequency signal based on a reference signal according to an example embodiment of the present disclosure is illustrated.

[0035] Figure 11 The example block diagram of a fractional PLL including a fractional frequency synthesizer according to an example embodiment of the present disclosure is illustrated. Detailed Description

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings, in which some, but not all embodiments of the invention of the present disclosure are shown. In fact, the embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numerals always refer to like elements.

[0037] Various example embodiments address technical problems associated with generating an accurate fractional frequency signal based on a reference signal. As will be understood by those skilled in the art in the field of the present disclosure, there are many example scenarios in which it may be necessary to generate a fractional frequency signal based on a provided reference signal.

[0038] For example, many modern electronic devices utilize a phase-locked loop (PLL) to perform various operations of the electronic device. A PLL is a control system that generates an output signal having a phase related to the phase of an input signal. A PLL can be used to generate a signal having a determined frequency, stabilize a signal, modulate or demodulate a signal, filter or recover a signal from a noisy communication channel, etc. A PLL can take the form of an integer PLL or a fractional PLL.

[0039] Generally speaking, an integer PLL is a PLL that generates an output signal as an integer multiple of the input frequency. For example, if the frequency of the reference signal provided to the PLL is F ref , and the output frequency of the PLL is F out , then the ratio of the output frequency to the reference frequency (F out / F ref ) is an integer. On the other hand, a fractional PLL can be used to generate an output frequency at non-integer intervals based on the reference frequency (e.g., F out / F ref is not an integer). A fractional PLL is capable of generating an output signal with a smaller step size (e.g., higher resolution). A fractional PLL can generate an output signal that serves as a clock signal for system logic, providing timing for data converters and radio frequency systems, as well as other applications.

[0040] Some previous examples have used the form of alternating division factors to obtain a fractional frequency signal output. For example, by alternately dividing by 10 and 11, an overall fractional frequency of approximately 10.5 can be obtained. With alternating division factors, an alternating division fractional PLL can effectively obtain a fractional output frequency. However, the alternating factor in an alternating division fractional PLL may have drawbacks. By the alternating factor in an alternating division fractional PLL, the frequency of the output signal may experience jitter due to a slight variation of the output signal at each clock edge. Jitter is the variation of the clock edge over time compared to an ideal clock edge.

[0041] At a frequency F idealIn a perfect clock that oscillates, the clock will assert precisely at each time t edge =(1 / F ideal )*n, where n is an integer. However, real signals may not be perfect, especially when generating fractional frequency signals. Therefore, there will be an error in the precision of the assertion at the clock edge. The error may be caused by noise, alternating division factors, or other variables. In fact, the real edge time will be t real =(1 / F ideal )*n + Δ(n), where Δ(n) is the time error for each cycle. The Δ(n) or time error in the clock edge assertion is jitter. Since jitter is a signal with a measurable value over time, some parameters of jitter (such as peak-to-peak variation (p2p)) can be calculated. For example, the p2p variation of jitter can be calculated as:

[0042] p2p(Δ(n)) = max(Δ(n)) - min(Δ(n))

[0043] Similarly, the root mean square (RMS) of jitter can be calculated as:

[0044]

[0045] Generally, a PLL is a loop system that uses a phase detector module to drive a voltage-controlled oscillator (VCO) configured to generate an output signal (e.g., a fractional frequency signal) with a desired frequency. In the absence of any noise, the clock edges of the reference signal provided to the PLL can be perfectly aligned with the clock edges of the fractional frequency feedback signal generated by the PLL. Therefore, the phase detector module will not adjust the voltage provided to the VCO. The frequency of the VCO will be constant, and all edges of the output signal will be perfectly aligned with the ideal clock output. In this case, the jitter of the fractional frequency signal is 0.

[0046] However, in practice, the fractional frequency feedback signal is not perfectly aligned with the edges of the reference signal. In this case, the phase detector module determines the output voltage based on the edge timing difference (e.g., phase difference) between the fractional frequency feedback signal and the reference signal. The output voltage will be transmitted to the VCO such that the VCO increases or decreases the frequency of the fractional frequency signal. The change in the frequency of the fractional frequency signal (even when reduced by the loop filter) means that the edge timing of the fractional frequency signal will change from cycle to cycle, resulting in jitter.

[0047] The problem of jitter in an alternating division fractional PLL can be particularly problematic. Therefore, there is a need for a fractional PLL configured to generate a fractional frequency signal based on a reference signal while minimizing the amount of jitter.

[0048] Various example embodiments of the present disclosure provide a fractional frequency synthesizer that utilizes a multi-phase clock vector and a multi-phase divider circuitry. The multi-phase clock vector includes a plurality of clock signals, and the multi-phase divider circuitry is configured to determine a selected clock signal of the multi-phase clock vector based on a toggle value of a reference accumulator count to generate a fractional output signal based on a reference frequency of a reference signal received by the fractional frequency synthesizer. The multi-phase clock vector and the multi-phase divider circuitry enable generation of a fractional frequency signal based on the reference signal, the fractional frequency signal having a fractional frequency relative to the reference signal and having reduced peak-to-peak and RMS jitter.

[0049] In some embodiments, a voltage-controlled ring oscillator may be used to generate the multi-phase clock vector based on the reference signal. The multi-phase clock vector may include a plurality of clock signals, each clock signal having a frequency equal to the frequency of the fractional frequency signal. However, the voltage-controlled ring oscillator may be configured to generate a plurality of clock signals, wherein each clock signal of the multi-phase clock vector is offset from an adjacent clock signal by a phase offset. In some embodiments, the phase offset between each successive clock signal of the plurality of clock signals may be equal.

[0050] The multi-phase divider circuitry may also be provided. Generally, the multi-phase divider circuitry may be configured with an accumulator that is configured to increment a count including the least significant bit of a counter width by a step value. The counter width and the step value may partially determine the fractional frequency of the fractional frequency signal generated by the multi-phase clock generator. Additionally, the multi-phase divider circuitry may be configured to detect a toggle event and a toggle value associated with the toggle event. The toggle value may be received by a phase calculation module that is configured to determine a selected clock signal from the plurality of clock signals to closely align with a clock event of a desired fractional frequency signal.

[0051] Due to the example embodiments described herein and in some examples, the jitter of the fractional frequency signal generated by the fractional frequency synthesizer may be greatly reduced. Additionally, using the concepts described in the present disclosure, high-precision fractional frequency signals may be generated using cost- and area-efficient components.

[0052] Now referring to Figure 1 , a block diagram of an example fractional frequency synthesizer 100 is provided. As shown in Figure 1As depicted in, example fractional frequency synthesizer 100 includes a multi-phase divider circuit device 102 configured to receive a multi-phase clock vector 108 including a plurality of clock signals generated by a multi-phase clock generator 104. The multi-phase clock generator 104 is configured to generate the multi-phase clock vector 108 based at least in part on a difference signal 116 corresponding to a phase difference and / or a frequency difference between the fractional frequency feedback signal 112 and the reference signal 106, the fractional frequency feedback signal 112 being generated by the multi-phase divider circuit device 102. The multi-phase divider circuit device 102 is further configured to determine a selected clock signal from the multi-phase clock vector 108 such that a fractional frequency signal 110 is generated, the fractional frequency signal 110 exhibiting a fractional frequency corresponding to the reference frequency of the reference signal 106.

[0053] As depicted in Figure 1 example fractional frequency synthesizer 100 includes a multi-phase clock generator 104. The multi-phase clock generator 104 is any circuit device including hardware and / or software configured to receive a difference signal 116 corresponding to a phase difference and / or a frequency difference between the reference signal 106 and the fractional frequency feedback signal 112 and generate a multi-phase clock vector 108 including a plurality of clock signals, each of the plurality of clock signals oscillating at a fractional frequency of the reference frequency but phase-shifted from other clock signals.

[0054] In some embodiments, the phase shift of each of the subsequent signals including the multi-phase clock vector 108 generated by the multi-phase clock generator 104 may be equal. For example, the second clock signal in the multi-phase clock vector 108 may be offset from the first clock signal by radians, the third clock signal in the multi-phase clock vector 108 may be offset from the first clock signal by radians, the fourth clock signal in the multi-phase clock vector 108 may be offset from the first clock signal by π radians, the fifth clock signal in the multi-phase clock vector 108 may be offset from the first clock vector by radians, and so on.

[0055] Furthermore, in some embodiments, the clock signals including the multi-phase clock vector 108 generated by the multi-phase clock generator 104 may be equally spaced across the period of the first clock signal. For example, in a case where the first clock signal oscillates with a period T and the multi-phase clock generator 104 is configured to generate a multi-phase clock vector 108 including ten clock signals, the multi-phase clock generator 104 may be configured to generate subsequent clock signals offset by 1 / 10 of the period of the first clock signal, in other words:

[0056]

[0057] where T is the clock period of the reference signal 106, n is the nth clock signal in the multi-phase clock vector 108, clock_vector size is the number of clock signals in the multi-phase clock vector 108, and is the phase offset of the nth clock signal in the multi-phase clock vector 108 relative to the first clock signal.

[0058] Now referring to Figure 2 , an example voltage-controlled ring oscillator 220 is provided. In some embodiments, the multi-phase clock generator 104 may include a voltage-controlled ring oscillator (e.g., the voltage-controlled ring oscillator 220 depicted in Figure 2 ). As depicted in Figure 2 , the example voltage-controlled ring oscillator 220 includes a plurality of delay elements 226a through 226n that are configured to generate the fractional frequency signal 210 based at least in part on the difference signal 216 and feedback of the fractional frequency signal 210. As further depicted in Figure 2 , the multi-phase clock vector 208 may include a plurality of clock signals 208a through 208z extracted from respective stages of the voltage-controlled ring oscillator 220, each clock signal 208a through 208z exhibiting a phase offset from an adjacent clock signal 208a through 208z.

[0059] As depicted in Figure 2 , the example voltage-controlled ring oscillator 220 may include a plurality of delay elements 226a through 226n. The delay elements 226a through 226n may be any electronic component configured to receive an input signal and generate an output signal having a delay corresponding to the difference signal 216. In some embodiments, the delay elements 226a through 226n may include an inverter or logic NOT gate configured to output an inverted signal corresponding to the received input signal. Thus, in the case where an odd number (e.g., 3, 5, 7, 9) of delay elements 226a through 226n comprise the voltage-controlled ring oscillator 220, the fractional frequency signal 210 oscillates between logic 1 and logic 0. Thus, the fractional frequency signal 210 oscillates between logic 0 and logic 1 at a fractional frequency.

[0060] As depicted in Figure 2As further depicted in, the delay of each of delay elements 226a through 226n varies with respect to the differential signal 216. For example, as the amplitude of the differential signal 216 increases, the delay of each of delay elements 226a through 226n can increase; and similarly, as the amplitude of the differential signal 216 decreases, the delay of each of delay elements 226a through 226n can decrease. Thus, the frequency of oscillation of the fractional frequency signal 210 can be adjusted based on the differential signal 216. As described herein, in the case where the differential signal 216 is generated by comparing a reference signal (e.g., reference signal 106) with a fractional frequency feedback signal (e.g., fractional frequency feedback signal 112), the fractional frequency signal 210 can converge to the fractional frequency of the reference signal as determined by a multi-phase divider circuit arrangement (e.g., multi-phase divider circuit arrangement 102).

[0061] As in Figure 2 As further depicted in, the voltage-controlled ring oscillator 220 is configured to output a multi-phase clock vector 208 including a plurality of clock signals 208a through 208z. As in Figure 2 As depicted in, a plurality of clock signals 208a through 208z can be extracted between respective ones of the delay elements 226a through 226n. Thus, the plurality of clock signals 208a through 208z can each oscillate at the same frequency, but each is phase-shifted from an adjacent signal. In the case where the delay elements 226a through 226n are equivalent and are configured to receive an equivalent voltage (e.g., differential signal 216), the delay of each delay element can be equivalent. Further, in the case where the delay elements 226a through 226n are equivalent and are configured to receive an equivalent voltage (e.g., differential signal 216), and in the case where an equal number of delay elements separate the extraction points of each successive clock signal among the plurality of clock signals 208a through 208z, the plurality of clock signals 208a through 208z can be equally spaced across the period of the fractional frequency signal 210.

[0062] In addition, in some embodiments, the voltage-controlled ring oscillator 220 may include a plurality of inverters 228a to 228n configured to invert a plurality of clock signals 208a, 208i, 208c, 208n, 208z to generate additional clock signals 208h, 208b, 208j, 208y, 208m. By inverting the clock signals 208a, 208i, 208c, 208n, 208z extracted between the delay elements 226a to 226n of the voltage-controlled ring oscillator 220, the clock vector 208 includes rising (or falling) edges that are equally spaced within a clock period. By generating a clock vector 208 that includes rising (or falling) edges that are equally spaced within a clock period, the connected electronic components (e.g., the multi-phase divider circuit device 102) can be configured to detect only the rising (or falling) clock edges instead of being configured to detect both rising and falling edges to obtain equally spaced clock edges. In addition, a smaller number of delay elements 226a - 226n can be used to achieve the number of equally spaced clocks within a clock period.

[0063] In some embodiments, the plurality of clock signals 208a to 208n may be transmitted to a multi-phase divider circuit device (e.g., the multi-phase divider circuit device 102) as a multi-phase clock vector (e.g., the multi-phase clock vector 108).

[0064] Now referring Figure 3 , Figure 3 is an example signal diagram 300 depicting a plurality of clock signals 308a to 308j each offset by an equivalent phase offset. As further depicted in Figure 3 , a set of 10 clock signals 308a to 308j is equally spaced across the period of the plurality of clock signals 308a to 308j. As described with respect to Figure 1 , the phase offset between successive clocks of an equally spaced multi-phase clock vector can be determined by the following equation

[0065]

[0066] where T is the period of the plurality of clock signals 308a to 308j, and clock_vector size is the number of clock signals among the plurality of clock signals 308a to 308j. Thus, as depicted in Figure 3 , the phase offset of each successive clock signal is 1 / 10 of the period (T) of the plurality of clock signals 308a to 308j, or π / 5 radians.

[0067] Returning to Figure 1, the exemplary fractional frequency synthesizer 100 further includes a multi-phase divider circuit arrangement 102. The multi-phase divider circuit arrangement 102 is any circuit arrangement including hardware and / or software configured to receive a multi-phase clock vector 108 and select a selected clock signal from among a plurality of clock signals included in the multi-phase clock vector 108 such that a fractional frequency feedback signal 112 is generated having a frequency and phase offset substantially equivalent to the reference signal 106. Figure 4 Depicts a non-limiting example of the multi-phase divider circuit arrangement 102 in accordance with the present disclosure.

[0068] Now referring to Figure 4 , an exemplary multi-phase divider circuit arrangement 402 is provided. As depicted in Figure 4 , the exemplary multi-phase divider circuit arrangement 402 includes an accumulator 440 configured to receive a fractional clock 439 and a step value 446 and generate a count value 447. The count value 447 is monitored by a toggle detector circuit arrangement 442 configured to detect a toggle event and generate a toggle value 437. As further depicted in Figure 4 , a phase calculation circuit arrangement 443 is configured to receive the toggle value 437 and determine a clock selection signal 450 corresponding to a clock signal in the multi-phase clock vector 408. A clock selection circuit arrangement 444 is configured to select a clock signal from the multi-phase clock vector 408 based on the clock selection signal 450 and transmit the selected clock signal 449 to a clock output circuit arrangement 445. As Figure 4 further depicted, the clock output circuit arrangement 445 is configured to receive a counter oscillation signal 448 from a comparator circuit arrangement 441 based on the count value 447. The clock output circuit arrangement 445 generates a fractional frequency feedback signal 412 based on the counter oscillation signal 448 and the selected clock signal 449.

[0069] As depicted in Figure 4 , the exemplary multi-phase divider circuit arrangement 402 includes an accumulator 440. The accumulator 440 is any circuit arrangement including hardware and / or software configured to increment a count value 447 by a step value 446 in accordance with an oscillation signal (e.g., fractional clock 439). The accumulator is configured to generate a count value 447 represented by the least significant bits of a counter (e.g., 5 bits, 7 bits, 16 bits, etc.). For example, the count value 447 may include 5 bits. In this case, the count value 447 may represent values from 0 (5’b00000) to 31 (5’b11111).

[0070] The accumulator 440 is also configured to increment the count value 447 based on an oscillation signal. The oscillation signal is any signal configured to oscillate between a high logic value and a low logic value, such as a clock. Thus, the count value 447 can be incremented in conjunction with an edge (e.g., rising edge, falling edge) of the oscillation signal. For example, the count value 447 can be incremented by one each time a rising edge of the oscillation signal is detected. In some embodiments, the oscillation signal can include a fractional clock 439 corresponding to a clock that oscillates at a fractional frequency relative to a reference clock (e.g., reference signal 106).

[0071] The accumulator 440 is also configured to increment the count value 447 based on a step value 446. The step value 446 determines the amount by which the count value 447 is incremented. For example, in the case where the step value is 3, the count value 447 can progress from 0 to 3, 6, 9, 12, etc. in coordination with the oscillation signal.

[0072] As further depicted in Figure 4 the example multi-phase divider circuit arrangement 402 includes a comparator circuit arrangement 441. The comparator circuit arrangement 441 is any circuit arrangement including hardware and / or software configured to receive the count value 447, compare the count value 447 with a fixed counter comparison value, and assert a counter oscillation signal 448 in the case where the count value 447 exceeds the fixed counter value. In some embodiments, the fixed counter comparison value can be equal to 2 n-1 , where n is the number of bits including the count value. In this case, the comparator circuit arrangement 441 is configured to essentially output the most significant bit of the counter. Thus, the counter oscillation signal is logic 0 during the first half of the counter cycle and logic 1 during the second half of the counter cycle. The counter oscillation signal 448 determines the logic value of the fractional frequency feedback signal 412 generated in coordination by the clock output circuit arrangement 445 and the selected clock signal 449.

[0073] The frequency of oscillation of the counter oscillation signal 448 is determined at least in part based on a predetermined step value 446, the number of counter bits representing the number of bits of the count value 447, and the frequency of the fractional clock 439. For example, in some embodiments, the frequency of the counter oscillation signal 448 can be determined by the following equation:

[0074]

[0075] where F CO is the frequency of the counter oscillation signal 448, step value is the step value 446, N is the number of bits including the count value 447, and F FC is the frequency of the fractional clock 439.

[0076] As Figure 4As further depicted in, example multi-phase divider circuit device 402 includes a flip detector circuit device 442. The flip detector circuit device 442 is any circuit device including hardware and / or software configured to detect a flip event (e.g., count value 447) of a counter and determine a flip value 437 associated with the flip event. In the case where the count value 447 increments during operation, the count value 447 may eventually exceed the maximum number representable by the number of bits including the count value. In this case, the count value 447 experiences a flip event, meaning the count returns to or passes 0 and begins incrementing from 0. For example, if the count value 447 includes 5 bits, it can represent values from 0 (5’b00000) to 31 (5’b11111). When the count value 447 is 31, incrementing the count value 447 by 1 causes the count value to return to 0. Similarly, any situation where the step value 446 is added to the count value 447 and the step value 446 exceeds the maximum value representable by the bits including the count value 447 when the count value 447 is incremented by the step value 446 triggers a flip event. Such an event can be detected by the flip detector circuit device 442.

[0077] In addition to detecting flip events, the flip detector circuit device 442 can also determine the flip value 437. The flip value 437 is the value by which the count value 447 exceeds the maximum value representable by the bits of the count value 447. For example, in the case where the count value 447 is 30, the maximum value representable by the bits of the count value 447 is 31, and the step value is 5, the flip value 437 is 4. The resulting increment will cause a count value 447 of 35; however, since the count value 447 can only represent numbers up to 31, 4 remains, and the flip value 437 is thus equal to 4.

[0078] As depicted in Figure 4 example multi-phase divider circuit device 402 includes a phase calculation circuit device 443. The phase calculation circuit device 443 is any circuit device including hardware and / or software configured to receive the flip value 437 and provide a clock selection signal 450 to a clock selection circuit device 444, where the clock selection signal 450 specifies the clock signal from the multi-phase clock phases 408 that most precisely aligns with an ideal signal oscillating at a desired fractional frequency.

[0079] As described herein, the flip detector circuit device 442 is configured to detect a flip event associated with the count value 447 based on a previous count value 447 and a step value 446. The flip value 437 is used to determine from the multi-phase clock vector 408 the clock signal that can be selected to compensate for the magnitude of the flip value 437. As described with respect to Figure 1 in some embodiments, the multi-phase clock vector 408 includes a phase offset across the period of a first clock in the multi-phase clock vector 408 Multiple clock signals at equal intervals. Clock signals at equal intervals using the period of the first clock in the multi-phase clock vector 408 can be used to select the clock signal in the sequence of clock signals that is most aligned with the flip event corresponding to the count value 447 for the desired fractional frequency.

[0080] For example, in some embodiments, the phase calculation circuitry 443 can determine the clock signal to be selected in the multi-phase clock vector 408 based on the following equation.

[0081]

[0082] where phase number is the number of phases to be selected, rollover value is the rollover value 437 determined by the rollover detector circuitry 442, step value is the step value 446 by which the count value 447 is incremented, and clock_vector size is the size of the multi-phase clock vector 408. In some embodiments, the phase numbers are assigned to the clock signals in decreasing order. For example, the first clock signal is assigned the phase number clock_vector size −1, the clock signal shifted by the phase offset is assigned the phase number clock_vector size −2, the clock signal shifted by the phase offset is assigned the phase number clock_vector size −3, and so on. Thus, in the case where the rollover value is 5, the step value is 7, and clock_vector size is 4, the phase number can be calculated as:

[0083]

[0084] In this case, the phase number can be rounded to the nearest clock signal phase, and the clock signal assigned the phase number 3 (e.g., the second phase in the multi-phase clock vector sequence) can be selected.

[0085] By selecting the phase number that exhibits the oscillation event (e.g., the rising clock edge) that is most aligned with the desired oscillation event, the amount of jitter in the fractional frequency signal (e.g., the fractional frequency signal 110) can be reduced. In particular, the peak-to-peak value and the RMS value of the jitter signal can be reduced.

[0086] As Figure 4Further depicted in, example polyphase divider circuit device 402 includes a clock selection circuit device 444. The clock selection circuit device 444 is any circuit device including hardware and / or software configured to transmit a selected clock signal 449 from a polyphase clock vector 408 based on a clock selection signal 450. In some embodiments, the clock selection circuit device 444 may include a multiplexer configured to select the selected clock signal 449 from the polyphase clock vector 408 based on the clock selection signal 450.

[0087] As further depicted in Figure 4 , example polyphase divider circuit device 402 includes a clock output circuit device 445. The clock output circuit device 445 is any circuit device including hardware and / or software configured to generate a fractional frequency feedback signal 412 based on the value of a counter oscillation signal 448 and to be timed according to the selected clock signal 449. For example, the fractional frequency feedback signal 412 may be configured to update in coordination with the selected clock signal 449 to a value provided by the counter oscillation signal 448. In some embodiments, the clock output circuit device 445 may include flip-flops, latches, or other similar circuit elements.

[0088] As depicted in Figure 4 , example polyphase divider circuit device 402 generates a fractional frequency feedback signal 412 based on a fractional clock 439. In some embodiments, the fractional frequency feedback signal 412 exhibits a fractional frequency when compared to the frequency of the fractional clock 439, in other words, F 412 / F 439 is not an integer. Thus, the fractional frequency feedback signal 412 may be configured as part of a feedback loop to align with a reference signal while the fractional clock 439 exhibits a non-integer frequency relative to the reference signal (e.g., reference signal 106).

[0089] Returning to Figure 1 , example fractional frequency synthesizer 100 further includes a comparison circuit device 114. The comparison circuit device 114 is any circuit device including hardware and / or software configured to receive two input signals (e.g., fractional frequency feedback signal 112, reference signal 106) and to generate a difference signal 116 based on the frequency difference and / or phase offset of the two input signals. When utilized as an input voltage to the polyphase clock generator 104, the difference signal 116 causes the polyphase clock generator 104 to generate a fractional frequency signal 110 such that the fractional frequency feedback signal 112 converges with the reference signal 106 in terms of frequency and phase offset.

[0090] Now referring to Figure 5 , an example embodiment of a polyphase divider circuit device 502 is provided. As depicted in Figure 5As depicted, an example embodiment of the multi-phase divider circuit device 502 includes an accumulator 540 that generates a count value 547 based on a step value 546 and a fractional clock 539. The multi-phase divider circuit device 502 further includes a comparator 541 configured to generate a counter oscillation signal 548 based on the count value 547. Also included is a toggle detector circuit device 542 configured to receive the count value 547 and generate a toggle value 537. The toggle value 537 is received by a phase calculation circuit device 543 configured to transmit a clock selection signal 550 to a clock selection multiplexer 552. A clock selection circuit device 544 transmits a selected clock signal 549 from a multi-phase clock vector 508 including clock signals 508a to 508n to a clock output circuit device 545. The clock output circuit device 545 generates a fractional frequency feedback signal 512 based at least in part on the counter oscillation signal 548 and the selected clock signal 549.

[0091] As further depicted in Figure 5 the accumulator 540 includes an adder 556 and a flip-flop 551. The adder 556 increments the count value 547 by the step value 546. The flip-flop 551 causes the increment in the count value 547 to coincide with the oscillation of the fractional clock 539. For example, in some embodiments, the count value 547 is incremented by the step value 546 with each rising clock edge of the fractional clock 539.

[0092] As further depicted in Figure 5 the comparator 541 includes an operational amplifier comparator 554. The operational amplifier comparator 554 compares the count value 547 with a fixed counter comparison value (e.g., 2 n-1 , where n is the number of bits including the count value 547), and generates the counter oscillation signal 548 based on the comparison. For example, by comparing with the value 2 n-1 , the counter oscillation signal 548 essentially represents the most significant bit of the count value 547. Thus, the counter oscillation signal 548 is logic 1 for the first half of the count value 547 and logic 0 for the second half of the count value 547.

[0093] As further depicted in Figure 5 the clock selection circuit device 544 of the example multi-phase divider circuit device 502 includes a clock selection multiplexer 552. The clock selection multiplexer 552 receives the clock selection signal 550 from the phase calculation circuit device 543 and transmits the clock signals 508a to 508n corresponding to the clock selection signal 550 as the selected clock signal to the clock output circuit device 545.

[0094] As further depicted in Figure 5As further depicted in, clock output circuit device 545 includes a flip-flop 555. By using the selected clock signal 549 as the clock to the flip-flop 555, the value of the counter oscillation signal 548 is output synchronously with the selected clock signal 549 as the fractional frequency feedback signal 512.

[0095] By selecting the selected clock signal 549 that exhibits the most alignment with the ideal oscillation event (e.g., the rising clock edge or the falling clock edge), the amount of jitter of the fractional frequency signal (e.g., fractional frequency signal 110) can be reduced. In particular, the peak-to-peak value and the RMS value of the jitter signal can be reduced.

[0096] Now referring to Figure 6 , an example signal diagram 600 is provided. Example signal diagram 600 depicts a plurality of clock signals 608a to 608j included in a multi-phase clock vector 608. As depicted in Figure 6 , each of the plurality of clock signals is equally offset over the period of the first clock signal (e.g., clock signal 608a). Thus, since the multi-phase clock vector 608 includes 10 clock signals 608a to 608j, each clock signal is offset by 1 / 10 of the clock period, or π / 5, from the previous clock signal 608a to 608j.

[0097] As further depicted in Figure 6 , the clock selection signal 650 can be determined by a phase calculation circuit device (e.g., phase calculation circuit device 443, phase calculation circuit device 543) to select the clock signal 608a to 608j that is most closely aligned with the reference signal 606. In some embodiments, the phases of the clock signals 608a to 608j can be assigned phase numbers. For example, 608a can be assigned phase number 0, 608b can be assigned phase number 1, 608c can be assigned phase number 2, 608d can be assigned phase number 3, and so on, until 608j is assigned phase number 9. In this embodiment, the clock selection signal 650 (e.g., clock selection signal 450, clock selection signal 550) corresponds to the phase offset within the multi-phase clock vector 608.

[0098] As further depicted in Figure 6 , the selected clock signals 608a to 608j based on the clock selection signal 650 change periodically to align with the reference signal 606. By utilizing the multi-phase clock vector 608 and selecting the phase of the multi-phase clock vector 608 that is most closely aligned with the ideal clock edge, a fractional frequency signal with minimum jitter can be generated.

[0099] Now referring to Figure 7 , an example accumulator count 700 is depicted. As depicted in Figure 7As depicted in, reference count 770 depicts an ideal count. The ideal count is the count value that is to be followed to obtain a desired fractional frequency. Depending on the magnitude of step value 746, the rollover of count value 747 may not align with the rollover point 772 of reference value 770. For example, as depicted in Figure 7 when count value 747 increments by step value 746, count value 747 increments through rollover point 772 with a certain rollover value 737. By detecting the rollover of count value 747 and determining rollover value 737, a clock signal of a multi-phase clock vector can be selected to align with rollover point 772.

[0100] Now referring to Figure 8A , an example phase selection diagram 800a is provided. As depicted in Figure 8A count value 847 increments by step value 846a. Count value 847a is configured to roll over at value 2 N where N is the number of bits of count value 847a. The trigger rollover point 872a represents the exact time at which the fractional frequency feedback signal should be asserted to generate a fractional frequency feedback signal with a desired frequency. However, due to step value 846a, trigger rollover point 872a may not align precisely with the increment of count value 847a. Instead, a detection rollover event 884a is not detected until count value 847a increments by step value 846a the next time. Detection rollover event 884a occurs at a delay 882a after trigger rollover point 872a. Delay 882a represents the time elapsed after trigger rollover point 872a at which detection rollover event 884a occurs.

[0101] Delay 882a can be derived from rollover value 837a. Rollover value 837a represents the count value 847a after count value 847a has been rolled over. Thus, rollover value 837a also represents the time elapsed after trigger rollover point 872a at which detection rollover event 884a occurs. In some embodiments, detection rollover event 884a can be detected before incrementing count value 847a. Additionally, the phase of the multi-phase clock vector closest to trigger rollover point 872a can be determined. For example, as described in Figure 4 the phase number of the clock signal closest to trigger rollover point 872a can be detected by the following equation:

[0102]

[0103] where rollover value is rollover value 837a, step value is step value 846a, and clock_vector size is the size of the multi-phase clock vector.

[0104] By detecting a detection flip event 884a before an incrementing count value 874a and determining the phase number of the clock signal closest to the trigger flip point 872a, the oscillation event of the reference signal can be made more precisely consistent with the trigger flip point 872a.

[0105] By selecting a selected clock signal that is most precisely aligned with the trigger flip point 872a, the amount of jitter in a fractional frequency signal (e.g., fractional frequency signal 110) can be reduced. In particular, the peak-to-peak value and the RMS value of the jitter signal can be reduced.

[0106] Now referring to Figure 8B , an example phase selection diagram 800b including a plurality of consecutive trigger flip points 872b_1, 872b_2 is provided. As depicted in Figure 8B , the count value 847b is incremented by a step value 846b. The count value 847b is configured to flip at a value of 2 N where N is the number of bits including the count value 847a.

[0107] As depicted in Figure 8B , a detection flip event 884b_1 is detected and a flip value 837b_1 is determined. Based on the determined flip value 837b_1, a clock signal having a phase number of 3 of a multi-phase clock vector is selected. The clock signal having a phase number of 3 experiences a clock signal event closest to the trigger flip point 872b_1 in the example depicted in Figure 8B . By determining the phase number of the clock signal closest to the trigger flip point 872b_1, the clock signal is selected such that the selected clock signal exhibits a clock signal event closest to the desired oscillation event of the generated reference signal.

[0108] Similarly, a subsequent detection flip event 884b_2 is detected and a flip value 837b_2 is determined. Based on the determined flip value 837b_2, a clock signal having a phase number of 6 of a multi-phase clock vector is selected. Since the clock signal having a phase number of 6 experiences a clock signal event closest to the trigger flip point 872b_2, a reference signal having a desired oscillation frequency is generated.

[0109] In some embodiments, a fractional clock (e.g., fractional clock 439, fractional clock 539) may remain static during operation. For example, the fractional clock may hold the first clock signal in a multi-phase clock vector. In such an embodiment, subsequent clock selection determination may determine the number of phases of the selected clock in an absolutely deterministic manner. For example, by determining the static phase number of the clock with the oscillation event closest to the trigger flip point. In some embodiments, the fractional clock may be updated to match the phase of the selected clock. In such an embodiment, the number of phases may be determined as an offset from the currently selected number of phases. For example, in the case where the clock signal associated with the static phase number 5 is selected, the fractional clock is updated to the clock signal associated with the static phase number 5, and the phase number determination may indicate the number of phases relative to the static phase number 5. For example, a calculation resulting in a phase number of 3 may indicate the selection of a clock signal associated with a phase number 3 that is less than the current phase number (e.g., 5). Thus, a clock signal associated with the phase number 2 may be selected.

[0110] As further depicted in Figure 8A there may be a quantization error 886b. The quantization error 886b represents the offset between the phase of the selected clock signal (e.g., phase 6) and the trigger flip point (e.g., trigger flip point 872b_2). As described herein, the calculation of the phase number associated with the clock signal having the oscillation point closest to the trigger flip point may result in a decimal number. However, only an integer number of phases can be selected. Thus, various rounding techniques may be used to select the number of phases. The difference between the selected phase number and the trigger flip point is the quantization error 886b. In some cases, the quantization error 886b may accumulate during operation. This accumulation of the quantization error 886b may cause a shift in the output edge of the generated fractional frequency feedback signal. To avoid such errors, in some embodiments, the quantization error 886b may be accumulated and stored. The accumulated quantization error 886b may be used in the determination of the phase number of the reference clock.

[0111] Now refer to Figure 9, an example flowchart of process 900 for generating a fractional frequency feedback signal (e.g., fractional frequency feedback signals 112, 412, 512) is provided. At block 902, a fractional frequency synthesizer (e.g., fractional frequency synthesizer 100) receives a clock vector (e.g., multi-phase clock vectors 108, 208, 308, 408, 508, 608) from a multi-phase clock generator (e.g., multi-phase clock generator 104) at a multi-phase divider circuitry (e.g., multi-phase divider circuitry 102, 404, 502). The clock vector includes a plurality of clock signals, each clock signal oscillating at a fractional frequency based at least in part on a reference frequency of a reference signal, and each clock signal being offset by a phase shift. As described herein, a multi-phase generator may generate a plurality of clocks, each clock oscillating at an oscillating frequency and being offset by a phase shift. In some embodiments, the plurality of clocks may be equally offset relative to a first clock of the plurality of clocks across a period of the first clock. For example, in the case where the clock vector includes 10 clocks, the second clock may be offset by π / 5 relative to the first clock, the third clock may be offset by 2π / 5 relative to the first clock, the fourth clock may be offset by 3π / 5 relative to the first clock, and so on.

[0112] At block 904, the fractional frequency synthesizer detects a rollover event (e.g., detecting rollover event 884a) of an accumulator (e.g., accumulators 440, 540) configured to increment count according to a fractional frequency (e.g., count values 447, 547, 747, 847a, 847b) at the multi-phase divider circuitry. As described herein, the multi-phase divider circuitry may include an accumulator. The accumulator may be configured to increment a count value according to a fractional frequency. The count value of the accumulator may be configured with a least significant bit of a counter bit width and may be further configured to increment according to a step value. The count value may increment by the step value, and each time the count value rolls over, a rising edge of the generated fractional frequency feedback signal may be asserted. The step value and the counter bit width thus determine the frequency at which the counter rolls over and the frequencies of the fractional frequency signal (e.g., fractional frequency signal 110) and the fractional frequency feedback signal.

[0113] At block 906, the fractional frequency synthesizer determines a rollover value (e.g., rollover values 737, 837a, 837b) corresponding to the count at the rollover event. The rollover value is equal to the count value at the time of the rollover event corresponding to the accumulator count value. From the rollover value, a delay of the rollover event from an ideal trigger rollover point can be inferred.

[0114] At block 908, a fractional frequency synthesizer selects a selected clock signal (e.g., selected clock signals 449, 549) from a plurality of clock signals based on a toggle value. As described herein, the number of phases associated with the selected clock signal can be determined based on the ratio of the toggle value to a step value, and also based on the number of clock signals in a multi-phase clock vector. In some embodiments, the determined number of phases can represent the absolute phase number of a clock signal among the plurality of clock signals. In some embodiments, the number of phases can represent an offset of a fractional clock counted from an operation accumulator. Additionally, in some embodiments, a quantization error based on rounding to the nearest number of phases can be accumulated and stored. The accumulated quantization error can be used to adjust clock selection in subsequent toggle events.

[0115] By selecting the selected clock signal that most precisely aligns with the trigger toggle point, the amount of jitter in the fractional frequency signal (e.g., fractional frequency signal 110) can be reduced. In particular, the peak-to-peak value and the RMS value of the jitter signal can be reduced.

[0116] At block 910, the fractional frequency synthesizer generates a fractional frequency feedback signal based at least in part on the selected clock signal. As described herein, the fractional frequency feedback signal can be generated to align with an input reference signal having a reference frequency. Aligning the fractional frequency feedback signal with the reference signal enables the generation of a fractional frequency signal that exhibits a non-integer frequency relative to the reference frequency.

[0117] Now referring Figure 10 , an example flowchart is provided that illustrates generating a fractional frequency signal that exhibits a non-integer frequency relative to a reference frequency at a fractional frequency synthesizer. At block 1002, a clock edge of a fractional clock is received at an accumulator that stores a count value incremented by a step value at a clock edge. The clock edge can correspond to a rising clock edge, a falling clock edge, or both. In some embodiments, the fractional clock can correspond to a first clock signal among a plurality of clock signals oscillating at a fractional frequency. In some embodiments, the fractional clock can correspond to a selected clock signal oscillating at a fractional frequency from among a plurality of clock signals.

[0118] At the clock edge, one or more upcoming counter values are calculated by adding the step value to the current count value. In some embodiments, one or more step values can be added to the current count value to determine the upcoming count value. For example, the next count value can be determined by adding the step value to the current count value. The second next count value can be determined by adding the step value to the next count value.

[0119] At block 1004, the fractional frequency synthesizer checks for an upcoming rollover event of the count value. The rollover event can be detected by comparing the next count value and / or the second next count value with the maximum count value (e.g., 2 N , where N is the number of bits in the count value). In the case where a rollover is detected, process 1000 continues at block 1006. In the case where no rollover is detected, process 1000 returns to block 1002 to wait for the next clock edge.

[0120] At block 1006, the fractional frequency synthesizer calculates the rollover value and the number of phases of the rollover. The rollover value can be calculated by the following equation:

[0121] rollover value=next count value (mod 2 N )

[0122] where N is the number of bits in the count value. The number of phases can be calculated by the following equation:

[0123]

[0124] where step value is the step value provided to the accumulator, and clock_vector size is the size of the multi-phase clock vector.

[0125] At block 1008, the fractional frequency synthesizer may need to calculate the phase offset to the number of phases based on the clock used to operate the accumulator. In the case where the clock provided to the accumulator is static (such as the first clock in the multi-phase clock vector), no adjustment is required. However, in the case where the clock is updated based on a selected clock signal, the number of phases can be adjusted to the offset to the number of phases of the selected clock signal.

[0126] At block 1010, the fractional frequency synthesizer selects the number of phases and determines the quantization error associated with the number of phases. As described herein, in some embodiments, the number of phases determined in blocks 1006 / 1008 can correspond to a non-integer value. However, an integer value must be determined when selecting the number of phases. In some cases, the selected phase can be determined by rounding up, rounding down, truncating, or other similar operations. The quantization error is any error introduced by selecting an integer number of phases. For example, in the case where the ideal trigger rollover point is determined to be at 2.7 phases before the next clock event, the clock signal 3 phases before the next clock event can be selected by rounding 2.7 up to 3. In this case, the quantization error is 0.3, representing the difference between the selected clock phase and the calculated clock phase. In some embodiments, the quantization error can be stored and / or accumulated for use in future clock phase selections.

[0127] At block 1012, the fractional frequency synthesizer determines whether the number of phases selected in block 1010 is negative. In some cases, particularly when determining a phase offset based on a previous flip value, the determined number of phases may be negative. In such cases, process 1000 continues at step 1014 where a positive equivalent amount is determined. Since phases are equally spaced across a cycle, a negative number of phases simply corresponds to a different number of phases on a previous or subsequent clock cycle. For example, during the next clock cycle, the number of phases -1 may correspond to the number of phases 8 (in the presence of 8 clock signals). The number of phases can be adjusted to accommodate such cases.

[0128] If the number of phases selected at block 1010 is positive, the number of phases remains unchanged at block 1016.

[0129] At block 1018, any phase offset to be considered in the next count flip is determined and stored.

[0130] At block 1020, the count value is updated based on the overflow and the selected clock. For example, in some embodiments, the count value may be set to 0 when a new phase clock is selected.

[0131] Now referring Figure 11 , an example fractional phase - locked loop (PLL) including a fractional frequency synthesizer is provided. As depicted in Figure 11 , the example fractional PLL includes a multi - phase divider circuit 1102. The multi - phase divider circuit 1102 receives a multi - phase clock vector 1108 and selects a clock signal from among the plurality of clock signals included in the multi - phase clock vector 1108 to generate a fractional frequency feedback signal 1112 that substantially matches the frequency and phase of a reference signal 1106.

[0132] As depicted in Figure 11 , the fractional frequency feedback signal 1112 is compared with the reference signal 1106 at a phase detector module 1132. The phase detector module 1132 is any circuit of hardware and / or software that includes means configured to receive two input signals (e.g., the fractional frequency feedback signal 1112 and the reference signal 1106) and output a phase difference signal 1190 representative of the difference in phase and / or frequency of the two input signals.

[0133] Example fractional PLL 1100 also includes a charge pump circuit device 1134. The charge pump circuit device 1134 is any circuit device including hardware and / or software configured to convert the phase difference signal 1190 into a signal compatible with the multi-phase clock generator circuit device 1104. The charge pump circuit device 1134 can increase the voltage, convert the voltage, or perform any other operation necessary to convert the phase difference signal 1190.

[0134] Example fractional PLL 1100 also includes a loop filter circuit device 1136. The loop filter circuit device 1136 is any circuit device including hardware and / or software configured to receive and filter the charge difference signal 1192 to generate a filtered difference signal 1116 (e.g., difference signals 116, 216) to be transmitted to the multi-phase clock generator circuit device 1104. The loop filter circuit device 1136 can remove high-frequency noise or perform other similar filtering operations to generate the charge difference signal 1192.

[0135] As further described in Figure 11 Example fractional PLL 1100 includes a multi-phase clock generator circuit device 1104. As described herein, the multi-phase clock generator circuit device 1104 is configured to generate a multi-phase clock vector 1108 including a plurality of clock signals, each clock signal being offset from a first clock signal among the plurality of clock signals by a phase shift. Each of the clock signals included in the multi-phase clock vector 1108 exhibits an oscillation frequency that can be a non-integer multiple of a reference frequency that can be a reference signal. The fractional frequency signal 1110 can be generated at least in part based on the multi-phase clock vector 1108.

[0136] Although this specification has set forth some embodiments of the invention, the appended claims cover other embodiments that differ from the described embodiments of the invention in accordance with various modifications and improvements. For example, those skilled in the art will understand that such principles can be applied to any electronic device using a fractional phase-locked loop. For example, radio frequency transmitters, radio frequency receivers, frequency modulation / demodulation, frequency shift keying, signal conditioning, clock synchronization, frequency synthesis, etc.

[0137] Within the appended claims, unless the specific terms "means for..." or "step for..." are used in a given claim, the claim is not intended to be interpreted under 35 U.S.C. 112, paragraph 6.

[0138] The use of broader terms such as "comprising", "including", and "having" should be understood as providing support for narrower terms such as "consisting of", "consisting essentially of", and "substantially consisting of". The use of terms such as "optional", "may", "might", "possibly", etc. for any element of an embodiment means that the element is not required or, alternatively, that the element is required, and both alternative scenarios are within the scope of the embodiment. Additionally, the reference to examples is used for illustrative purposes only and is not intended to be exclusive.

Claims

1. A fractional frequency synthesizer, comprising: a multi-phase clock generator configured to generate a clock vector based on a reference signal, the reference signal having a reference frequency, wherein the clock vector comprises a plurality of clock signals, each clock signal oscillating according to a fractional frequency relative to the reference frequency, and wherein each clock signal is offset by a phase offset; as well as a multi-phase divider circuit arrangement electrically connected to the multi-phase clock generator and configured to receive the clock vector and select a selected clock signal from the plurality of clock signals to generate a fractional frequency feedback signal, the multi-phase divider circuit arrangement comprising: an accumulator configured to count up according to the fractional frequency; and a rollover detector configured to determine a rollover value associated with a rollover event of the count on the accumulator; wherein the selected clock signal is selected based on the toggle value, and Wherein the fractional frequency feedback signal is generated based at least in part on the selected clock signal.

2. The fractional frequency synthesizer of claim 1, wherein the multi-phase clock generator comprises a voltage controlled ring oscillator.

3. The fractional frequency synthesizer of claim 2, wherein the voltage controlled ring oscillator comprises: a delay line comprising a plurality of delay elements, The plurality of clock signals including the clock vector are transmitted from a plurality of contact points along the delay line.

4. The fractional frequency synthesizer of claim 1 , wherein the accumulator comprises: A counter, the counter comprising a counter digit number, Wherein the counter is configured to increment the count by a step value.

5. The fractional frequency synthesizer of claim 4, wherein the fractional frequencies of the plurality of clock signals are determined based at least in part on the number of counter bits and the step value.

6. The fractional frequency synthesizer of claim 4, wherein the rollover value represents the count after the rollover event of the accumulator.

7. The fractional frequency synthesizer of claim 6, wherein the selected clock signal is determined based at least in part on a comparison of the rollover value to the step size value.

8. The fractional frequency synthesizer of claim 7, wherein the comparison of the rollover value to the step size value is determined using a division lookup table.

9. The fractional frequency synthesizer of claim 7 , wherein a frequency offset is determined between a clock edge of the selected clock signal and an ideal clock edge of the fractional frequency signal, and wherein a second selected clock signal is determined based at least in part on the frequency offset, the second selected clock signal corresponding to a next accumulator rollover event.

10. The fractional frequency synthesizer of claim 1, wherein the selected clock signal is asserted prior to the rollover event of the accumulator.

11. The fractional frequency synthesizer of claim 1, wherein the phase offset between each subsequent clock signal of the plurality of clock signals comprising the clock vector is equal.

12. The fractional frequency synthesizer of claim 1, wherein the clock vector comprises at least four clock signals.

13. A method for generating a fractional frequency feedback signal, comprising: receiving, at a multi-phase divider circuit arrangement, a clock vector from a multi-phase clock generator, the clock vector comprising a plurality of clock signals, each clock signal oscillating according to a fractional frequency based at least in part on a reference frequency of a reference signal, and each clock signal offset by a phase offset; detecting, at the multi-phase divider circuit arrangement, a rollover event of an accumulator, the accumulator being configured to count up according to the fractional frequency; determining a rollover value corresponding to the count at the rollover event; selecting a selected clock signal from the plurality of clock signals based on the flip value; as well as The fractional frequency feedback signal is generated based at least in part on the selected clock signal.

14. The method of claim 13, wherein the accumulator comprises: A counter, the counter comprising a counter digit number, Wherein the counter is configured to increment the count by a step value based at least in part on the reference frequency.

15. The method of claim 14, wherein the fractional frequencies of the plurality of clock signals are determined based at least in part on the number of counter bits and the step value. The method of claim 14 , wherein the rollover value represents the count after the rollover event of the accumulator.

17. The method according to claim 14, further comprising: Determining a relationship between the flip value and the step value; as well as The selected clock signal is selected based at least in part on the relationship.

18. The method according to claim 13, further comprising: determining a phase difference between a clock edge of the selected clock signal and an ideal clock edge of the reference signal; as well as A second selected clock signal is determined based at least in part on the frequency difference, the second selected clock signal corresponding to a next accumulator rollover event.

19. The method of claim 13, wherein the phase offset between each subsequent clock signal of the plurality of clock signals comprising the clock vector is equal.

20. A fractional phase-locked loop, comprising: a phase detector module configured to generate a difference signal corresponding to a difference between a phase of the reference signal and a phase of the fractional frequency feedback signal; a loop filter configured to generate a filtered difference signal based at least in part on the difference signal; as well as A fractional frequency synthesizer, the fractional frequency synthesizer being configured to generate the fractional frequency feedback signal, the fractional frequency synthesizer comprising: a multi-phase clock generator configured to generate a clock vector based on the filtered difference signal, the clock vector comprising a plurality of clock signals, each clock signal oscillating according to a fractional frequency based at least in part on a reference frequency of the reference signal, and each clock signal offset by a phase offset; and a multi-phase divider circuit arrangement electrically connected to the multi-phase clock generator and configured to receive the clock vector and select a selected clock signal from the clock vector to generate the fractional frequency feedback signal, the multi-phase divider circuit arrangement comprising: an accumulator configured to count up according to the fractional frequency; and a rollover detector configured to detect a rollover value associated with a rollover event of the accumulator; wherein the selected clock signal is selected based on the toggle value, and Wherein the fractional frequency feedback signal is generated based at least in part on the selected clock signal.

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