State control method, state machine and state machine of in-memory computing circuit

Abstract

The invention relates to a state control method, a state machine and a state machine of an in-memory computing circuit. The method comprises the following steps: acquiring the time delay of the current state of the in-memory computing circuit from the time delays of a plurality of pre-configured states; if an input request and input data are received, the next state is determined according to the current state and the input data after the time delay of the current state, and the input request is used for indicating the switching state of the in-memory computing circuit; and controlling the in-memory computing circuit to switch the state based on the next state so as to process the input data.

Description

Technical Field

[0001] The present disclosure relates to the technical field of digital integrated circuits, and in particular to a state control method, state, and state machine of an in-memory computing circuit. Background Art

[0002] A large amount of data needs to be moved between the storage unit and the computing unit of the von Neumann architecture chip. This "storage wall" problem limits the energy efficiency and throughput of the chip. To solve the "storage wall" problem, people proposed an in-memory computing architecture, which designs the storage unit and the computing unit into an in-memory computing unit, thereby eliminating the need to move intermediate data, thereby eliminating the delay and power consumption caused by data movement, and greatly improving the chip energy efficiency.

[0003] The in-memory computing circuit requires a peripheral control circuit, such as a state machine, to control its state. However, in the related art, the peripheral control circuit of the in-memory computing circuit consumes high power, which limits the energy efficiency improvement of the in-memory computing system. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the embodiments of the present disclosure provide a state control method and state and state machine of an in-memory computing circuit to solve the defects in the related art.

[0005] According to a first aspect of an embodiment of the present disclosure, a state control method for an in-memory computing circuit is provided, the method comprising:

[0006] Obtaining the delay of the current state of the in-memory computing circuit from the delays of the pre-configured multiple states;

[0007] If an input request and input data are received, then after a delay of the current state, a next state is determined according to the current state and the input data, wherein the input request is used to instruct the in-memory computing circuit to switch states;

[0008] The in-memory computing circuit is controlled to switch state based on a next state to process the input data.

[0009] In some embodiments of the present disclosure, the step of obtaining the delay of the current state of the in-memory computing circuit from the delays of the pre-configured multiple states includes:

[0010] If the in-memory computing circuit switches state, the delay of the current state of the in-memory computing circuit is obtained from the delays of the pre-configured multiple states.

[0011] In some embodiments of the present disclosure, the method further includes:

[0012] If an input request and input data are received, an input response is returned for the input request after a delay of the current state.

[0013] In some embodiments of the present disclosure, the method further includes:

[0014] Initialize the pre-configured delays of multiple states to reliable durations, and configure the delays of each state in the multiple states in turn as follows:

[0015] configuring the delay of any state that has not yet been configured as the initial delay, and after inputting sample data and an input request, determining whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0016] If the processing result output by the in-memory computing circuit is inconsistent with the correct result corresponding to the sample data, then the preset time length is increased for the delay currently configured for the state, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0017] If the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data, the delay currently configured for the state is reduced by a preset time length, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0018] If the processing result output by the in-memory computing circuit under the previously configured delay of this state is consistent with the correct result corresponding to the sample data, and the processing result output by the in-memory computing circuit under the currently configured delay of this state is inconsistent with the correct result corresponding to the sample data, then the delay of this state is configured to the previously configured delay to complete the configuration of this state.

[0019] According to a second aspect of an embodiment of the present disclosure, a state control device for an in-memory computing circuit is provided, the device comprising:

[0020] An acquisition module, used for acquiring the delay of the current state of the in-memory computing circuit from the delays of multiple states pre-configured;

[0021] A determination module, for determining a next state according to the current state and the input data after a delay of the current state if an input request and input data are received;

[0022] A control module is used to control the switching state of the in-memory computing circuit based on a next state to process the input data.

[0023] In some embodiments of the present disclosure, the acquisition module is used to:

[0024] If the in-memory computing circuit switches state, the delay of the current state of the in-memory computing circuit is obtained from the delays of the pre-configured multiple states.

[0025] In some embodiments of the present disclosure, the device further includes a response module, which is used to:

[0026] If an input request and input data are received, an input response is returned for the input request after a delay of the current state.

[0027] In some embodiments of the present disclosure, the device further includes a configuration module, which is used to:

[0028] Initialize the pre-configured delays of multiple states to reliable durations, and configure the delays of each state in the multiple states in turn as follows:

[0029] configuring the delay of any state that has not yet been configured as the initial delay, and after inputting sample data and an input request, determining whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0030] If the processing result output by the in-memory computing circuit is inconsistent with the correct result corresponding to the sample data, then the preset time length is increased for the delay currently configured for the state, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0031] If the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data, the delay currently configured for the state is reduced by a preset time length, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0032] If the processing result output by the in-memory computing circuit under the previously configured delay of this state is consistent with the correct result corresponding to the sample data, and the processing result output by the in-memory computing circuit under the currently configured delay of this state is inconsistent with the correct result corresponding to the sample data, then the delay of this state is configured to the previously configured delay to complete the configuration of this state.

[0033] According to a third aspect of an embodiment of the present disclosure, a state machine is provided for controlling a state of an in-memory computing circuit, the state machine comprising:

[0034] an asynchronous controller, configured to receive an input request, send an output request to a delay manager, and send a clock signal to a state controller after receiving an output response sent by the delay manager, wherein the input request is used to indicate a switching state of an in-memory computing circuit;

[0035] A delay manager, configured to store pre-configured delays of multiple states, determine a delay of a current state, and send an output response to the asynchronous controller after receiving the output request and after the delay of the current state;

[0036] The state controller is used to save the current state, and after receiving the input data and the clock signal, determine the next state according to the current state and the input data, and send the next state to the in-memory computing circuit and the delay manager respectively, so that the in-memory computing circuit and the delay manager switch states respectively.

[0037] In some embodiments of the present disclosure, the delay manager includes a configurable delay chain and a delay configuration storage unit;

[0038] The delay configuration storage unit is used to store the pre-configured delays of multiple states, and send the delay of the current state to the configurable delay chain after each state switching;

[0039] The configurable delay chain is used to send an output response to the asynchronous controller after receiving an input request and after a delay of a current state.

[0040] In some embodiments of the present disclosure, the delay configuration storage unit is used to configure the delay of the state indicated by the delay configuration instruction to the duration indicated by the delay configuration instruction after receiving the delay configuration instruction.

[0041] In some embodiments of the present disclosure, the state controller includes a current state register, a next state calculation logic unit, and an in-memory calculation control logic unit;

[0042] The current state register is used to save the current state, send the current state to the next state calculation logic unit, receive the next state sent by the next state calculation logic unit after receiving the clock signal and update the current state to the next state, and send the updated current state to the in-memory calculation control logic unit and the delay manager respectively;

[0043] a next state calculation logic unit, for determining a next state according to the current state and the input data after receiving the input data and the current state, and sending the next state to the current state register;

[0044] The in-memory computing control logic unit is used to send the next state to the in-memory computing circuit after receiving the next state, so that the in-memory computing circuit switches the state.

[0045] According to a fourth aspect of an embodiment of the present disclosure, there is provided a digital control circuit based on an in-memory computing circuit, comprising an in-memory computing circuit and a state machine as described in any one of the third aspects.

[0046] According to a fifth aspect of an embodiment of the present disclosure, there is provided a computer program product, comprising a computer program / instruction, which implements the steps of the method described in the first aspect when the computer program / instruction is executed by a processor.

[0047] According to a sixth aspect of an embodiment of the present disclosure, an electronic device is provided, comprising a memory and a processor, wherein the memory is used to store computer instructions executable on the processor, and the processor is used to implement the method described in the first aspect when executing the computer instructions.

[0048] According to a seventh aspect of an embodiment of the present disclosure, there is provided a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the method described in the first aspect is implemented.

[0049] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0050] The state control method of the in-memory computing circuit provided by the embodiment of the present disclosure, first, obtains the delay of the current state of the in-memory computing circuit from the delay of multiple states pre-configured; next, if an input request and input data are received, the next state is determined according to the current state and the input data after the delay of the current state; finally, the in-memory computing circuit is controlled to switch state based on the next state to process the input data. The method determines the next state according to the current state and the input data only after receiving an input request for indicating the switching state of the in-memory computing circuit, that is, performs state switching, thereby reducing power consumption relative to the method of triggering the state machine to try to switch states according to the clock cycle in the related art; and the method pre-configures corresponding delays for multiple states, so that when switching from the current state to the next state, the switch can be executed after accurately waiting for the delay of the current state, thereby ensuring the complete execution of the current state and avoiding excessive waiting and reducing the computing efficiency, especially relative to the method of using the delay of the state with the longest delay as the clock cycle in the related art, and triggering the state machine to try to switch states according to the clock cycle, which can improve the computing efficiency and avoid excessive waiting. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0052] Figure 1 is a structural diagram of a state machine shown in an exemplary embodiment of the present disclosure;

[0053] Figure 2 is an example diagram of an asynchronous clock generated by an asynchronous controller in a state machine shown in an exemplary embodiment of the present disclosure;

[0054] Figure 3 is a flow chart of a state control method shown in an exemplary embodiment of the present disclosure;

[0055] Figure 4 is a state delay configuration logic diagram shown in an exemplary embodiment of the present disclosure;

[0056] Figure 5 is a structural schematic diagram of a state control device shown in an exemplary embodiment of the present disclosure;

[0057] Figure 6 It is a structural block diagram of an electronic device shown in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0059] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0060] It should be understood that although the terms first, second, third, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0061] A large amount of data needs to be moved between the storage unit and the computing unit of the von Neumann architecture chip. This "storage wall" problem limits the energy efficiency and throughput of the chip. To solve the "storage wall" problem, people proposed an in-memory computing architecture, which designs the storage unit and the computing unit into an in-memory computing unit, thereby eliminating the need to move intermediate data, thereby eliminating the delay and power consumption caused by data movement, and greatly improving the chip energy efficiency.

[0062] The in-memory computing circuit requires a peripheral control circuit, such as a state machine, to control its state. However, in the related art, the peripheral control circuit of the in-memory computing circuit consumes high power, which limits the energy efficiency improvement of the digital control circuit.

[0063] For example, since the in-memory computing circuit has the characteristic of high throughput, in order to give full play to this advantage, the state machine in the related technology uses a high-frequency clock to control the state of the in-memory computing circuit, that is, the delay of the state with the longest delay is used as the clock cycle, and the state switching is triggered according to the clock cycle. This clock will bring higher power consumption, and the states other than the state with the longest delay will also have excessive waiting, which will affect the computing efficiency and make the in-memory computing circuit unable to operate at the highest speed.

[0064] Based on this, on the first aspect, at least one embodiment of the present disclosure provides a state machine for performing state control on an in-memory computing circuit. The state machine is driven by an event (i.e., an event that requires state switching), and uses a delay corresponding to the current state to replace the clock cycle in different states, that is, replacing the fixed clock cycle with a flexible clock cycle with a delay corresponding to the state, thereby saving power consumption by reducing the number of drives, and improving the accuracy of state switching and the computing efficiency of the in-memory computing circuit by accurately waiting for the state through the delay corresponding to the state.

[0065] Please refer to the attached Figure 1 , which exemplarily shows the structural diagram of the state machine.

[0066] The state machine includes an asynchronous controller, a delay manager and a state controller.

[0067] The asynchronous controller is used to: receive an input request, send an output request to the delay manager, and send a clock signal to the state controller after receiving an output response sent by the delay manager;

[0068] The delay manager is used to: store pre-configured delays of multiple states, determine the delay of the current state, and send an output response to the asynchronous controller after receiving the output request and after the delay of the current state;

[0069] The state controller is used to: save the current state, and determine the next state according to the current state and the input data after receiving the input data and the clock signal, and send the next state to the in-memory computing circuit and the delay manager respectively, so that the in-memory computing circuit and the delay manager switch states respectively.

[0070] Among them, the input request and input data are input by external devices, and generally the input request and input data exist together and are input simultaneously. The input data is the data that requires the in-memory computing circuit to process, and the input request is used to trigger the in-memory computing circuit to process the input data by switching the state. The output request is used for the asynchronous controller to request the delay manager to send a clock signal, and the output response is used for the delay manager to instruct the asynchronous controller to send a clock signal.

[0071] Among them, the clock signal sent by the asynchronous controller is an asynchronous clock signal, which is triggered by the input request and the delay manager. The delay manager is used to control the timing of the asynchronous controller sending the clock signal. The delay manager switches the state synchronously every time the state controller switches the state, and determines the delay of the current state based on the stored delays of multiple states, and instructs the asynchronous controller to output the clock signal through the output response after the asynchronous controller sends the output request and the delay of the current state. After waiting for the delay of the current state, the calculation of the current state must have been completed. At this time, the delay manager instructs the asynchronous controller to send a clock signal to trigger the state controller to switch the state, which can ensure the timing of the state switching is accurate and precise, that is, to ensure that the calculation of the current state is completed without excessive waiting.

[0072] The delay manager switches the current state according to the latest state of the state controller, and re-determines the delay of the current state after each current state update. In other words, when the current state switches to the next state, the next state has become the new current state, and the current state and the delay of the current state should be updated adaptively. For example, please refer to the attached Figure 1 The delay manager may include a configurable delay chain and a delay configuration storage unit; the delay configuration storage unit is used to store pre-configured delays of multiple states, and send the (re-determined) delay of the current state to the configurable delay chain after each state switching; the configurable delay chain is used to send an output response to the asynchronous controller after receiving an input request and after the delay of the current state.

[0073] For example, the delay configuration storage unit may send the (re-determined) delay of the current state to the configurable delay chain using a delay selection signal.

[0074] In addition, the delay configuration storage unit is used to configure the delay of the state indicated by the delay configuration instruction to the duration indicated by the delay configuration instruction after receiving the delay configuration instruction. In other words, the delay of multiple states in the delay configuration storage unit can be configured externally, and the specific configuration method will be described in detail below, which will not be repeated here.

[0075] For example, please refer to the attached Figure 1 , the state controller may include a current state register, a next state calculation logic unit and an in-memory calculation control logic unit; the current state register is used to save the current state, send the current state to the next state calculation logic unit, receive the next state sent by the next state calculation logic unit after receiving the clock signal and update the current state to the next state, and send the updated current state to the in-memory calculation control logic unit and the delay manager respectively; the next state calculation logic unit is used to determine the next state according to the current state and the input data after receiving the input data and the current state, and send the next state to the current state register; the in-memory calculation control logic unit is used to send the next state to the in-memory calculation circuit after receiving the next state, so that the in-memory calculation circuit switches the state.

[0076] Among them, the current state register is used to manage the current state, that is, after updating the current state, the current state is sent to the next state calculation logic unit so that the next state calculation logic unit determines the next state after receiving the input data; the next state calculation logic unit will send the next state to the current state register after determining the next state; the current state register will not receive the next state sent by the next state calculation logic unit when it does not receive the clock signal, but will receive the next state after receiving the clock signal, and perform state switching accordingly, that is, switching the current state to the next state, and synchronizing the state switching to the next state calculation logic unit, the in-memory calculation control logic unit and the delay configuration storage unit, so that the next state calculation logic unit can determine the next state according to the input data and the current state after receiving the input data next time, so that the delay configuration storage unit can re-determine the delay of the current state, and the in-memory calculation control logic unit can control the in-memory calculation circuit to switch the state and perform the corresponding calculation.

[0077] Please refer to the attached Figure 2, which exemplarily shows an example of an asynchronous clock generated by an asynchronous controller in a state machine provided by the present disclosure. By configuring the delay, the time interval between the rising edges of the asynchronous clock is controlled. Compared with the synchronous circuit, the flexible clock can provide more fine-grained control, thereby improving the computational efficiency of the in-memory calculation, reducing time waste, and reducing unnecessary clock flips to reduce power consumption. The read and write enable of the bit line or word line of the in-memory calculation circuit are both controlled by the bit line or word line asynchronous clock. During the configuration process, the write enable is turned on by the asynchronous clock and the bit line address and word line address are passed in according to the timing requirements, so as to write data to the in-memory calculation unit. In the reading process (that is, the calculation process), the read enable is turned on, and the source line address, bit line address, and word line address are controlled in sequence to enable the in-memory calculation circuit to start working, and finally the ADC enable is turned on to read the in-memory calculation result.

[0078] This state machine is an asynchronous finite state machine. Compared with the traditional synchronous finite state machine, this asynchronous finite state machine has the characteristics of event-driven and flexible clock cycle. The event-driven feature ensures that the in-memory computing circuit is active only when needed, otherwise there will be no internal signal flipping. The flexible clock cycle allows the next state to be entered immediately after the current state calculation is completed, without considering the worst case in multiple states. Therefore, this asynchronous finite state machine significantly reduces the power consumption caused by peripheral circuits and improves the computing speed. And by configuring the delay of the asynchronous finite state machine, the calibration process of the in-memory computing circuit can be quickly and efficiently implemented.

[0079] The state machine can at least solve the following technical problems in related technologies:

[0080] The in-memory computing circuit requires complex peripheral control, which also requires complex states, and the time requirements for the intervals between adjacent states are different. The asynchronous finite state machine of the present invention can enter the next state as quickly as possible while meeting the interval time requirements. The traditional synchronous finite state machine requires a high-frequency clock to achieve the same state conversion efficiency. Therefore, the asynchronous finite state machine of the present invention can help reduce the power consumption caused by the peripheral circuit.

[0081] The in-memory computing circuit is affected by the non-ideal process factors in the chip manufacturing process, and there are differences in the control delay between different chips. The asynchronous finite state machine of the present invention can adjust the value in the delay configuration storage according to different chip conditions, control the delay between different state transitions, and realize chip calibration.

[0082] According to a second aspect of the embodiments of the present disclosure, a digital control circuit based on an in-memory computing circuit is provided, comprising an in-memory computing circuit and a state machine as described in any one of the first aspects. For example, the digital control circuit may be a chip.

[0083] In a third aspect, at least one embodiment of the present disclosure provides a state control method for an in-memory computing circuit. The method can be executed by a state machine provided by any embodiment of the first aspect, or by other peripheral control circuits of the in-memory computing circuit, and the present disclosure is not limited to this.

[0084] Please refer to the attached Figure 3 , which exemplarily shows the process of the method, including steps S301 to S303.

[0085] In step S301, the delay of the current state of the in-memory computing circuit is obtained from the pre-configured delays of multiple states.

[0086] For example, when the method is executed by the state machine provided by any embodiment of the first aspect, the delay of obtaining the current state of the computing circuit in the memory from the configurable delay chain to the delay configuration storage.

[0087] Moreover, this step can be performed in the following manner: if the in-memory computing circuit switches state, the delay of the current state of the in-memory computing circuit is obtained from the delays of the pre-configured multiple states, that is, the delay of the newly determined new current state is obtained when the state is switched.

[0088] In step S302, if an input request and input data are received, the next state is determined according to the current state and the input data after a delay of the current state, wherein the input request is used to instruct the in-memory computing circuit to switch state.

[0089] For example, when the method is executed by the state machine provided by any embodiment of the first aspect, the asynchronous controller receives an input request, and the next state calculation logic unit receives input data. When the asynchronous controller receives the input request, it sends an output request to the configurable delay chain, and the configurable delay chain sends an output response to the asynchronous controller after receiving the output request and after the current delay; then, the asynchronous controller outputs a clock signal to the current state register, the current state register receives the next state sent by the next state calculation logic unit, and updates the current state to the next state, and sends the updated current state to the next state calculation logic unit, so that the next state calculation logic unit determines the next state according to the input data and the current state after receiving the input data next time.

[0090] In addition, the method further includes: if an input request and input data are received, an input response is returned for the input request after a delay of the current state. In other words, the method can return a response to the device that sent the input request after starting the state switch. For example, when the method is executed by the state machine provided by any embodiment of the first aspect, the asynchronous controller can generate a clock signal and return the input response at the same time.

[0091] In step S303, the in-memory computing circuit is controlled to switch state based on the next state to process the input data.

[0092] For example, when the method is executed by the state machine provided by any embodiment of the first aspect, the next state calculation logic unit sends the determined next state to the current state register, and the current state register sends the next state to the in-memory calculation control logic unit, so that the in-memory calculation control logic unit sends the next state to the in-memory calculation circuit, so that the in-memory calculation circuit switches the state. Moreover, the current state register also sends the next state to the delay configuration storage unit, so that the delay configuration storage unit re-determines the delay of the current state.

[0093] The method also includes the following delay configuration steps for the various states:

[0094] Initialize the pre-configured delays of multiple states to reliable durations, and configure the delays of each state in the multiple states in turn as follows:

[0095] configuring the delay of any state that has not yet been configured as the initial delay, and after inputting sample data and an input request, determining whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0096] If the processing result output by the in-memory computing circuit is inconsistent with the correct result corresponding to the sample data, then the preset time length is increased for the delay currently configured for the state, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0097] If the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data, the delay currently configured for the state is reduced by a preset time length, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0098] If the processing result output by the in-memory computing circuit under the previously configured delay of this state is consistent with the correct result corresponding to the sample data, and the processing result output by the in-memory computing circuit under the currently configured delay of this state is inconsistent with the correct result corresponding to the sample data, then the delay of this state is configured to the previously configured delay to complete the configuration of this state.

[0099] The above process is described as follows:

[0100] Reliable duration refers to a longer duration, which is set based on empirical knowledge and requires that each state must be able to complete the corresponding calculation within this duration.

[0101] The initial delay can be set based on empirical knowledge.

[0102] Please refer to the attached Figure 4 , which is attached Figure 1 The state machine shown is taken as an example to exemplarily show the logical sequence of the delay configuration process of any state.

[0103] After configuring the initial delay to the delay configuration storage, sample data can be input and input requests can be input at the same time to trigger the state machine to control the state of the in-memory computing circuit, that is, trigger the in-memory computing circuit to process the number of samples, and further judge whether the in-memory computing circuit is working normally by whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data. If it is not working normally, it means that the delay currently configured in this state is incorrect, because other states or delays are configured as reliable durations, or have been configured, and will not affect the normal operation of the in-memory computing circuit.

[0104] Next, if the in-memory computing circuit does not work normally, the delay is reconfigured by increasing the delay; if the in-memory computing circuit works normally, the delay is reconfigured by reducing the delay; after each reconfiguration of the delay, sample data and input requests are input to trigger the in-memory computing circuit to work and to determine whether the in-memory computing circuit works normally; thus forming a loop until the in-memory computing circuit works normally under the last configured delay, and the in-memory computing circuit does not work normally under the currently configured delay, then the last configured delay is determined as the delay for this state to complete the delay configuration for this state.

[0105] In simple terms, the essence of this process is to control the states of other unfinished configurations except the current configuration state through reliable duration so as not to affect the normal operation of the in-memory computing circuit, and then continuously search for the shortest delay that can ensure the normal operation of the in-memory computing circuit as the delay of this state in the process of increasing or decreasing the delay.

[0106] This configuration process is adapted to the state machine and state control method provided by the present disclosure, and can enable the state machine and state control method to ensure the accuracy of the delay of each state in state control, so that the calculation corresponding to the state can be completed without excessive waiting, thereby ensuring the calculation quality and improving the calculation efficiency.

[0107] In a fourth aspect, at least one embodiment of the present disclosure provides a state control device for an in-memory computing circuit, see the attached Figure 5 , the device comprises:

[0108] An acquisition module 501 is used to acquire the delay of the current state of the in-memory computing circuit from the delays of multiple states that are pre-configured;

[0109] A determination module 502, for determining a next state according to the current state and the input data after a delay of the current state if an input request and input data are received;

[0110] The control module 503 is used to control the in-memory computing circuit to switch states based on a next state so as to process the input data.

[0111] In some embodiments of the present disclosure, the acquisition module is used to:

[0112] If the in-memory computing circuit switches state, the delay of the current state of the in-memory computing circuit is obtained from the delays of the pre-configured multiple states.

[0113] In some embodiments of the present disclosure, the device further includes a response module, which is used to:

[0114] If an input request and input data are received, an input response is returned for the input request after a delay of the current state.

[0115] In some embodiments of the present disclosure, the device further includes a configuration module, which is used to:

[0116] Initialize the pre-configured delays of multiple states to reliable durations, and configure the delays of each state in the multiple states in turn as follows:

[0117] configuring the delay of any state that has not yet been configured as the initial delay, and after inputting sample data and an input request, determining whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0118] If the processing result output by the in-memory computing circuit is inconsistent with the correct result corresponding to the sample data, then the preset time length is increased for the delay currently configured for the state, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0119] If the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data, the delay currently configured for the state is reduced by a preset time length, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data;

[0120] If the processing result output by the in-memory computing circuit under the previously configured delay of this state is consistent with the correct result corresponding to the sample data, and the processing result output by the in-memory computing circuit under the currently configured delay of this state is inconsistent with the correct result corresponding to the sample data, then the delay of this state is configured to the previously configured delay to complete the configuration of this state.

[0121] Regarding the device in the above embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment of the first aspect related to the method, and will not be elaborated here.

[0122] According to a fifth aspect of an embodiment of the present disclosure, there is provided a computer program product, comprising a computer program / instruction, which implements the steps of the method described in the first aspect when the computer program / instruction is executed by a processor.

[0123] According to the sixth aspect of the embodiment of the present disclosure, please refer to the attached Figure 6 , which exemplarily shows a block diagram of an electronic device. For example, the device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0124] Reference Figure 6 , device 600 may include one or more of the following components: a processing component 602 , a memory 604 , a power component 606 , a multimedia component 608 , an audio component 610 , an input / output (I / O) interface 612 , a sensor component 614 , and a communication component 616 .

[0125] The processing component 602 generally controls the overall operation of the device 600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0126] The memory 604 is configured to store various types of data to support operations on the device 600. Examples of such data include instructions for any application or method operating on the device 600, contact data, phone book data, messages, pictures, videos, etc. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0127] The power component 606 provides power to the various components of the device 600. The power component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device 600.

[0128] The multimedia component 608 includes a screen that provides an output interface between the device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the device 600 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and the rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0129] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC), and when the device 600 is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 604 or sent via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0130] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0131] The sensor assembly 614 includes one or more sensors for providing various aspects of status assessment for the device 600. For example, the sensor assembly 614 can detect the open / closed state of the device 600, the relative positioning of components, such as the display and keypad of the device 600, and the sensor assembly 614 can also detect the position change of the device 600 or a component of the device 600, the presence or absence of user contact with the device 600, the orientation or acceleration / deceleration of the device 600, and the temperature change of the device 600. The sensor assembly 614 can also include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 614 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0132] The communication component 616 is configured to facilitate wired or wireless communication between the device 600 and other devices. The device 600 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G or 6G or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0133] In an exemplary embodiment, the device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to execute the state control method of the electronic device described above.

[0134] In a seventh aspect, the present disclosure, in an exemplary embodiment, further provides a non-transitory computer-readable storage medium including instructions, such as a memory 604 including instructions, and the instructions can be executed by a processor 620 of a device 600 to complete the main steam control method of the electronic device. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0135] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0136] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A state control method for an in-memory computing circuit, characterized in that: The method comprises: Obtaining the delay of the current state of the in-memory computing circuit from the delays of the pre-configured multiple states; If an input request and input data are received, then after a delay of the current state, a next state is determined according to the current state and the input data, wherein the input request is used to instruct the in-memory computing circuit to switch states; The in-memory computing circuit is controlled to switch state based on a next state to process the input data.

2. The state control method of the in-memory computing circuit according to claim 1, characterized in that: The step of obtaining the delay of the current state of the in-memory computing circuit from the delays of the pre-configured multiple states includes: If the in-memory computing circuit switches state, the delay of the current state of the in-memory computing circuit is obtained from the delays of the pre-configured multiple states.

3. The state control method of the in-memory computing circuit according to claim 1, characterized in that: The method further comprises: If an input request and input data are received, an input response is returned for the input request after a delay of the current state.

4. The state control method of the in-memory computing circuit according to claim 1, characterized in that: The method further comprises: Initialize the pre-configured delays of multiple states to reliable durations, and configure the delays of each state in the multiple states in turn as follows: configuring the delay of any state that has not yet been configured as the initial delay, and after inputting sample data and an input request, determining whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data; If the processing result output by the in-memory computing circuit is inconsistent with the correct result corresponding to the sample data, then the preset time length is increased for the delay currently configured for the state, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data; If the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data, the delay currently configured for the state is reduced by a preset time length, and after the sample data and the input request are input, it is determined whether the processing result output by the in-memory computing circuit is consistent with the correct result corresponding to the sample data; If the processing result output by the in-memory computing circuit under the previously configured delay of this state is consistent with the correct result corresponding to the sample data, and the processing result output by the in-memory computing circuit under the currently configured delay of this state is inconsistent with the correct result corresponding to the sample data, then the delay of this state is configured to the previously configured delay to complete the configuration of this state.

5. A state control device for an in-memory computing circuit, characterized in that: The device comprises: An acquisition module, used for acquiring the delay of the current state of the in-memory computing circuit from the delays of multiple states pre-configured; A determination module, for determining a next state according to the current state and the input data after a delay of the current state if an input request and input data are received; A control module is used to control the switching state of the in-memory computing circuit based on a next state to process the input data.

6. A state machine, characterized in that: Used to control the state of the in-memory computing circuit, the state machine includes: an asynchronous controller, configured to receive an input request, send an output request to a delay manager, and send a clock signal to a state controller after receiving an output response sent by the delay manager, wherein the input request is used to indicate a switching state of an in-memory computing circuit; A delay manager, configured to store pre-configured delays of multiple states, determine a delay of a current state, and send an output response to the asynchronous controller after receiving the output request and after the delay of the current state; The state controller is used to save the current state, and after receiving the input data and the clock signal, determine the next state according to the current state and the input data, and send the next state to the in-memory computing circuit and the delay manager respectively, so that the in-memory computing circuit and the delay manager switch states respectively.

7. The state machine according to claim 6, characterized in that: The delay manager includes a configurable delay chain and a delay configuration storage unit; The delay configuration storage unit is used to store the pre-configured delays of multiple states, and send the delay of the current state to the configurable delay chain after each state switching; The configurable delay chain is used to send an output response to the asynchronous controller after receiving an input request and after a delay of a current state.

8. The state machine according to claim 7, characterized in that: The delay configuration storage unit is used to configure the delay of the state indicated by the delay configuration instruction to the duration indicated by the delay configuration instruction after receiving the delay configuration instruction.

9. The state machine according to claim 6, characterized in that: The state controller includes a current state register, a next state calculation logic unit, and an in-memory calculation control logic unit; The current state register is used to save the current state, send the current state to the next state calculation logic unit, receive the next state sent by the next state calculation logic unit after receiving the clock signal and update the current state to the next state, and send the updated current state to the in-memory calculation control logic unit and the delay manager respectively; A next state calculation logic unit, configured to determine a next state according to the current state and the input data after receiving the input data and the current state, and send the next state to the current state register; The in-memory computing control logic unit is used to send the next state to the in-memory computing circuit after receiving the next state, so that the in-memory computing circuit switches the state.

10. A digital control circuit based on an in-memory computing circuit, characterized in that: The method comprises an in-memory computing circuit and a state machine as claimed in any one of claims 6 to 9.

11. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

12. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory is used to store computer instructions executable on the processor, and the processor is used to implement the method according to any one of claims 1 to 4 when executing the computer instructions.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

Images