High-Reliability Storage Chip Packaging and Testing Method and System

Abstract

The present invention relates to the field of electronic information technology, and discloses a high-reliability storage chip packaging and testing method and system, including: First, obtain the storage chip to be tested and its original parameter information, collect packaging structure data to construct a three-dimensional model and extract chip feature data, then compare with standard reference data, mine potential defect information, screen suspicious packaging parts and monitor their sensitivity to environmental parameters, then evaluate the type of failure risk based on this, locate weak links and detect performance, find out specific problem points, then formulate test planning objectives, clarify test means and standards, generate test operation instructions, and finally perform packaging testing, collect electrical performance data to verify stability, and generate a packaging test report. The present invention can improve the stability of storage chips.

Description

Technical Field

[0001] The present invention relates to a high-reliability storage chip packaging and testing method and system, belonging to the field of electronic information technology. Background Art

[0002] In the current era of rapid development of digital information, data has become the core asset for the development of various industries. As a key component for carrying and protecting this data, the performance and reliability of storage chips directly determine the data storage and processing capabilities of various electronic devices.

[0003] At present, traditional storage chip packaging and testing methods have gradually exposed many problems in meeting the continuously increasing storage requirements. On the one hand, as the capacity of storage chips continues to increase and their size continues to shrink, the circuit layout inside the chips becomes more compact. Traditional packaging materials and technologies are difficult to effectively protect the chips from the influence of external environmental factors (such as temperature, humidity, mechanical stress, etc.), thereby reducing the reliability and service life of storage chips. On the other hand, traditional testing often only detects some basic functions of storage chips and is difficult to discover potential minor defects and performance hidden dangers. For problems that occur under extreme working conditions (such as high temperature, high pressure, high frequency, etc.), traditional testing methods are even more unable to effectively predict and evaluate. This leads to serious failures such as data loss and read / write errors in storage chips during actual use, thus affecting the stability of storage chips. Therefore, a high-reliability storage chip packaging and testing method is needed to improve the stability of storage chips. Summary of the Invention

[0004] The present invention provides a high-reliability storage chip packaging and testing method and system, and its main purpose is to improve the stability of storage chips.

[0005] To achieve the above object, a high-reliability storage chip packaging and testing method provided by the present invention includes:

[0006] Obtain the original parameter information corresponding to the storage chip to be tested, collect the packaging structure data in the original parameter information, construct a three-dimensional model corresponding to the storage chip to be tested based on the packaging structure data, perform feature extraction on the three-dimensional model, and obtain chip feature data;

[0007] Compare and analyze the chip feature data with the reference data of a standard storage chip to obtain difference analysis data, mine the potential defect information in the difference analysis data, screen the suspicious packaging parts corresponding to the potential defect information, and real-time monitor the real-time working environment parameters of the storage chip to be tested, and calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters;

[0008] Based on the sensitivity value, evaluate the types of potential fault risks that the storage chip to be tested may have. Based on the types of fault risks, locate the weak links in the package of the storage chip to be tested, perform performance detection on the weak links to obtain the performance status of the links, and find the specific problem points in the performance status of the links;

[0009] Based on the specific problem points, formulate the test planning objectives corresponding to the storage chip to be tested, analyze the test means in the test planning objectives, and query the test standards corresponding to the test means. Based on the test standards, generate the test operation instructions corresponding to the storage chip to be tested;

[0010] After applying the test operation instructions to the storage chip to be tested, perform a package test operation on the storage chip to be tested to obtain a packaged test chip, collect the electrical performance data corresponding to the packaged test chip, and perform stability verification on the electrical performance data to obtain verification result data. Based on the verification result data, generate the package test report corresponding to the storage chip to be tested.

[0011] Optionally, the feature extraction of the three-dimensional model to obtain chip feature data includes:

[0012] Identify the contour edge lines corresponding to the internal structure in the three-dimensional model;

[0013] Perform grid processing on the contour edge lines to obtain regular grid units;

[0014] Analyze the connection relationship between adjacent grids of the regular grid units;

[0015] Based on the connection relationship, determine the topological structure points corresponding to the three-dimensional model;

[0016] Based on the topological structure points, perform feature extraction on the three-dimensional model to obtain chip feature data.

[0017] Optionally, the comparison and analysis of the chip feature data with the reference data of the standard storage chip to obtain difference analysis data includes:

[0018] Determine the data dimensions corresponding to the chip feature data and the reference data of the standard storage chip;

[0019] Based on the data dimensions, calculate the absolute difference between the chip feature data and the reference data of the standard storage chip;

[0020] Perform data statistics on the absolute difference to obtain a difference statistics set;

[0021] Based on a preset threshold range, divide the data threshold points in the difference statistics set;

[0022] Based on the data threshold point, compare and analyze the chip feature data with the reference data of the standard storage chip to obtain differential analysis data.

[0023] Optionally, calculating the absolute difference between the chip feature data and the reference data of the standard storage chip based on the data dimension includes:

[0024] Calculate the absolute difference between the chip feature data and the reference data of the standard storage chip using the following formula:

[0025]

[0026] Where represents the absolute difference between the chip feature data and the reference data of the standard storage chip, represents the total quantity corresponding to the data dimension, represents the quantity index corresponding to the data dimension, represents at the th data dimension, the feature data value corresponding to the chip feature data, represents at the th data dimension, the reference data value corresponding to the standard storage chip, represents the importance coefficient corresponding to the th data dimension.

[0027] Optionally, calculating the sensitivity value of the suspicious packaging part affected by environmental parameters includes:

[0028] Calculate the sensitivity value of the suspicious packaging part affected by environmental parameters using the following formula:

[0029]

[0030] Where represents the sensitivity value of the suspicious packaging part affected by environmental parameters, represents the type quantity corresponding to the environmental parameter, represents the quantity index corresponding to the environmental parameter, represents the change range corresponding to the th environmental parameter, represents the influence weight coefficient of the th environmental parameter on the suspicious packaging part, and respectively represent the start time and end time of the evaluation period, represents at time the performance change function corresponding to the suspicious packaging part.

[0031] Optionally, locating the weak link in the package of the storage chip to be tested based on the type of failure risk includes:

[0032] Analyze the factor influence weight corresponding to the failure risk factor in the type of failure risk;

[0033] Based on the factor influence weight, sort the failure risk factors to obtain a risk factor sequence;

[0034] Construct an association map between the risk factor sequence and the corresponding package components of the storage chip to be tested;

[0035] Screen the strong association nodes in the association map;

[0036] Based on the strong association nodes, locate the weak link in the package of the storage chip to be tested.

[0037] Optionally, finding the specific problem points in the performance state of the link includes:

[0038] Analyze the state performance indicators corresponding to the performance state of the link;

[0039] Construct a mapping relationship framework corresponding to the state performance indicators;

[0040] Based on the mapping relationship framework, analyze the preliminary classification problems corresponding to the performance state of the link;

[0041] Collect the historical case data corresponding to the preliminary classification problems;

[0042] Based on the historical case data, find the specific problem points in the performance state of the link.

[0043] Optionally, formulating the test planning objective corresponding to the storage chip to be tested based on the specific problem points includes:

[0044] Analyze the relationship characteristics between the specific problem points and the functional modules in the storage chip to be tested;

[0045] Based on the relationship characteristics, identify the module influence degree corresponding to the functional modules in the storage chip to be tested;

[0046] Perform a hierarchical processing on the module influence degree to obtain a hierarchical result;

[0047] According to the hierarchical result, determine the range of functional modules corresponding to the key tests;

[0048] Based on the range of functional modules, formulate the test planning objective corresponding to the storage chip to be tested.

[0049] Optionally, generating the test operation instructions corresponding to the storage chip to be tested based on the test criteria includes:

[0050] Analyze the item clause details corresponding to the test criteria;

[0051] Based on the item clause details, sort out the item test phases corresponding to the storage chip to be tested;

[0052] Extract the key test elements in the item test phases;

[0053] Based on the key test elements, determine the operation test process corresponding to the storage chip to be tested;

[0054] Based on the operation test process, generate the test operation instructions corresponding to the storage chip to be tested.

[0055] To solve the above problems, the present invention also provides a high-reliability storage chip package testing system, and the system includes:

[0056] A feature extraction module, configured to obtain the original parameter information corresponding to the storage chip to be tested, collect the package structure data in the original parameter information, construct a three-dimensional model corresponding to the storage chip to be tested based on the package structure data, and perform feature extraction on the three-dimensional model to obtain chip feature data;

[0057] A sensitivity calculation module, configured to compare and analyze the chip feature data with the reference data of a standard storage chip to obtain difference analysis data, mine the potential defect information in the difference analysis data, screen the suspicious package parts corresponding to the potential defect information, and real-time monitor the real-time working environment parameters of the storage chip to be tested, and calculate the sensitivity value of the suspicious package parts affected by the environmental parameters;

[0058] A problem finding module, configured to evaluate the types of potential failure risks that the storage chip to be tested may have based on the sensitivity value, locate the weak links in the package of the storage chip to be tested based on the types of failure risks, perform performance detection on the weak links to obtain the link performance status, and find the specific problem points in the link performance status;

[0059] An instruction generation module, configured to formulate the test planning objective corresponding to the storage chip to be tested based on the specific problem points, analyze the test means in the test planning objective, query the test criteria corresponding to the test means, and generate the test operation instructions corresponding to the storage chip to be tested based on the test criteria;

[0060] A report generation module, which is used to apply the test operation instruction to the storage chip to be tested, perform a package test operation on the storage chip to be tested to obtain a packaged test chip, collect electrical performance data corresponding to the packaged test chip, verify the stability of the electrical performance data to obtain verification result data, and generate a package test report corresponding to the storage chip to be tested based on the verification result data.

[0061] Compared with the problems described in the background art, the present invention helps to deeply understand the internal structure and physical characteristics of the chip by obtaining the original parameter information corresponding to the storage chip to be tested and collecting the package structure data in the original parameter information, provides a basic basis for subsequent performance evaluation, can accurately determine whether the chip meets specific design and production standards, and ensures product quality. By comparing and analyzing the chip feature data with the reference data of the standard storage chip, the present invention obtains difference analysis data, can accurately locate the deviations of the chip in terms of performance, structure, etc., provides a clear direction for quality control, helps to screen out unqualified products in a timely manner. Further, based on the sensitivity value, the present invention evaluates the possible failure risk types of the storage chip to be tested, can predict the possible failure types in advance, provides a clear direction for preventive maintenance, reduces the probability of sudden failures of the chip in actual use, and improves the stability of the system. Further, based on the specific problem points, the present invention formulates the test planning objectives corresponding to the storage chip to be tested, can achieve precise focus of the test, avoid resource waste and time consumption caused by blind comprehensive testing, and improve the quality and reliability of the storage chip. Finally, after applying the test operation instruction to the storage chip to be tested, the present invention performs a package test operation on the storage chip to be tested to obtain a packaged test chip, which can effectively ensure the package quality of the storage chip, and can accurately detect problems that may occur during the chip packaging process, such as poor pin connection and poor package sealing, so as to make improvements in a timely manner and enhance the overall stability of the chip. Therefore, the high-reliability storage chip package test method and system provided by the embodiments of the present invention can improve the stability of the storage chip. Description of the Drawings

[0062] Figure 1 It is a schematic flow chart of a high-reliability storage chip package test method provided by an embodiment of the present invention;

[0063] Figure 2 It is a schematic module diagram of a high-reliability storage chip package test system provided by an embodiment of the present invention.

[0064] The implementation, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed Embodiments

[0065] It should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0066] The embodiment of the present application provides a high-reliability storage chip packaging and testing method. The execution subject of the high-reliability storage chip packaging and testing method includes, but is not limited to, at least one of electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiment of the present application. In other words, the high-reliability storage chip packaging and testing method can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to: a single server, a server cluster, a cloud server, or a cloud server cluster, etc.

[0067] Embodiment 1:

[0068] Refer to Figure 1 As shown, it is a schematic flowchart of the high-reliability storage chip packaging and testing method provided by an embodiment of the present invention. In this embodiment, the high-reliability storage chip packaging and testing method includes:

[0069] S1. Obtain the original parameter information corresponding to the storage chip to be tested, collect the package structure data in the original parameter information, construct a three-dimensional model corresponding to the storage chip to be tested based on the package structure data, and perform feature extraction on the three-dimensional model to obtain chip feature data.

[0070] By obtaining the original parameter information corresponding to the storage chip to be tested and collecting the package structure data in the original parameter information, the present invention helps to deeply understand the internal structure and physical characteristics of the chip, provides a basic basis for subsequent performance evaluation, can accurately judge whether the chip meets specific design and production standards, and ensures product quality.

[0071] Among them, the storage chip to be tested refers to an individual chip that needs to be evaluated and verified in terms of its performance, reliability, etc. during the production, R & D or quality inspection of the storage chip. It can be a newly produced untested chip or a chip sample used in the R & D stage to test the effects of new designs and new processes. The original parameter information refers to various inherent parameter data that the storage chip to be tested has in its initial state. These parameters include the basic technical specifications of the chip, such as the storage capacity (e.g., 1TB, 2TB, etc.), data transfer rate (such as how many GB of data can be transferred per second), operating voltage range (the voltage range required for the chip to work properly), interface type (such as common interface standards like SATA, NVMe, etc.), as well as the circuit design parameters and logical structure parameters inside the chip. The package structure data refers to the data describing the package form and internal structure of the storage chip to be tested, including the type of packaging material (e.g., plastic packaging, ceramic packaging, etc.), the geometric dimensions of the package (specific values of length, width, and height), the number, arrangement, and function definition of the pins (different pins are responsible for different functions such as power supply, data transfer, control signals, etc.), and the connection method between the die inside the chip and the package (such as information related to connection technologies like wire bonding, flip chip, etc.). Optionally, the acquisition of the original parameter information corresponding to the storage chip to be tested can be achieved through electronic test equipment, such as oscilloscopes, logic analyzers, etc., by connecting the chip pins to obtain the original parameter information related to the electrical signals. The acquisition of the package structure data in the original parameter information can be achieved through three-dimensional X-ray detection technology. For example, using three-dimensional X-ray detection technology can penetrate the chip package and clearly present a three-dimensional image of the internal structure, and then extract the package structure data.

[0072] Furthermore, based on the package structure data, the present invention constructs a three-dimensional model corresponding to the storage chip to be tested, which can realize visual display, more intuitively understand the internal structure and packaging details of the chip, and can perform virtual simulation and testing to predict the performance of the chip under different environments and working conditions before actual operation, discover potential problems in advance, and reduce R & D costs and time.

[0073] Among them, the three-dimensional model refers to a three-dimensional digital model constructed based on the data of the package structure of the storage chip to be tested, through means such as computer graphics, three-dimensional modeling software or algorithms. It comprehensively and intuitively presents the external package form of the storage chip with accurate dimensions and shapes, including the geometric outline of the package, the position and arrangement of pins, etc. At the same time, it can also show the internal structure layout of the chip, such as the position of the chip die, the connection method between the chip and the package (such as wire bonding, flip chip, etc.), the details of the internal circuit routing, etc. This model can not only provide the spatial structure information of the chip, but also incorporate parameters such as material properties into the model to perform various simulation analyses on the chip in a virtual environment, such as heat conduction analysis, mechanical property analysis, etc. Optionally, the construction of the three-dimensional model corresponding to the storage chip to be tested can be achieved through three-dimensional modeling tools, such as: SolidWorks, AutoCAD 3D and other tools.

[0074] Furthermore, by extracting features from the three-dimensional model of the present invention, chip feature data can be obtained, which can provide a strong basis for the accurate classification and identification of chips, facilitate the rapid distinction of different types of chips during the production and quality inspection processes, contribute to the in-depth analysis of the performance bottlenecks and potential defects of chips, provide key references for optimizing the design and improving the process, and thus improve the overall quality and performance of the chips.

[0075] Among them, the chip feature data refers to the data set that can comprehensively and accurately describe the structural and performance characteristics of the chip after a series of the above-mentioned feature extraction operations on the three-dimensional model. These data include but are not limited to the geometric parameters of the contour edge lines, the attribute parameters of the regular grid cells, the feature descriptions of the connection relationships, and the relevant information of the topological structure points, etc.

[0076] As an embodiment of the present invention, the extraction of features from the three-dimensional model to obtain chip feature data includes: identifying the contour edge lines corresponding to the internal structure in the three-dimensional model; performing grid processing on the contour edge lines to obtain regular grid cells; analyzing the connection relationships between adjacent grids of the regular grid cells; determining the topological structure points corresponding to the three-dimensional model based on the connection relationships; and extracting features from the three-dimensional model based on the topological structure points to obtain chip feature data.

[0077] Among them, the contour edge lines refer to the boundary lines between the internal structure of the chip (such as chip die, pins, connecting lines, etc.) and the surrounding space or other structures in the three-dimensional model. These lines precisely outline the external contours of each component inside the chip and can be identified from the geometric information of the three-dimensional model, being able to intuitively reflect the basic characteristics such as the shape and size of the internal structure of the chip; the regular grid cells refer to the small cells with uniform shape and size obtained after meshing the contour edge lines. These grid cells can be square, triangular or other regular geometric shapes, and they evenly cover the area enclosed by the contour edge lines. Through this meshing process, the complex internal structure area of the chip is divided into multiple simple and easy-to-analyze small cells; the connection relationship refers to the mutual association method between adjacent grids in the regular grid cells. This connection relationship can include situations such as the shared edges and shared vertices of adjacent grids, as well as the relative position and direction information between grids; the topological structure points refer to the key nodes determined based on the connection relationship between adjacent grids and can represent the topological structure characteristics of the three-dimensional model. These points are usually located at important positions of the connection relationship, such as the intersection points connecting multiple grids and the positions where the connection relationship changes. The topological structure points can reflect the topological morphology of the internal structure of the chip, such as whether there are branches, loops, etc.

[0078] Furthermore, the identification of the contour edge lines corresponding to the internal structure in the three-dimensional model can be achieved through edge detection algorithms, such as: Canny edge detection algorithm. Applying this algorithm to the three-dimensional model converted into a two-dimensional projection image or on the two-dimensional slices of the three-dimensional model can identify the contour edge lines; the meshing process of the contour edge lines can be achieved through triangulation algorithms, such as: constructing triangular grids based on the points on the contour edge lines to make the grids as close to equilateral triangles as possible, thereby obtaining regular grid cells; the analysis of the connection relationship between adjacent grids in the regular grid cells can be achieved through the adjacency matrix method, such as: by constructing a matrix, where the elements of the matrix represent the connection relationship between grid cells (adjacent is 1, not adjacent is 0), the connection relationship between adjacent grids can be clearly analyzed; the determination of the topological structure points corresponding to the three-dimensional model can be achieved through model simplification algorithms, such as: during the process of simplifying the three-dimensional model, those key points that have a greater impact on the overall shape of the model are the topological structure points; the feature extraction of the three-dimensional model can be achieved through principal component analysis algorithms, such as: the main feature components can be extracted from the multi-dimensional data of the three-dimensional model (such as size, shape, etc.) to obtain the chip feature data.

[0079] S2. Compare and analyze the chip feature data with the reference data of the standard storage chip to obtain difference analysis data, mine the potential defect information in the difference analysis data, screen the suspicious packaging parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the storage chip to be tested in real time, and calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters.

[0080] By comparing and analyzing the chip feature data with the reference data of the standard storage chip, the present invention obtains difference analysis data, which can accurately locate the deviations of the chip in terms of performance, structure, etc., provide a clear direction for quality control, and help screen out unqualified products in a timely manner.

[0081] Among them, the reference data of the standard storage chip refers to a set of specification data sets covering aspects such as physical structure, performance parameters, and internal structure, which includes standard packaging dimensions, pin characteristics, material specifications, as well as clear performance indicators such as storage capacity, transmission rate, and working voltage, and also information such as standard chip die size and internal connection method; the difference analysis data refers to a data set that comprehensively reflects the difference between the chip feature data and the reference data of the standard storage chip after a series of processing and analysis. For example, it will clearly point out which data dimensions have significant differences, what impacts these differences may have on the performance, reliability, and stability of the chip, and whether these differences are within an acceptable range, etc.

[0082] As an embodiment of the present invention, the comparing and analyzing the chip feature data with the reference data of the standard storage chip to obtain difference analysis data includes: determining the data dimensions corresponding to the chip feature data and the reference data of the standard storage chip; calculating the absolute difference between the chip feature data and the reference data of the standard storage chip based on the data dimensions; performing data statistics on the absolute difference to obtain a difference statistics set; dividing the data threshold points in the difference statistics set based on a preset threshold range; and comparing and analyzing the chip feature data with the reference data of the standard storage chip based on the data threshold points to obtain difference analysis data.

[0083] Among them, the data dimension refers to the data classification method used to describe chip features, which covers the attribute information of the chip in different aspects. For example, in a storage chip, the data dimension can include the physical structure dimension, such as the package size, number of pins, and arrangement of the chip; the performance parameter dimension, like the storage capacity, read / write speed, power consumption, etc.; the electrical characteristic dimension, such as the operating voltage, current, etc. The absolute difference refers to the absolute value of the difference between the chip feature data and the reference data of the standard storage chip under the same data dimension, which eliminates the influence of the positive and negative directions of the difference and only focuses on the magnitude of the numerical difference between the two. For example, if the storage capacity in the chip feature data is 512GB, while the storage capacity in the reference data of the standard storage chip is 1024GB, then the absolute difference in the storage capacity data dimension is |512 - 1024| = 512GB. The difference statistics set refers to the data set formed after statistical analysis of multiple absolute differences, which contains the results of various statistical operations on the absolute differences, such as the mean, median, mode, standard deviation, etc., and can reflect the average deviation degree of the chip feature data from the standard reference data as a whole. The standard deviation can reflect the dispersion degree of these absolute differences, that is, the fluctuation of the data. The data threshold point refers to a numerical point with specific significance determined in the difference statistics set based on a preset threshold range. For example, for the read / write speed data dimension of a storage chip, it may be preset that when the absolute difference exceeds a certain value (such as 50MB / s), it is considered that this difference has a greater impact, then this 50MB / s is a data threshold point.

[0084] Furthermore, the data dimension corresponding to the chip feature data and the reference data of the standard storage chip can be determined through a metadata management tool, such as tools like Apache Atlas, to match and determine the data dimension corresponding to the chip feature data and the reference data. The calculation of the absolute difference between the chip feature data and the reference data of the standard storage chip can be achieved through the following calculation formula. The data statistics of the absolute difference can be realized through a statistical analysis tool, such as tools like SPSS. The division of the data threshold point in the difference statistics set can be achieved through a clustering algorithm, such as clustering the absolute difference data, determining the centers and boundaries of different categories according to the clustering results, and taking the boundary points as the data threshold points. The comparative analysis of the chip feature data and the reference data of the standard storage chip can be achieved through a multi-dimensional data analysis method, such as the principal component analysis method. The chip feature data and the reference data are formed into a data matrix, and the PCA algorithm is applied to perform dimensionality reduction and feature extraction on it, and the comparative analysis is carried out in the low-dimensional space to obtain the difference analysis data.

[0085] As an embodiment of the present invention, calculating the absolute difference between the chip characteristic data and the reference data of the standard memory chip based on the data dimension includes:

[0086] Calculating the absolute difference between the chip characteristic data and the reference data of the standard memory chip by using the following formula:

[0087]

[0088] Wherein, represents the absolute difference between the chip characteristic data and the reference data of the standard memory chip, represents the total quantity corresponding to the data dimension, represents the quantity index corresponding to the data dimension, represents at the th data dimension, the characteristic data value corresponding to the chip characteristic data, represents at the th data dimension, the reference data value corresponding to the standard memory chip, represents the th importance coefficient corresponding to the data dimension.

[0089] Specifically, the absolute difference refers to the absolute value of the difference between the chip characteristic data and the reference data of the standard memory chip on each data dimension. After considering the weighting of the importance coefficients of each data dimension, a comprehensive calculation is performed to obtain a value, which is used to measure the overall difference degree between the chip characteristic data and the standard reference data; the characteristic data value refers to the specific value of the chip actually measured or obtained on each data dimension, and these values reflect the actual performance, specifications and other characteristics of the chip; the reference data value refers to the value specified or expected to be achieved by the standard memory chip on each data dimension, which is a benchmark for comparing with the actual chip characteristic data value to evaluate whether the chip meets the standard or expected performance and specifications; the importance coefficient refers to the value used to represent the relative importance of each data dimension in the overall evaluation. Different data dimensions have different influence degrees on the performance, quality, applicability, etc. of the chip, and the importance coefficient is used to quantify this difference.

[0090] By mining the potential defect information in the difference analysis data, the present invention can early warn of possible chip performance problems or fault hazards, provide a key basis for quality control in the production process, and help to timely adjust the production process and reduce the defective rate.

[0091] Among them, the potential defect information refers to various types of information that are hidden in the result of the difference analysis between the chip feature data and the reference data of the standard memory chip, have not been significantly manifested yet, but can have an adverse impact on aspects such as chip performance, reliability, and stability. For example, minor differences in certain data dimensions may indicate potential process defects in the internal structure of the chip, or performance deviation trends that may cause failures under specific working conditions, etc. Optionally, the mining of potential defect information in the difference analysis data can be achieved through information mining tools, such as tools like Minitab, TensorFlow, etc.

[0092] Furthermore, by screening the suspicious packaging parts corresponding to the potential defect information and real-time monitoring the real-time working environment parameters of the storage chip to be tested, the present invention can accurately locate the packaging areas that may have problems, providing a clear direction for subsequent fault troubleshooting and repair, and improving the repair efficiency.

[0093] Among them, the suspicious packaging parts refer to the physical positions of the chips that may have packaging problems pointed to after mining potential defect information through the difference analysis of the chip feature data and the standard reference data. These parts can be parts such as the outer shell, pins, and sealing area of the chip packaging. For example, when it is found that there are differences between the electrical performance parameters of the chip and the standard values, after in-depth analysis, it is speculated that it may be due to the loose connection between the pins and the package body, resulting in unstable signal transmission. Then the connection part between this pin and the package body belongs to the suspicious packaging part; the real-time working environment parameters refer to various dynamic physical quantities in the environment where the storage chip to be tested is located during actual operation, which mainly include parameters such as environmental temperature, humidity, air pressure, and electromagnetic interference intensity. Too high or too low environmental temperature can affect the performance and stability of the chip, and even cause chip damage, so it is very crucial to monitor the temperature in real time. Changes in humidity may cause water vapor condensation inside the chip, triggering problems such as short circuits. Therefore, humidity is also an important monitoring parameter. Optionally, the screening of the suspicious packaging parts corresponding to the potential defect information can be achieved through the fault tree analysis method, such as: through the fault tree analysis, the packaging level and specific parts that may cause this problem can be traced, such as specific pin connections or internal circuit areas, so as to determine the suspicious packaging parts; the real-time monitoring of the real-time working environment parameters of the storage chip to be tested can be achieved through a sensor network, such as: installing high-precision temperature sensors on the test platform of the chip can obtain the temperature change situation around the chip in real time, so as to obtain the real-time working environment parameters.

[0094] Furthermore, by calculating the sensitivity value of the suspicious packaging parts affected by the environmental parameters, the present invention can quantify the specific influence degree of the environmental factors on the suspicious packaging parts, providing an accurate basis for formulating targeted protection measures, and helping to improve the stability and reliability of the chip in different environments.

[0095] Among them, the sensitivity value refers to a comprehensive index used to quantify the sensitivity of a suspicious packaging part to changes in environmental parameters. The larger this value, the more easily the suspicious packaging part is affected by changes in environmental parameters, resulting in changes in chip performance or the emergence of potential defects.

[0096] As an embodiment of the present invention, calculating the sensitivity value of the suspicious packaging part affected by environmental parameters includes:

[0097] Calculating the sensitivity value of the suspicious packaging part affected by environmental parameters using the following formula:

[0098]

[0099] Among them, represents the sensitivity value of the suspicious packaging part affected by environmental parameters, represents the number of types of corresponding environmental parameters, represents the quantity index corresponding to the environmental parameters, represents the th change range of the th type of environmental parameter, represents the influence weight coefficient of the and respectively represent the start time and end time of the evaluation time period, represents at time the performance change function corresponding to the suspicious packaging part.

[0100] Specifically, the change range refers to the change range or degree of each environmental parameter under certain conditions. For example, for the temperature environmental parameter, the change range can be the difference between the highest value and the lowest value of the temperature within a period of time; for the humidity environmental parameter, it can be the maximum fluctuation value of the humidity, etc. The influence weight coefficient refers to a value used to measure the importance degree of the influence of each environmental parameter on the suspicious packaging part. Different environmental parameters have different influence degrees on the packaging part. By assigning a weight coefficient to each environmental parameter; the evaluation time period refers to a specific time interval used to observe and calculate the influence of environmental parameters on the suspicious packaging part, which is determined by the start time and the end time . During this time period, the changes in environmental parameters and the performance changes of the suspicious packaging part are monitored and data is collected to calculate the sensitivity value; the performance change function refers to a function that describes the performance of the suspicious packaging part over time A changing mathematical function that reflects how the performance of a suspicious package site (such as resistance, capacitance, signal transmission quality, etc.) changes over time due to changes in environmental parameters during the evaluation period.

[0101] S3. Based on the sensitivity value, evaluate the types of failure risks that the storage chip to be tested may have. Based on the types of failure risks, locate the weak links in the package of the storage chip to be tested, perform performance detection on the weak links to obtain the link performance status, and find the specific problem points in the link performance status.

[0102] Based on the sensitivity value, the present invention evaluates the types of failure risks that the storage chip to be tested may have, can predict in advance the possible types of failures, provides a clear direction for preventive maintenance, reduces the probability of sudden failures occurring in the actual use of the chip, and improves the stability of the system.

[0103] Among them, the types of failure risks refer to various forms and categories of failure manifestations that may be caused by the influence of environmental parameters on the suspicious package sites of the storage chip. For example, thermal stress failures caused by temperature changes can cause package cracking or damage to the internal structure of the chip; short - circuit or leakage failures that may be caused by humidity; package sealing failure faults that can be caused by changes in air pressure; and signal transmission errors or data loss faults that may occur in an electromagnetic interference environment, etc. Optionally, the evaluation of the types of failure risks that the storage chip to be tested may have can be implemented through machine - learning algorithms, such as decision - tree algorithms, support vector machines and other algorithms.

[0104] Furthermore, based on the types of failure risks, the present invention locates the weak links in the package of the storage chip to be tested, can accurately focus on the problem area, provides a clear direction for subsequent optimization and improvement work, avoids blind troubleshooting, and improves the R & D and production efficiency.

[0105] Among them, the weak links refer to the parts or components in the package of the storage chip to be tested that are relatively vulnerable to the influence of failure risk factors, which may then lead to chip failures. Through a series of steps such as analyzing the influence weight of factors, sorting the risk factor sequence, constructing an association graph, and screening strong - association nodes, these weak links are finally located. These links may be due to reasons such as material properties, structural design, manufacturing processes, etc.

[0106] As an embodiment of the present invention, locating the weak links in the package of the storage chip to be tested based on the failure risk type includes: analyzing the factor influence weights corresponding to the failure risk factors in the failure risk type; sorting the failure risk factors based on the factor influence weights to obtain a risk factor sequence; constructing an association map between the risk factor sequence and the corresponding package components of the storage chip to be tested; screening the strong association nodes in the association map; and locating the weak links in the package of the storage chip to be tested based on the strong association nodes.

[0107] Among them, the factor influence weight refers to a numerical value used to measure the degree of influence of each failure risk factor in the failure risk type on the failure of the storage chip package, which reflects the relative importance of each risk factor when the chip package has problems. Different failure risk factors include temperature change, humidity fluctuation, mechanical stress, etc.; the risk factor sequence refers to an ordered list formed by sorting the failure risk factors according to the factor influence weights. In this sequence, each failure risk factor is arranged in order from largest to smallest (or from smallest to largest, depending on the specific sorting rule) according to its weight value; the association map refers to a graphical representation method that shows the relationship between the risk factor sequence and the corresponding package components of the storage chip to be tested. In this map, the risk factors are used as one type of node, and the package components are used as another type of node. The connection between the two is represented by a line, and the attributes such as the thickness or color of the line can be used to represent the strength of the association; the strong association nodes refer to the package component nodes in the association map that have a strong association relationship with the risk factors. The package components corresponding to these nodes are more likely to be affected by the risk factors. If the association strength threshold is set to 0.5, then the package housing node and the pin solder joint node with an association strength greater than 0.5 with the temperature change node belong to the strong association nodes.

[0108] Furthermore, the factor influence weights corresponding to the fault risk factors in parsing the fault risk types can be implemented through a weight parsing tool, such as tools like MATLAB, SPSS, etc.; the sorting process of the fault risk factors can be achieved through a sorting algorithm, such as algorithms like bubble sort, quick sort, etc.; the construction of the association map between the risk factor sequence and the corresponding packaging components of the storage chip to be tested can be realized through a map construction method, such as using a graph database (such as Neo4j) to store and manage these entities and relationships, and constructing an association map with risk factors and packaging components as nodes and relationships as edges; the screening of strong association nodes in the association map can be achieved through a threshold-based screening method, such as by traversing all the edges in the association map and screening out the packaging component nodes connected by the edges with an association strength greater than the threshold as strong association nodes; the positioning of the weak links in the storage chip package to be tested can be realized through a link positioning tool, such as tools like ATE, ANSYS, etc.

[0109] By performing performance detection on the weak links, the present invention obtains the link performance status, and can accurately and intuitively understand the actual operating conditions of the weak links, providing exact data support for subsequent optimization and improvement.

[0110] Among them, the link performance status refers to the comprehensive performance of various performance indicators presented by the weak links in the storage chip package after performance detection, which covers the characteristics of the weak links in multiple aspects such as physics and electricity, such as the mechanical strength and heat conduction performance of the weak parts of the packaging shell, and the conductivity and connection stability of the weak parts such as pin soldering points. Optionally, the performance detection of the weak links can be realized through machine learning algorithms, such as algorithms like support vector machines, neural networks, etc.

[0111] Furthermore, by searching for specific problem points in the link performance status, the present invention can achieve a fine diagnosis of the weak links, clarify the specific factors leading to poor performance, and provide a strong basis for targeted measures.

[0112] Among them, the specific problem points refer to the precise fault locations or causes leading to performance anomalies determined after a comprehensive analysis of the link performance status, which are the final results obtained after a series of steps such as analyzing the state performance indicators, constructing a mapping relationship framework, determining preliminary classification problems, and referring to historical case data. The specific problem points can be actual fault situations such as the cracking of a certain solder joint in the chip package, the short circuit of a certain circuit segment, and the material aging of a certain component.

[0113] As an embodiment of the present invention, the finding of specific problem points in the performance state of the link includes: analyzing the state performance indicators corresponding to the performance state of the link; constructing a mapping relationship framework corresponding to the state performance indicators; based on the mapping relationship framework, analyzing the preliminary classification problems corresponding to the performance state of the link; collecting historical case data corresponding to the preliminary classification problems; and based on the historical case data, finding specific problem points in the performance state of the link.

[0114] Among them, the state performance indicators refer to a series of quantitative parameters used to measure and describe the performance state of weak links. These indicators can reflect the performance characteristics of weak links from multiple dimensions. For example, in terms of electrical performance, they can include resistance, capacitance, inductance, signal transmission delay, etc.; in terms of thermal performance, they cover thermal conductivity, thermal resistance, temperature distribution, etc.; in terms of mechanical performance, there are strength, hardness, elastic modulus, etc. The mapping relationship framework refers to a logical structure that establishes a connection between state performance indicators and problem types that may occur. Through in-depth research on the physical characteristics, working principles, and past failure experiences of weak links, it summarizes the corresponding relationships between changes in different performance indicators and corresponding problems. This framework can help quickly locate the potential problem directions caused by abnormal performance indicators. The preliminary classification problems refer to the preliminary classification of possible problems based on the abnormal conditions of the link performance state indicators under the guidance of the mapping relationship framework. They are not specific problem points but roughly classify problems according to nature and category, narrowing the scope of problem finding. By matching and analyzing the state performance indicators with the mapping relationship framework, the problem categories to which performance anomalies can belong are determined, such as electrical fault categories, thermal performance fault categories, mechanical structure fault categories, etc. The historical case data refers to the records of similar situations that have occurred in the past in similar memory chip packages or related electronic components and are similar to the current preliminary classification problems. These data contain information such as the performance state indicators at that time, the specific problems found, the methods to solve the problems, and the final processing results.

[0115] Furthermore, the state performance indicators corresponding to the analysis of the performance state of the link can be implemented through filtering algorithms. For example, when the temperature sensor collects the temperature data of the chip package, the Kalman filtering algorithm is used to predict and update the data, removing noise interference to obtain more accurate temperature performance indicator data. The construction of the mapping relationship framework corresponding to the state performance indicators can be implemented through association rule mining algorithms. For example, by analyzing the electrical performance indicator data and the electrical fault data that occur in a large number of chips, the association rules between a certain electrical performance indicator (such as capacitance value) changing within a certain range and a certain electrical fault (such as short circuit) are mined, thereby constructing the mapping relationship framework. The analysis of the preliminary classification problem corresponding to the performance state of the link can be implemented through data analysis tools. For example, tools such as Excel can analyze and organize the performance indicator data through functions such as pivot tables to assist in the preliminary classification problem. The collection of the historical case data corresponding to the preliminary classification problem can be implemented through web crawler tools. For example, write a Scrapy crawler program to crawl the posts about chip package failures from electronic technology forums and extract the historical case data from them. The search for specific problem points in the performance state of the link can be implemented through a logic analyzer. For example, use a logic analyzer to collect the digital signals of the chip, analyze the timing relationship and logical state of the signals, and find the specific problem points caused by signal anomalies.

[0116] S4. Based on the specific problem points, formulate the test planning objectives corresponding to the storage chip to be tested, analyze the test means in the test planning objectives, query the test standards corresponding to the test means, and based on the test standards, generate the test operation instructions corresponding to the storage chip to be tested.

[0117] Based on the specific problem points, the present invention formulates the test planning objectives corresponding to the storage chip to be tested, which can achieve precise focus of the test, avoid resource waste and time consumption caused by blind comprehensive testing, and improve the quality and reliability of the storage chip.

[0118] Among them, the test planning objective refers to a detailed test plan and the expected test effect formulated for the storage chip to be tested based on the determined functional module scope. It includes clarifying the specific content of the test, such as which performance indicators to test for each functional module, what test methods and tools to use; determining the execution order of the test, reasonably arranging the sequence of testing for each functional module to improve the test efficiency; setting the expected results of the test, that is, the chip performance indicators and functional requirements expected to be achieved through the test; and also including the resource allocation plan, such as the allocation of human, material and time resources, etc.

[0119] As an embodiment of the present invention, formulating a test planning objective corresponding to the storage chip to be tested based on the specific problem points includes: analyzing the relationship characteristics between the specific problem points and the functional modules in the storage chip to be tested; based on the relationship characteristics, identifying the influence degree of the functional modules in the storage chip to be tested; performing hierarchical processing on the module influence degree to obtain a hierarchical result; determining the range of functional modules corresponding to key tests according to the hierarchical result; and formulating a test planning objective corresponding to the storage chip to be tested based on the range of functional modules.

[0120] Among them, the functional module refers to an independent component with a specific function in the storage chip to be tested. These modules work together to jointly implement various functions of the storage chip, such as data storage, reading, erasing, etc. Each functional module has its unique circuit structure and design purpose. For example, the address decoding module is responsible for converting the input address signal into a corresponding storage unit selection signal; the storage array module is the place where data is actually stored and consists of a large number of storage units; the control logic module is used to coordinate the work of each module to ensure the correct reading and writing of data and the normal operation of the chip. The module influence degree refers to the size and scope of the influence of the specific problem points on the performance and normal operation of each functional module in the storage chip. This influence degree can be measured in various ways, such as the probability of the problem point causing a failure in the functional module, the amplitude of the performance degradation of the functional module, and the influence of the problem point on the key degree of the entire chip function on the functional module. The hierarchical result refers to the result obtained after classifying and hierarchically dividing the module influence degree. According to certain rules and standards, each functional module is divided into different levels according to the degree of its influence by the specific problem points. The range of functional modules refers to the set of functional modules that need to be key tested determined according to the hierarchical result. This range clarifies the functional modules that need to be focused on and detected during the test to ensure that functional module failures that may be caused by specific problem points can be discovered and solved in a timely manner.

[0121] Further, the analysis of the relationship characteristics between the specific problem points and the functional modules in the storage chip to be tested can be achieved through the FMEA method. For example, in the FMEA analysis, for the control logic module of the storage chip, considering its failure modes may include logical errors, signal transmission delays, etc., the signal interference problem in the specific problem points is associated with it, and the impact on the function of this module is analyzed, so as to determine the relationship characteristics between the two. The identification of the impact degree of the functional modules corresponding to the storage chip to be tested can be achieved through an automatic test equipment. For example, when testing the data transmission module, different data sequences are input by the ATE, and at the same time, the conditions of the specific problem points (such as signal attenuation) are introduced, and the error rate of data transmission is measured by the ATE, so as to quantify the impact degree of the module. The hierarchical processing of the impact degree of the module can be achieved through a threshold-based hierarchical method. For example, different impact degree thresholds are set, and the impact degree of the functional module is compared with them, and divided into different levels, and finally the hierarchical result is obtained. The determination of the range of the functional modules corresponding to the key tests can be achieved through a data visualization tool. For example, the data of the impact degree of the module is visually displayed in Tableau, and by setting different screening conditions and color markings, the range of the functional modules for key tests is intuitively determined. The formulation of the test planning objectives corresponding to the storage chip to be tested can be achieved through a test management tool. For example, information such as the range of the functional modules of the storage chip and the specific problem points is input into the TestLink tool, and according to its template and functions, test cases and test plans are formulated for each functional module, so as to generate the test planning objectives.

[0122] By analyzing the test means in the test planning objectives of the present invention and querying the test standards corresponding to the test means, the scientificity and standardization of the test means can be ensured. Operating according to the clear test standards helps to discover possible deficiencies or irrationalities in the test planning, and timely adjust and improve it, making the test planning more reasonable and efficient.

[0123] Among them, the test means refer to the specific methods, technologies, tools, and operation processes adopted when testing a storage chip to achieve the test planning objectives. It includes actual measures for detecting various aspects such as the chip's function, performance, and reliability. For example, when testing the data read and write function of a storage chip, the test means can be using a dedicated storage test device to write a specific data sequence into the chip and then read these data to check the accuracy of the read and write operations; it can also be using software tools to simulate different read and write operation environments, such as different data transfer rates, different storage capacity loads, etc. for testing. The test standard refers to a series of specifications, guidelines, and indicators widely recognized in the field of storage chip testing for measuring whether the test results are qualified. These standards are usually formulated by industry organizations, national standards institutions, or chip manufacturers themselves according to factors such as the type, use, and performance requirements of the chip. The test standards cover various performance dimensions of the chip, including functional integrity, performance index ranges (such as read and write speeds, storage capacity, power consumption, etc.), reliability indicators (such as lifespan, fault tolerance ability, etc.), and security requirements, etc. Optionally, the analysis of the test means in the test planning objectives can be achieved through function-oriented analysis methods. For example, for the data storage function module of a storage chip, analyze how to test functions such as storage capacity, storage speed, and data retention ability to determine the corresponding test means. The query of the test standards corresponding to the test means can be achieved through standard database retrieval methods. For example, using a professional standard database, by inputting relevant parameters of the storage chip (such as chip type, functional characteristics, application scenarios, etc.) as retrieval conditions, query the corresponding test standards.

[0124] Furthermore, based on the test standards, the present invention generates test operation instructions corresponding to the storage chip to be tested, which can standardize and regularize the test operations, ensure that each test is executed according to a unified standard, reduce human errors, and improve the consistency and repeatability of the tests.

[0125] Among them, the test operation instructions refer to converting each operation step into specific and executable instructions according to the operation test process. These instructions are usually presented in a concise and clear language or a specific code form, and are used to guide testers or automated test systems to perform actual test operations. The test operation instructions should be detailed and accurate, and include information such as the object of the operation, the content of the operation, and the requirements of the operation.

[0126] As an embodiment of the present invention, generating the test operation instructions corresponding to the storage chip to be tested based on the test standard includes: parsing the item clause details corresponding to the test standard; sorting out the item test phases corresponding to the storage chip to be tested based on the item clause details; extracting the key test elements in the item test phases; determining the operation test process corresponding to the storage chip to be tested based on the key test elements; and generating the test operation instructions corresponding to the storage chip to be tested based on the operation test process.

[0127] Among them, the item clause details refer to the specific articles that specify various test contents in the test standard, which include detailed information in multiple aspects such as the purpose of the test, scope of application, test conditions, test methods, pass / fail criteria, etc. For example, in the read / write speed test standard of a storage chip, the item clause details will clearly specify specific parameters such as the data block size used during the test, the frequency of read / write operations, and the temperature and humidity range of the test environment; the item test phase refers to dividing the entire test process into different phases according to the item clause details, each phase having its specific test objectives and tasks, and there being a certain logical order between the phases. For example, for the test of a storage chip, it can usually be divided into an initial detection phase, a function test phase, a performance test phase, a reliability test phase, and an environmental adaptability test phase, etc.; the key test elements refer to the factors that play a key role in achieving the test objectives during the item test phase, and these elements include test equipment, test methods, test environmental conditions, the number of test samples, etc. For example, during the performance test phase of a storage chip, the accuracy and stability of the test equipment, the scientific nature of the test method, and the temperature and humidity control of the test environment are all key test elements; the operation test process refers to the process formed by arranging each operation step in the test process in sequence based on the key test elements, which details the entire process from test preparation to test end, including how to connect the test equipment, how to set the test parameters, how to perform the test operations, how to record the test data, and the handling methods when problems occur during the test process.

[0128] Further, the parsing of the project clause details corresponding to the test standard can be achieved through a syntactic analysis tool. For example, by using a syntactic analysis tool, the logical relationships between key terms and clauses can be extracted, and finally the project clause details can be obtained. The sorting of the project test phases corresponding to the storage chip to be tested can be achieved through the work breakdown structure method. For example, according to the functional characteristics and test requirements of the storage chip, the test can be divided into different phases such as initialization test, functional test, performance test, and reliability test, and finally the project test phases can be obtained. The extraction of the key test elements in the project test phases can be achieved through the principal component analysis method. For example, by performing PCA analysis through the Scikit-learn library in Python, the key indicators that have a greater impact on the test results, that is, the key test elements, can be found. The determination of the operation test process corresponding to the storage chip to be tested can be achieved through the Petri net modeling method. For example, use the CPN Tools software to establish a Petri net model for the storage chip test, and through the reachability analysis and simulation of the model, optimize and determine the operation test process. The generation of the test operation instructions corresponding to the storage chip to be tested can be achieved through a scripting language tool. For example, for the read and write function test of the storage chip, use the unittest framework of Python to write specific test cases and operation instructions, and finally obtain the test operation instructions.

[0129] S5. After applying the test operation instructions to the storage chip to be tested, perform a package test operation on the storage chip to be tested to obtain a packaged test chip, collect the electrical performance data corresponding to the packaged test chip, and perform stability verification on the electrical performance data to obtain verification result data. Based on the verification result data, generate a package test report corresponding to the storage chip to be tested.

[0130] By applying the test operation instructions to the storage chip to be tested and then performing a package test operation on the storage chip to be tested to obtain a packaged test chip, the present invention can effectively guarantee the packaging quality of the storage chip, and can accurately detect problems that may occur during the chip packaging process, such as poor pin connection and poor packaging tightness, so as to make timely improvements and enhance the overall stability of the chip.

[0131] Among them, the packaged and tested chip refers to a chip product that has completed the transformation from a bare chip to a complete physical form and has undergone comprehensive performance testing after packaging and testing operations. After chip manufacturing, it is first packaged in a specific housing, which not only protects the internal circuits of the chip but also provides electrical connection and physical support for the chip. Subsequently, according to strict test operation instructions, it undergoes comprehensive performance testing, covering aspects such as electrical performance, mechanical performance, and environmental adaptability. Optionally, applying the test operation instructions to the storage chip to be tested can be achieved through an automated test device. For example, the written test operation instructions are imported into the ATE system, and then through the interface connection between the ATE and the storage chip to be tested, the chip is automatically tested according to the instructions; performing the packaging and testing operation on the storage chip to be tested can be achieved through a packaging and testing platform. For example, the storage chip to be tested is placed on a test fixture, and parameters such as temperature, pressure, and humidity of the chip during the packaging process are monitored in real time through sensors and compared and analyzed with preset standard values to finally obtain the packaged and tested chip.

[0132] Furthermore, the present invention collects the electrical performance data corresponding to the packaged and tested chip and verifies the stability of the electrical performance data to obtain verification result data, which can promptly detect potential problems in the electrical performance of the chip, such as voltage fluctuations and current instability. Moreover, the verification result data provides a key basis for evaluating whether the chip meets the usage standards, ensuring that the chips put into use have stable and reliable electrical performance and reducing the failure risk in actual applications.

[0133] Among them, the electrical performance data refers to a set of key parameters characterizing the electrical characteristics of the packaged and tested chip, covering values such as resistance, capacitance, inductance, voltage, current, signal transmission delay, and frequency response, reflecting the electrical performance of the chip under different working conditions; the verification result data refers to the analysis results obtained after verifying the stability of the electrical performance data, including stability evaluation conclusions, data fluctuation ranges, abnormal data records, and comparison with standards. Optionally, collecting the electrical performance data corresponding to the packaged and tested chip can be achieved through electrical test instruments. For example, taking an oscilloscope as an example, the probe is connected to the relevant pins of the packaged and tested chip, appropriate sampling frequencies and time ranges are set, and data such as voltage, current, and signal waveforms of the chip under different working states are collected to finally obtain the electrical performance data; verifying the stability of the electrical performance data can be achieved through SPC tools. For example, a control chart is drawn, and by observing whether the data points in the control chart exceed the control limits and whether there are abnormal fluctuation trends, the stability of the electrical performance data is judged to finally obtain the verification result data.

[0134] Furthermore, based on the verification result data, the present invention generates a package test report corresponding to the storage chip to be tested, providing a comprehensive and objective evaluation record for the package quality and performance of the chip, facilitating a clear understanding of the actual situation of the chip. This report can serve as an important basis for quality control, helping to timely detect problems, trace the causes, and take effective improvement measures during the production process to improve product quality.

[0135] Among them, the package test report refers to a detailed record and summary document of the process and results of the storage chip package test, which covers basic chip information, including model, specifications, etc.; details the test items, such as test contents of electrical performance, mechanical performance, environmental adaptability, etc.; focuses on presenting the verification result data, such as the stability evaluation conclusion of electrical performance data, the specific values of various performance indicators and their comparison with the standards; and also gives a comprehensive evaluation to determine whether the chip passes the test, and if not, points out the existing problems and improvement suggestions. Optionally, generating the package test report corresponding to the storage chip to be tested can be achieved through a report generation tool. For example, input the verification result data and relevant test information (such as test items, test methods, test equipment, etc.) into the TestRail system, and the system will automatically generate a package test report with a standardized format according to a preset template.

[0136] Compared with the problems described in the background art, the present invention helps to deeply understand the internal structure and physical characteristics of the chip by obtaining the original parameter information corresponding to the storage chip to be tested and collecting the package structure data in the original parameter information, providing a basic basis for subsequent performance evaluation, and being able to accurately judge whether the chip meets specific design and production standards to ensure product quality. By comparing and analyzing the chip feature data with the reference data of the standard storage chip, the present invention obtains differential analysis data, which can accurately locate the deviations of the chip in terms of performance, structure, etc., providing a clear direction for quality control and helping to screen out unqualified products in a timely manner. Further, based on the sensitivity value, the present invention evaluates the types of potential failure risks that the storage chip to be tested may have, can predict in advance the types of possible failures, provides a clear direction for preventive maintenance, reduces the probability of sudden failures occurring during the actual use of the chip, and improves the stability of the system. Further, based on the specific problem points, the present invention formulates the test planning objectives corresponding to the storage chip to be tested, can achieve precise focus of the test, avoid resource waste and time consumption caused by blind comprehensive testing, and improve the quality and reliability of the storage chip. Finally, after applying the test operation instructions to the storage chip to be tested, the present invention performs a package test operation on the storage chip to be tested to obtain a package test chip, which can effectively ensure the package quality of the storage chip and can accurately detect problems that may occur during the chip packaging process, such as poor pin connection and poor package sealing, so as to improve in a timely manner and enhance the overall stability of the chip. Therefore, the high-reliability storage chip package test method and system provided by the embodiments of the present invention can improve the stability of the storage chip.

[0137] Embodiment 2:

[0138] As Figure 2 shown, it is a functional module diagram of a high-reliability storage chip package test system of the present invention.

[0139] The high-reliability storage chip package test system 200 of the present invention can be installed in an electronic device. According to the functions achieved, the high-reliability storage chip package test system may include a feature extraction module 201, a sensitivity calculation module 202, a problem search module 203, an instruction generation module 204, and a report generation module 205. The modules of the present invention can also be referred to as units, which refer to a series of computer program segments that can be executed by a processor of an electronic device and can complete fixed functions, and are stored in the memory of the electronic device.

[0140] In the embodiments of the present invention, the functions of each module / unit are as follows:

[0141] The feature extraction module 201 is configured to obtain the original parameter information corresponding to the storage chip to be tested, collect the package structure data in the original parameter information, construct a three-dimensional model corresponding to the storage chip to be tested based on the package structure data, perform feature extraction on the three-dimensional model, and obtain chip feature data;

[0142] The sensitivity calculation module 202 is configured to compare and analyze the chip feature data with the reference data of a standard storage chip to obtain difference analysis data, mine potential defect information in the difference analysis data, screen the suspicious package parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the storage chip to be tested in real time, and calculate the sensitivity value of the suspicious package parts affected by the environmental parameters;

[0143] The problem finding module 203 is configured to evaluate the type of fault risk that the storage chip to be tested may have based on the sensitivity value, locate the weak link in the package of the storage chip to be tested based on the type of fault risk, perform performance detection on the weak link to obtain the link performance status, and find the specific problem points in the link performance status;

[0144] The instruction generation module 204 is configured to formulate a test planning target corresponding to the storage chip to be tested based on the specific problem points, analyze the test means in the test planning target, query the test standards corresponding to the test means, and generate test operation instructions corresponding to the storage chip to be tested based on the test standards;

[0145] The report generation module 205 is configured to, after applying the test operation instructions to the storage chip to be tested, perform a package test operation on the storage chip to be tested to obtain a package test chip, collect the electrical performance data corresponding to the package test chip, perform stability verification on the electrical performance data to obtain verification result data, and generate a package test report corresponding to the storage chip to be tested based on the verification result data.

[0146] Specifically, each module in the high-reliability storage chip package test system 200 in the embodiments of the present invention uses the same technical means as those Figure 1 described in the high-reliability storage chip package test method described above, and can produce the same technical effects, which will not be elaborated here.

[0147] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A high reliability memory chip packaging test method, characterized in that: The method comprises: Acquire original parameter information corresponding to the memory chip to be tested, collect package structure data in the original parameter information, construct a three-dimensional model corresponding to the memory chip to be tested based on the package structure data, perform feature extraction on the three-dimensional model, and obtain chip feature data; Compare and analyze the chip feature data with reference data of a standard memory chip to obtain difference analysis data, mine potential defect information in the difference analysis data, screen suspicious packaging parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the memory chip to be tested in real time, and calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters, wherein the calculation of the sensitivity value of the suspicious packaging parts affected by the environmental parameters includes: The following formula is used to calculate the sensitivity value of the suspected packaging part affected by the environmental parameters: in, Indicates the sensitivity value of the suspected packaging part affected by environmental parameters, Indicates the number of types corresponding to environmental parameters, Indicates the quantity index corresponding to the environmental parameters, Indicates The range of change corresponding to the environmental parameters, Indicates The weight coefficient of the influence of various environmental parameters on the suspicious packaging parts, and Respectively represent the start time and end time of the evaluation period, Indicates at time The performance change function corresponding to the suspicious packaging part at the moment; Based on the sensitivity value, evaluate the possible fault risk type of the memory chip to be tested, locate the weak link in the package of the memory chip to be tested based on the fault risk type, perform performance detection on the weak link, obtain the link performance status, and find the specific problem point in the link performance status; Based on the specific problem points, formulate a test planning target corresponding to the memory chip to be tested, analyze the test means in the test planning target, and query the test standard corresponding to the test means, and generate a test operation instruction corresponding to the memory chip to be tested based on the test standard; After applying the test operation instruction to the memory chip to be tested, a packaging test operation is performed on the memory chip to be tested to obtain a packaging test chip, electrical performance data corresponding to the packaging test chip is collected, and stability verification is performed on the electrical performance data to obtain verification result data, and based on the verification result data, a packaging test report corresponding to the memory chip to be tested is generated.

2. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The step of extracting features from the three-dimensional model to obtain chip feature data includes: Identifying contour edge lines corresponding to internal structures in the three-dimensional model; Performing grid processing on the contour edge lines to obtain regular grid units; Analyzing the connection relationship between adjacent grids of the regular grid unit; Based on the connection relationship, determining the topological structure point corresponding to the three-dimensional model; Based on the topological structure points, feature extraction is performed on the three-dimensional model to obtain chip feature data.

3. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The step of comparing and analyzing the chip characteristic data with reference data of a standard memory chip to obtain difference analysis data includes: Determine the data dimension corresponding to the chip characteristic data and the reference data of the standard memory chip; Based on the data dimension, calculating the absolute difference between the chip characteristic data and the reference data of the standard memory chip; Performing data statistics on the absolute differences to obtain a difference statistics set; Based on a preset threshold range, dividing the data threshold points in the difference statistical set; Based on the data threshold point, the chip characteristic data is compared and analyzed with reference data of a standard memory chip to obtain difference analysis data.

4. The high reliability memory chip packaging and testing method according to claim 3, characterized in that: The calculating, based on the data dimension, an absolute difference between the chip characteristic data and reference data of a standard memory chip comprises: The absolute difference between the chip characteristic data and the reference data of the standard memory chip is calculated using the following formula: in, represents the absolute difference between the chip characteristic data and the reference data of the standard memory chip, Indicates the total number corresponding to the data dimension, Indicates the quantity index corresponding to the data dimension, Indicated in The characteristic data value corresponding to the chip characteristic data in the data dimension, Indicated in The reference data value corresponding to the standard storage chip in the data dimension is: Indicates The importance coefficient corresponding to each data dimension.

5. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The locating the weak link in the memory chip package to be tested based on the failure risk type includes: Analyze the factor impact weights corresponding to the fault risk factors in the fault risk type; Based on the factor influence weights, the fault risk factors are sorted to obtain a risk factor sequence; Constructing a correlation map between the risk factor sequence and the packaging components corresponding to the memory chip to be tested; Filtering strongly associated nodes in the association graph; Based on the strongly associated nodes, weak links in the memory chip package to be tested are located.

6. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The step of searching for specific problem points in the performance status of the link includes: Analyze the status performance indicators corresponding to the performance status of the link; Constructing a mapping relationship framework corresponding to the state performance indicators; Based on the mapping relationship framework, analyzing the preliminary classification problems corresponding to the performance status of the links; Collect historical case data corresponding to the preliminary classification questions; Based on the historical case data, find the specific problem points in the performance status of the link.

7. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The formulating of a test planning target corresponding to the memory chip to be tested based on the specific problem point includes: Analyzing the relationship characteristics between the specific problem points and the functional modules in the memory chip to be tested; Based on the relationship characteristics, identifying the module impact degree corresponding to the functional module in the memory chip to be tested; Performing hierarchical processing on the impact degree of the modules to obtain hierarchical results; According to the stratification results, determine the functional module scope corresponding to the key test; Based on the functional module scope, a test planning target corresponding to the memory chip to be tested is formulated.

8. The high reliability memory chip packaging and testing method according to claim 1, characterized in that: The step of generating a test operation instruction corresponding to the memory chip to be tested based on the test standard includes: Analyze the project terms and conditions corresponding to the test standards; Based on the project terms and conditions, sort out the project test phases corresponding to the memory chip to be tested; Extract key test elements in the project testing phase; Based on the key test elements, determining the operation test process corresponding to the memory chip to be tested; Based on the operation test process, a test operation instruction corresponding to the memory chip to be tested is generated.

9. A high reliability memory chip packaging and testing system, characterized in that: The system comprises: A feature extraction module is used to obtain original parameter information corresponding to the memory chip to be tested, collect package structure data in the original parameter information, construct a three-dimensional model corresponding to the memory chip to be tested based on the package structure data, and perform feature extraction on the three-dimensional model to obtain chip feature data; The sensitivity calculation module is used to compare and analyze the chip feature data with the reference data of the standard memory chip to obtain difference analysis data, mine the potential defect information in the difference analysis data, screen the suspicious packaging parts corresponding to the potential defect information, and monitor the real-time working environment parameters of the memory chip to be tested in real time, and calculate the sensitivity value of the suspicious packaging parts affected by the environmental parameters, wherein the calculation of the sensitivity value of the suspicious packaging parts affected by the environmental parameters includes: The following formula is used to calculate the sensitivity value of the suspected packaging part affected by the environmental parameters: in, Indicates the sensitivity value of the suspected packaging part affected by environmental parameters, Indicates the number of types corresponding to environmental parameters, Indicates the quantity index corresponding to the environmental parameters, Indicates The range of change corresponding to the environmental parameters, Indicates The weight coefficient of the influence of various environmental parameters on the suspicious packaging parts, and Respectively represent the start time and end time of the evaluation period, Indicates at time The performance change function corresponding to the suspicious packaging part at the moment; A problem finding module is used to evaluate the possible fault risk type of the memory chip to be tested based on the sensitivity value, locate the weak link in the package of the memory chip to be tested based on the fault risk type, perform performance detection on the weak link, obtain the link performance status, and find the specific problem point in the link performance status; An instruction generation module is used to formulate a test planning target corresponding to the memory chip to be tested based on the specific problem point, analyze the test means in the test planning target, and query the test standard corresponding to the test means, and generate a test operation instruction corresponding to the memory chip to be tested based on the test standard; A report generation module is used to apply the test operation instruction to the memory chip to be tested, perform a packaging test operation on the memory chip to be tested, obtain a packaging test chip, collect electrical performance data corresponding to the packaging test chip, and perform stability verification on the electrical performance data to obtain verification result data, and generate a packaging test report corresponding to the memory chip to be tested based on the verification result data.

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