Chip patch detection method and system based on machine vision

Abstract

The invention discloses a chip patch detection method and system based on machine vision, and the method comprises the steps: collecting PCB chip patch pictures of different manufacturers through a CMOS industrial camera, and obtaining an original picture data set; performing manual annotation and data amplification on the original picture data set to generate a first data set and a second data set; according to the method, a ResNet50-based multi-task network is designed, chip classification and detection training are performed on a first data set, and a chip classification test result and a chip state test result are obtained; and then, screening and carrying out lightweight YOLOv10 model training on the second data set to obtain a chip defect test result, and the method realizes comprehensive detection of chip types and chip defects by a factory, realizes double improvement of chip detection precision and chip detection efficiency, and improves automatic quality detection efficiency of the factory.

Description

Technical Field

[0001] The present invention relates to the field of machine learning technology, and in particular to a chip patch detection method and system based on machine vision. Background Art

[0002] In recent years, with the rapid development of my country's electronic industry, the demand for chips in electronic products has also increased, and the chip industry has been formed. Chip packaging technology is an important link in the chip industry and is developing towards high density, high precision and high speed. Among them, chip mounting is one of the core industries of packaging. The quality of chip mounting directly affects the performance, reliability and yield of the chip. Traditional manual or mechanical alignment methods can no longer meet the stringent requirements of modern advanced packaging. The introduction of machine vision provides a key solution for high-precision mounting.

[0003] At present, a Chinese invention with application number CN115861259A discloses a lead defect detection algorithm based on template matching and color contrast. The algorithm can check the lead position and color defects, but cannot determine whether there are contaminated areas on the chip lead surface and whether the chip body has scratches; the paper "Research on Automatic Optical Detection of Partial Defects of Surface Mount Chips" proposes a defect detection method for surface mount chips. The method uses FAST feature point extraction based on local and global grayscale differences to achieve coarse positioning and pin group extraction, but still requires manual feature design, and there is a possibility of poor performance in complex scenarios, and poor generalization ability; in addition, a type of chip requires a template to be made for matching, which has a small scope of application and requires more R&D costs. Summary of the invention

[0004] The technical problems solved by the present invention are: failure to detect whether there is a contaminated area on the chip surface, and the specific location of defects such as scratches on the chip body; failure to get rid of manual design during the chip detection process, and poor generalization ability under complex defect scenarios; the chip type model is too low in terms of chip model and has a small scope of application.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: In the first aspect, a chip patch detection method and system based on machine vision is characterized by comprising: Step S100, using a CMOS industrial camera to collect PCB chip patch images from different manufacturers to obtain an original image data set; Step S200, performing a first process on the original image data set to obtain first data and second data, and performing a second process on the first data and the second data to generate a first data set and a second data set; Step S300, inputting the first data set into a multi-task network based on ResNet50, performing chip classification and detection training, and obtaining chip classification test results and chip status test results; Step S400, screening the second data set, and performing lightweight YOLOv10 model training to obtain chip defect test results.

[0006] The first data set includes: picture number, picture storage location, chip model and chip status; The second data set includes: picture number, picture storage location, chip model and chip defect type; The chip models include: 01, 02 and 03; The chip status includes: normal status and defective status; The chip defect types include: A, B, C and D.

[0007] Preferably, step S100 specifically includes: The lens of the CMOS industrial camera is fine-tuned, the lens magnification of the CMOS industrial camera is matched with the chip size of different manufacturers, and the PCB board chip patches of three different manufacturers are photographed to obtain the original image data set, which includes the image number, the image storage path and the chip model.

[0008] Preferably, step S200 specifically includes: The first processing includes: extracting the original image data set, manually labeling the original image data set at the frame level using the labelImg tool, manually marking the chip status and the chip defect type, saving the chip status and the original image data set as first data, screening the data with defective chip status and making a one-to-one correspondence with the original image data set, and saving as second data; The second processing includes: performing data augmentation processing on the first data and the second data, performing horizontal and vertical flipping, Gaussian noise perturbation and random rotation on the image, and amplifying the labeled image data three times to obtain a first data set and a second data set.

[0009] Preferably, step S300 specifically includes: Step S301, designing a multi-task network based on ResNet50, wherein the multi-task network includes a chip classification branch network and a state detection branch network; Step S302, inputting the first data set into the chip classification branch network for training to obtain a chip classification test result; Step S303: input the first data set into the state detection branch network for training to obtain a chip state test result.

[0010] Preferably, step S400 specifically includes: According to the defect type data in the second data set, the lightweight YOLOv10 model is trained using the defect type data to obtain a chip defect test result.

[0011] Preferably, the frame-level manual labeling includes: manually screening out defective image data in the original image data set, using LabelImg to label the defective image data with rectangular frames, using rectangular frames of different colors to circle different categories of defect types in the image, and generating a corresponding label document.

[0012] Preferably, the multi-task network includes: a chip classification branch network and a state detection branch network; ResNet50 is used as the basic model of the multi-task network, and the layers before the threshold in ResNet50 are used as shared feature extraction layers, the shared feature extraction layers include the initial convolution layer and the first two residual stage layers, and the layers after the threshold are divided into two branches for the two tasks of chip classification and state detection; The chip classification branch network includes: after the image passes through the convolutional neural network of the shared feature extraction layer, a feature map is output, the feature map is resized through a convolutional layer and enters the average pooling layer for further dimensionality reduction, and the fully connected layer is set to , classification is performed through the classification loss activation function to obtain the chip model classification result. The calculation expression of the classification loss activation function is: ; in, is the classification loss value, is the sample size, is the number of categories, The actual label is Sample The probability of For the multi-task network, for the sample Belongs to category The predicted probability of The state detection branch network includes: adopting a two-layer fully connected structure, the image data is reduced in the number of channels through the first layer of full connection, and activated by RELU, and then input into the second layer of full connection, the number of channels is increased to the original number, and the Sigmoid function is used for normalization. Finally, the state detection is performed through the defect loss function to obtain the state detection structure. The defect loss function calculation expression is: ; in, is the defect loss value, Output prediction for the state detection branch network, is the true label value; The final loss is obtained by using the classification loss activation function of the chip classification branch network and the defect loss function calculation results of the state detection branch network. The calculation expression of the final loss is: ; in, is the overall loss function, is the task weight.

[0013] Preferably, the lightweight YOLOv10 model includes: The number of training rounds, batch size, learning rate, and weight decay were set. The Adam optimization algorithm was used to divide the second data set into an 8:2 ratio and substitute it into the YOLOv10 model for training to obtain the accuracy of the defect results.

[0014] Second, the chip placement inspection system based on machine vision is implemented, including image acquisition module, image processing module, chip inspection module and defect classification module; The image acquisition module is used to collect original image data, and uses an industrial camera to shoot PCB board chips of various manufacturers, and the collected chip patch images are used as the original image data set; The image processing module is used to process the original image data set, manually label the images according to the labelImg tool used in the first processing, and then perform a second processing on the data set to perform data amplification on the data set to obtain a first data set and a second data set; The chip detection module is used to perform model classification and defect detection on the chip image, and uses the multi-task network of ResNet50 to train the chip image and obtain test results; The defect classification module is used to build a lightweight YOLOv10 test model to perform real-time defect classification detection on defective chips and compare the detection results with those of the YOLOv8 model.

[0015] The beneficial effects of the present invention are as follows: based on a standardized CMOS industrial camera, chip images are collected, and a two-stage process of manual annotation and data amplification is used to greatly improve the defect recognition rate of small samples. In addition, the present invention supports an adaptive white balance algorithm for PCBs of multiple manufacturers. When a new chip defect type appears, the model can be effectively trained and a new defect classification can be generated. The present invention also proposes a multi-task network model structure based on ResNet, which specifically classifies chip models and whether the chip has defects. Finally, a real-time defect type detection method based on YOLOv10 is used to mark the chip defect position and give the defect type, thereby achieving a balance between accuracy and efficiency and improving the factory's automated quality inspection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the basic flow of a chip placement detection method based on machine vision provided by an embodiment of the present invention.

[0017] Figure 2 A schematic diagram of basic modules of a chip placement detection system based on machine vision provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings. It is obvious that the described embodiments are only part of the embodiments of the present invention, but not all of the embodiments.

[0019] Example 1, reference Figure 1 , as an embodiment of the present invention, provides a chip patch detection method based on machine vision, comprising: Step S100, using a CMOS industrial camera to collect PCB chip patch images from different manufacturers to obtain an original image data set; Step S200, performing a first process on the original image data set to obtain first data and second data, and performing a second process on the first data and the second data to generate a first data set and a second data set; Step S300, inputting the first data set into a multi-task network based on ResNet50, performing chip classification and detection training, and obtaining chip classification test results and chip status test results; Step S400, screening the second data set, and performing lightweight YOLOv10 model training to obtain chip defect test results.

[0020] In this embodiment, chip samples from three factories are collected by CMOS industrial cameras to ensure the richness and diversity of the data. The collected data sets are then processed to obtain a first data set and a second data set. The first data set is used for chip classification and state analysis, and the second data set is used for defect type detection to improve data utilization. Multi-task network training is then performed on the data sets to achieve collaborative learning, reduce repeated calculations and enhance the generalization ability of the model. Finally, the YOLOv10 lightweight model is selected for chip defect detection, which can perform real-time quality inspection on chips produced by the factory, greatly improving production efficiency and batch inspection yield.

[0021] The first data set includes: picture number, picture storage location, chip model and chip status; The second data set includes: picture number, picture storage location, chip model and chip defect type; Chip models include: 01, 02 and 03; The chip status includes: normal status and defective status; Chip defect types include: A, B, C and D.

[0022] In this embodiment, the chip models are divided into three categories, namely BGA, QFN and MLCC, and are replaced by 01, 02 and 03. Each chip model category has two states: the chip is normal or defective. The types of defective chips are scratches, oil stains, missing pins and bent pins, and are replaced by A, B, C, D in turn.

[0023] Step S100 specifically includes: The lens of the CMOS industrial camera is fine-tuned to match the lens magnification of the CMOS industrial camera with the chip size of different manufacturers. The PCB chip patches of three different manufacturers are photographed to obtain the original image data set, which includes the image number, image storage path and chip model.

[0024] In this embodiment, the optical parameters of Intel's BGA package, TI's QFN package, and Murata's MLCC device are calibrated respectively, and a unified acquisition environment (light source color temperature 6500K, illumination 1000lux±5%) is used for image acquisition to reduce the noise introduced by hardware differences and improve the cross-vendor migration capability of subsequent models.

[0025] Step S200 specifically includes: The first processing includes: extracting the original image data set, manually annotating the original image data set at the frame level using the labelImg tool, manually marking the chip status and chip defect type, saving the chip status and the original image data set as the first data, screening the data with defective chip status and making a one-to-one correspondence with the original image data set, and saving it as the second data; The second processing includes: performing data augmentation processing on the first data and the second data, performing horizontal and vertical flipping, Gaussian noise perturbation and random rotation on the image, and amplifying the labeled image data three times to obtain the first data set and the second data set.

[0026] In this embodiment, the first data is fully labeled, and the chip status is manually labeled on the original image data set, that is, whether the chip has defects and the chip defect type. The second data is a special defect label to form a high-purity defect data set, which improves the fine-grained and defect detection capabilities for subsequent YOLOv10 training; in the data augmentation process, the image data is flipped, rotated, and Gaussian noise is introduced. Gaussian noise , the dataset has been expanded three times, providing a diverse and realistic dataset for subsequent model training.

[0027] Step S300 specifically includes: Step S301, designing a multi-task network based on ResNet50, where the multi-task network includes a chip classification branch network and a state detection branch network; Step S302, inputting the first data set into the chip classification branch network for training to obtain a chip classification test result; Step S303: input the first data set into the state detection branch network for training to obtain a chip state test result.

[0028] In this embodiment, the multi-task network of ResNet50 is divided into two branches, and the first data set is processed separately to generate different test results. The first branch is the chip classification branch, which is mainly used to classify and identify chip models. The second branch is defect detection, which is mainly used to distinguish whether the chip is defective. The training of the above two steps performs coarse classification of the chip images in the data set to prepare data for subsequent real-time detection.

[0029] Step S400 specifically includes: According to the defect type data in the second data set, the lightweight YOLOv10 model is trained using the defect type data to obtain the chip defect test results, and a performance comparison analysis is performed with the current YOLOv8 model to generate a lightweight YOLOv10 test model.

[0030] In this embodiment, through structural reparameterization and dynamic label allocation technology, the advantages of using YOLOv10 reasoning are significant while maintaining the accuracy of YOLOv8.

[0031] Table 1: Comparison table of YOLOv8 and YOLOv10.

[0032] Through table comparison, the YOLOv10 model has significantly improved the speed and accuracy of chip detection.

[0033] Box-level manual annotation includes: The defective image data in the original image data set is manually screened out, and LabelImg is used to annotate the defective image data with rectangular frames. Rectangular frames of different colors are used to circle the different types of defects in the image, and the corresponding label documents are generated.

[0034] In this embodiment, red, yellow, blue and green borders are used on the picture to frame the defective parts of chip scratches, oil stains, missing pins and bent pins respectively. This method intuitively presents complex defects through refined labeling in human-machine collaboration, and uses the LabelImg tool to relatively reduce the labeling error rate.

[0035] The multi-task network includes: chip classification branch network and state detection branch network; ResNet50 is used as the basic model of the multi-task network. The layers before 23 in ResNet50 are used as shared feature extraction layers. The shared feature extraction layers include the initial convolution layer and the first two residual stage layers. The layers after the threshold are divided into two branches for the two tasks of chip classification and status detection. The chip classification branch network includes: after the image passes through the convolutional neural network of the shared feature extraction layer, the feature map is output, the feature map is resized through a convolutional layer and enters the average pooling layer for further dimensionality reduction, and the fully connected layer is set to , classification is performed through the classification loss activation function to obtain the chip model classification result. The calculation expression of the classification loss activation function is: ; in, is the classification loss value, is the sample size, is the number of categories, The actual label is Sample The probability of For the multi-task network, for the sample Belongs to category The predicted probability of The state detection branch network includes: a two-layer fully connected structure, the image data is fully connected in the first layer to reduce the number of channels, and activated by RELU, and then input into the second layer of full connection to increase the number of channels to the original number, and normalized by Sigmoid function, and finally the state detection is performed by the defect loss function to obtain the state detection structure. The defect loss function calculation expression is: ; in, is the defect loss value, Output prediction for the state detection branch network, is the true label value; The final loss is obtained by using the classification loss activation function of the chip classification branch network and the defect loss function calculation results of the state detection branch network. The calculation expression of the final loss is: ; in, is the overall loss function, is the task weight.

[0036] In this example, the Adam optimizer is used, the number of training rounds of the multi-task network is set to 100 epochs, the batch size is set to 32, the learning rate is set to 0.00001, the weight decay is set to 5e-4, and the input image resolution is uniformly adjusted to , Table 2: Experimental sample data table.

[0037] As shown in the chart, the chip category label (chip_type) is represented by 01, 02 and 03, corresponding to the three chip categories of BGA, QFN and MLCC respectively. The chip status (Status) is divided into NG and OK, corresponding to the presence of defects and normal without defects respectively. The storage path (image_path) indicates the folder location of the image. In addition, set different weight factors , in order to comprehensively examine the effect of multi-task learning network in balancing tasks, in each The multi-task learning network was trained under the value of , and the overall loss value of the multi-task network model was calculated by evaluating the accuracy of the performance on the validation set. The following figure shows the experimental results of different weight factors: Table 3: Loss results for different weight factor settings.

[0038] From the table data, when When the value is 0.4, the overall model achieves the highest accuracy of 98.4%, thus achieving a balanced effect of the multi-task network.

[0039] The lightweight YOLOv10 model includes: Set the number of training rounds, batch size, learning rate, and weight decay. Use the Adam optimization algorithm to divide the second data set into an 8:2 ratio and substitute it into the YOLOv10 model for training to obtain the accuracy of the defect results.

[0040] In this embodiment, the training parameters of the YOLOv10 model are set, the number of training rounds is 200 epochs, the batch size is 16, the initial learning rate is 0.001, and the weight decay is 5e-4. The defective data set is imported into the YOLOv10 model for training. Through the coordinated optimization of hyperparameters and the improvement of the model structure, while maintaining the real-time performance of the YOLO series, the Pareto optimality of accuracy-speed-volume is achieved compared with the YOLOv8 model, thereby achieving a comprehensive improvement in chip detection speed and accuracy.

[0041] Example 2, reference Figure 2 This is another embodiment of the present invention. This embodiment is different from the first embodiment in that it provides a chip placement detection system based on machine vision.

[0042] The chip placement inspection system based on machine vision includes an image acquisition module, an image processing module, a chip inspection module, and a defect classification module; The image acquisition module is used to collect original image data. It uses industrial cameras to photograph PCB chips from various manufacturers, and the collected chip patch images are used as the original image data set. The image processing module is used to process the original image data set, manually label the images according to the labelImg tool used in the first processing, and then perform the second processing on the data set to amplify the data to obtain the first data set and the second data set; The chip detection module is used to classify the chip model and detect defects. It uses the ResNet50 multi-task network to train the chip image and obtain test results. The defect classification module is used to build a lightweight YOLOv10 test model to perform real-time defect classification detection on defective chips and compare the detection results with those of the YOLOv8 model.

[0043] In this embodiment, through the pipeline design of image acquisition, processing, detection and classification, the whole process from raw data to defect classification is automated, which significantly improves the factory inspection efficiency. The labelImg tool is used for manual labeling and data amplification to manually adjust the data set, which effectively solves the problem of insufficient scene samples in the factory. When entering the chip inspection module and the defect classification module, the method of fusion of dual model advantages is used. First, the ResNet50 multi-task network is used to simultaneously realize chip model classification and defect existence detection according to its residual structure, and the data set is processed efficiently. Secondly, for defect type differentiation, the latest YOLOv10 lightweight model is used to improve the detection speed and maintain the advantage of high-precision inspection, providing a more efficient technical means for factory chip defect detection.

[0044] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. Among them, the storage medium may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random Access Memory, referred to as SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, referred to as EEPROM), erasable programmable read-only memory (Erasable Programmable Read Only Memory, referred to as EPROM), programmable read-only memory (Programmable Red-Only Memory, referred to as PROM), read-only memory (Read-Only Memory, referred to as ROM), magnetic memory, flash memory, magnetic disk or optical disk. These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0045] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A chip placement detection method based on machine vision, characterized in that: include: Step S100, using a CMOS industrial camera to collect PCB chip patch images from different manufacturers to obtain an original image data set; Step S200, performing a first process on the original image data set to obtain first data and second data, and performing a second process on the first data and the second data to generate a first data set and a second data set; Step S300, inputting the first data set into a multi-task network based on ResNet50, performing chip classification and detection training, and obtaining chip classification test results and chip status test results; Step S400, screening the second data set, and performing lightweight YOLOv10 model training to obtain chip defect test results.

2. The chip placement detection method based on machine vision as claimed in claim 1, characterized in that: The first data set includes: picture number, picture storage location, chip model and chip status; The second data set includes: picture number, picture storage location, chip model and chip defect type; The chip models include: 01, 02 and 03; The chip status includes: normal status and defective status; The chip defect types include: A, B, C and D.

3. The chip placement detection method based on machine vision as claimed in claim 1, characterized in that: Step S100 specifically includes: The lens of the CMOS industrial camera is fine-tuned, the lens magnification of the CMOS industrial camera is matched with the chip size of different manufacturers, and the PCB board chip patches of three different manufacturers are photographed to obtain the original image data set, which includes the image number, the image storage path and the chip model.

4. The chip placement detection method based on machine vision as claimed in claim 1, characterized in that: Step S200 specifically includes: The first processing includes: extracting the original image data set, manually labeling the original image data set at the frame level using the labelImg tool, manually marking the chip status and the chip defect type, saving the chip status and the original image data set as first data, screening the data with defective chip status and making a one-to-one correspondence with the original image data set, and saving as second data; The second processing includes: performing data augmentation processing on the first data and the second data, performing horizontal and vertical flipping, Gaussian noise perturbation and random rotation on the image, and amplifying the labeled image data three times to obtain a first data set and a second data set.

5. The chip placement detection method based on machine vision as claimed in claim 1, characterized in that: Step S300 specifically includes: Step S301, designing a multi-task network based on ResNet50, wherein the multi-task network includes a chip classification branch network and a state detection branch network; Step S302, inputting the first data set into the chip classification branch network for training to obtain a chip classification test result; Step S303: input the first data set into the state detection branch network for training to obtain a chip state test result.

6. The chip placement detection method based on machine vision as claimed in claim 1, characterized in that: Step S400 specifically includes: The lightweight YOLOv10 model is trained according to the defect type data in the second data set and using the defect type data.

7. The chip placement detection method based on machine vision as claimed in claim 4, characterized in that: The frame-level manual labeling includes: manually screening out defective image data in the original image data set, using LabelImg to label the defective image data with rectangular frames, using rectangular frames of different colors to circle different categories of defect types in the image, and generating corresponding label documents.

8. The chip placement detection method based on machine vision as claimed in claim 5, characterized in that: The multi-task network includes: a chip classification branch network and a state detection branch network; ResNet50 is used as the basic model of the multi-task network, and the layers before the threshold in ResNet50 are used as shared feature extraction layers, the shared feature extraction layers include the initial convolution layer and the first two residual stage layers, and the layers after the threshold are divided into two branches for the two tasks of chip classification and state detection; The chip classification branch network includes: after the image passes through the convolutional neural network of the shared feature extraction layer, a feature map is output, the feature map is resized through a convolutional layer and enters the average pooling layer for further dimensionality reduction, and the fully connected layer is set to , classification is performed through the classification loss activation function to obtain the chip model classification result. The calculation expression of the classification loss activation function is: ； in, is the classification loss value, is the sample size, is the number of categories, The actual label is Sample The probability of For the multi-task network, for the sample Belongs to category The predicted probability of The state detection branch network includes: adopting a two-layer fully connected structure, the image data is reduced in the number of channels through the first layer of full connection, and activated by RELU, and then input into the second layer of full connection, the number of channels is increased to the original number, and the Sigmoid function is used for normalization. Finally, the state detection is performed through the defect loss function to obtain the state detection structure. The defect loss function calculation expression is: ; in, is the defect loss value, Output prediction for the state detection branch network, is the true label value; The final loss is obtained by using the classification loss activation function of the chip classification branch network and the defect loss function calculation results of the state detection branch network. The calculation expression of the final loss is: ; in, is the overall loss function, is the task weight.

9. The chip placement detection method based on machine vision as claimed in claim 6, characterized in that: The lightweight YOLOv10 model includes: setting the number of training rounds, batch size, learning rate, and weight decay, using the Adam optimization algorithm, dividing the second data set in a ratio of 8:2, substituting it into the YOLOv10 model for training, and obtaining the accuracy of the defect results.

10. A chip patch detection system based on machine vision, which is implemented based on the chip patch detection method based on machine vision according to any one of claims 1 to 9, characterized in that: It includes image acquisition module, image processing module, chip detection module and defect classification module; The image acquisition module is used to collect original image data, and uses an industrial camera to shoot PCB board chips of various manufacturers, and the collected chip patch images are used as the original image data set; The image processing module is used to process the original image data set, manually label the images according to the labelImg tool used in the first processing, and then perform a second processing on the data set to perform data amplification on the data set to obtain a first data set and a second data set; The chip detection module is used to perform model classification and defect detection on the chip image, and uses the multi-task network of ResNet50 to train the chip image and obtain test results; The defect classification module is used to build a lightweight YOLOv10 test model to perform real-time defect classification detection on defective chips and compare the detection results with those of the YOLOv8 model.

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