Offset calibration method and apparatus for high bandwidth memory 3

Abstract

The invention discloses a computer-implemented method for offset calibration and an integrated circuit memory controller for offset calibration. The method comprises the steps of: performing an offset calibration of a read data gated replica receiver; adjusting pad voltages of the read data strobe original receiver and the read data strobe replica receiver based on the offset calibration value of the read data strobe replica receiver; and performing offset calibration of the original receiver of the read data strobe based on the offset calibration value of the pad voltage, wherein the differential input from the differential strobe signal pin to the pass gate of the replica receiver of the read data strobe is disabled during offset calibration of the replica receiver of the read data strobe.

Description

Technical Field

[0001] The present invention relates to an offset calibration method for High Bandwidth Memory 3 (HBM3), and in particular to an offset calibration method using a pad voltage divider to reduce signal attenuation. Background Art

[0002] A memory technology called HBM3 provides bandwidth and data transfer rates for modern computer systems. As memory technology advances to reach its full potential, precise signal integrity becomes increasingly necessary. A key factor in ensuring resilient data transfer is the adjustment of signal skew.

[0003] Offset calibration techniques have been limited in previous HBM3 inventions, especially in terms of reducing signal degradation. Conventional methods have difficulty maintaining signal integrity, which often leads to a reduced need for creative calibration methods that can handle signal degradation. A method to strategically reduce signal degradation is needed to further enhance signal quality and ensure seamless high-speed data transmission.

[0004] Many solutions have been proposed for transferring data in computer memory, some of which are discussed below:

[0005] US10720201B2 discloses a device for receiving an input signal in a semiconductor device. An exemplary information receiver receiving a signal includes: a control circuit providing a plurality of control signals, and a signal receiver replica circuit receiving a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each of the plurality of receivers receives the first reference signal and a corresponding control signal in the plurality of control signals, and further provides an output signal.

[0006] US2014314173A1 discloses an automatically calibrated differential amplifier, comprising: an input stage differential amplifier for receiving an input differential signal, differentially amplifying the input differential signal to generate an input stage output differential signal, and having an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental changes. The differential amplifier can be included in, for example, a comparator and a multi-stage receiver.

[0007] The replica circuit disclosed in JP2012090167A is variable in impedance and outputs a voltage corresponding to the impedance. A reference voltage generating part outputs a reference voltage according to a power supply voltage to an output buffer. A comparing part compares the output voltage of the replica circuit with the reference voltage. An adjusting part adjusts the impedance of the replica circuit according to the comparison result of the comparing part.

[0008] However, there are still many problems with the above references and other prior art, and the purpose and features of the present invention attempt to solve these problems. For example, industries such as computer architecture need to deal with signal attenuation problems. Therefore, it can be seen that it is necessary to provide a solution, especially to overcome the above problems, to achieve better performance in high-speed slot HBM3. Summary of the invention

[0009] A simplified summary of the present invention is given below to provide a basic understanding of some aspects of the present invention. This summary is not an extensive overview of the present invention. Its sole purpose is to present some concepts of the present invention in a simplified form as a prelude to a more detailed description presented later.

[0010] It is an object of the present invention to provide a computer-implemented method of an offset calibration method to minimize pad attenuation.

[0011] Another object of the present invention is to form a potential divider to adjust the pad voltage for original receiver offset calibration of read-data strobe.

[0012] Another object of the present invention is to use the replica receiver of the read data strobe as a comparator to calibrate the differential pad voltage to a common reference voltage value for offset calibration of the original receiver of the read data strobe.

[0013] Another object of the present invention is to provide a replica of an original receiver delay for read data strobe for timing calibration of an original receiver signal period VT for read data strobe.

[0014] Accordingly, these objects can be achieved by following the teachings of the present invention. The present invention relates to an integrated circuit (IC) memory controller for offset calibration, comprising: an original receiver of a read data strobe, for receiving and processing a read data strobe signal; a replica receiver of the read data strobe, communicatively connected to the original receiver of the read data strobe; a pad voltage divider, connecting the pad voltage of the original receiver of the read data strobe and the pad voltage of the replica receiver of the read data strobe; and a transmitter, each transmitter being connected to a positive read data strobe and a negative read data strobe to adjust the pad voltage; wherein the replica receiver of the read data strobe calibrates the pad voltage of the differential voltage to a common voltage for the read data strobe offset calibration of the receiver.

[0015] The present invention also relates to a computer-implemented method based on a pad voltage divider, which is used for offset calibration of an integrated circuit memory controller, comprising the following steps: performing offset calibration of a replica receiver of read data enable; adjusting the pad voltages of an original receiver of read data enable and a replica receiver of read data enable based on the offset calibration value of the replica receiver of read data enable; and performing offset calibration of the original receiver of read data enable according to the offset calibration value of the pad voltage; wherein the transmission gate from the differential enable signal pin to the differential input of the replica receiver of read data enable is disabled during the offset calibration of the replica receiver of read data enable.

[0016] The foregoing and other objects, features, aspects and advantages of the present invention will be better understood by carefully reading the detailed description provided below and referring to the accompanying drawings as appropriate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to enable the above-mentioned features of the present invention to be understood in detail, a more specific description of the present invention briefly summarized above may have been mentioned by way of examples, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present invention and therefore should not be considered as limiting the scope of the present invention, as the present invention may allow other equally effective embodiments.

[0018] These and other features, benefits and advantages of the present invention will become apparent by reference to the following text and drawings, in which like reference numerals refer to like structures throughout the several views, and in which:

[0019] Figure 1 is a flow chart illustrating a computer-implemented method for original receiver offset calibration of a read data strobe according to an embodiment of the present invention;

[0020] Figure 2 is a flow chart illustrating a computer-implemented method for replica receiver offset calibration of a read data strobe according to an embodiment of the present invention;

[0021] Figure 3 is a flow chart illustrating a computer-implemented method for adjusting a positive receiver pad voltage for a read data strobe according to an embodiment of the present invention;

[0022] Figure 4 shows an iterative process of pull-up and pull-down drive control adjustment according to an embodiment of the present invention;

[0023] Figure 5 is a flow chart illustrating a computer-implemented method for original receiver offset calibration of a read data strobe according to an embodiment of the present invention; and

[0024] Figure 6 An overview of the offset calibration scheme based on pad divider design is shown. DETAILED DESCRIPTION

[0025] Although the present invention is described herein by using the examples of embodiments and illustrative drawings, it will be appreciated by those skilled in the art that the present invention is not limited to the one or more embodiments of the drawings described, and is not intended to represent the scope of various components. In addition, for ease of explanation, some components that may form a part of the present invention may not be shown in some drawings, and such omissions do not limit the embodiments outlined in any way. It should be understood that the drawings and detailed descriptions are not intended to limit the present invention to the specific form disclosed, on the contrary, the present invention covers all modifications, equivalents and alternatives falling within the scope of the present invention defined by the appended claims. As used throughout the specification, the word "may" is used in a permissive sense (i.e., meaning with possibility) rather than in a mandatory sense (i.e., meaning must). In addition, unless otherwise mentioned, the word "one" or "an" means "at least one", and the word "multiple" means "one or more". In addition, the terms and wordings used herein are for descriptive purposes only and should not be interpreted as limiting the scope. Language such as "includes," "comprising," "having," "containing," or "involving" and variations thereof are intended to be broad and include the subject matter listed thereafter, equivalents, and additional subject matter not recited, and are not intended to exclude other additives, components, integrations, or steps. Likewise, the term "includes" is considered synonymous with the terms "including" or "containing" for applicable legal purposes. Any discussion of documents, acts, materials, devices, articles, etc. is included in the specification solely to provide a context for the present invention. There is no suggestion or representation that any or all of these matters form part of the prior art base or are common general knowledge in the field relevant to the present invention.

[0026] In the present disclosure, whenever a composition, element or group of elements is preceded by the transition phrase "comprising", it should be understood that we also contemplate the same composition, element or group of elements wherein the transition phrase "consisting of", "consisting of", "selected from the group consisting of", "including" or "is" is recited before the composition, element or group of elements, and vice versa.

[0027] The present invention will be described below by various embodiments with reference to the accompanying drawings, wherein the reference numerals used in the accompanying drawings correspond to the same elements throughout the specification. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. In the following detailed description, numerical values ​​and ranges for various aspects of the described implementation are provided. These values ​​and ranges are considered as examples only and are not intended to limit the scope of the claims. In addition, many materials are determined to be suitable for various aspects of the embodiments. These materials will be considered as exemplary and are not intended to limit the scope of the present invention.

[0028] refer to Figures 1 to 6 With reference to the accompanying drawings, the invention will now be described in more detail.

[0029] One embodiment of the present invention relates to a computer-implemented method for offset calibration of an integrated circuit memory controller, comprising the following steps: performing offset calibration of a replica receiver of a read data strobe; adjusting the pad voltages of an original receiver of the read data strobe and a replica receiver of the read data strobe based on the offset calibration value of the replica receiver of the read data strobe; performing offset calibration of the original receiver of the read data strobe according to the offset calibration value of the pad voltage; wherein, during the offset calibration of the replica receiver of the read data strobe, a transmission gate from a differential selection signal pin to a differential input of the replica receiver of the read data strobe is disabled; wherein, during the read data strobe pad voltage adjustment, a double calibration of a drive control signal is performed, and an average value is taken for the calibration results.

[0030] According to an embodiment of the present invention, a computer-implemented method for performing offset calibration of a replica of a read data selected original receiver signal includes the following steps: shortening the differential inputs of the read data selected replica receiver and assigning the differential inputs of the read data selected replica receiver to a common reference voltage value; outputting the voltage value to an offset calibration finite state machine for decision making; and repeatedly short-circuiting until the read data selected replica receiver output changes to a transition point.

[0031] According to an embodiment of the present invention, the transmission gates from the differential strobe signal to the replica receiver differential inputs of the read data strobe are disabled to prevent any contention.

[0032] According to an embodiment of the present invention, a positive offset is introduced by repeatedly shorting until the replica receiver output of the read data strobe changes to a transition point where the intrinsic offset of the replica receiver of the read data strobe changes from a negative offset to a positive offset.

[0033] According to an embodiment of the present invention, the last code before triggering the switch is stored and applied as the offset control code of the final replica receiver.

[0034] According to an embodiment of the present invention, the receiver replica offset calibration ends and the process continues with the read data strobe pad voltage adjustment.

[0035] According to an embodiment of the present invention, a computer-implemented method for adjusting the pad voltages of an original receiver of read data strobe and a replica receiver of read data strobe based on an offset calibration value of a replica receiver of read data strobe includes the following steps: based on the offset calibration value of the replica receiver of read data strobe, aligning the pad voltages, positive read data strobe and negative read data strobe to a common reference voltage value; passing a differential strobe signal voltage to the input of the replica receiver of read data strobe and creating a potential voltage divider at the differential strobe signal to transmit the voltage to the original receiver of read data strobe.

[0036] According to an embodiment of the present invention, memory drive strength options for both pull-up and pull-down are adjusted during read data strobe pad voltage regulation.

[0037] According to an embodiment of the present invention, a differential strobe signal voltage is delivered to the input of a replica receiver of a read data strobe and prevents a short circuit between a transmission gate at the input of the replica receiver of the read data strobe and an internal reference voltage from being generated.

[0038] According to an embodiment of the present invention, the memory drive control signal is calibrated twice with an input chop control setting, and the final value of the drive control signal is obtained by averaging the calibration results obtained from the input chop control setting. The input chop control is performed to eliminate any residual offset in the replica receiver of the read data strobe so that it does not affect the read data strobe pad voltage regulation.

[0039] According to an embodiment of the present invention, performing offset calibration of an original receiver with read data enabled based on an offset calibration value of a pad voltage includes the following steps: allocating a common reference voltage on the original receiver with read data enabled based on the calibration value of the pad voltage of the original receiver with read data enabled; configuring the transmission of the differential enable signal to be tristate to restore the electrical signal of the differential pad voltage; and converting the differential pad voltage back to a functional mode.

[0040] According to an embodiment of the present invention, an integrated circuit (IC) memory controller for offset calibration includes: an original receiver of read data enable, which is used to receive and process a read data enable signal; a replica receiver of read data enable is communicatively connected to the original receiver of read data enable; a pad voltage divider, which connects the pad voltage of the original receiver of read data enable and the pad voltage of the replica receiver of read data enable; and a transmitter, each transmitter is connected to a positive read data enable and a negative read data enable to adjust the pad voltage; wherein the replica receiver of read data enable calibrates the pad voltage of the differential voltage to a common voltage for use in the receiver's read data enable offset calibration.

[0041] According to an embodiment of the present invention, a differential strobe signal pin is connected to a receiver data strobe input.

[0042] According to an embodiment of the present invention, the finite state machine (FSM) in the design can be implemented as synthetic hardware logic on a chip, or can be programmed by firmware by reading and writing control registers related to offset cancellation.

[0043] According to an embodiment of the present invention, the receiver data strobe replica acts as a comparator to calibrate the differential pad voltage to a common reference voltage value for receiver data strobe offset calibration.

[0044] According to an embodiment of the present invention, the transmission of the read data strobe enables conversion of the read data strobe pin into a write data strobe pin for chip-to-chip connection.

[0045] According to an embodiment of the present invention, a read data strobe transmission acts as a variable resistor to form a potential voltage divider with a dynamic random access memory (DRAM) differential strobe signal transmitter to adjust the pad voltage for original receiver offset calibration of the read data strobe.

[0046] According to an embodiment of the present invention, the offset control of the original receiver and the offset control of the replica receiver behave perpendicular to the offset cancellation, where the lowest code is the maximum negative offset and the highest code is the maximum positive offset.

[0047] Below, embodiments of the present invention will be provided to explain in more detail. From these embodiments, advantages of the present invention can be more easily understood and put into practice. However, it should be understood that the following embodiments do not limit the scope of the present invention in any way.

[0048] Description of the Subcircuit

[0049] RxDQS Read data strobe to the original receiver RxDQS Copy Read data strobe replica receiver diff_vcal_en Differential voltage calibration enable Rep_oc_cal Replica offset calibration enable Vref Reference voltage OC CAL FSM(REP) Replica finite state machine for offset calibration OC CAL FSM(ACT) Original finite state machine for offset calibration Pu_drv_ctrl Pull-up drive control Pd_drv_ctrl Pull-down drive control RDQS_t Positive read data strobe RDQS_c Negative Read Data Strobe Input_chop Input truncation control RxDQS_offset_ctrl Offset control of the original receiver RxDQS_replica_offset_ctrl Drift Control for Replica Receivers Tx RxDQS Read data strobe transmitter

[0050] Example

[0051] Example 1: RxDQS replica offset calibration

[0052] For context of the ensuing discussion, Figure 6 The behavior of the receiver offset control (RxDQS_offset_ctrl) and the receiver replica offset control (RxDQS_replica_offset_ctrl) can be assumed in Table 1 below. A 5-bit bus width is used as an example, and the actual design may be different. As shown in Table 1, offset_ctrl 0 is the setting with the largest negative offset, and offset_ctrl 31 is the setting with the largest positive offset. From offset_ctrl 0 to offset_ctrl 31, positive offset is gradually introduced. The middle value of offset_ctrl 16 is the middle point where no offset cancellation is introduced, so it is the point where the offset cancellation is neutral.

[0053] First, the differential inputs of the replica receiver of the read data strobe (RxDQS replica) are shorted and assigned to a common reference voltage. This is accomplished by setting the replica offset calibration enable (Rep_oc_cal) to a logic 0, which tri-states the differential drivers within the delay voltage / temperature calibration stimulus generator and allows the internal reference voltage to be passed to the differential inputs. To prevent any contention from the differential strobe signals (RDQS_t / RDQS_c), the differential voltage calibration enable (diff_vcal_en) needs to be a logic 0, which disables all transmission gates from RDQS_t / RDQS_c to the RxDQS replica differential inputs.

[0054] Then, RxDQS_replica_offset_ctrl is set to 0, and the output of the RxDQS replica is obtained by the RxDQS replica's offset calibration replica finite state machine (OC CAL FSM REP) for decision making. Since RxDQS_replica_offset_ctrl == 5'd0 will produce the maximum negative offset, the RxDQS replica should output a logic 1 when the differential inputs are at the same voltage value. The process iteratively continues to increase the RxDQS_replica_offset_ctrl code to introduce a positive offset until the RxDQS replica output changes state from 1 to 0, which is the transition point at which the inherent offset of the RxDQS replica changes from a negative offset to a positive offset.

[0055] The last code before triggering the transition is stored and applied as the final RxDQS_replica_offset_ctrl code. The RxDQS replica offset calibration is finished and the process continues with the RxDQS pad voltage adjustment.

[0056] Example 2: RDQS pad voltage adjustment

[0057] After calibrating the offset of the RxDQS replica, the RxDQS replica is used as a comparator to calibrate and adjust the pad voltage, the positive read data strobe (RDQS_t), and the negative read data strobe (RDQS_c) to a common reference voltage value. Figure 3 The entire process of RDQS pad voltage adjustment is shown. By setting diff_vcal_en to 1, the voltages of RDQS_t and RDQS_c are passed to the input of the RxDQS replica. In addition, the replica offset calibration enable (Rep_oc_cal) must be set to "0" to prevent a short circuit with the internal reference voltage through the transmission gate at the input of the RxDQS replica.

[0058] In addition, the Mode Register 6 (MR6) of the HBM3 device is programmed to 7'd0, which will set the weakest DRAM driver strength option for both pull-up and pull-down. The transmitter for RDQS_t is then set to transmit logic "1", while the transmitter for RDQS_c is set to transmit logic "0". This will result in a potential voltage divider at RDQS_t and RDQS_c, as the DRAM transmits and drives "0" to RDQS_t and "1" to RDQS_c.

[0059] Figure 4 The figure shows that the pull-up drive control (Pu_drv_ctrl) and the pull-down drive control (Pd_drv_ctrl) are set to the initial value of the weakest driver strength of 0, where the pull-up drive control (Pu_drv_ctrl) and the pull-down drive control (Pd_drv_ctrl) control the pull-up drive strength and the pull-down drive strength of the transmitter of the read data strobe. Then, it will go through an iterative process to lock the Pu_drv_ctrl value and the Pd_drv_ctrl value.

[0060] Pu_drv_ctrl and Pd_drv_ctrl are calibrated twice, once when the input choke control (Input_chop) is set to 0 and once when Input_chop is set to 1. The final Pu_drv_ctrl and Pd_drv_ctrl values ​​are obtained by averaging the Pu_drv_ctrl and Pd_drv_ctrl values ​​obtained from Input_chop 0 and Input_chop 1. The main purpose of this process is to eliminate any residual offset in the RxDQS replica to avoid affecting the RDQS pad voltage regulation. As a result, an accurate common reference voltage value for RDQS_t and RDQS_c can be achieved.

[0061] Example 3: RxDQS offset calibration

[0062] After the RDQS pad voltage adjustment, the RDQS_t voltage and the RDQS_c voltage are now at a common reference voltage value, which can then be used to calibrate the offset of the original receiver of the read data strobe (RxDQS). Figure 6 The entire process of RxDQS offset calibration is shown. This process is very similar to the RxDQS replica offset calibration in Example 1, with the only difference being that the common reference voltage value on the RxDQS input is achieved through RDQS pad voltage adjustment. After the RxDQS offset is calibrated, the transmitter RDQS_t and the transmitter RDQS_c are configured as tri-states to allow the differential pad voltage to recover to the proper electrical signal before switching back to functional mode. In summary, since there is no need to switch pads for offset calibration at the RxDQS input, signal attenuation can be reduced and higher operating speeds are allowed.

[0063] The present invention overcomes the disadvantages of the prior art by providing an offset calibration method for HBM3, preferably using the proposed offset calibration method using pad voltage division. The offset correction method of the present invention helps reduce signal attenuation and allows higher operating speeds.

[0064] Various modifications to these embodiments will be apparent to those skilled in the art from the description and drawings. The principles associated with the various embodiments described herein may be applied to other embodiments. Therefore, this description is not intended to be limited to the embodiments described in conjunction with the attached drawings. Figure 1 The present invention is intended to provide the broadest scope consistent with the principles and novel and inventive features disclosed or proposed herein, and to apply to all other such substitutions, modifications and changes that fall within the scope of the present invention and the appended claims.

Claims

1. A computer-implemented method for offset calibration of an integrated circuit (IC) memory controller, characterized in that: The method comprises the following steps: performing an offset calibration of the replica receiver of the read data strobe; adjusting pad voltages of an original receiver of the read data strobe and a replica receiver of the read data strobe based on an offset calibration value of the replica receiver of the read data strobe, and performing an offset calibration of a copy receiver of the read data strobe based on the offset calibration value of the pad voltage; During the offset calibration of the replica receiver of the read data strobe, the differential inputs from the differential strobe signal pins to the transmission gates of the replica receiver of the read data strobe are disabled.

2. The computer-implemented method of claim 1, wherein: The offset calibration of the replica receiver of the read data strobe is performed by the following steps: shortening differential inputs of replica receivers of the read data strobe and assigning differential inputs of replica receivers of the read data strobe to a common reference voltage value; Outputting the voltage value to the offset calibration finite state machine for decision making; as well as The short circuit is repeated until the replica receiver output of the read data strobe changes to a transition point.

3. The computer-implemented method of claim 2, wherein: Also included is storing and applying a final receiver offset control code for a replica receiver of the read data strobe based on the transition point.

4. The computer-implemented method of claim 1, wherein: Adjusting pad voltages of the original receiver of the read data strobe and the replica receiver of the read data strobe based on the offset calibration value of the receiver replica comprises the following steps: Calibrate the pad voltage and the differential strobe signal and align to a common value based on an offset calibration value of a replica receiver of the read data strobe; passing the differential strobe signal voltage to an input of a replica receiver of the read data strobe; and A potential voltage divider is created at the differential strobe signal for delivering a voltage to a positive receiver of the read data strobe.

5. The computer-implemented method of claim 1, wherein: During the read data strobe pad voltage adjustment, memory drive strength options for both pull-up and pull-down are adjusted.

6. The computer-implemented method of claim 1, wherein: During the read data strobe pad voltage adjustment, a double calibration of the drive control signal is performed via an input cutoff control setting, and the calibration results are averaged.

7. The computer-implemented method of claim 1, wherein: Based on the offset calibration value of the pad voltage, performing an offset calibration of the original receiver of the read data strobe comprises the following steps: allocating a common reference voltage across the original receivers of the read data strobes based on a calibrated value of a pad voltage of the original receivers of the read data strobes; configuring a transmitter of a differential strobe signal to be tri-stated to restore an electrical signal of the differential pad voltage; and The differential pad voltage is switched back to functional mode.

8. An integrated circuit (IC) memory controller for performing the computer-implemented method of offset calibration as claimed in claim 1, comprising: The original receiver of the read data strobe is used to receive and process the read data strobe signal. It is characterized by further comprising: a replica receiver of the read data strobe, communicatively coupled to an original receiver of the read data strobe; a pad voltage divider connecting a pad voltage of an original receiver of the read data strobe and a pad voltage of a replica receiver of the read data strobe; and transmitters, each of the transmitters connected to a positive read data strobe and a negative read data strobe to adjust the pad voltage; The replica receiver of the read data strobe calibrates the pad voltage of the differential voltage to a common voltage for offset calibration of the original receiver of the read data strobe.

9. The IC memory controller according to claim 8, characterized in that: The differential strobe signal pins connect to the original receiver input of the read data strobe.

10. The IC memory controller according to claim 8, characterized in that The transmitter of the read data strobe forms a potential voltage divider together with the positive read data strobe transmitter and the negative read data strobe transmitter of the dynamic random access memory.

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