Memory chip and operating method thereof

Abstract

The invention discloses a storage chip and an operation method thereof, and the operation method comprises the steps: determining an operation state of a storage space as a partial programming state through one of the conditions that the written number of storage units in the storage space is smaller than or equal to a preset number, or a write address corresponding to a write instruction is smaller than a storage address of the storage space; the error correction mechanism is forbidden for the storage space in the partial programming state, and due to the fact that the number of written storage units in the storage space in the partial programming state is small, the high reading success rate can still be achieved even if the error correction mechanism is not adopted, and the adverse effects caused by the adoption of the error correction mechanism are reduced, for example, the error correction efficiency is improved. In the reading process, a thread for implementing an error correction mechanism needs to be added, so that the reading efficiency is reduced.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage chip and an operating method thereof. Background Art

[0002] In NOR Flash, error correction codes are usually calculated based on a storage space with a certain number of storage cells (CELLs). Each storage space may be in a different operating state. For storage cells in different operating states, some problems may be encountered during error correction. Summary of the invention

[0003] The present application provides a storage chip and an operating method thereof to alleviate the technical problem that it is difficult to determine the operating state of a storage space and whether an error correction mechanism is enabled.

[0004] In a first aspect, the present application provides an operating method for a memory chip, which includes one or more memory spaces, the operating method including: in response to the number of memory cells written in a memory space being less than or equal to a preset number, or the write address corresponding to a write instruction being less than one of the memory addresses of the memory space, determining that the operating state of the memory space is a partially programmed state; disabling an error correction mechanism for the memory space in the partially programmed state.

[0005] In some of the embodiments, in response to the number of storage cells written in a storage space being less than or equal to a preset number, the method includes: when the storage cells in the storage space are in an erased state or an unwritten state, disabling the error correction mechanism for the storage space that is judged to be in a partially programmed state based on the cumulative number of storage cells written in the storage space; or when there is already written data in the storage space, disabling the error correction mechanism for the storage space that is judged to be in a partially programmed state based on the total number of the already existing written data and the currently written data.

[0006] In some of the embodiments, in response to the number of storage units written in a storage space being less than or equal to a preset number, the method includes setting the preset number to be less than or equal to 1 / 2 or 1 / 3 of the total number of storage units in the storage space.

[0007] In some of the embodiments, the operating method also includes: in response to the number of storage units written in the storage space being greater than a preset number, or the write address corresponding to the write instruction includes the last address of the storage space, determining that the operating state of the storage space is an error correction protection state; enabling an error correction mechanism for the storage space in the error correction protection state.

[0008] In some of the embodiments, the error correction mechanism is disabled during the reading process for the storage space in the partially programmed state; and the error correction mechanism is enabled during the reading process for the storage space in the error correction protection state.

[0009] In some of the implementation modes, the operation method further includes: setting at least one flag bit to represent the operation status of the corresponding storage space.

[0010] In some embodiments, at least one mark bit is set to characterize the operating status of the corresponding storage space, including: configuring at least one mark bit to include a first mark bit, a second mark bit, and an error correction bit storing an error correction code; setting the first mark bit, the second mark bit, and the error correction bit to characterize the operating status of the corresponding storage space.

[0011] In some embodiments, the storage space includes a storage array, and a first mark bit, a second mark bit, and an error correction bit are set to represent the operating state of the corresponding storage space, including: setting the data in the first mark bit, the second mark bit, and the error correction bit in the storage array to all "1" to represent the partial programming state, the erased state, or the storage initial state of the corresponding storage space; or, setting the data in the first mark bit, the second mark bit, and the error correction bit in the storage array to all "0" to represent the multiple programming state of the corresponding storage space; or, setting the data in the first mark bit, the second mark bit, and the error correction bit in the storage array to neither all "1" nor all "0" to represent the error correction protection state of the corresponding storage space.

[0012] In some embodiments, the storage space also includes a page cache, the first mark bit includes a first cache mark bit located in the page cache and a first storage mark bit located in the storage unit, the second mark bit includes a second cache mark bit located in the page cache and a second storage mark bit located in the storage unit, the error correction bit includes a cache error correction bit located in the page cache and a storage error correction bit located in the storage unit, and the first mark bit, the second mark bit, and the error correction bit are set to characterize the operating state of the corresponding storage space, including: setting the first storage mark bit to have a first storage initial mark value or a first storage final mark value, the first storage initial mark value is the value of the first storage mark bit before the input data is written to the storage unit, and the first storage final mark value is the value of the first storage mark bit after the input data is written to the storage unit. The first storage mark bit after the input data is written to the storage unit is set; the second storage mark bit is set to have a second storage initial mark value or a second storage final mark value, the second storage initial mark value is the value of the second storage mark bit before the input data is written to the storage unit, and the second storage final mark value is the value of the second storage mark bit after the input data is written to the storage unit; the storage error correction bit is set to have a storage error correction initial value or a storage error correction final value, the storage error correction initial value is the value of the storage error correction bit before the input data is written to the storage unit, and the storage error correction final value is the value of the storage error correction bit after the input data is written to the storage unit; the operation state of the corresponding storage space is determined according to the first storage final mark value, the second storage final mark value, and the storage error correction final value.

[0013] In some embodiments, the operating method also includes: setting the first cache mark bit to have a first cache initial mark value, or a first cache intermediate mark value, the second cache mark bit to have a second cache initial mark value, or a second cache intermediate mark value, and the cache error correction bit to have a cache error correction initial value, or a cache error correction intermediate value; assigning the first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value as the first storage final mark value, the second storage final mark value, and the storage error correction final value, respectively.

[0014] In some of the embodiments, the operating method also includes: setting the first cache intermediate mark value to 0, 1, or the first cache calculated mark value; setting the second cache intermediate mark value to 0, 1, or the second cache calculated mark value; setting the cache error correction intermediate value to all 0, all 1, or the cache error correction calculated value; determining the first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value based on the first stored initial mark value, the second stored initial mark value, and the stored error correction initial value.

[0015] In some embodiments, the operating method also includes: setting the page cache data to the data of the data bit in the page cache after the input data is written to the page cache; setting the storage data to the data of the data bit in the storage unit before the input data is written to the storage unit; determining the first cache calculation mark value, the second cache calculation mark value, and the cache error correction calculation value based on the page cache data and the storage data.

[0016] In some embodiments, a first cache calculation mark value, a second cache calculation mark value, and a cache error correction calculation value are determined according to page cache data and storage data, including: determining the result of an AND logic operation of the page cache data and the storage data as intermediate comparison data; calculating an initial error correction code according to the intermediate comparison data; calculating the second cache calculation mark value according to the intermediate comparison data and the initial error correction code, and calculating the first cache calculation mark value and the cache error correction calculation value according to the initial error correction code; wherein, the result of a non-AND logic operation of a first logic detection result of determining whether each bit value of the initial error correction code is a logic value "0" and a second logic detection result of determining whether each bit value of the initial error correction code is a logic value "1" is the intermediate control data; wherein, a parity check is performed on the initial error correction code to obtain a parity check result, and the parity check result is inverted to obtain to a non-parity check result; wherein, an XOR operation is performed on the intermediate comparison data and the initial error correction code to obtain an XOR operation result, and the XOR operation result is inverted to obtain a non-XOR operation result; wherein, when the intermediate control data is "1", the non-XOR operation result and the non-parity check result are selected as the first cache calculation mark value and the second cache calculation mark value respectively; when the intermediate control data is "0", the XOR operation result and the parity check result are selected as the first cache calculation mark value and the second cache calculation mark value respectively; wherein, when the bit values ​​of the initial error correction code are all logical values ​​"0", a code different from the initial error correction code is converted as a cache error correction calculation value; or, when the bit values ​​of the initial error correction code are not all logical values ​​"0", the initial error correction code is directly output as the cache error correction calculation value.

[0017] In some of the embodiments, the operation state of the corresponding storage space is determined according to the first storage final mark value, the second storage final mark value, and the storage error correction final value, including: when the first storage final mark value, the second storage final mark value, and the storage error correction final value are all "0", the operation state of the storage space corresponding to the write instruction is determined to be a multiple programming state; or, when the first storage final mark value, the second storage final mark value, and the storage error correction final value are respectively the first cache calculation mark value, the second cache calculation mark value, and the cache error correction calculation value, the operation state of the storage space corresponding to the write instruction is determined to be an error correction protection state; or, when the first storage final mark value, the second storage final mark value, and the storage error correction final value are all logical values ​​"1", the operation state of the storage space is determined to be a partial programming state.

[0018] In a second aspect, the present application provides a storage chip, which includes a storage space, a determination module, and an execution module. The determination module is used to determine that the operating state of the storage space is a partially programmed state in response to the number of storage cells written in a storage space being less than or equal to a preset number, or the write address corresponding to the write instruction is less than one of the storage addresses of the storage space; the execution module is used to disable the error correction mechanism for the storage space in the partially programmed state.

[0019] In some of the embodiments, the determination module is also used to determine that the operating state of the storage space is an error correction protection state in response to the number of storage units written in the storage space being greater than a preset number, or the write address corresponding to the write instruction includes the last address of the storage space; the execution module is also used to enable an error correction mechanism for the storage space in the error correction protection state.

[0020] In some embodiments, the memory chip includes a first mark bit, a second mark bit, and an error correction bit for storing an error correction code, wherein the first mark bit, the second mark bit, and the error correction bit are used to characterize the operating state of the corresponding storage space, and the operating state also includes multiple programming states in which the error correction mechanism is disabled for the storage space.

[0021] In some of the embodiments, the storage space includes a storage array, and the data in the first mark bit, the second mark bit, and the error correction bit in the storage array are all "1", which is used to represent the partial programming state of the corresponding storage space; or, the data in the first mark bit, the second mark bit, and the error correction bit in the storage array are all "0", which is used to represent the multiple programming state of the corresponding storage space; or, the data in the first mark bit, the second mark bit, and the error correction bit in the storage array are neither all "1" nor all "0", which is used to represent the error correction protection state of the corresponding storage space.

[0022] In some embodiments, the storage space also includes a page buffer, the first mark bit includes a first cache mark bit located in the page buffer and a first storage mark bit located in the storage unit, the second mark bit includes a second cache mark bit located in the page buffer and a second storage mark bit located in the storage unit, the error correction bit includes a cache error correction bit located in the page buffer and a storage error correction bit located in the storage unit; the first storage mark bit has a first storage initial mark value or a first storage final mark value, the first storage initial mark value is the value of the first storage mark bit before the input data is written to the storage unit, and the first storage final mark value is the value of the first storage mark bit after the input data is written to the storage unit; the second storage The mark bit has a second storage initial mark value or a second storage final mark value, the second storage initial mark value is the value of the second storage mark bit before the input data is written to the storage unit, and the second storage final mark value is the value of the second storage mark bit after the input data is written to the storage unit; the storage error correction bit has a storage error correction initial value or a storage error correction final value, the storage error correction initial value is the value of the storage error correction bit before the input data is written to the storage unit, and the storage error correction final value is the value of the storage error correction bit after the input data is written to the storage unit; the determination module determines the operation status of the corresponding storage space according to the first storage final mark value, the second storage final mark value, and the storage error correction final value.

[0023] In some embodiments, the first cache mark bit has a first cache initial mark value or a first cache intermediate mark value, the second cache mark bit has a second cache initial mark value or a second cache intermediate mark value, and the storage error correction bit has a cache error correction initial value or a cache error correction intermediate value; the determination module assigns the first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value as the first storage final mark value, the second storage final mark value, and the storage error correction final value, respectively.

[0024] In some embodiments, the first cache intermediate mark value is 0, 1, or the first cache calculated mark value; the second cache intermediate mark value is 0, 1, or the second cache calculated mark value; the cache error correction intermediate value is all 0, all 1, or the cache error correction calculated value; the determination module determines the first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value based on the first stored initial mark value, the second stored initial mark value, and the stored error correction initial value.

[0025] In some embodiments, the memory chip stores page cache data and storage data, the page cache data is the data of the data bits in the page cache after the input data is written to the page cache; the storage data is the data of the data bits in the storage unit before the input data is written to the storage unit; the determination module determines the first cache calculation mark value, the second cache calculation mark value, and the cache error correction calculation value according to the page cache data and the storage data.

[0026] In some embodiments, the determination module includes a first determination module, a first error correction calculation unit, and a second determination module, the first determination module is used to determine that the result of the AND logic operation of the page cache data and the storage data is the intermediate comparison data; the first error correction calculation unit is used to calculate the initial error correction code according to the intermediate comparison data; the second determination module is used to calculate the second cache calculation mark value according to the intermediate comparison data and the initial error correction code, and calculate the first cache calculation mark value and the cache error correction calculation value according to the initial error correction code; wherein the second determination module includes a first detection unit, a second detection unit, a NAND logic unit, a first parity check unit, a first inverter, a second parity check unit, a second inverter, a first data selector, a second data selector, and an error correction conversion unit, the first detection unit is used to output a first logic detection result of whether each bit value of the initial error correction code is a logic value "0"; the second detection unit is used to output a second logic detection result of whether each bit value of the initial error correction code is a logic value "1"; the NAND logic unit is used to determine whether the first logic detection result is equal to the second logic detection result. The result of the logical AND-NOT operation of the logical detection result is the intermediate control data; the first parity check unit is used to perform a parity check on the initial error correction code to obtain a parity check result; the first inverter is used to invert the parity check result to obtain a non-parity check result; the second parity check unit is used to perform an XOR operation on the intermediate comparison data and the initial error correction code to obtain an XOR operation result; the second inverter is used to invert the XOR operation result to obtain a non-XOR operation result; the first data selector is used to select the non-parity check result as the second cache calculation mark value when the intermediate control data is "1"; and select the parity check result as the second cache calculation mark value when the intermediate control data is "0"; the second data selector is used to select the non-XOR operation result as the first cache calculation mark value when the intermediate control data is "1"; and select the XOR operation result as the first cache calculation mark value when the intermediate control data is "0"; the error correction conversion unit is used to convert a code different from the initial error correction code as the cache error correction calculation value when the bit values ​​of each bit of the initial error correction code are all logical values ​​"0".

[0027] The memory chip and the operation method thereof provided in the present application can determine that the operation state of the memory space is a partially programmed state by the fact that the number of memory cells written in the memory space is less than or equal to a preset number, or the write address corresponding to the write instruction is less than one of the memory addresses of the memory space; and the error correction mechanism is disabled for the memory space in the partially programmed state. Since the number of memory cells written in the memory space in the partially programmed state is small, even if the error correction mechanism is not adopted, the read success rate is still high, and the adverse effects brought about by the adoption of the error correction mechanism are reduced, for example, the need to increase the thread for implementing the error correction mechanism during the reading process reduces the reading efficiency, etc.

[0028] Furthermore, since the operating state of the storage space can be determined to be a partially programmed state by the fact that the number of storage units written in the storage space is less than or equal to a preset number, or the operating state of the storage space can be determined to be a partially programmed state by the fact that the write address corresponding to the write instruction is less than one of the storage addresses of the storage space, this increases the methods for judging the partial programming state, thereby improving applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0030] Figure 1 The present invention is a schematic block diagram of the structure of data storage in a page cache of a storage chip in the related art.

[0031] Figure 2 for Figure 1 Schematic diagram of the structure of data storage shown.

[0032] Figure 3 A schematic diagram of multiple programming states of a memory cell in the related art.

[0033] Figure 4 A flowchart of the operating method provided in the embodiment of the present application.

[0034] Figure 5 A schematic diagram of the error correction conversion process provided in an embodiment of the present application.

[0035] Figure 6 A schematic diagram of the operation flow of a partial programming state provided in an embodiment of the present application.

[0036] Figure 7 A schematic diagram of the operation flow of the error correction protection state provided in an embodiment of the present application.

[0037] Figure 8 A schematic diagram of the operation flow of multiple programming states provided in an embodiment of the present application.

[0038] Fig. 9 A schematic diagram of the structure of a memory chip provided in an embodiment of the present application.

[0039] Fig.10 Another structural schematic diagram of the memory chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0042] Figure 1 The present invention is a schematic block diagram of the structure of data storage in a page cache of a storage chip in the related art. Figure 2 for Figure 1 The structural diagram of data storage is shown in Figure 1. The page buffer or data input buffer (Page Buffer) of NOR Flash is generally 256 BYTEs. The error correction mechanism of NOR Flash is generally calculated based on the storage space of 16 BYTEs or 8 BYTEs as a unit to obtain the corresponding initial error correction code (ECC). The ECC corresponding to each storage space is 8 BITs or 7 BITs. ECC generally uses Hamming code, which can correct 1 BIT errors in the storage space of 16 BYTEs or 8 BYTEs.

[0043] Among them, User is used to represent user data or input data, and ALL1 means that each bit value of the corresponding data is a logical value "1".

[0044] Figure 2 for Figure 1The structural diagram of data storage is shown. Taking the size of the page cache as 256 BYTEs as an example, each page cache is divided into 16 storage spaces (0Unit...15Unit) with 16 BYTEs as a unit, and an error correction mechanism is performed on each storage space to obtain an ECC of 8BITs. For example, the error correction mechanism is performed on the storage space of 0Unit to obtain an 8BITs 0ECC. By analogy, the error correction mechanism is performed on the storage space of 15Unit to obtain an 8BITs 15ECC. In some cases, each page cache is divided into 32 storage spaces (0Unit...31Unit) with 8BYTEs as a unit, and an error correction mechanism is performed on each storage space to obtain an ECC of 7BITs. For example, the error correction mechanism is performed on the storage space of 0Unit to obtain a 7BITs 0ECC. By analogy, the error correction mechanism is performed on the storage space of 31Unit to obtain a 7BITs 31ECC.

[0045] Figure 3 A schematic diagram of multiple programming states of a storage cell in the related art. In NOR Flash, for example, after the erase operation is completed, the initial state of each storage cell (CELL) is "1". Programming (Program) is to change the state "1" of the storage cell whose data is "0" to the state "0", while the storage cell corresponding to the data to be written as "1" does not need to be programmed. Generally, an erase operation is required, and the program (Program) operation cannot rewrite the original data "0" in the storage cell to "1".

[0046] When the user data or input data is less than 16BYTEs or 8BYTEs of each storage space, the user data and all the original 1s in this unit are used together to calculate ECC (8BITs or 7BITs), and the user data and ECC are programmed (Program) into the storage unit (CELL) of NOR FLASH. Before erasing these storage units (CELL), after programming (Program) the all-1 parts in these storage units (CELL), the error correction code will be recalculated to obtain ECC1. If ECC1 is different from ECC, since multiple programming (DoubleProgram) is performed in the same storage unit without erasing, the logic value "1" in ECC1 cannot replace the logic value "0" in ECC, which will cause errors in the process of reading data from ECC1. Of course, in some embodiments, ECC can also be calculated based on the 0 in the storage unit.

[0047] It can be seen that performing a programming operation on the same memory cell between two erasing operations still has a high accuracy; and in order to improve storage life or to improve operation efficiency, it is still necessary to perform two or more programming operations between two erasing operations on the memory cell.

[0048] This embodiment provides an operation method of a memory chip, wherein the memory chip includes one or more memory spaces. Figure 4 As shown, the operation method includes the following steps:

[0049] Step S10: In response to the number of storage cells in a storage space being written being less than or equal to a preset number, or the write address corresponding to the write instruction being less than one of the storage addresses of the storage space, determining that the operation state of the storage space is a partially programmed state.

[0050] Step S20: disabling the error correction mechanism for the memory space in the partially programmed state.

[0051] It can be understood that the operating method provided in this embodiment can determine that the operating state of the storage space is a partial programming state by the number of storage cells written in the storage space being less than or equal to a preset number, or the write address corresponding to the write instruction being less than one of the storage addresses of the storage space; and the error correction mechanism is disabled for the storage space in the partial programming state. Since the number of storage cells written in the storage space in the partial programming state is small, even if the error correction mechanism is not adopted, it still has a high read success rate and reduces the adverse effects brought about by the use of the error correction mechanism, for example, the need to increase the thread for implementing the error correction mechanism during the reading process, thereby reducing the reading efficiency.

[0052] Furthermore, since the operating state of the storage space can be determined to be a partially programmed state by the fact that the number of storage units written in the storage space is less than or equal to a preset number, or the operating state of the storage space can be determined to be a partially programmed state by the fact that the write address corresponding to the write instruction is less than one of the storage addresses of the storage space, this increases the methods for judging the partial programming state, thereby improving applicability.

[0053] It should be noted that how to distinguish whether it is a partial programming state, an error correction protection state, or a multiple programming state is not limited to the method provided in this application. For example, it is also possible to determine whether the storage space is in a multiple programming state by setting a count bit or a mark bit.

[0054] Among them, disabling the error correction mechanism during the reading process for the storage space in a partially programmed state can reduce the adverse effects of using the error correction mechanism under the condition of a higher reading success rate.

[0055] In one of the embodiments, in response to the number of storage units in a storage space being written being less than or equal to a preset number, the method includes setting the preset number to be less than or equal to 1 / 2 or 1 / 3 of the total number of storage units in the storage space.

[0056] It should be noted that, in a storage space with 8-byte storage units, the preset number is less than 64, which can ensure that all storage units in the corresponding storage space have not been written, for example, at least one storage unit has not been written. In a storage space with 16-byte storage units, the preset number is less than 128, which can also ensure that all storage units in the corresponding storage space have not been written, for example, at least one storage unit has not been written.

[0057] The last address of the storage space may be the largest one among the storage addresses corresponding to the storage space, so that in the process of writing in order of the storage addresses, the storage unit corresponding to the last address is always written after the other storage units are written. This can also ensure that all the storage units in the corresponding storage space have not been written, for example, at least one storage unit has not been written.

[0058] In one of the embodiments, disabling an error correction mechanism for a storage space in a partially programmed state includes: when a storage cell in the storage space is in an erased state or an unwritten state, disabling the error correction mechanism for the storage space that is judged to be in a partially programmed state based on the number of storage cells that have been cumulatively written in the storage space.

[0059] It should be noted that the erased state or unwritten state may refer to a state in which a storage unit in the storage space has been erased but not written, and in this state, the data in each storage unit is in the initial state "1". In this case, disabling the error correction mechanism can save thread operations in the storage chip.

[0060] In one of the embodiments, the operating method also includes: in response to the number of storage units written in the storage space being greater than a preset number, or the write address corresponding to the write instruction includes the last address of the storage space, determining that the operating state of the storage space is an error correction protection state; enabling an error correction mechanism for the storage space in the error correction protection state.

[0061] It can be understood that the operating method provided in this embodiment determines that the operating state of the storage space is the error correction protection state by virtue of the number of storage units written in the storage space being greater than a preset number or the write address corresponding to the write instruction containing the last address of the storage space. This is beneficial to increasing the number of storage spaces in the error correction protection state. On this basis, enabling the error correction mechanism during the reading process for the storage space in the error correction protection state can improve the reading accuracy of a larger number of storage spaces in the error correction protection state.

[0062] Furthermore, since the operating state of the storage space can be determined to be the error correction protection state by the fact that the number of storage units written in the storage space where the error correction code is calculated in units is greater than a preset number, and the operating state of the storage space can also be determined to be the error correction protection state by the fact that the write address corresponding to the write instruction contains the last address of the storage space, this increases the methods for judging the error correction protection state, thereby improving applicability.

[0063] It should be noted that in some embodiments, the error correction mechanism can also be disabled during operation of the storage space in the error correction protection state, such as during reading. This can reduce the error correction links in the reading process and improve the reading speed or reading efficiency.

[0064] It should be noted that the present application calculates the error correction code based on one or more storage spaces.

[0065] In one embodiment, the operation method further includes: setting at least one flag bit to indicate an operation state of the corresponding storage space. The operation state includes a multiple programming state in which an error correction mechanism is disabled for the storage space.

[0066] In some embodiments, at least one mark bit is set to characterize the operating status of the corresponding storage space, including: configuring at least one mark bit to include a first mark bit, a second mark bit, and an error correction bit storing an error correction code; setting the first mark bit, the second mark bit, and the error correction bit to characterize the operating status of the corresponding storage space.

[0067] In some embodiments, the storage space includes a storage array, and setting a first mark bit, a second mark bit, and an error correction bit to represent the operating state of the corresponding storage space includes: setting the data in the first mark bit, the second mark bit, and the error correction bit in the storage array to all "1" to represent the partial programming state, erased state, or storage initial state of the corresponding storage space; or, setting the data in the first mark bit, the second mark bit, and the error correction bit in the storage array to all "0" to represent the multiple programming state of the corresponding storage space; or, setting the data in the first mark bit, the second mark bit, and the error correction bit in the storage array to neither all "1" nor all "0" to represent the error correction protection state of the corresponding storage space.

[0068] In some embodiments, the storage space also includes a page cache, the first mark bit includes a first cache mark bit located in the page cache and a first storage mark bit located in the storage unit, the second mark bit includes a second cache mark bit located in the page cache and a second storage mark bit located in the storage unit, the error correction bit includes a cache error correction bit located in the page cache and a storage error correction bit located in the storage unit, and the first mark bit, the second mark bit, and the error correction bit are set to characterize the operating state of the corresponding storage space, including: setting the first storage mark bit to have a first storage initial mark value or a first storage final mark value, the first storage initial mark value is the value of the first storage mark bit before the input data is written to the storage unit, and the first storage final mark value is the value of the first storage mark bit after the input data is written to the storage The first storage mark bit after the input data is written to the storage unit; the second storage mark bit is set to have a second storage initial mark value or a second storage final mark value, the second storage initial mark value is the value of the second storage mark bit before the input data is written to the storage unit, and the second storage final mark value is the value of the second storage mark bit after the input data is written to the storage unit; the storage error correction bit is set to have a storage error correction initial value or a storage error correction final value, the storage error correction initial value is the value of the storage error correction bit before the input data is written to the storage unit, and the storage error correction final value is the value of the storage error correction bit after the input data is written to the storage unit; the operation state of the corresponding storage space is determined according to the first storage final mark value, the second storage final mark value, and the storage error correction final value.

[0069] In some embodiments, the operating method also includes: setting the first cache mark bit to have a first cache initial mark value, or a first cache intermediate mark value, the second cache mark bit to have a second cache initial mark value, or a second cache intermediate mark value, and the cache error correction bit to have a cache error correction initial value, or a cache error correction intermediate value; assigning the first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value as the first storage final mark value, the second storage final mark value, and the storage error correction final value, respectively.

[0070] In some embodiments, the operating method also includes: setting the first cache intermediate mark value to 0, 1, or the first cache calculated mark value; setting the second cache intermediate mark value to 0, 1, or the second cache calculated mark value; setting the cache error correction intermediate value to all 0, all 1, or the cache error correction calculated value; determining the first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value based on the first stored initial mark value, the second stored initial mark value, and the stored error correction initial value.

[0071] In some embodiments, the operating method also includes: setting the page cache data to the data of the data bit in the page cache after the input data is written to the page cache; setting the storage data to the data of the data bit in the storage unit before the input data is written to the storage unit; determining the first cache calculation mark value, the second cache calculation mark value, and the cache error correction calculation value based on the page cache data and the storage data.

[0072] In some embodiments, the operating status of the storage space may be determined in any of the following three ways:

[0073] The first method: determining the operating state of the storage space by at least one mark bit in the storage array. The second method: determining the operating state of the storage space by the storage error correction final value and at least one storage final mark value in the storage array. The third method: determining the operating state of the storage space by the storage error correction final value, at least one storage final mark value, and intermediate comparison data in the storage array.

[0074] Figure 5 A schematic diagram of the error correction conversion process provided by an embodiment of the present application. For 16BYTEs / 8BYTEs units, the initial state of these units is ALL1, and ALL1 means that the initial state of these units is 1. The corresponding ECC is calculated based on the user data (User) accessed in the storage space and the data in the initial state that has not been written; the flag bit (Flag) of 2BITs, i.e., F0 of 1BIT and F1 of 1BIT, can also be further obtained.

[0075] In some cases, the ECC needs to be converted to obtain the corresponding cache error correction calculation value. Then, the error correction protection state or the multiple programming state can be determined according to the cache error correction calculation value; or, in order to improve accuracy, the partial programming state, the error correction protection state, or the multiple programming state can also be determined according to the first storage final level mark value, the second storage final level mark value, and the storage error correction final level value. The specific process of this conversion is described in detail later.

[0076] It should be noted that TECC is used to represent the error correction bit, F0 is used to represent the first mark bit, and F1 is used to represent the second mark bit. TECC, F0, F1 are further divided into TECC, F0, F1 in the storage array or storage unit, TECC, F0, F1 in the initial state in the page buffer, and calculated TECC, F0, F1.

[0077] Figure 6 A schematic diagram of the operation flow of some programming states provided in an embodiment of the present application. In a memory chip, in an initial state or after an erase operation without a programming operation, the data (DATA), TECC, F0, and F1 in the page buffer (Page Buffer) are all 1, and the data (DATA), TECC, F0, and F1 in the storage cell (Flash CELL) of the storage array are also all 1. Among them, ALL1 indicates that the corresponding data are all logical values ​​"1". Among them, the buffer is a page buffer in some embodiments.

[0078] When the input data (User) corresponding to the write command is written into the page buffer but not into the corresponding storage unit, TECC, F0, and F1 in the page buffer are all 1 (the initial state has not changed), and the data (DATA) in the page buffer is updated to data (User+ALL1); TECC, F0, and F1 in the storage unit (Flash CELL) in the storage array are all 1, and the data (DATA) in the storage unit (Flash CELL) in the storage array is ALL1. The data in the page buffer can be called Page_DATA, and the data in the storage array can be called Flash_DATA.

[0079] Perform an AND logic operation on Page_DATA and Flash_DATA, i.e., AND(Page_DATA, Flash_DATA), to obtain the corresponding intermediate comparison data (i.e., User+ALL1), perform an error correction mechanism on the intermediate comparison data to calculate the corresponding initial error correction code (ECC), and write the intermediate comparison data back to the page buffer. TECC, F0, and F1 are calculated based on the ECC and the intermediate comparison data.

[0080] The TECC, F0 and F1 in the storage array are all 1 detected. If the TECC, F0 and F1 in the storage array are all 1 and meet the conditions of the partial programming state, the enable state (ECC enable) will select the TECC, F0 and F1 in the page cache that are all 1 as the cache error correction intermediate value, the first cache intermediate mark value, and the second cache intermediate mark value respectively.

[0081] Program the cache error correction intermediate value, the first cache intermediate mark value, and the second cache intermediate mark value in the page cache to TECC, F0, and F1 in the storage array, and program the data (User+ALL1) in the page cache to the storage array. The data, TECC, F0, and F1 in the page cache are all 1; the data in the storage array is updated to the data (User+ALL1), and TECC, F0, and F1 in the storage array are all 1. This situation is a partial programming state.

[0082] It should be noted that the condition of the partial programming state is that the number of storage units written in a storage space is less than or equal to a preset number, or the write address corresponding to the write instruction is less than one of the storage addresses in the storage space.

[0083] Figure 7 This is a schematic diagram of the operation flow of the error correction protection state provided in the embodiment of the present application. Figure 6 On the basis of, the data (DATA), TECC, F0, and F1 in the page buffer (Page Buffer) are all 1; the data (DATA) in the storage cell (Flash CELL) of the storage array is data (User+ALL1), and TECC, F0, and F1 in the storage array are all 1. Among them, ALL1 means that the corresponding data are all logical values ​​"1".

[0084] When the input data (User1) corresponding to the write command is written into the page buffer but not into the storage array, TECC, F0, and F1 in the page buffer are all 1 (the initial state has not changed), and the data (DATA) in the page buffer is updated to the input data + the data in the initial state (User1+ALL1); TECC, F0, and F1 in the storage array are all 1, and the data (DATA) in the storage unit of the storage array is User+ALL1. At this time, the data in the page buffer can be called Page_DATA, and the data in the storage array can be called Flash_DATA. In some embodiments, the buffer is a page buffer.

[0085] Perform an AND logic operation on Page_DATA and Flash_DATA, i.e., AND(Page_DATA, Flash_DATA), to obtain the corresponding intermediate comparison data (User+User1), perform an error correction mechanism on the intermediate comparison data to obtain the corresponding initial error correction code (ECC), and write the intermediate comparison data back to the page buffer. TECC, F0, and F1 are calculated based on the ECC and the intermediate comparison data.

[0086] The TECC, F0 and F1 in the storage array are all 1 detected (i.e., ECC_ALL1, F0=1, and F1=1 detected). If the TECC, F0 and F1 in the storage array are all 1 and meet the conditions of the error correction protection state, the enable state (ECC enable) will select the TECC, F0 and F1 calculated in the page buffer as the cache error correction intermediate value, the first cache intermediate mark value, and the second cache intermediate mark value respectively.

[0087] Program the storage array (Program Flash CELL) to write the data (User+User1) in the page cache to the corresponding storage cell (Flash CELL). At this time, the data, TECC, F0, and F1 in the page cache are all "1", and the logical values ​​of TECC, F0, and F1 in the storage array, and the data are respectively the calculated logical values ​​of TECC, F0, and F1, and the data (User+User1). This state is the error correction protection state.

[0088] It should be noted that after each data in the page buffer is written to the storage array, each data in the page buffer will be reset to "1". The condition of the error correction protection state is that the number of storage units in the storage space written is greater than the preset number, or the write address corresponding to the write instruction includes the last address of the storage space.

[0089] Figure 8 This is a schematic diagram of the operation flow of multiple programming states provided in the embodiment of the present application. Figure 7 Based on the write command, after the input data (User2) corresponding to the write command is written into the page buffer, in some embodiments, the page buffer is a buffer, TECC, F0, and F1 in the page buffer (Page Buffer) are all 1, and the data (DATA) in the page buffer (Page Buffer) is data (ALL1+User2); the data (DATA) in the storage cell (Flash CELL) of the storage array is data (User+User1), and TECC, F0, and F1 are Figure 7At this point, the data in the page cache can be called Page_DATA, and the data in the storage array can be called Flash_DATA.

[0090] Perform an AND logic operation on Page_DATA and Flash_DATA, i.e., AND(Page_DATA, Flash_DATA), to obtain the corresponding intermediate comparison data (User+User1+User2), write the intermediate comparison data back to the page buffer, and calculate the corresponding initial error correction code (ECC) for the intermediate comparison data. TECC, F0, and F1 are calculated based on the ECC and the intermediate comparison data; perform an all-1 detection on TECC, F0, and F1 in the storage array (i.e., ECC_ALL1, F0=1, and F1=1 detection), and when TECC, F0, and F1 in the storage array are not all-1, the enable state (ECC enable) selects TECC, F0, and F1 in the page buffer, which are all 0, as the cache error correction intermediate value, the first cache intermediate mark value, and the second cache intermediate mark value, respectively.

[0091] Program the memory cells in the memory array (Program Flash CELL) to modify TECC, F0 and F1 in the memory array to logic values ​​"0", and write the data (User+User1+User2) in the page buffer to the memory array.

[0092] At this time, the data in the page cache, TECC, F0, and F1 are all logic values ​​"1". TECC, F0, and F1 in the storage array are all logic values ​​"0", and the data in the storage array is data (User+User1+User2). This state is the multi-programming state. In this case, the error correction mechanism is disabled.

[0093] It should be noted that after the data in the page buffer is written into the storage array, each data in the page buffer will be set (returned) to a logic value of "1".

[0094] In general, the calculated TECC = ECC, and when ECC is all 0, a value other than all 0 needs to be used as the calculated TECC. Of course, this is just one of the solutions, and there can be other definitions, such as defining ECC as all 1 or other values ​​to represent multiple programming states, and the calculated TECC performs corresponding operations.

[0095] In one embodiment, this embodiment provides a memory chip, such as Fig. 9 , Fig.10As shown, the memory chip includes a storage space 100, a determination module 300, and an execution module 400. The determination module 300 is used to determine that the operating state of the storage space 100 is a partially programmed state in response to the number of storage cells written in a storage space 100 being less than or equal to a preset number, or the write address corresponding to the write instruction is less than one of the storage addresses of the storage space 100; the execution module 400 is used to disable the error correction mechanism for the storage space 100 in the partially programmed state.

[0096] It can be understood that the storage chip provided in this embodiment can determine that the operating state of the storage space 100 is a partial programming state by the fact that the number of storage cells written in the storage space 100 is less than or equal to a preset number, or the write address corresponding to the write instruction is less than one of the storage addresses of the storage space 100; and the error correction mechanism is disabled for the storage space 100 in the partial programming state. Since the number of storage cells written in the storage space 100 in the partial programming state is small, even if the error correction mechanism is not adopted, it still has a high read success rate and reduces the adverse effects brought about by the use of the error correction mechanism, for example, the need to increase the thread for implementing the error correction mechanism during the reading process, thereby reducing the reading efficiency.

[0097] Furthermore, since the operating state of the storage space 100 can be determined to be a partially programmed state by the fact that the number of storage cells written in the storage space 100 is less than or equal to a preset number, or the operating state of the storage space 100 can be determined to be a partially programmed state by the fact that the write address corresponding to the write instruction is less than one of the storage addresses of the storage space 100, this increases the methods for judging the partial programming state, thereby improving applicability.

[0098] It should be noted that the determination module 300 is also used to determine that the operating state of the storage space 100 is an error correction protection state in response to the number of storage units written in the storage space 100 being greater than a preset number, or the write address corresponding to the write instruction contains the last address of the storage space 100; the execution module 400 is also used to enable the error correction mechanism for the storage space 100 in the error correction protection state.

[0099] in, Fig.10 The storage space 100 in the memory includes a storage array and a page buffer.

[0100] It should be noted that by determining that the operating state of the storage space 100 is the error correction protection state when the number of storage units written in the storage space 100 is greater than the preset number or the write address corresponding to the write instruction includes the last address of the storage space 100, it is beneficial to increase the number of storage spaces 100 in the error correction protection state. For example, if the error correction protection state is entered when only a small amount of data is written, the storage space 100 will enter a multiple write state (multiple programming state) when data is written again. In this way, the storage space 100 cannot be protected from error correction. On this basis, enabling the error correction mechanism for the storage space 100 in the error correction protection state during the reading process can improve the reading accuracy of a larger number of storage spaces 100 in the error correction protection state.

[0101] It should be noted that the above-mentioned memory chip can be but not limited to NOR Flash, and can also be other applicable memories. The error correction mechanism can be a technology that can implement "error checking and correction", which can calculate the corresponding error correction code (Error Correct Code, ECC).

[0102] In one embodiment, if Fig. 9 , Fig.10 As shown, the determination module 300 includes a first determination module 200, a first error correction calculation unit 310, and a second determination module 320. The first determination module 200 is used to determine that the result of the AND logic operation of the page cache data and the storage data is the intermediate comparison data (CMP_DATA). The first error correction calculation unit 310 is used to calculate the initial error correction code (ECC) according to the intermediate comparison data. The second determination module 320 is used to calculate the second cache calculation mark value according to the intermediate comparison data and the initial error correction code, and calculate the first cache calculation mark value and the cache error correction calculation value according to the initial error correction code.

[0103] It needs to be explained that Fig.10 TECC, F0, and F1 shown in the figure represent the cache error correction calculation value, the first cache calculation mark value, and the second cache calculation mark value respectively. DATA represents the input data of the user.

[0104] Among them, the second determination module 320 includes a first detection unit 312, a second detection unit 313, a NAND logic unit 314, a first parity check unit 315, a first inverter INV1, a second parity check unit 316, a second inverter INV2, a first data selector MUX1, a second data selector MUX2, and an error correction conversion unit 311.

[0105] The first detection unit 312 is used to output a first logic detection result of whether each bit value of the initial error correction code is a logic value “0”.

[0106] It should be noted that the first detection unit 312 is used to output a logic value "1" when the initial error correction code is all logic value "0", that is, ECC_ALL0. When the initial error correction code is not all logic value "0", the first detection unit 312 outputs a logic value "0".

[0107] The second detection unit 313 is used to output a second logic detection result of whether each bit value of the initial error correction code is a logic value “1”.

[0108] It should be noted that the second detection unit 313 is used to output a logic value "1" when the initial error correction codes are all logic values ​​"1", i.e., ECC_ALL1; when the initial error correction codes are not all logic values ​​"1", the second detection unit 313 outputs a logic value "0".

[0109] The NAND logic unit 314 is used to determine a NAND logic operation result of the first logic detection result and the second logic detection result as intermediate control data.

[0110] The first parity check unit 315 is used to perform a parity check, ie, XOR (ECC), on the initial error correction code to obtain a parity check result.

[0111] The first inverter INV1 is used to invert the parity check result to obtain a non-parity check result.

[0112] The second parity check unit 316 is used to perform an XOR operation on the intermediate comparison data and the initial error correction code, ie, XOR (CMP_DATA, ECC) to obtain an XOR operation result. The second inverter INV2 is used to invert the XOR operation result to obtain a non-XOR operation result.

[0113] The first data selector MUX1 is used to select the non-parity check result as the second cache calculation tag value when the intermediate control data is "1", and to select the parity check result as the second cache calculation tag value when the intermediate control data is "0".

[0114] The second data selector MUX2 is used to select the non-XOR operation result as the first cache calculation tag value when the intermediate control data is "1", and to select the XOR operation result as the first cache calculation tag value when the intermediate control data is "0".

[0115] The error correction conversion unit 311 is used to convert a code different from the initial error correction code as a buffer error correction calculation value when all bit values ​​of the initial error correction code are logic values ​​"0". Alternatively, when all bit values ​​of the initial error correction code are not all logic values ​​"0", the initial error correction code is directly output as the buffer error correction calculation value.

[0116] In summary, after user data is written into the storage array, TECC, F0, and F1 in the storage array are all logic values ​​"0", which are used to define or characterize the multiple programming state, that is, before erasing a storage cell (NOR FLASH CELL), multiple programming (Program) operations are performed on this storage cell. After user data is written into the storage array, TECC, F0, and F1 in the storage array are neither all 1 nor all 0, which are used to define or characterize the error correction protection state, that is, before erasing a storage cell (NOR FLASH CELL), only one programming (Program) operation is performed on a storage cell.

[0117] Among them, F0 can be used to indicate that ECC can correct 1BIT errors and detect 2BITs errors. F1 can be used to distinguish whether it is a multiple programming state.

[0118] It is understandable that the present application can determine storage cells that can be programmed multiple times based on user input data, which can increase the user's selection width or applicability compared to performing only one programming operation per erase.

[0119] In one of the embodiments, the data in the first mark bit, the second mark bit, and the error correction bit in the storage array are all "1", which is used to represent the partial programming state of the storage space 100; or, the data in the first mark bit, the second mark bit, and the error correction bit in the storage array are all "0", which is used to represent the multiple programming state of the storage space 100; or, the data in the first mark bit, the second mark bit, and the error correction bit in the storage array are neither all "1" nor all "0", which is used to represent the error correction protection state of the storage space 100.

[0120] The “multiple times” recorded in this case means twice or more than twice.

[0121] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0122] The above is a detailed introduction to the memory chip and its operating method provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A method for operating a memory chip, It is characterized in that The storage chip includes one or more storage spaces, and the operation method includes: In response to the number of storage units in the storage space being written being less than or equal to a preset number, or the write address corresponding to the write instruction being less than one of the storage addresses in the storage space, determining that the operation state of the storage space is a partially programmed state; An error correction mechanism is disabled for the memory space in the partially programmed state.

2. The operating method according to claim 1, It is characterized in that The step of responding that the number of storage units in the storage space that are written is less than or equal to a preset number comprises: disabling an error correction mechanism for a storage space determined to be in the partially programmed state according to a cumulative number of written storage cells in the storage space, when the storage cells in the storage space are in an erased state or an unwritten state; Alternatively, when there is already written data in the storage space, the error correction mechanism is disabled for the storage space in the partial programming state according to the total number of the already existing written data and the currently written data.

3. The operating method according to claim 1, It is characterized in that The step of responding that the number of storage units in the storage space that are written is less than or equal to a preset number comprises: The preset number is set to be less than or equal to 1 / 2 or 1 / 3 of the total number of storage units in the storage space.

4. The operating method according to claim 1, It is characterized in that The operation method also includes: In response to the number of the storage units in the storage space being written being greater than the preset number, or the write address corresponding to the write instruction including the last address of the storage space, determining that the operation state of the storage space is an error correction protection state; An error correction mechanism is enabled for the storage space in the error correction protection state.

5. The operating method according to claim 4, It is characterized in that The operation method further includes: The error correction mechanism is disabled during the reading process for the storage space in the partial programming state; and the error correction mechanism is enabled during the reading process for the storage space in the error correction protection state.

6. The operating method according to claim 1, It is characterized in that The operation method further includes: At least one flag bit is set to indicate the operation status of the corresponding storage space.

7. The operating method according to claim 6, It is characterized in that The step of setting at least one flag bit to indicate the operation status of the corresponding storage space includes: Configuring the at least one flag bit to include a first flag bit, a second flag bit, and an error correction bit storing an error correction code; The first mark bit, the second mark bit, and the error correction bit are set to represent the operation status of the corresponding storage space.

8. The operating method according to claim 7, It is characterized in that The storage space includes a storage array, and the setting of the first mark bit, the second mark bit, and the error correction bit to represent an operation state of the corresponding storage space includes: Setting the data in the first flag bit, the second flag bit, and the error correction bit in the storage array to all "1" to indicate the partial programming state, erased state, or storage initial state of the corresponding storage space; or, Setting the data in the first mark bit, the second mark bit, and the error correction bit in the storage array to all "0" to represent the multiple programming states of the corresponding storage space; or, The data in the first mark bit, the second mark bit, and the error correction bit in the storage array are set to be non-all "1" and non-all "0" to represent the error correction protection state of the corresponding storage space.

9. The operating method according to claim 8, It is characterized in that The storage space further includes a page buffer, the first mark bit includes a first cache mark bit located in the page buffer and a first storage mark bit located in the storage unit, the second mark bit includes a second cache mark bit located in the page buffer and a second storage mark bit located in the storage unit, the error correction bit includes a cache error correction bit located in the page buffer and a storage error correction bit located in the storage unit, and the first mark bit, the second mark bit, and the error correction bit are set to characterize the operation state of the corresponding storage space, including: The first storage mark bit is set to have a first storage initial mark value or a first storage final mark value, wherein the first storage initial mark value is the value of the first storage mark bit before the input data is written into the storage unit, and the first storage final mark value is the value of the first storage mark bit after the input data is written into the storage unit; The second storage mark bit is set to have a second storage initial mark value or a second storage final mark value, wherein the second storage initial mark value is the value of the second storage mark bit before the input data is written into the storage unit, and the second storage final mark value is the value of the second storage mark bit after the input data is written into the storage unit; Setting the storage error correction bit to have a storage error correction initial value or a storage error correction final value, wherein the storage error correction initial value is the value of the storage error correction bit before the input data is written into the storage unit, and the storage error correction final value is the value of the storage error correction bit after the input data is written into the storage unit; An operation state of a corresponding storage space is determined according to the first storage final level flag value, the second storage final level flag value, and the storage error correction final level value.

10. The operating method according to claim 9, It is characterized in that The operation method further includes: Setting the first cache mark bit to have a first cache initial mark value or a first cache intermediate mark value, setting the second cache mark bit to have a second cache initial mark value or a second cache intermediate mark value, and setting the cache error correction bit to have a cache error correction initial value or a cache error correction intermediate value; The first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value are assigned as the first storage final mark value, the second storage final mark value, and the storage error correction final value respectively.

11. The operating method according to claim 10, It is characterized in that The operation method further includes: Set the first cache intermediate mark value to 0, 1, or the first cache calculated mark value; Set the second cache intermediate mark value to 0, 1, or the second cache calculated mark value; Setting the cache error correction intermediate value to all 0s, all 1s, or a cache error correction calculated value; The first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value are determined based on the first stored initial mark value, the second stored initial mark value, and the stored error correction initial value.

12. The operating method according to claim 11, It is characterized in that The operation method further includes: Setting the page cache data to the data of the data bit in the page cache after the input data is written into the page cache; Setting the storage data to the data of the data bit in the storage unit before the input data is written into the storage unit; The first cache calculation tag value, the second cache calculation tag value, and the cache error correction calculation value are determined according to the page cache data and the storage data.

13. The operating method according to claim 12, It is characterized in that Determining the first cache calculation tag value, the second cache calculation tag value, and the cache error correction calculation value according to the page cache data and the storage data includes: Determine the result of a logical operation of the page cache data and the storage data as intermediate comparison data; Calculating an initial error correction code according to the intermediate comparison data; Calculating the second cache calculation mark value according to the intermediate comparison data and the initial error correction code, and calculating the first cache calculation mark value and the cache error correction calculation value according to the initial error correction code; The intermediate control data is a result of a first logic detection result for determining whether each bit value of the initial error correction code is a logic value "0" and a second logic detection result for determining whether each bit value of the initial error correction code is a logic value "1". wherein, performing a parity check on the initial error correction code to obtain a parity check result, and inverting the parity check result to obtain a non-parity check result; wherein, performing an XOR operation on the intermediate comparison data and the initial error correction code to obtain an XOR operation result, and negating the XOR operation result to obtain a non-XOR operation result; Wherein, when the intermediate control data is "1", the non-XOR operation result and the non-parity check result are selected as the first cache calculation mark value and the second cache calculation mark value respectively; when the intermediate control data is "0", the XOR operation result and the parity check result are selected as the first cache calculation mark value and the second cache calculation mark value respectively; Among them, when the bit values ​​of the initial error correction code are all logical values ​​"0", a code different from the initial error correction code is converted as the cache error correction calculation value; or, when the bit values ​​of the initial error correction code are not all logical values ​​"0", the initial error correction code is directly output as the cache error correction calculation value.

14. The operating method according to any one of claims 9 to 13, It is characterized in that The determining the operation state of the corresponding storage space according to the first storage final level mark value, the second storage final level mark value, and the storage error correction final level value includes: In the case where the first storage final level mark value, the second storage final level mark value, and the storage error correction final level value are all "0", determining that the operation state of the storage space corresponding to the write instruction is the multiple programming state; or In a case where the first storage final level tag value, the second storage final level tag value, and the storage error correction final level value are respectively the first cache calculation tag value, the second cache calculation tag value, and the cache error correction calculation value, determining that the operation state of the storage space corresponding to the write instruction is the error correction protection state; or When the first storage final level mark value, the second storage final level mark value, and the storage error correction final level value are all logic values ​​"1", it is determined that the operation state of the storage space is the partial programming state.

15. A memory chip, It is characterized in that The memory chip comprises: Storage space; a determination module, the determination module being configured to determine that the operation state of the storage space is a partially programmed state in response to the number of storage units in the storage space being written being less than or equal to a preset number, or the write address corresponding to the write instruction being less than one of the storage addresses of the storage space; An execution module is configured to disable an error correction mechanism for the storage space in the partially programmed state.

16. The memory chip according to claim 15, It is characterized in that The determination module is further configured to determine that the operation state of the storage space is an error correction protection state in response to the number of storage units in the storage space being written being greater than the preset number, or the write address corresponding to the write instruction including the last address of the storage space; The execution module is further configured to enable an error correction mechanism for the storage space in the error correction protection state.

17. The memory chip according to claim 16, It is characterized in that The memory chip includes a first mark bit, a second mark bit, and an error correction bit storing an error correction code, wherein the first mark bit, the second mark bit, and the error correction bit are used to characterize the operating state of the corresponding storage space, and the operating state includes multiple programming states in which the error correction mechanism is disabled for the storage space.

18. The memory chip according to claim 17, It is characterized in that The storage space includes a storage array, and data in the first mark bit, the second mark bit, and the error correction bit in the storage array are all "1", which is used to represent a partial programming state of the corresponding storage space; Alternatively, the data in the first mark bit, the second mark bit, and the error correction bit in the storage array are all "0", which is used to represent the multiple programming states of the corresponding storage space; Alternatively, the data in the first mark bit, the second mark bit, and the error correction bit in the storage array are not all "1" and not all "0", which are used to represent the error correction protection state of the corresponding storage space.

19. The memory chip according to claim 18, It is characterized in that The storage space further includes a page buffer, the first mark bit includes a first cache mark bit located in the page buffer and a first storage mark bit located in the storage unit, the second mark bit includes a second cache mark bit located in the page buffer and a second storage mark bit located in the storage unit, and the error correction bit includes a cache error correction bit located in the page buffer and a storage error correction bit located in the storage unit; The first storage mark bit has a first storage initial mark value or a first storage final mark value, the first storage initial mark value is the value of the first storage mark bit before the input data is written into the storage unit, and the first storage final mark value is the value of the first storage mark bit after the input data is written into the storage unit; The second storage mark bit has a second storage initial mark value or a second storage final mark value, the second storage initial mark value is the value of the second storage mark bit before the input data is written into the storage unit, and the second storage final mark value is the value of the second storage mark bit after the input data is written into the storage unit; The storage error correction bit has a storage error correction initial value or a storage error correction final value, wherein the storage error correction initial value is the value of the storage error correction bit before the input data is written into the storage unit, and the storage error correction final value is the value of the storage error correction bit after the input data is written into the storage unit; The determination module determines an operation state of a corresponding storage space according to the first storage final level mark value, the second storage final level mark value, and the storage error correction final level value.

20. The memory chip according to claim 19, It is characterized in that The first cache mark bit has a first cache initial mark value or a first cache intermediate mark value, the second cache mark bit has a second cache initial mark value or a second cache intermediate mark value, and the cache error correction bit has a cache error correction initial value or a cache error correction intermediate value; The determination module assigns the first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value as the first storage final mark value, the second storage final mark value, and the storage error correction final value respectively.

21. The memory chip according to claim 20, It is characterized in that The first cache intermediate mark value is 0, 1, or a first cache calculated mark value; the second cache intermediate mark value is 0, 1, or a second cache calculated mark value; the cache error correction intermediate value is all 0, all 1, or a cache error correction calculated value; The determination module determines the first cache intermediate mark value, the second cache intermediate mark value, and the cache error correction intermediate value according to the first storage initial mark value, the second storage initial mark value, and the storage error correction initial value.

22. The memory chip according to claim 21, It is characterized in that The memory chip stores page cache data and storage data, wherein the page cache data is data of data bits in the page cache after the input data is written into the page cache; and the storage data is data of data bits in the storage unit before the input data is written into the storage unit; The determination module determines the first cache calculation tag value, the second cache calculation tag value, and the cache error correction calculation value according to the page cache data and the storage data.

23. The memory chip according to claim 22, It is characterized in that The determination module comprises: A first determining module, the first determining module is used to determine that a result of an AND logic operation between the page cache data and the storage data is intermediate comparison data; a first error correction calculation unit, the first error correction calculation unit being used to calculate an initial error correction code according to the intermediate comparison data; a second determination module, the second determination module being used to calculate the second cache calculation mark value according to the intermediate comparison data and the initial error correction code, and to calculate the first cache calculation mark value and the cache error correction calculation value according to the initial error correction code; Wherein, the second determining module includes: a first detection unit, the first detection unit being used to output a first logic detection result of whether each bit value of the initial error correction code is a logic value "0"; a second detection unit, the second detection unit being used to output a second logic detection result of whether each bit value of the initial error correction code is a logic value "1"; a NAND logic unit, the NAND logic unit being used to determine a NAND logic operation result of the first logic detection result and the second logic detection result as intermediate control data; A first parity check unit, wherein the first parity check unit is used to perform a parity check on the initial error correction code to obtain a parity check result; A first inverter, wherein the first inverter is used to invert the parity check result to obtain a non-parity check result; a second parity check unit, the second parity check unit being used for performing an XOR operation on the intermediate comparison data and the initial error correction code to obtain an XOR operation result; A second inverter, the second inverter is used to invert the XOR operation result to obtain a non-XOR operation result; a first data selector, the first data selector being used to select the non-parity check result as the second cache calculation mark value when the intermediate control data is "1"; and to select the parity check result as the second cache calculation mark value when the intermediate control data is "0"; a second data selector, the second data selector being used to select the non-XOR operation result as the first cache calculation tag value when the intermediate control data is "1"; and to select the XOR operation result as the first cache calculation tag value when the intermediate control data is "0"; An error correction conversion unit, wherein the error correction conversion unit is used to convert a code different from the initial error correction code as the buffer error correction calculation value when each bit value of the initial error correction code is a logic value "0".

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