Image sensing readout circuit, readout system and solid-state imaging device

Abstract

The present invention discloses a readout circuit, a readout system, and a solid-state imaging device for image sensing, relating to the field of image sensing readout technology, and includes a pixel array unit for photoelectric signal conversion; a current mirror circuit unit; wherein the current mirror circuit unit includes: a common-source common-gate current mirror or two N-channel field-effect transistors; a negative impedance conversion unit; and a charge-discharge acceleration unit. The present invention utilizes a negative impedance conversion unit and a charge-discharge acceleration unit, and uses the negative impedance generated by the negative impedance conversion unit to offset the parasitic impedance that affects the VSL establishment speed, thereby accelerating the small signal establishment speed; and uses the charge-discharge acceleration unit to selectively cooperate with the VSL falling establishment process or rising establishment process to provide charge and discharge current to accelerate the large signal establishment speed. That is, the present application can respond and cooperate with the VSL falling establishment process or rising establishment process accordingly.

Description

Technical Field

[0001] The present invention relates to the field of image sensor readout technology, and in particular to a readout circuit, a readout system and a solid-state imaging device for image sensing. Background Art

[0002] The ADC (A / D Converter) in existing CMOS image sensors consists of a load current source array, a comparator array, and a counter array. The load current source array provides a constant current for the source follower of the pixel array. During the pixel array signal readout process, the charge in the photon diode (PD) is transferred to the floating diffusion (FD), causing the FD voltage to drop. This voltage is then passed through the pixel source follower (SF), causing the pixel array output signal (VSL) to drop.

[0003] During the above readout process, since the VSL drop process is affected by the parasitic resistance and capacitance of the metal traces and the equivalent output impedance of SF, the VSL drop process will be slowed down, so that the entire image sensor needs to spend time waiting for VSL to completely drop to a stable level during the readout process. The time consumed in this process is called the VSL settling time.

[0004] In the current image sensor configuration, if the VSL setup time is to be accelerated, the bias current of the load current source is often increased. On the one hand, the transconductance of the SF of the pixel array is increased to reduce its equivalent output impedance. On the other hand, during the large signal setup period, increasing the bias current of the load current source can speed up the setup of the large signal.

[0005] However, increasing the bias current of the load current source can usually only accelerate the falling build-up process of the pixel array output signal VSL (Vertical Signal Line), and may not respond when the pixel array output signal VSL rises from a low level. Summary of the Invention

[0006] The purpose of the present invention is to solve the problem in the prior art that the pixel array output signal VSL cannot respond when it is built up from a low level, and to propose a readout circuit, a readout system and a solid-state imaging device for image sensing.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A first aspect of the present invention provides an image sensing readout circuit, comprising:

[0009] A pixel array unit, wherein the pixel array unit is used for photoelectric signal conversion;

[0010] a current mirror circuit unit, the current mirror circuit unit being electrically connected to the pixel array unit and configured to provide a bias current;

[0011] Wherein, the current mirror circuit unit includes: a cascode current mirror or two N-channel field effect transistors;

[0012] A negative impedance conversion unit, the negative impedance conversion unit being electrically connected to the current mirror circuit unit, and the negative impedance conversion unit being used to generate a negative impedance to offset the parasitic impedance of the VSL itself;

[0013] A charge and discharge acceleration unit is used to provide charge and discharge current during the VSL drop establishment process or the VSL rise establishment process.

[0014] In some feasible solutions, the charge and discharge acceleration unit includes:

[0015] a rising voltage-current conversion circuit, one end of which is connected to the drain power supply voltage, and the rising voltage-current conversion circuit is used to perform voltage-current conversion in the VSL rising establishment process;

[0016] A falling voltage-current conversion circuit, wherein the falling voltage-current conversion circuit is used to perform voltage-current conversion in a VSL falling establishment process;

[0017] A switch circuit is electrically connected to the rising voltage-current conversion circuit and the falling voltage-current conversion circuit respectively, and the switch circuit is used to selectively connect the rising voltage-current conversion circuit and the falling voltage-current conversion circuit.

[0018] In some feasible solutions, the step-down voltage-current conversion circuit includes:

[0019] a first P-channel field effect transistor, one end of the first P-channel field effect transistor being connected to a drain power supply voltage, and the first P-channel field effect transistor being configured to provide a current source;

[0020] a second P-channel field effect transistor, one end of the second P-channel field effect transistor also being connected to a drain power supply voltage, and the second P-channel field effect transistor being configured to provide a bias current;

[0021] a capacitor, the capacitor being disposed on one side of the second P-channel field effect transistor, the capacitor being electrically connected to the second P-channel field effect transistor, and the capacitor being a bypass capacitor of the second P-channel field effect transistor;

[0022] a third P-channel field effect transistor, wherein a gate of the third P-channel field effect transistor is connected to a signal output node of a vertical signal line, and a source of the third P-channel field effect transistor is connected to the second P-channel field effect transistor;

[0023] a first N-channel field effect transistor, wherein the first N-channel field effect transistor is connected to the second P-channel field effect transistor, and the first N-channel field effect transistor is connected to a drain of the third P-channel field effect transistor;

[0024] A second N-channel field effect transistor, wherein the second N-channel field effect transistor and the first N-channel field effect transistor form a current mirror.

[0025] In some feasible solutions, the rising voltage-current conversion circuit includes:

[0026] a fifth N-channel field effect transistor, wherein the fifth N-channel field effect transistor is used for voltage-current conversion;

[0027] a sixth N-channel field-effect transistor, the sixth N-channel field-effect transistor being electrically connected to the fifth N-channel field-effect transistor, a gate of the sixth N-channel field-effect transistor being connected to a bias voltage, and the sixth N-channel field-effect transistor serving as a bias current source for the fifth N-channel field-effect transistor;

[0028] a fourth P-channel field-effect transistor, the fourth P-channel field-effect transistor being electrically connected to the fifth N-channel field-effect transistor;

[0029] a fifth P-channel field-effect transistor, the fifth P-channel field-effect transistor being electrically connected to the fourth P-channel field-effect transistor, the fifth P-channel field-effect transistor and the fourth P-channel field-effect transistor forming a current mirror;

[0030] a seventh N-channel field-effect transistor, the seventh N-channel field-effect transistor being electrically connected to the fifth P-channel field-effect transistor, a gate of the seventh N-channel field-effect transistor being connected to a bias voltage, and the seventh N-channel field-effect transistor being used as a bias current source for the fifth P-channel field-effect transistor;

[0031] A second capacitor is electrically connected to the fifth N-channel field effect transistor, and the second capacitor is used as a bypass capacitor of the fifth N-channel field effect transistor.

[0032] In some feasible solutions, the switching circuit includes:

[0033] A sixth P-channel field effect transistor, wherein a gate of the sixth P-channel field effect transistor is connected to CTRL, and the sixth P-channel field effect transistor is electrically connected to the drain of the second N-channel field effect transistor and the drain of the fifth P-channel field effect transistor respectively.

[0034] In some feasible solutions, the negative impedance conversion unit includes:

[0035] a first capacitor electrically connected to the pixel array unit;

[0036] a third N-channel field effect transistor, wherein a gate of the third N-channel field effect transistor is electrically connected to a bias voltage;

[0037] a fourth N-channel field-effect transistor, wherein a gate of the fourth N-channel field-effect transistor is electrically connected to the pixel array unit, a drain of the fourth N-channel field-effect transistor is connected to a power supply, and a source of the fourth N-channel field-effect transistor is electrically connected to the drain of the third N-channel field-effect transistor;

[0038] One end of the first capacitor is electrically connected to the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit unit.

[0039] In some feasible solutions, the current mirror circuit unit further includes:

[0040] The two N-channel field effect transistors are connected via a cascode connection, the gates of the cascode connected N-channel field effect transistors are connected to a bias voltage, and the sources of the cascode connected N-channel field effect transistors are electrically connected to the pixel array unit, the negative impedance conversion unit, and the charge and discharge acceleration unit respectively.

[0041] In some feasible solutions, the charge and discharge acceleration unit includes:

[0042] A rising voltage-current conversion circuit and / or a falling voltage-current conversion circuit.

[0043] A second aspect of the present invention provides an image sensing readout system, which employs an image sensing readout circuit according to any one of the first aspects, and further comprises:

[0044] A pixel driving module, wherein the pixel driving module comprises: a plurality of pixel array units;

[0045] a pixel noise detection module, the pixel noise detection module being electrically connected to the pixel driving module and configured to detect a pixel array unit in the pixel driving module;

[0046] a reference slope generating module, the reference slope generating module being electrically connected to the pixel driving module;

[0047] a comparator, the comparator being electrically connected to the readout circuit and the reference ramp generating module respectively;

[0048] a counter electrically connected to the comparator;

[0049] A data transmission module is electrically connected to the counter.

[0050] A third aspect of the present invention provides a solid-state imaging device, which uses an image sensing readout circuit according to any one of the first aspects or an image sensing readout system according to the second aspect.

[0051] The beneficial effects of the present invention are:

[0052] The present invention utilizes a negative impedance conversion unit and a charge-discharge acceleration unit. The negative impedance conversion unit generates negative impedance to offset the parasitic impedance that affects the VSL build-up speed, thereby accelerating the small signal build-up speed. The charge-discharge acceleration unit selectively provides charge and discharge current during the VSL falling or rising build-up process to accelerate the large signal build-up speed. In other words, the present invention can respond to and coordinate with the VSL falling or rising build-up process accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A schematic diagram of the working connection of an image sensing readout circuit provided in an embodiment of the present invention;

[0054] Figure 2 Schematic diagram of the structure of a pixel array unit in a pixel driving module provided in an embodiment of the present invention;

[0055] Figure 3 A schematic diagram of the connection between an image sensing readout circuit and a pixel array provided in an embodiment of the present invention;

[0056] Figure 4 This is a connection diagram of a current mirror circuit unit of an image sensing readout circuit provided in an embodiment of the present invention;

[0057] Figure 5 A schematic diagram of a negative impedance conversion circuit for generating negative resistance in an image sensing readout circuit provided in an embodiment of the present invention;

[0058] Figure 6 Schematic diagram of a VSL establishment process in an image sensing readout circuit provided in an embodiment of the present invention;

[0059] Figure 7The present invention provides a schematic diagram of the connection of a charge-discharge conversion unit in an image sensing readout circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0061] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0062] In the present invention, unless otherwise specified or limited, the terms "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can mean fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0063] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the meaning of "and / or" appearing throughout the text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme in which A and B are satisfied at the same time. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0064] Reference Figures 1 to 7The present invention aims to address the prior art's inability to respond to the rise of the pixel array output signal VSL from a low level. In a first aspect, a readout circuit for image sensing is provided. The readout circuit utilizes a negative impedance conversion unit 1062 and a charge-discharge acceleration unit 1063. The negative impedance generated by the negative impedance conversion unit 1062 offsets the parasitic capacitance 1102 that affects the VSL build-up speed, thereby accelerating the small signal build-up speed. The charge-discharge acceleration unit 1063 selectively provides charge and discharge current during the VSL falling or rising build-up process, thereby accelerating the large signal build-up speed. Specifically, the present invention is capable of responding to either the VSL falling or rising build-up process.

[0065] Reference Figure 4 、 Figure 5 Specifically, the first aspect of the present invention provides a readout circuit for image sensing, comprising: a pixel array unit 100, a current mirror circuit unit 1061, a negative impedance conversion unit 1062, and a charge and discharge acceleration unit 1063, wherein the pixel array unit 100 is used for photoelectric signal conversion; the current mirror circuit unit 1061 is electrically connected to the pixel array unit 100, and the current mirror circuit unit 1061 is used to provide a bias current; wherein the current mirror circuit unit 1061 may include: a cascode current mirror or two N-channel field effect transistors; The current mirror circuit 1061 includes a cascode current mirror or two N-channel field-effect transistors. Specifically, the current mirror circuit 1061 can be composed of two N-channel field-effect transistors (i.e., N-channel field-effect transistor 10611 and N-channel field-effect transistor 10612) connected via a cascode connection. The gates of the cascode-connected N-channel field-effect transistors are connected to a bias voltage, and the sources of the cascode-connected N-channel field-effect transistors are electrically connected to the pixel matrix unit 100, the negative impedance conversion unit 1062, and the charge-discharge acceleration unit 1063, respectively. That is, the gates of the two cascode-connected N-channel field-effect transistors are connected to VB2 and VB1, respectively, as the bias voltages for the cascode current mirror. The vertical signal line output node VSL_OUT 1103 is then connected to the negative impedance conversion unit 1062 and the charge-discharge acceleration unit 1063. It should be noted that the negative impedance conversion unit 1062 and the charge-discharge acceleration unit 1063 can be connected to the vertical signal line output node VSL_OUT1103 at the same time, or only one of them can be connected to the vertical signal line output node VSL_OUT1103 separately. The negative impedance conversion unit 1062 is electrically connected to the current mirror circuit unit 1061. The negative impedance conversion unit 1062 is used to generate a negative impedance to offset the parasitic impedance of VSL itself (such as parasitic capacitance 1101); the charge-discharge acceleration unit 1063 is used to provide charge and discharge current during the VSL falling or rising process.

[0066] Reference Figure 2 and Figure 3 In this embodiment, the pixel array unit 100 may be provided in plurality, and the pixel array unit 100 includes: a photodiode 1001, an N-channel field effect transistor 1002, an N-channel field effect transistor 1003, an N-channel field effect transistor 1004, and an N-channel field effect transistor 1005. When exposed to light, the photodiode 1001 completes photoelectric conversion, generating photogenerated electrons. When resetting, the gate connection signal RST of the N-channel field effect transistor 1003 is set high, the N-channel field effect transistor 1003 is turned on, and the potential of the floating diffusion point FD (Floating Diffusion) 1006 is reset to a level slightly lower than the power supply VDD. Subsequently, the RST signal is set low, ending the reset operation. When reading a signal, the gate connection signal TX of N-channel field effect transistor 1002 is set high, turning N-channel field effect transistor 1002 on. Since the potential of floating diffusion point FD1006 is higher than the positive terminal of photodiode 1001, photogenerated electrons generated by photodiode 1001 migrate toward floating diffusion point FD1006 through N-channel field effect transistor 1002, causing its voltage to drop. At this time, if the pixel row in which pixel unit 1000 is located is in a readout state, the gate connection signal SEL of N-channel field effect transistor 1005 is set high. When N-channel field effect transistor 1004 is turned on, it operates in a source-follower mode. When the potential of floating diffusion point FD1006 drops, it causes vertical signal line node VSL1007 to drop by a voltage slightly less than the voltage change of floating diffusion point FD1006. At this time, the voltage change of vertical signal line node VSL1007 corresponds to the signal intensity caused by the photogenerated electrons. In addition, the metal trace parasitic resistance 1101 of the vertical signal line node VSL1007 can be represented by resistor R0, its metal trace parasitic capacitance 1102 can be represented by capacitor C0, the load current source can be represented by an ideal current source 1104, and the vertical signal line output node connected to the load current source 1104 is VSL_OUT1103.

[0067] Reference Figure 5In this embodiment, in order to facilitate understanding of how to use the negative impedance conversion unit 1062 to generate negative impedance and offset the parasitic impedance during the rise or fall of VSL, the following description is given. In this embodiment, the negative impedance conversion unit 1062 further includes: a first capacitor 10621, a third N-channel field effect transistor 10622, and a fourth N-channel field effect transistor 10623. The first capacitor 10621 is electrically connected to the pixel array unit 100; the gate of the third N-channel field effect transistor 10622 is electrically connected to the pixel array unit 100; connected to a bias voltage; the gate of the fourth N-channel field effect transistor 10623 is electrically connected to the pixel array unit, the drain of the fourth N-channel field effect transistor 10623 is connected to a power supply, and the source of the fourth N-channel field effect transistor 10623 is electrically connected to the drain of the third N-channel field effect transistor 10622; wherein, one end of the first capacitor 10621 is electrically connected to the source of the fourth N-channel field effect transistor 10623, and the other end of the first capacitor 10621 is electrically connected to the current mirror circuit unit 1061. That is, in this embodiment, in negative impedance conversion unit 1062, third N-channel field-effect transistor 10622 serves as a bias current source for fourth N-channel field-effect transistor 10623. Fourth N-channel field-effect transistor 10623 functions as a source follower. The gate of fourth N-channel field-effect transistor 10623 is connected to vertical signal line output node VSL_OUT1103, the drain of fourth N-channel field-effect transistor 10623 is connected to a power supply, and the source of fourth N-channel field-effect transistor 10623 is connected to the drain of third N-channel field-effect transistor 10622 and one end of first capacitor 10621. The other end of first capacitor 10621 is connected to the source of an N-channel field-effect transistor 10611 in cascode current mirror circuit unit 1061. Therefore, in this embodiment, when the vertical signal line output node VSL_OUT1103 drops Vin=V1, assuming the input current is Iin and ignoring the body effect of the fourth N-channel field effect transistor 10623 (for example, connecting its substrate to the source), it can be considered that the transfer gain of the source follower is approximately equal to 1. At this time, for the negative impedance conversion unit in this embodiment, the transconductance of one N-channel field effect transistor 10611 in the cascode current mirror circuit unit 1061 is gm1, the change in its source voltage is Vx, the change in the source voltage of the fourth N-channel field effect transistor 10623 is Vy, the output impedance of the third N-channel field effect transistor 10622 is Ro, and the transconductance of the fourth N-channel field effect transistor 10623 is gm2. Then, according to Kirchhoff's current-voltage theorem, it can be obtained:

[0068] gm2*(Vin-Vy)+(Vx-Vy) / (1 / (s*C_NI))=Vy / Ro;

[0069] Iin=-gm1*Vx=(Vx-Vy) / (1 / (s*C_NI));

[0070] After transforming and simplifying the above equations, we can get approximately:

[0071] Zin=Vin / Iin=[gm1+gm1*gm2*Ro+s*C_NI*(gm2*Ro+gm1*Ro)] / gm1*gm2*Ro*s*C_NI;

[0072] In the formula, C_NI is the first capacitor. It can be seen from the above formula that at this time, the equivalent input impedance of the negative impedance conversion unit 1062 at low frequency is expressed as the sum of a negative resistance and a negative capacitance, and the equivalent input impedance at high frequency is expressed as a negative resistance, but the resistance value is small; therefore, gm2 and Ro can be reasonably designed according to actual conditions, so that the negative impedance conversion unit 1062 has a negative capacitance that can offset the parasitic capacitance 1102, thereby accelerating the speed of small signal establishment.

[0073] Reference Figure 6 and Figure 7 In this embodiment, in order to facilitate understanding of how the charge and discharge acceleration unit 1063 can provide charge and discharge currents respectively for the VSL rising establishment process or the falling establishment process, the following explanation is given here. Specifically, the charge and discharge acceleration unit 1063 includes: a rising voltage-current conversion circuit, a falling voltage-current conversion circuit, and a switching circuit. One end of the rising voltage-current conversion circuit is connected to the drain power supply voltage. The rising voltage-current conversion circuit is used to perform voltage-current conversion in the VSL rising establishment process; the falling voltage-current conversion circuit is used to perform voltage-current conversion in the VSL falling establishment process; the switching circuit is electrically connected to the rising voltage-current conversion circuit and the falling voltage-current conversion circuit respectively, and the switching circuit is used to select the rising voltage-current conversion circuit and the falling voltage-current conversion circuit for connection. That is, in this embodiment, a switching circuit, a falling voltage-current conversion circuit, and a rising-falling voltage-current conversion circuit are provided in the charge-discharge acceleration unit 1063, the gate of the switching circuit is externally connected to CTRL, and the switching circuit is electrically connected to the rising voltage-current conversion circuit and the falling voltage-current conversion circuit, respectively, so as to realize that when the vertical signal line node VSL1007 falls, the switching circuit is turned on; when the vertical signal line node VSL1007 rises, the switching circuit is turned off.

[0074] Reference Figure 7Specifically, the falling voltage-current conversion circuit includes: a first P-channel field effect transistor 10636, a second P-channel field effect transistor 10631, a capacitor 10632, a third P-channel field effect transistor 10633, a first N-channel field effect transistor 10634 and a second N-channel field effect transistor 10635. One end of the first P-channel field effect transistor 10636 is connected to a drain power supply voltage, and the first P-channel field effect transistor 10636 is used to provide a current source; one end of the second P-channel field effect transistor 10631 is also connected to a drain power supply voltage, and the second P-channel field effect transistor 10631 is used to provide a bias current; the capacitor 10632 is arranged on one side of the second P-channel field effect transistor 10631, and the capacitor 10632 is electrically connected to the second P-channel field effect transistor 10631. The capacitor 10632 is a bypass capacitor of the second P-channel field effect transistor 10631 (i.e., it reduces the second P-channel field effect transistor 10631). 31); the gate of the third P-channel field-effect transistor 10633 is connected to the vertical signal line signal output node VSL_OUT1103, and the source of the third P-channel field-effect transistor 10633 is connected to the second P-channel field-effect transistor 10631; the first N-channel field-effect transistor 10634 is connected to the second P-channel field-effect transistor 10631, and the first N-channel field-effect transistor 10634 is connected to the drain of the third P-channel field-effect transistor 10633; the second N-channel field-effect transistor 10635 and the first N-channel field-effect transistor 10634 form a current mirror. In this embodiment, the first P-channel field-effect transistor 10636 and the second P-channel field-effect transistor 10631 can function as current sources, and the capacitor 10632 can function as a bypass capacitor for the second P-channel field-effect transistor 10631. Second P-channel field-effect transistor 10631 is connected to third P-channel field-effect transistor 10633 and first N-channel field-effect transistor 10634. The gate of third P-channel field-effect transistor 10633 is connected to vertical signal line output node VSL_OUT1103. The drain of third P-channel field-effect transistor 10633, first N-channel field-effect transistor 10634, and first N-channel field-effect transistor 10634 and second N-channel field-effect transistor 10635 form a current mirror. The current mirror ratio is determined by the ratio of the width-to-length ratio of second N-channel field-effect transistor 10635 to the width-to-length ratio of first N-channel field-effect transistor 10634. First P-channel field-effect transistor 10636, acting as a current source, is set to a current that is approximately equal to the saturation current of second N-channel field-effect transistor 10635.During the falling establishment process of the vertical signal line output node VSL_OUT1103, the gate voltage of the third P-channel field effect transistor 10633 drops by ΔV. At this time, the third P-channel field effect transistor 10633 acts as a source follower, and its source voltage will drop. At this time, the capacitor 10632, which acts as a bypass capacitor, acts as a current source to provide a transient current ΔI=C1*dΔV / dt for the second P-channel field effect transistor 10631. The transient current is amplified by the current mirror composed of the first N-channel field effect transistor 10634 and the second N-channel field effect transistor 10635. The amplification factor is, as mentioned above, the ratio of the width-to-length ratio of the second N-channel field effect transistor 10635 to the first N-channel field effect transistor 10634:.

[0075] K=(W / L)_10635 / (W / L)_10634.

[0076] Therefore, it can be seen that the transient output current generated by the drain of the second N-channel field-effect transistor 10635 is K*ΔI. Since the first P-channel field-effect transistor 10636 is set to a constant current operating state, this transient current K*ΔI will be provided by the load capacitor through the vertical signal line output node VSL_OUT1103. If the current source current is set to I, then in this embodiment, the current flowing out of the load capacitor during the large signal setup period can be expressed as I+K*ΔI. Its magnitude can be adjusted by adjusting the capacitance value and the current mirror ratio K. Therefore, in this embodiment, the charge and discharge acceleration circuit 1063 speeds up the large signal setup speed of the vertical signal line output node VSL_OUT1103 by increasing the transient current flowing out of the load capacitor during the large signal setup period. It should be noted that under this operating condition, all field-effect transistors operate in saturation.

[0077] Specifically, the rising voltage-current conversion circuit includes: a fifth N-channel field effect transistor 10637, a sixth N-channel field effect transistor 106371, a fourth P-channel field effect transistor 106373, a fifth P-channel field effect transistor 106374, a seventh N-channel field effect transistor 106372, and a second capacitor 106376, wherein the fifth N-channel field effect transistor 10637 is used for voltage-current conversion; the sixth N-channel field effect transistor 106371 is electrically connected to the fifth N-channel field effect transistor 10637, the gate of the sixth N-channel field effect transistor 106371 is connected to a bias voltage, and the sixth N-channel field effect transistor 106371 is used as a bias current source for the fifth N-channel field effect transistor 10637; the fourth P-channel field effect transistor 106373 is electrically connected to the fifth N-channel field effect transistor The fifth P-channel field effect transistor 106374 is electrically connected to the fourth P-channel field effect transistor 106373, and the fifth P-channel field effect transistor 106374 and the fourth P-channel field effect transistor 106373 form a current mirror; the seventh N-channel field effect transistor 106372 is electrically connected to the fifth P-channel field effect transistor 106374, and the gate of the seventh N-channel field effect transistor 106372 is connected to the bias voltage, and the seventh N-channel field effect transistor 106372 is used as a bias current source for the fifth P-channel field effect transistor 106374; the second capacitor 106376 is electrically connected to the fifth N-channel field effect transistor 10637, and the second capacitor 106376 is used as a bypass capacitor for the fifth N-channel field effect transistor 10637. That is, in this embodiment, the fifth N-channel field-effect transistor 10637 functions as a voltage-to-current converter in the charge-discharge acceleration circuit 1063. The sixth N-channel field-effect transistor 106371 serves as a bias current source for the fifth N-channel field-effect transistor 10637, with its gate connected to bias voltage VB5. The fourth P-channel field-effect transistor 106373 and the fifth P-channel field-effect transistor 106374 form a current mirror, such that the current flowing through the fifth N-channel field-effect transistor 10637 also flows through the fourth P-channel field-effect transistor 106373. The seventh N-channel field-effect transistor 106372 serves as a bias current source for the fifth P-channel field-effect transistor 106374, with its gate connected to bias voltage VB6. VB6 is designed so that the DC current of the seventh N-channel field-effect transistor 106372 is approximately equal to that of the fifth P-channel field-effect transistor 106374.In the aforementioned charge-discharge acceleration unit, the switching circuit includes a sixth P-channel field-effect transistor 106375, the gate of which is connected to a CTRL. The sixth P-channel field-effect transistor is electrically connected to the drain of the second N-channel field-effect transistor and the drain of the fifth P-channel field-effect transistor 106374. In other words, the connection of the CTRL to the gate of the sixth P-channel field-effect transistor can be utilized to selectively switch on or off the rising voltage-current conversion circuit or the falling voltage-current conversion circuit based on the actual VSL establishment situation.

[0078] In this embodiment, a rising voltage-to-current conversion circuit is employed. When the vertical signal line node VSL1007 rises, causing the vertical signal line node VSL_OUT1103 to rise, the fifth N-channel field-effect transistor 10637 operates as a source follower. When its source voltage rises by ΔV, the voltage difference between the two plates of the second capacitor 106376 increases. At this time, the charging current of the second capacitor 106376 changes by: ΔI = C2 * dΔV / dt, where C2 is the value of the second capacitor 106376. This portion of ΔI also flows through the fourth P-channel field-effect transistor 106373, which forms a current mirror. This transient current is amplified by the current mirror formed by the fourth P-channel field-effect transistor 106373 and the fifth P-channel field-effect transistor 106374. The amplification factor is the ratio of the width-to-length ratio of the fourth P-channel field-effect transistor 106373 to the fifth P-channel field-effect transistor 106374:

[0079] K=(W / L)_106374 / (W / L)_106373;

[0080] As can be seen from the above, the transient output current generated by the drain of the fifth P-channel field-effect transistor 106374 is K*ΔI. Since the seventh N-channel field-effect transistor 106372 is set to a constant current operating state, this transient current K*ΔI will charge the load capacitor through the vertical signal line node VSL_OUT1103. If the current flowing through the N-channel field-effect transistor 1004 of the pixel array unit 100 is I, then in this embodiment, the current flowing into the load capacitor during the rise and build-up period of the vertical signal line node VSL_OUT1103 can be expressed as I+K*ΔI. The current can be adjusted by adjusting the capacitance of the bypass capacitor (i.e., the second capacitor 106376) and the current mirror ratio K. Therefore, in this embodiment, the charge-discharge acceleration circuit 1602 accelerates the rise and build-up period of the vertical signal line node VSL_OUT1103 by increasing the transient current that charges the load capacitor during the rise and build-up period.

[0081] Reference Figure 1According to a second aspect of the present invention, a readout system for image sensing is provided, which adopts an image sensing readout circuit 106 according to any one of the first aspects. The readout system further includes: a pixel driving module 101, a pixel noise detection module 102, and a reference ramp generation module 103. The pixel driving module 101 includes: a plurality of pixel array units 100, each configured to perform photoelectric conversion; the pixel noise detection module 102 is electrically connected to the pixel driving module 101, and is configured to detect the pixel array units 100 in the pixel driving module 101; the reference ramp generation module 103 is electrically connected to the pixel driving module 101; the comparator 107 is electrically connected to the readout circuit 106 and the reference ramp generation module 103, respectively; the counter 108 is electrically connected to the comparator 107; and the data transmission module 109 is electrically connected to the counter 108. The readout system is equipped with a charge and discharge acceleration unit that can be used for the VSL rising establishment process and / or the VSL falling establishment process, so that the establishment time of the vertical signal line node VSL1007 can be accelerated regardless of whether it is a rising establishment process or a falling establishment process.

[0082] It should be noted that in this readout system, the rising voltage-to-current conversion circuit and the falling voltage-to-current conversion circuit may both exist in the readout system or may exist separately. That is, the readout system may include the rising voltage-to-current conversion circuit and / or the falling voltage-to-current conversion circuit.

[0083] In some embodiments, the readout system can communicate using any currently known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication (e.g., a communication network) of any form or medium. Examples of communication networks include local area networks ("LAN"), wide area networks ("WAN"), internets (e.g., the Internet), and end-to-end networks (e.g., adhoc end-to-end networks), as well as any currently known or future developed networks. The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0084] A third aspect of the present invention provides a solid-state imaging device, utilizing the image sensing readout circuit described in any one of the first aspects or the image sensing readout system described in the second aspect. Specifically, the solid-state imaging device can establish a VSL signal by utilizing the aforementioned current mirror circuit unit 1061, negative impedance conversion unit, and charge / discharge acceleration unit 1063. Simultaneously, the rising voltage-to-current conversion circuit and the falling voltage-to-current conversion circuit can accelerate the establishment time of the vertical signal line node VSL 1007, whether in the rising or falling establishment process, to meet imaging requirements.

[0085] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0086] The above description is only an illustration of some preferred embodiments of the present disclosure and the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, the above-mentioned features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A readout circuit for image sensing, characterized in that: include: A pixel array unit, wherein the pixel array unit is used for photoelectric signal conversion; a current mirror circuit unit, the current mirror circuit unit being electrically connected to the pixel array unit and configured to provide a bias current; Wherein, the current mirror circuit unit includes: a cascode current mirror or two N-channel field effect transistors; A negative impedance conversion unit, the negative impedance conversion unit being electrically connected to the current mirror circuit unit, and the negative impedance conversion unit being used to generate a negative impedance to offset the parasitic impedance of the VSL itself; A charge and discharge acceleration unit, configured to provide a charge and discharge current during a VSL drop establishment process or a VSL rise establishment process; The charge and discharge acceleration unit includes: a rising voltage-current conversion circuit, one end of which is connected to the drain power supply voltage, and the rising voltage-current conversion circuit is used to perform voltage-current conversion in the VSL rising establishment process; A falling voltage-current conversion circuit, wherein the falling voltage-current conversion circuit is used to perform voltage-current conversion in a VSL falling establishment process; a switching circuit, the switching circuit being electrically connected to the rising voltage-current conversion circuit and the falling voltage-current conversion circuit, respectively, and the switching circuit being used to selectively connect the rising voltage-current conversion circuit and the falling voltage-current conversion circuit; The step-down voltage-current conversion circuit includes: a first P-channel field effect transistor, one end of the first P-channel field effect transistor being connected to a drain power supply voltage, and the first P-channel field effect transistor being configured to provide a current source; a second P-channel field effect transistor, one end of the second P-channel field effect transistor also being connected to a drain power supply voltage, and the second P-channel field effect transistor being configured to provide a bias current; a capacitor, the capacitor being disposed on one side of the second P-channel field effect transistor, the capacitor being electrically connected to the second P-channel field effect transistor, and the capacitor being a bypass capacitor of the second P-channel field effect transistor; a third P-channel field effect transistor, wherein a gate of the third P-channel field effect transistor is connected to a signal output node of a vertical signal line, and a source of the third P-channel field effect transistor is connected to the second P-channel field effect transistor; a first N-channel field effect transistor, wherein the first N-channel field effect transistor is connected to the second P-channel field effect transistor, and the first N-channel field effect transistor is connected to a drain of the third P-channel field effect transistor; a second N-channel field effect transistor, wherein the second N-channel field effect transistor and the first N-channel field effect transistor form a current mirror; The rising voltage-current conversion circuit includes: a fifth N-channel field effect transistor, wherein the fifth N-channel field effect transistor is used for voltage-current conversion; a sixth N-channel field-effect transistor, the sixth N-channel field-effect transistor being electrically connected to the fifth N-channel field-effect transistor, a gate of the sixth N-channel field-effect transistor being connected to a bias voltage, and the sixth N-channel field-effect transistor serving as a bias current source for the fifth N-channel field-effect transistor; a fourth P-channel field-effect transistor, the fourth P-channel field-effect transistor being electrically connected to the fifth N-channel field-effect transistor; a fifth P-channel field-effect transistor, the fifth P-channel field-effect transistor being electrically connected to the fourth P-channel field-effect transistor, the fifth P-channel field-effect transistor and the fourth P-channel field-effect transistor forming a current mirror; a seventh N-channel field-effect transistor, the seventh N-channel field-effect transistor being electrically connected to the fifth P-channel field-effect transistor, a gate of the seventh N-channel field-effect transistor being connected to a bias voltage, and the seventh N-channel field-effect transistor being used as a bias current source for the fifth P-channel field-effect transistor; A second capacitor is electrically connected to the fifth N-channel field effect transistor, and the second capacitor is used as a bypass capacitor of the fifth N-channel field effect transistor.

2. The image sensing readout circuit according to claim 1, wherein: The switching circuit comprises: A sixth P-channel field effect transistor, wherein a gate of the sixth P-channel field effect transistor is connected to CTRL, and the sixth P-channel field effect transistor is electrically connected to the drain of the second N-channel field effect transistor and the drain of the fifth P-channel field effect transistor respectively.

3. The image sensing readout circuit according to claim 2, wherein: The negative impedance conversion unit includes: a first capacitor electrically connected to the pixel array unit; a third N-channel field effect transistor, wherein a gate of the third N-channel field effect transistor is electrically connected to a bias voltage; a fourth N-channel field-effect transistor, wherein a gate of the fourth N-channel field-effect transistor is electrically connected to the pixel array unit, a drain of the fourth N-channel field-effect transistor is connected to a power supply, and a source of the fourth N-channel field-effect transistor is electrically connected to the drain of the third N-channel field-effect transistor; One end of the first capacitor is electrically connected to the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit unit.

4. The image sensing readout circuit according to claim 3, wherein: The current mirror circuit unit further includes: The two N-channel field effect transistors are connected via a cascode connection, the gates of the cascode connected N-channel field effect transistors are connected to a bias voltage, and the sources of the cascode connected N-channel field effect transistors are electrically connected to the pixel array unit, the negative impedance conversion unit, and the charge and discharge acceleration unit respectively.

5. The image sensing readout circuit according to claim 4, wherein: The charge and discharge acceleration unit includes: A rising voltage-current conversion circuit and / or a falling voltage-current conversion circuit.

6. A readout system for image sensing, characterized in that: An image sensing readout circuit according to any one of claims 1 to 5 is used, wherein the readout system further comprises: A pixel driving module, wherein the pixel driving module comprises: a plurality of pixel array units; a pixel noise detection module, the pixel noise detection module being electrically connected to the pixel driving module and configured to detect a pixel array unit in the pixel driving module; a reference slope generating module, the reference slope generating module being electrically connected to the pixel driving module; a comparator, the comparator being electrically connected to the readout circuit and the reference ramp generating module respectively; a counter electrically connected to the comparator; A data transmission module is electrically connected to the counter.

7. A solid-state imaging device, characterized in that An image sensing readout circuit according to any one of claims 1 to 5 or an image sensing readout system according to claim 6 is used.

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