Groove type IGBT device and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a groove type IGBT device and a manufacturing method thereof, and the method comprises a substrate, and a P-base region, a gate region and an emitter region which are located on the substrate; the P-base region is located between the gate regions, and the P-base region is in contact with the gate regions; the emitter region comprises an N + active region, a short circuit region, a latch region and an emitter metal region; the N + active region is located on the P-base region, located between the gate regions and located between the gate regions and the short circuit region; the short circuit regions are distributed on the P-base region at intervals, are positioned on the latch region and are in contact with the latch region; the latch region is located in the P-base region and is correspondingly located below the interval region between the short circuit regions; the spacer region is filled with the emitter metal region, and the emitter metal region covers the N + active region, the short circuit region and the gate region. According to the device structure, the saturation current of the IGBT device is effectively reduced, the anti-short-circuit capability of the IGBT is greatly improved, and the anti-latch-up capability of the IGBT device is improved at the same time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench IGBT device and a manufacturing method thereof. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a core power electronic device with a wide range of applications, playing a huge role in rail transit, smart grid, new energy vehicles and other fields. At present, IGBT devices mainly use trench technology. In order to pursue a lower saturation voltage drop, the trench density of IGBT devices is getting larger and larger, which greatly increases the saturation current of IGBT devices. As a result, the short-circuit resistance of existing IGBT devices has become increasingly poor, which needs to be optimized and improved.

[0003] In order to solve the problem of the deterioration of the short-circuit resistance of existing IGBT devices, the existing solution proposes to introduce a lightly doped N-ballast resistor in the emitter region of the IGBT device. This solution can reduce the saturation current to a certain extent and improve the short-circuit resistance of the IGBT device. However, the ballast resistor of this solution has a negative temperature coefficient. When the IGBT device is short-circuited and the temperature rises, the resistance value of the IGBT device decreases, which makes the improvement of the short-circuit resistance limited. Therefore, the existing IGBT device still has the problem of poor short-circuit resistance. Summary of the invention

[0004] The embodiments of the present application provide a trench IGBT device and a method for manufacturing the same, thereby solving the technical problem in the prior art that the IGBT device still has poor short-circuit resistance, and achieving technical effects such as effectively reducing the saturation current of the IGBT device, greatly improving the short-circuit resistance of the IGBT, and improving the anti-latch capability of the IGBT device.

[0005] In a first aspect, an embodiment of the present invention provides a trench IGBT device, comprising: a substrate, and a P-base region, a gate region, and an emitter region located on the substrate; The P-base region is located between the gate regions, and the P-base region is in contact with the gate region; The emitter region includes: an N+ active region, a short circuit region, a latch region and an emitter metal region; The N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region; The short-circuit regions are spaced apart on the P-base region, located between the gate regions, and located on the latch region and in contact with the latch region; The latch region is located in the P-base region, between the gate regions, and below the spacing region corresponding to the spacing region between the short-circuit regions; The emitter metal region is filled in the spacer area and covers the N+ active area, the short circuit area and the gate area.

[0006] Optionally, the short-circuit area includes: a short-circuit trench and short-circuit polysilicon; the short-circuit polysilicon is filled in the short-circuit trench, so that the short-circuit area forms a ballast resistor to improve the short-circuit resistance of the IGBT device.

[0007] Optionally, the latch region includes: a latch trench and latch polysilicon, and the latch polysilicon is filled in the latch trench so that the latch region serves as a polysilicon electrode to improve the anti-latch capability of the IGBT device.

[0008] Optionally, the junction depth of the N+ active region is not less than the depth of the short-circuit trench.

[0009] Optionally, the depth of the short-circuit groove is smaller than the depth of the latch groove, and the width of the short-circuit groove is larger than the depth of the latch groove.

[0010] Optionally, the depth of the short-circuit groove ranges from 0.1 to 0.3 um, and the width of the short-circuit groove ranges from 0.4 to 2 um; the depth of the latch groove ranges from 0.2 to 1 um, and the width of the latch groove ranges from 0.2 to 1.8 um.

[0011] Optionally, the gate region includes: a gate trench, a gate oxide layer and gate polysilicon; The gate oxide layer is located on the inner wall of the gate trench; The gate polysilicon fills the space formed by the gate oxide layer.

[0012] Optionally, it also includes: a dielectric layer; the dielectric layer is located above the gate area, the N+ active area and the short circuit area, and is located below the emitter metal area, and the perforations of the dielectric layer correspond to the spacing area so that the emitter metal area is filled in the perforations.

[0013] Optionally, it also includes: an N-type field stop region, a P-type collector region and a collector metal region; The N-type field termination region is located below the substrate; The P-type collector region is located below the N-type field stop region; The collector metal region is located below the P-type collector region.

[0014] Based on the same inventive concept, in a second aspect, the present invention further provides a method for manufacturing a trench IGBT device, which is used to manufacture the trench IGBT device as described in the first aspect, and the method comprises: forming a gate region on the substrate; forming a P-base region and an emitter region between the gate regions, wherein the P-base region is located between the gate regions and the P-base region is in contact with the gate regions; The emitter region includes: an N+ active region, a short circuit region, a latch region and an emitter metal region; The N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region; The short-circuit regions are spaced apart on the P-base region, located between the gate regions, and located on the latch region and in contact with the latch region; The latch region is located in the P-base region, between the gate regions, and below the spacing region corresponding to the spacing region between the short-circuit regions; The emitter metal region is filled in the spacer area and covers the N+ active area, the short circuit area and the gate area.

[0015] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: In an embodiment of the present invention, a short-circuit region is introduced in the emitter region so that the short-circuit region forms a ballast resistor, and the short-circuit resistance of the IGBT device is improved by the short-circuit region. Moreover, when the short-circuit temperature of the IGBT device increases, the resistance value of the short-circuit region becomes larger, which can greatly reduce the saturation current and improve the short-circuit resistance of the device. At the same time, a latch region is introduced in the emitter region so that when the IGBT device is turned on, most holes will reach the emitter metal region of the IGBT device from the latch region, thereby reducing the hole concentration below the N+ active region, making it difficult for the parasitic triode to turn on, and improving the anti-latch capability of the IGBT device. In this way, by setting the emitter region on the P-base region between the gate regions, not only the structure of the IGBT device is improved, but also the short-circuit resistance of the IGBT device is improved, and the anti-latch capability of the device is enhanced. Under the premise of the same short-circuit resistance of the IGBT device, compared with the usual IGBT device, the IGBT device of this embodiment does not affect the forward conduction voltage drop and does not increase the conduction loss. The purpose of reducing costs and increasing efficiency is achieved through the structure of the IGBT device in the embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings: Figure 1 A schematic diagram showing the structure of a trench IGBT device in an embodiment of the present invention is shown; Figure 2 A schematic diagram of a structure in which a gate trench is formed on a substrate in an embodiment of the present invention is shown; Figure 3 A schematic diagram of the structure of forming a short-circuit trench in an embodiment of the present invention is shown; Figure 4 A schematic diagram of a structure for forming a latch groove in an embodiment of the present invention is shown; Figure 5 A schematic diagram of a structure in which a gate oxide layer is formed in a gate trench in an embodiment of the present invention is shown; Figure 6 A schematic diagram of a structure in which polysilicon is filled in a gate trench, a short-circuit trench and a latch trench in an embodiment of the present invention is shown; Figure 7 A schematic diagram of the structure of forming a P-base region, an N+ active region, a dielectric layer and an emitter metal region in an embodiment of the present invention is shown; Figure 8 A short-circuit current curve diagram of a trench IGBT device in an embodiment of the present invention is shown; Fig. 9 An equivalent circuit diagram of a trench IGBT device in an embodiment of the present invention is shown; Fig.10 A schematic flow chart of the steps of a method for manufacturing a trench IGBT device in an embodiment of the present invention is shown.

[0017] In the accompanying drawings, 110, substrate; 111, P-base region; 120, gate region; 130, emitter region; 140, dielectric layer; 150, N-type field stop region; 160, P-type collector region; 170, collector metal region; 121, gate trench; 122, gate oxide layer; 123, gate polysilicon; 131. N+ active region; 132. short-circuit region; 133. latch region; 134. emitter metal region; 1321. short-circuit trench; 1322. short-circuit polysilicon; 1331. latch trench; 1332. latch polysilicon. DETAILED DESCRIPTION

[0018] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0019] Embodiment 1 A first embodiment of the present invention provides a trench IGBT device, such as Figure 1 As shown, it includes: a substrate 110, and a P-base region 111, a gate region 120, and an emitter region 130 located on the substrate 110. The P-base region 111 is located between the gate regions 120, and the P-base region 111 is in contact with the gate region 120.

[0020] The emitter region 130 includes: an N+ active region 131, a short-circuit region 132, a latch region 133, and an emitter metal region 134. The N+ active region 131 is located on the P-base region 111, between the gate regions 120, and between the gate region 120 and the short-circuit region 132. The short-circuit region 132 is spaced apart on the P-base region 111, between the gate regions 120, and above the latch region 133, and in contact with the latch region 133. The latch region 133 is located in the P-base region 111, between the gate regions 120, and under the spaced region corresponding to the spaced region between the short-circuit regions 132. The emitter metal region 134 is filled in the spaced region and covers the N+ active region 131, the short-circuit region 132, and the gate region 120.

[0021] It should be noted that N-type single crystal silicon material is used as the material of the substrate 110, which serves as the drift region of the IGBT device. The substrate 110 is an N-type lightly doped substrate. The P-base region 111 is a P-type lightly doped base region.

[0022] In this embodiment, a short-circuit region 132 is introduced in the emitter region 130 so that the short-circuit region 132 forms a ballast resistor, and the short-circuit resistance of the IGBT device is improved by the short-circuit region 132. In addition, when the short-circuit temperature of the IGBT device increases, the resistance value of the short-circuit region 132 becomes larger, which can greatly reduce the saturation current and improve the short-circuit resistance of the device. At the same time, a latch region 133 is introduced in the emitter region 130, so that when the IGBT device is turned on, most holes will reach the emitter metal region 134 of the IGBT device from the latch region 133, thereby reducing the hole concentration below the N+ active region 131, making it difficult for the parasitic transistor to turn on, and improving the anti-latch capability of the IGBT device. In this way, by setting the emitter region 130 on the P-base region 111 between the gate regions 120, not only the structure of the IGBT device is improved, but also the short-circuit resistance of the IGBT device is improved, and the anti-latch capability of the device is enhanced. Under the premise that the IGBT device has the same short-circuit resistance, compared with the common IGBT device, the IGBT device of this embodiment does not affect the forward conduction voltage drop and does not increase the conduction loss. The structure of the IGBT device of this embodiment achieves the purpose of reducing costs and increasing efficiency.

[0023] Next, combine Figure 1 The specific structure of the trench IGBT device provided in this embodiment is described in detail: Figure 1 The structure shown is the minimum repeating unit structure of the IGBT device. Figure 1 In the embodiment, the IGBT device includes: a substrate 110, and a P-base region 111, two gate regions 120, and an emitter region 130 located on the substrate 110. The P-base region 111 is located between the gate regions 120, the left side of the P-base region 111 contacts the gate region 120 on the left, and the right side of the P-base region 111 contacts the gate region 120 on the right.

[0024] The emitter region 130 includes two N+ active regions 131 , two short-circuit regions 132 , a latch region 133 and an emitter metal region 134 .

[0025] Specifically, the short-circuit region 132 includes a short-circuit trench 1321 and a short-circuit polysilicon 1322. The short-circuit polysilicon 1322 is made of polysilicon. The short-circuit polysilicon 1322 is filled in the short-circuit trench 1321 so that the short-circuit region 132 forms a ballast resistor to improve the short-circuit resistance of the IGBT device. Figure 1As shown, the emitter region 130 of this embodiment includes two short-circuit regions 132, and the two short-circuit regions 132 are formed by the same short-circuit groove 1321 during the manufacturing process. In the same short-circuit groove 1321, polysilicon is filled on the left and right sides respectively to form two short-circuit regions 132 distributed at intervals. The empty area between the two short-circuit regions 132 is a spacing region, and the depth of the spacing region is less than the depth of the short-circuit groove 1321 to ensure the stability of the emitter. Among them, the depth range of the short-circuit groove 1321 is 0.1~0.3um, and the width range of the short-circuit groove 1321 is 0.4~2um.

[0026] Principle of the short-circuit region 132: In this embodiment, a polysilicon resistor, i.e., a ballast resistor with a positive temperature coefficient, is formed by etching a short-circuit groove 1321 and then depositing polysilicon at the N+ active region 131 in the emitter region 130. When the IGBT device is short-circuited, it is equivalent to a resistor connected in series to the IGBT. Therefore, under the same bus voltage, the total resistance increases, thereby reducing the short-circuit current and improving the short-circuit resistance. The ballast resistor (i.e., the polysilicon resistor) of this embodiment is a resistor with a positive temperature coefficient. Compared with the ballast resistor with a negative temperature coefficient, when the IGBT device of this embodiment is short-circuited, as the short-circuit temperature increases, the ballast resistor will become larger, thereby making the short-circuit current smaller and improving the short-circuit resistance more efficiently. In addition, the larger the width of the polysilicon resistor and the smaller the depth, the larger the polysilicon resistance value, the smaller the short-circuit current, and the stronger the short-circuit resistance.

[0027] In this embodiment, highly doped polysilicon is deposited in the short-circuit trench 1321 to introduce a highly doped polysilicon ballast resistor into the emitter region 130. Since the polysilicon ballast resistor is a ballast resistor with a positive temperature coefficient, when the IGBT device is short-circuited, as the short-circuit temperature increases, the polysilicon ballast resistor increases, which can greatly reduce the saturation current and improve the short-circuit resistance of the IGBT device.

[0028] Two N+ active regions 131 are located on the P-base region 111 and between the gate regions 120. The N+ active region 131 is an active region with a heavy N-type doping concentration. The left N+ active region 131 is located between the left gate region 120 and the left short-circuit region 132, the left side of the left N+ active region 131 contacts the left gate region 120, and the right side of the left N+ active region 131 contacts the left short-circuit region 132. Similarly, the right N+ active region 131 is located between the right gate region 120 and the right short-circuit region 132, the left side of the right N+ active region 131 contacts the right short-circuit region 132, and the right side of the right N+ active region 131 contacts the right gate region 120.

[0029] The junction depth of the N+ active region 131 is not less than the depth of the short-circuit trench 1321 to improve the short-circuit resistance of the device. It should be noted that when the junction depth of the N+ active region 131 is greater than the depth of the short-circuit trench 1321, the N+ active region 131 wraps around the short-circuit trench 1321, that is, the N+ active region 131 wraps around the short-circuit region 132.

[0030] The latching region 133 is located in the P-base region 111 between the two gate regions 120, and is located below the two short-circuit regions 132, and is arranged corresponding to the spacing region between the two short-circuit regions 132, and is also in contact with the two short-circuit regions 132 respectively. The latching region 133 includes: a latching groove 1331 and a latching polysilicon 1332. The latching polysilicon 1332 is made of polysilicon. The latching polysilicon 1332 is filled in the latching groove 1331 so that the latching region 133 serves as a polysilicon electrode to improve the anti-latch capability of the IGBT device. The short-circuit groove 1321 and the latching groove 1331 form a T-shaped groove. Highly doped polysilicon is deposited in the T-shaped groove to introduce a positive temperature coefficient polysilicon resistor and a polysilicon electrode in the emitter region 130.

[0031] The depth of the short-circuit groove 1321 is less than the depth of the latch groove 1331, and the width of the short-circuit groove 1321 is greater than the depth of the latch groove 1331, so as to increase the ballast resistance value, which is more conducive to improving the short-circuit resistance. The depth of the short-circuit groove 1321 is less than or equal to the junction depth of the N+ active area 131, and the depth of the latch groove 1331 needs to be greater than the junction depth of the N+ active area 131, which is more conducive to improving the anti-latch capability. The depth range of the latch groove 1331 is 0.2~1um, and the width range of the latch groove 1331 is 0.2~1.8um. The bottom of the latch region 133 of the present application is close to the bottom of the P-base region 111, so that when the IGBT device is turned on, most holes will reach the emitter metal region 134 from the polysilicon electrode in the latch trench 1331, thereby reducing the hole concentration under the N+ active region 131, making it difficult for the parasitic transistor to turn on, thereby improving the anti-latch capability.

[0032] Principle of latching region 133: In the structure of a conventional IGBT device (i.e., the IGBT device structure without the latching region 133 of this embodiment), when the IGBT device is turned on, most holes will pass through the bottom of the N+ active region 131 to reach the emitter metal region 134, making the P-N+ diode (i.e., the diode formed by the P-base region 111 and the N+ active region 131) easy to turn on. This causes the N+PN- parasitic triode (i.e., the triode formed by the N+ active region 131, the P-base region 111, and the N-substrate 110) to turn on, causing the latching effect. By setting the bottom of the polysilicon electrode in the latching groove 1331 close to the bottom of the P-base region 111, when the IGBT device is turned on, most holes will reach the emitter metal region 134 from the polysilicon electrode in the latching groove 1331, thereby reducing the hole concentration under the N+ active region 131, making it difficult for the parasitic triode to turn on, and improving the anti-latch capability. In addition, the greater the depth of the latching groove 1331 and the polysilicon electrode formed by polysilicon and the smaller the width, the stronger the anti-latch capability.

[0033] It should be noted that the width and depth of the short-circuit groove 1321 and the latch groove 1331 of the T-shaped groove can be set according to actual needs to meet different short-circuit resistance and latch-up resistance capabilities.

[0034] The gate region 120 includes a gate trench 121, a gate oxide layer 122 and a gate polysilicon 123. The gate oxide layer 122 is located on the inner wall of the gate trench 121, that is, the gate oxide layer 122 is located on the bottom wall and the inner side wall of the gate trench 121. The gate polysilicon 123 fills the space formed by the gate oxide layer 122.

[0035] The IGBT device of this embodiment further includes: a dielectric layer 140. The dielectric layer 140 is located above the gate region 120, the N+ active region 131 and the short-circuit region 132, and below the emitter metal region 134, and the perforations of the dielectric layer 140 correspond to the spacing regions, so that the emitter metal region 134 is filled in the perforations. The dielectric layer 140 is an ILD dielectric layer (InterLayerDielectric, interlayer dielectric layer) to play a role in electrical isolation, improve signal transmission speed and reduce power consumption, and provide physical support for the emitter metal region 134 to ensure structural stability.

[0036] The IGBT device of this embodiment further includes: an N-type field stop region 150, a P-type collector region 160 and a collector metal region 170. The N-type field stop region 150 is located below the substrate 110. The N-type field stop region 150 is a field stop region with an N-type heavy doping concentration. The P-type collector region 160 is located below the N-type field stop region 150. The P-type collector region 160 is a collector region with a P-type heavy doping concentration. The collector metal region 170 is located below the P-type collector region 160.

[0037] Next, combine Figure 1 The manufacturing process of the IGBT device of this embodiment is described below: like Figure 2 As shown, a gate trench 121 is etched on the N-substrate 110, and the gate trench 121 has a depth ranging from 3 to 6 um and a width ranging from 0.6 to 1.2 um.

[0038] like Figure 3 As shown, a short-circuit trench 1321 is etched on the N-substrate 110 between two adjacent gate trenches 121. The depth of the short-circuit trench 1321 ranges from 0.1 to 0.3 um, and the width of the short-circuit trench 1321 ranges from 0.4 to 2 um.

[0039] like Figure 4 As shown, a latching groove 1331 is etched in the short-circuit groove 1321 , the depth of the latching groove 1331 is in the range of 0.2-1 um, and the width of the latching groove 1331 is in the range of 0.2-1.8 um.

[0040] like Figure 5 As shown, an oxide layer is thermally grown on the inner wall of the gate trench 121 to obtain a gate oxide layer 122 in the gate trench 121. The oxide layers on the surface of the short-circuit trench 1321, the latch trench 1331 and the N-substrate 110 are removed, and the gate oxide layer 122 in the gate trench 121 is retained.

[0041] like Figure 6 As shown, polysilicon with high doping concentration is deposited in the space formed by the gate oxide layer 122 in the gate trench 121, in the short-circuit trench 1321 and in the latch trench 1331 to obtain the gate region 120, the continuous short-circuit region 132 (i.e., the short-circuit trench 1321, the short-circuit polysilicon 1322) and the latch region 133 (i.e., the latch trench 1331, the latch polysilicon 1332). The etching is then performed to make the surface of the gate region 120, the surface of the short-circuit trench 1321 and the surface of the N-substrate 110 at the same level. The doping concentration of the polysilicon ranges from 1E10 19 ~1E10 21 cm -3 .

[0042] like Figure 7As shown, an implantation and junction pushing process is performed to form a P-base region 111 and an N+ active region 131 between the two gate regions 120. The junction depth of the N+ active region 131 is greater than or equal to the depth of the short-circuit trench 1321, and the junction depth of the P-base region 111 is greater than the depth of the latch trench 1331. Then, a dielectric layer 140 is deposited, and after hole etching is performed in the dielectric layer 140 and the polysilicon in the short-circuit trench 1321 (the depth of the hole is less than the depth of the short-circuit trench 1321), metal is deposited to obtain short-circuit regions 132 distributed at intervals, and metal filled in the interval region formed by the hole, to form an emitter metal region 134. The emitter metal region 134 covers the N+ active region 131, the short-circuit region 132 and the gate region 120.

[0043] like Figure 1 As shown, by performing conventional back side processes such as ion implantation, annealing, and back side metal deposition on the back side of the substrate 110, an N-type field termination region 150, a P-type collector region 160, and a collector metal region 170 are sequentially formed on the back side of the substrate 110, and finally a complete IGBT device structure is formed.

[0044] The manufacturing process of this embodiment is compatible with the existing process, improves the structure of the IGBT device, and realizes the structure of the short-circuit region 132 and the latch region 133 of the emitter region 130. Therefore, the short-circuit region 132 greatly improves the short-circuit resistance of the IGBT, and the latch region 133 enhances the latch resistance of the IGBT device.

[0045] The principle of the trench IGBT device of this embodiment is as follows: Figure 8 The short-circuit current curves of the trench IGBT device of the present embodiment and the trench IGBT device without the short-circuit region 132 and the latch region 133 (i.e., the comparative device) are shown, with the horizontal axis representing time and the vertical axis representing the short-circuit current Ic of the device. Among them, the other structures of the comparative device except that the short-circuit region 132 and the latch region 133 are not provided are consistent with the structure of the trench IGBT device of the present embodiment. P represents the short-circuit current curve of the trench IGBT device of the present embodiment, and Q represents the short-circuit current curve of the comparative device. P1 and Q1 represent the inflection points when the short circuit occurs, that is, the device current starts to rise and reaches the saturation current point of the device. P2 and Q2 represent the failure inflection points, that is, after the short circuit of the device occurs, the device fails after a certain period of time, and the current keeps rising and is uncontrolled. The short-circuit current of the trench IGBT device of the present embodiment is much smaller than the short-circuit current of the comparative device, and the short-circuit tolerance time is also much higher than that of the comparative device. Therefore, the trench IGBT device structure of the present embodiment greatly improves the short-circuit resistance.

[0046] like Fig. 9The equivalent circuit diagram of the trench IGBT device of the present embodiment is shown, the dotted box is a parasitic NPN transistor, and the transistor in the lower right corner represents the PNP transistor at the collector. The trench IGBT device of the present embodiment introduces the latch region 133, so that most of the holes flow from the latch region 133 into the emitter E (i.e., the emitter metal region 134), and only a small part of the holes pass directly under the N+ active region 131, thereby greatly reducing the Rs resistance, thereby greatly reducing the conduction risk of the parasitic NPN transistor, and improving the anti-latch capability. Fig. 9 Here G represents the gate of the device, and C represents the collector of the transistor.

[0047] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: In an embodiment of the present invention, a short-circuit region is introduced in the emitter region so that the short-circuit region forms a ballast resistor, and the short-circuit resistance of the IGBT device is improved by the short-circuit region. Moreover, when the short-circuit temperature of the IGBT device increases, the resistance value of the short-circuit region becomes larger, which can greatly reduce the saturation current and improve the short-circuit resistance of the device. At the same time, a latch region is introduced in the emitter region so that when the IGBT device is turned on, most holes will reach the emitter of the IGBT device from the latch region, thereby reducing the hole concentration below the N+ active region, making it difficult for the parasitic triode to turn on, and improving the anti-latch capability of the IGBT device. In this way, by setting the emitter region on the P-base region between the gate regions, not only the structure of the IGBT device is improved, but also the short-circuit resistance of the IGBT device is improved, and the anti-latch capability of the device is enhanced. Under the premise of the same short-circuit resistance of the IGBT device, compared with the usual IGBT device, the IGBT device of this embodiment does not affect the forward conduction voltage drop and does not increase the conduction loss. The purpose of reducing costs and increasing efficiency is achieved through the structure of the IGBT device in the embodiment of the present invention.

[0048] Embodiment 2 Based on the same inventive concept, the second embodiment of the present invention further provides a method for manufacturing a trench IGBT device, which is used to manufacture the trench IGBT device as described in the first embodiment. Fig.10 As shown, the method includes: S201, forming a gate region on a substrate; S202, forming a P-base region and an emitter region between the gate regions, wherein the P-base region is located between the gate regions, and the P-base region is in contact with the gate regions; The emitter region includes: an N+ active region, a short circuit region, a latch region and an emitter metal region; The N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region; The short-circuit regions are spaced apart on the P-base region, located between the gate regions, and located on the latch region and in contact with the latch region; The latch region is located in the P-base region, between the gate regions, and below the spacing region corresponding to the spacing region between the short-circuit regions; The emitter metal region is filled in the spacer area and covers the N+ active area, the short circuit area and the gate area.

[0049] Since the manufacturing method of the trench IGBT device introduced in this embodiment is the manufacturing method adopted by the trench IGBT device in the first embodiment of the present application, based on the trench IGBT device introduced in the first embodiment of the present application, the technical personnel in the field can understand the specific implementation method and various variations of the manufacturing method of the trench IGBT device in this embodiment, so how the manufacturing method of the trench IGBT device implements the trench IGBT device in the first embodiment of the present application is not described in detail here. As long as the technical personnel in the field implement the manufacturing method adopted by the trench IGBT device in the first embodiment of the present application, it belongs to the scope of protection of this application.

[0050] Those skilled in the art will appreciate that, although the preferred embodiments of the present invention have been described, those skilled in the art, once informed of the basic creative concept, may make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0051] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A trench IGBT device, characterized in that: include: A substrate, and a P-base region, a gate region, and an emitter region located on the substrate; The P-base region is located between the gate regions, and the P-base region is in contact with the gate region; The emitter region includes: an N+ active region, a short circuit region, a latch region and an emitter metal region; The N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region; The short-circuit regions are spaced apart on the P-base region, located between the gate regions, and located on the latch region and in contact with the latch region; The latch region is located in the P-base region, between the gate regions, and below the spacing region corresponding to the spacing region between the short-circuit regions; The emitter metal region is filled in the spacer area and covers the N+ active area, the short circuit area and the gate area.

2. The device according to claim 1, characterized in that The short-circuit area includes: a short-circuit groove and short-circuit polysilicon; the short-circuit polysilicon is filled in the short-circuit groove, so that the short-circuit area forms a ballast resistor to improve the short-circuit resistance of the IGBT device.

3. The device according to claim 2, characterized in that The latching region includes a latching groove and latching polysilicon. The latching polysilicon is filled in the latching groove so that the latching region serves as a polysilicon electrode to improve the anti-latch capability of the IGBT device.

4. The device according to claim 2, characterized in that The junction depth of the N+ active region is not less than the depth of the short-circuit trench.

5. The device according to claim 3, characterized in that The depth of the short-circuit groove is smaller than the depth of the latch groove, and the width of the short-circuit groove is larger than the depth of the latch groove.

6. The device according to claim 5, characterized in that The depth of the short-circuit groove ranges from 0.1 to 0.3 um, and the width of the short-circuit groove ranges from 0.4 to 2 um; the depth of the latch groove ranges from 0.2 to 1 um, and the width of the latch groove ranges from 0.2 to 1.8 um.

7. The device according to claim 1, characterized in that The gate region includes: a gate trench, a gate oxide layer and a gate polysilicon; The gate oxide layer is located on the inner wall of the gate trench; The gate polysilicon fills the space formed by the gate oxide layer.

8. The device according to claim 1, characterized in that Also includes: dielectric layer; The dielectric layer is located above the gate region, the N+ active region and the short-circuit region and below the emitter metal region, and the through-holes of the dielectric layer correspond to the spacing regions so that the emitter metal region is filled in the through-holes.

9. The device according to claim 1, characterized in that Also includes: N-type field stop region, P-type collector region and collector metal region; The N-type field termination region is located below the substrate; The P-type collector region is located below the N-type field stop region; The collector metal region is located below the P-type collector region.

10. A method for manufacturing a trench IGBT device, characterized in that: For manufacturing a trench IGBT device according to any one of claims 1 to 9, the method comprises: forming a gate region on the substrate; forming a P-base region and an emitter region between the gate regions, wherein the P-base region is located between the gate regions and the P-base region is in contact with the gate regions; The emitter region includes: an N+ active region, a short circuit region, a latch region and an emitter metal region; The N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region; The short-circuit regions are spaced apart on the P-base region, located between the gate regions, and located on the latch region and in contact with the latch region; The latch region is located in the P-base region, between the gate regions, and below the spacing region corresponding to the spacing region between the short-circuit regions; The emitter metal region is filled in the spacer area and covers the N+ active area, the short circuit area and the gate area.

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