Channel voltage drop avoiding method, device and equipment in chip back-end design and medium
By identifying and processing low-intensity channels in the layout planning stage of the chip backend design, and using the power network creation and partition constraint density process, the channel voltage drop problem is solved and the normal function and speed of the chip are achieved.
Patent Information
- Application Number
- CN202510207987.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-06-10
AI Technical Summary
In the chip backend design, the voltage drop problem in the channel is more serious, especially in channels where high-power standard units are required, resulting in chip functional failure and reduced speed.
The chip circuit diagram is automatically processed by identifying low-intensity channels during the layout planning phase of the chip circuit diagram, and using the power network creation process and the partition constraint density process. Specific methods include creating a cryptographic power network for low-intensity channels and dividing them into multiple grids, distributing standard cell density between 10% and 30%.
It effectively reduces the voltage drop in the channel, avoids timing degradation and increased workload problems, and ensures the normal function and speed of the chip.
Smart Images
Figure CN120124568A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip design, and in particular relates to a method, device, equipment and medium for avoiding channel voltage drop in chip back-end design. Background Art
[0002] Voltage drop (IR drop) refers to a phenomenon in which the voltage on the power supply and ground network in an integrated circuit drops or rises. With the evolution of semiconductor technology, the width of metal interconnects is getting narrower, resulting in an increase in its resistance value, so there will be a certain IR drop in the entire chip. The size of the IR drop (the magnitude of the voltage drop or increase) is determined by the size of the equivalent resistance from the power pad PAD to the logic gate unit to be calculated.
[0003] The current of each logic gate unit in the SoC design will cause different degrees of IR drop to other logic gate units in the design. If the logic gate units connected to the metal lines flip at the same time, the IR drop caused by this will be very large. However, it is very important for some parts of the design to flip at the same time, such as the clock network and the registers it drives. In a synchronous design, they must flip at the same time. Therefore, a certain degree of IR drop is inevitable.
[0004] IR drop problems often manifest themselves as timing or even signal integrity issues. If the global IR drop of a chip is too high, the logic gates will have functional failures, causing the chip to fail completely, even though logic simulation shows that the design is correct. Local IR drop is more sensitive and can only occur under certain conditions, such as when all bus data is flipped synchronously, so the chip will intermittently exhibit some functional failures. The more common effect of IR drop is that it reduces the speed of the chip. Experiments have shown that a 5% IR drop on a logic gate unit will reduce the normal gate speed by 15%.
[0005] In digital back-end design, the strength of the power network will determine the IR drop of the entire design. However, in the channels between memories, the strength of the power network is often insufficient, which will lead to a large IR drop in the channel. In addition, for some special designs, it is necessary to place more high-power standard units in the channel, which will cause the IR drop in the channel to be more serious.
[0006] In the existing technology, the IR drop in the channel is reduced mainly through the following methods:
[0007] 1. Use the partial_blockage command of the ICC2 tool to limit the placement of only buffer drivers in the channel (buffer drivers are a type of standard unit). This method is not applicable to some designs that require a large number of timing logic units to be placed in the channel, because if only buffer drivers are allowed to be placed in the channel, these important logic units will be moved to the core area, which will lengthen the timing path and cause timing violations.
[0008] 2. Use the partial_blockage command of the ICC2 tool to constrain the density of standard cells in the channel. Assuming that the density of standard cells in the channel is limited to 80% through the partial_blockage command, the density of the upper half of the channel may be 100% and the density of the lower half may be 60%. The overall density still meets 80%, but the upper half will still cause IR drop problems due to too dense standard cells.
[0009] 3. When the IR drop problem is found in the channel in the later stage of chip back-end design, the power network is manually encrypted in the channel. This method not only wastes time, but may also affect other windings and cause timing degradation.
[0010] 4. When the IR drop problem is found in the channel in the later stage of chip back-end design, the placement of standard cells is manually dispersed. This method requires constant analysis of the impact on timing, and if a path with tight timing is involved, it will cause timing degradation and increase the workload. Summary of the invention
[0011] Based on this, in order to solve the above technical problems, a method, device, equipment and medium for avoiding channel voltage drop in chip back-end design are provided.
[0012] The technical solution adopted by the present invention is as follows:
[0013] As a first aspect of the present invention, a method for avoiding channel voltage drop in chip back-end design is provided, characterized in that the method is used in the layout planning stage of chip back-end design, and comprises:
[0014] Identify low-intensity channels in the chip circuit diagram, where the low-intensity channels are channels that cannot meet the requirement of having two sets of power bands every 5 um in their width direction;
[0015] Automatically processing the chip circuit diagram using at least one of a power network creation process and a partition constraint density process;
[0016] The power network encryption process includes: creating an encrypted power network for low-intensity channels;
[0017] The partition constraint density process includes: dividing the low-intensity channel into a plurality of grids, distributing a plurality of standard cells belonging to the low-intensity channel into the plurality of grids, and the density of the standard cells in each grid meets 10%-30%.
[0018] As a second aspect of the present invention, a device for avoiding channel voltage drop in chip back-end design is provided, characterized in that the device is used in the layout planning stage of chip back-end design, and comprises:
[0019] The first module is used to identify low-intensity channels in the chip circuit diagram, where the low-intensity channels refer to channels that cannot meet the requirement of having two sets of power bands every 5um in the width direction;
[0020] A second module is used to automatically process the chip circuit diagram by using at least one of a power network creation process and a partition constraint density process;
[0021] The power network encryption process includes: creating an encrypted power network for low-intensity channels;
[0022] The partition constraint density process includes: dividing the low-intensity channel into a plurality of grids, distributing a plurality of standard cells belonging to the low-intensity channel into the plurality of grids, and the density of the standard cells in each grid meets 10%-30%.
[0023] As a third aspect of the present invention, there is provided an electronic device, characterized in that it comprises a storage module, wherein the storage module comprises instructions loaded and executed by a processor, wherein when the instructions are executed, the processor executes a channel voltage drop avoidance method in a chip back-end design according to the first aspect.
[0024] As a fourth aspect of the present invention, a computer-readable storage medium is provided, which stores one or more programs, and is characterized in that when the one or more programs are executed by a processor, a channel voltage drop avoidance method in a chip back-end design of the first aspect is implemented.
[0025] The present invention first identifies the low-intensity channel in the chip circuit diagram, and then uses at least one of the power network creation process and the partition constraint density process to automatically process the chip circuit diagram, effectively reducing the voltage drop. For the power network creation process, since it is carried out in the layout planning stage of the chip back-end design, it is not like the prior art that the power network is manually encrypted in the later stage of the chip back-end design, and the problem of timing degradation will not occur. For the partition constraint density process, it first divides the low-intensity channel into multiple grids, and then distributes multiple standard cells belonging to the channel to multiple grids. The density of the standard cells in each grid meets 10%-30%, so that the distribution of the standard cells is more dispersed and uniform, avoiding the problem of voltage drop caused by local density after constraining the density of the standard cells in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:
[0027] Figure 1 A flow chart of a method for avoiding channel voltage drop in chip back-end design provided by an embodiment of the present invention;
[0028] Figure 2 A schematic diagram of a channel voltage drop avoidance device in a chip back-end design provided by an embodiment of the present invention;
[0029] Figure 3 A schematic diagram of an electronic device provided by an embodiment of the present invention;
[0030] Figure 4 Schematic diagram of an embodiment of the present invention. DETAILED DESCRIPTION
[0031] The following will illustrate the implementation methods of the present invention in conjunction with the drawings in the specification. It should be noted that the implementation methods involved in this specification are not exhaustive and do not represent the only implementation methods of the present invention. The following corresponding embodiments are only for the purpose of clearly illustrating the invention content of the patent of the present invention, and are not intended to limit its implementation methods. For ordinary technicians in this field, different forms of changes and modifications can be made on the basis of the description of this embodiment. All obvious changes or modifications that belong to the technical concept and invention content of the present invention are also within the scope of protection of the present invention.
[0032] The embodiment of the present application is based on the ICC2 tool (Innovus Compiler Compiler 2, an integrated circuit design implementation tool of Synopsys, used in the back-end design process of the chip), which is used in the layout planning stage (floorplan, floorplan is the initial stage of the back-end design of the chip) of the back-end design of the chip. Before implementation, it is necessary to import the front-end Verilog code into the ICC2 tool to generate the chip circuit diagram.
[0033] like Figure 1 As shown, the embodiment of the present application provides a method for avoiding channel voltage drop in chip back-end design, which can be automatically performed through a script, and includes:
[0034] S101, identifying low intensity channels in a chip circuit diagram.
[0035] Among them, the low-intensity channel refers to the channel that cannot meet the requirement of having two sets of power straps every 5um in its width direction. It can be seen that if the width of the channel is narrow, the strength of the power network on it will be insufficient. Therefore, the identify_channel command of the ICC2 tool can be used to locate the channel with a width less than the threshold as a low-intensity channel, where the threshold can be set to 11um.
[0036] Figure 4 A low intensity channel 31 is shown.
[0037] S102: Automatically process the chip circuit diagram using at least one of a power network creation process and a partition constraint density process.
[0038] In this embodiment, the chip circuit diagram is automatically processed through the power network creation process and the partition constraint density process respectively, so that the voltage drop can be minimized, wherein the power network creation process and the partition constraint density process are not in a particular order.
[0039] Specifically, the specific process of the power network creation process is as follows:
[0040] 201. Use the create_pg_regin command of the ICC2 tool to create each low-intensity channel as a power network region (pg region), and perform routing blocking (routing blockage) on each power network region;
[0041] 202. Use the Create_pg_strape command of the ICC2 tool to create a non-encrypted power network, that is, a normal power network, for the core area.
[0042] The core area refers to the area where standard units are concentrated.
[0043] 203. Use the Remove_routing_blockage-all command of the ICC2 tool to remove the routing blockage in the power network area, and use the Create_pg_strape command to create an encrypted power network for the power network area.
[0044] It should be pointed out that in the floorplan stage of the prior art, an ordinary power supply network is usually created for the channel and the core area. When the voltage drop problem is found later, the power supply network of the channel is encrypted. The present application directly creates an encrypted power supply network for the low-intensity channel in the floorplan stage. The purpose of creating it as a power supply network area is to allow the tool to directly identify each low-intensity channel later to avoid re-identification, and then create encrypted power supply networks for these channels separately. The purpose of routing blocking the power supply network area is to prevent the creation of a non-encrypted power supply network in the power supply network area when creating a non-encrypted power supply network for the core area. Therefore, it is also possible to first perform routing blocking on the core area, and then create an encrypted power supply network for the power supply network area. Finally, remove the routing blocking of the core area and create a non-encrypted power supply network on it.
[0045] The specific process of the partition constraint density process is as follows:
[0046] 301. Divide the low intensity channel into multiple grids:
[0047] The width and length directions of the low-intensity channel are defined as the x-direction and the y-direction, respectively. Figure 4 Taking the low-intensity channel 31 as an example, 1 / 4 of its width W is used as the side length of the square grid 31a, and the low-intensity channel 31 is divided into a plurality of square grids 31a along the y direction;
[0048] If there is a remaining area of the low-intensity channel 31 that has not been divided, the remaining area is equally divided into four rectangular grids 31b in the x direction;
[0049] The Create_placement command is used to distribute multiple standard cells belonging to the low-intensity channel 31 to multiple grids. The partial_blockage command of the ICC2 tool is used to constrain the density of the standard cells in each grid so that the density of the standard cells in each grid meets 10%-30%. In this embodiment, the density of the standard cells to be met is set to 20%.
[0050] Of course, the chip circuit diagram can be processed by only using any one of the power network creation process and the partition constraint density process to reduce the voltage drop to an acceptable level.
[0051] From the above, it can be seen that an embodiment of the present application provides a method for avoiding channel voltage drop in chip back-end design. After identifying the low-intensity channel in the chip circuit diagram, it uses at least one of the power network creation process and the partition constraint density process to automatically process the chip circuit diagram to effectively reduce the voltage drop. For the power network creation process, since it is carried out in the layout planning stage of the chip back-end design, it is not like the prior art that the power network is manually encrypted in the later stage of the chip back-end design, and the problem of timing degradation will not occur. For the partition constraint density process, it first divides the low-intensity channel into multiple grids, and then distributes multiple standard cells belonging to the channel to multiple grids. The density of the standard cells in each grid meets 10%-30%, so that the distribution of the standard cells is more dispersed and uniform, avoiding the problem of voltage drop caused by local density after constraining the standard cell density in the prior art, and there will be no timing violations and increased workload.
[0052] In addition, the voltage drop can be minimized by processing the chip circuit diagram through the power network creation process and the partition constraint density process respectively.
[0053] The following will describe in detail the channel voltage drop avoidance device in chip back-end design of one or more embodiments of the present invention. Those skilled in the art will understand that these devices can be configured using commercially available hardware components through the steps taught in this solution. Figure 2 FIG. 4 shows a device for avoiding channel voltage drop in a chip back-end design provided by an embodiment of the present invention. Figure 2 As shown, the device includes a first module 11 and a second module 12 .
[0054] The first module 11 is used to identify low-intensity channels in the chip circuit diagram.
[0055] Among them, the low-intensity channel refers to the channel that cannot meet the requirement of having two sets of power straps every 5um in its width direction. It can be seen that if the width of the channel is narrow, the strength of the power network on it will be insufficient. Therefore, the identify_channel command of the ICC2 tool can be used to locate the channel with a width less than the threshold as a low-intensity channel, where the threshold can be set to 11um.
[0056] Figure 4 A low intensity channel 31 is shown.
[0057] The second module 12 is used to automatically process the chip circuit diagram by using at least one of a power network creation process and a partition constraint density process.
[0058] In this embodiment, the chip circuit diagram is automatically processed through the power network creation process and the partition constraint density process respectively, so that the voltage drop can be minimized, wherein the power network creation process and the partition constraint density process are not in a particular order.
[0059] Specifically, the specific process of the power network creation process is as follows:
[0060] 201. Use the create_pg_regin command of the ICC2 tool to create each low-intensity channel as a power network region (pg region), and perform routing blocking (routing blockage) on each power network region;
[0061] 202. Use the Create_pg_strape command of the ICC2 tool to create a non-encrypted power network, that is, a normal power network, for the core area.
[0062] The core area refers to the area where standard units are concentrated.
[0063] 203. Use the Remove_routing_blockage-all command of the ICC2 tool to remove the routing blockage in the power network area, and use the Create_pg_strape command to create an encrypted power network for the power network area.
[0064] It should be pointed out that in the floorplan stage of the prior art, an ordinary power supply network is usually created for the channel and the core area. When the voltage drop problem is found later, the power supply network of the channel is encrypted. The present application directly creates an encrypted power supply network for the low-intensity channel in the floorplan stage. The purpose of creating it as a power supply network area is to allow the tool to directly identify each low-intensity channel later to avoid re-identification, and then create encrypted power supply networks for these channels separately. The purpose of routing blocking the power supply network area is to prevent the creation of a non-encrypted power supply network in the power supply network area when creating a non-encrypted power supply network for the core area. Therefore, it is also possible to first perform routing blocking on the core area, and then create an encrypted power supply network for the power supply network area. Finally, remove the routing blocking of the core area and create a non-encrypted power supply network on it.
[0065] The specific process of the partition constraint density process is as follows:
[0066] 301. Divide the low intensity channel into multiple grids:
[0067] The width and length directions of the low-intensity channel are defined as the x-direction and the y-direction, respectively. Figure 4Taking the low-intensity channel 31 as an example, 1 / 4 of its width W is used as the side length of the square grid 31a, and the low-intensity channel 31 is divided into a plurality of square grids 31a along the y direction;
[0068] If there is a remaining area of the low-intensity channel 31 that has not been divided, the remaining area is equally divided into four rectangular grids 31b in the x direction;
[0069] The Create_placement command is used to distribute multiple standard cells belonging to the low-intensity channel 31 to multiple grids. The partial_blockage command of the ICC2 tool is used to constrain the density of the standard cells in each grid so that the density of the standard cells in each grid meets 10%-30%. In this embodiment, the density of the standard cells to be met is set to 20%.
[0070] Of course, the chip circuit diagram can be processed by only using any one of the power network creation process and the partition constraint density process to reduce the voltage drop to an acceptable level.
[0071] In summary, the device for avoiding channel voltage drop in chip back-end design provided in the above embodiments can execute the method for avoiding channel voltage drop in chip back-end design provided in the above embodiments.
[0072] The same as above concept, Figure 2 The structure of the channel voltage drop avoidance device in the chip back-end design shown can be implemented as an electronic device. Figure 3 A schematic block diagram of the structure of an electronic device provided by an embodiment of the present invention is shown.
[0073] Exemplarily, the electronic device includes a storage module 21 and a processor 22, the storage module 21 includes instructions loaded and executed by the processor 22, and when the instructions are executed, the processor 22 executes the steps of various exemplary embodiments of the present invention described in the section of the channel voltage drop avoidance method in the above-mentioned chip back-end design in this specification.
[0074] It should be understood that the processor 22 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
[0075] A computer-readable storage medium is also provided in an embodiment of the present invention, which stores one or more programs. When the one or more programs are executed by a processor, the steps of various exemplary embodiments of the present invention described in the above-mentioned channel voltage drop avoidance method in a chip back-end design are implemented.
[0076] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer-readable storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).
[0077] As is known to those of ordinary skill in the art, the term computer-readable storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.
[0078] Exemplarily, the computer-readable storage medium may be an internal storage unit of the electronic device of the aforementioned embodiment, such as a hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart memory card (SmartMediaCard, SMC), a secure digital (SecureDigital, SD) card, a flash memory card (FlashCard), etc. equipped on the electronic device.
[0079] The electronic device and computer-readable storage medium provided by the aforementioned embodiments, after identifying the low-intensity channel in the chip circuit diagram, automatically process the chip circuit diagram using at least one of the power network creation process and the partition constraint density process, thereby effectively reducing the voltage drop. For the power network creation process, since it is performed in the layout planning stage of the chip back-end design, instead of manually encrypting the power network in the later stage of the chip back-end design as in the prior art, the problem of timing degradation will not occur. For the partition constraint density process, the low-intensity channel is first divided into multiple grids, and then multiple standard cells belonging to the channel are distributed to multiple grids. The density of the standard cells in each grid meets 10%-30%, so that the distribution of the standard cells is more dispersed and uniform, avoiding the problem of voltage drop caused by local density after constraining the density of the standard cells in the prior art, and there will be no timing violations and increased workload.
[0080] In addition, the voltage drop can be minimized by processing the chip circuit diagram through the power network creation process and the partition constraint density process respectively.
[0081] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A method for avoiding channel voltage drop in chip back-end design, characterized in that: The method is used in the layout planning stage of chip back-end design, which includes: Identify low-intensity channels in the chip circuit diagram, where the low-intensity channels are channels that cannot meet the requirement of having two sets of power bands every 5 um in the width direction; Automatically processing the chip circuit diagram using at least one of a power network creation process and a partition constraint density process; The power network encryption process includes: creating an encrypted power network for low-intensity channels; The partition constraint density process includes: dividing the low-intensity channel into a plurality of grids, distributing a plurality of standard cells belonging to the low-intensity channel into the plurality of grids, and the density of the standard cells in each grid meets 10%-30%.
2. The method for avoiding channel voltage drop in chip back-end design according to claim 1, characterized in that: The identification chip circuit diagram of the low intensity channel further comprises: The identify_channel command of the ICC2 tool is used to locate the channel whose width is smaller than the threshold value as the low-intensity channel.
3. The method for avoiding channel voltage drop in chip back-end design according to claim 1, characterized in that: The chip circuit diagram is automatically processed using a power network creation process and a partition constraint density process.
4. The method for avoiding channel voltage drop in chip back-end design according to claim 3, characterized in that: The power network creation process and the partition constraint density process are not prioritized.
5. The method for avoiding channel voltage drop in chip back-end design according to claim 1, characterized in that: The step of creating an encrypted power network and a non-encrypted power network for the low-intensity channel and the core area, respectively, further includes: Use the ICC2 tool to create each low-intensity channel as a power network area, and perform routing blocking on each power network area; Create a non-encrypted power network for core areas; Remove routing blockages from each power network area and create an encrypted power network for each power network area.
6. The method for avoiding channel voltage drop in chip back-end design according to claim 1, characterized in that: The step of dividing the low intensity channel into a plurality of grids further comprises: Taking 1 / 4 of the width of the low-intensity channel as the side length of the square grid, dividing the low-intensity channel into a plurality of the square grids along the length direction; If there is a remaining area of the low-intensity channel that has not been divided, the remaining area is equally divided into four rectangular grids in the width direction of the low-intensity channel.
7. The method for avoiding channel voltage drop in chip back-end design according to claim 1, characterized in that: The standard cell density in each grid satisfies 10%-30%, further comprising: The partial_blockage command of the ICC2 tool was used to constrain the standard cell density in each grid to 10%-30%.
8. A device for avoiding channel voltage drop in chip back-end design, characterized in that: The device is used in the layout planning stage of chip back-end design, and includes: The first module is used to identify low-intensity channels in the chip circuit diagram, where the low-intensity channels refer to channels that cannot meet the requirement of having two sets of power bands every 5um in the width direction; A second module is used to automatically process the chip circuit diagram by using at least one of a power network creation process and a partition constraint density process; The power network encryption process includes: creating an encrypted power network for low-intensity channels; The partition constraint density process includes: dividing the low-intensity channel into a plurality of grids, distributing a plurality of standard cells belonging to the low-intensity channel into the plurality of grids, and the density of the standard cells in each grid meets 10%-30%.
9. An electronic device, characterized in that: It comprises a storage module, wherein the storage module comprises instructions loaded and executed by a processor, and when the instructions are executed, the processor executes a channel voltage drop avoidance method in a chip back-end design according to any one of claims 1 to 7.
10. A computer-readable storage medium storing one or more programs, characterized in that: When the one or more programs are executed by the processor, the method for avoiding channel voltage drop in chip back-end design as described in any one of claims 1 to 7 is implemented.