Chip module layout design generation method and device, computer equipment, storage medium and computer program product

Abstract

The invention relates to a chip module layout design generation method and device, computer equipment, a storage medium and a computer program product. The method comprises the steps of determining each target basic module corresponding to a target system in each preset basic module according to a function requirement of the target system for a chip module, and determining an additional chip corresponding to the target system; generating at least one alternative layout design for the target system; under the condition that all the alternative layout designs do not meet the design requirement of the target system for the chip module, a to-be-split basic module is determined, the to-be-split basic module is split into at least two target basic modules based on first importance information of the connection relation between all the chips in the to-be-split basic module, and the at least two target basic modules are arranged on the basis of the at least two target basic modules. The target layout design meets the design requirement of the target system for the chip module. By adopting the method, the design efficiency of the chip module adaptive to the target system can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip layout, and particularly to a method, device, computer device, storage medium, and computer program product for generating a chip module layout design. Background Art

[0002] When developing a chip module, it is often necessary to adapt the chip module to different platform systems. Due to differences in the size requirements, chip pin definitions, peripheral circuit schemes, etc. of different platform systems for the chip module, when adapting the chip module to different platform systems, it is often necessary to re-layout all the chips in the module, resulting in low design efficiency of the chip module. Summary of the Invention

[0003] Based on this, it is necessary to provide a method, device, computer device, storage medium, and computer program product for generating a chip module layout design in view of the above technical problems.

[0004] In a first aspect, the present application provides a method for generating a chip module layout design. The method includes:

[0005] According to the functional requirements of the target system for the chip module, determine each target basic module corresponding to the target system in each preset basic module, and determine the additional chips corresponding to the target system; the preset basic module consists of at least one chip;

[0006] Based on each of the target basic modules and each of the additional chips, generate at least one alternative layout design for the target system;

[0007] In the case where none of the alternative layout designs meet the design requirements of the target system for the chip module, determine a basic module to be split from each of the target basic modules, and based on the first importance information of the connection relationships between the chips in the basic module to be split, split the basic module to be split into at least two target basic modules, and jump to the step of generating at least one alternative layout design for the target system based on each of the target basic modules and each of the additional chips, until there is a target layout design that meets the design requirements of the target system for the chip module;

[0008] Take the target layout design as the chip module layout design corresponding to the target system.

[0009] In one embodiment, the design requirements of the target system for the chip module include at least one of size requirements, heat dissipation requirements, and signal integrity requirements.

[0010] In one embodiment, the method further includes:

[0011] For any chip in any of the preset basic modules, determine the chip importance information corresponding to the chip according to at least one of the number of connection relationships corresponding to the chip, the power consumption corresponding to the chip, and the function information of the chip;

[0012] For the connection relationship between any two chips in any of the preset basic modules, determine the first importance information corresponding to the connection relationship according to the chip importance information corresponding to the two chips and the transmission signal type corresponding to the connection relationship.

[0013] In one embodiment, splitting the to-be-split basic module into at least two target basic modules based on the first importance information of the connection relationships between the chips in the to-be-split basic module includes:

[0014] Determine a plurality of splitting strategies for the to-be-split basic module, and respectively determine the to-be-split connection relationships corresponding to each splitting strategy;

[0015] For any of the splitting strategies, determine the strategy score corresponding to the splitting strategy according to the first importance information corresponding to the to-be-split connection relationships in the splitting strategy;

[0016] According to the strategy scores corresponding to each splitting strategy, determine a target splitting strategy from each splitting strategy, and split the to-be-split basic module into at least two target basic modules according to the target splitting strategy.

[0017] In one embodiment, determining the to-be-split basic module from each of the target basic modules includes:

[0018] Based on the number of chips included in each of the target basic modules and / or the signal integrity requirements corresponding to each of the target basic modules, respectively determine the second importance information of each of the target basic modules;

[0019] Based on the second importance information of each of the target basic modules, determine the to-be-split basic module from each of the target basic modules.

[0020] In one embodiment, each preset basic module corresponds to a preset layout design. Generating at least one alternative layout design for the target system based on each of the target basic modules and each of the additional chips includes:

[0021] According to the second importance information of each of the target basic modules, classify each of the target basic modules into a first basic module and a second basic module;

[0022] Perform layout on each of the first basic modules based on the preset layout design to obtain a basic layout design;

[0023] Generate at least one alternative layout design for the target system based on the basic layout design, each of the second basic modules, and the additional chip.

[0024] In a second aspect, the present application also provides a device for generating a chip module layout design. The device includes:

[0025] A first determination module, configured to determine, according to the functional requirements of the target system for the chip module, each target basic module corresponding to the target system in each preset basic module, and determine the additional chip corresponding to the target system; the preset basic module consists of at least one chip;

[0026] A generation module, configured to generate at least one alternative layout design for the target system based on each of the target basic modules and each of the additional chips;

[0027] A second determination module, in the case where none of the alternative layout designs meet the design requirements of the target system for the chip module, determine a basic module to be split from each of the target basic modules, and based on the first importance information of the connection relationships between the chips in the basic module to be split, split the basic module to be split into at least two target basic modules, and jump to the step of generating at least one alternative layout design for the target system based on each of the target basic modules and each of the additional chips, until there is a target layout design that meets the design requirements of the target system for the chip module;

[0028] A processing module, configured to use the target layout design as the chip module layout design corresponding to the target system.

[0029] In one embodiment, the design requirements of the target system for the chip module include at least one of size requirements, heat dissipation requirements, and signal integrity requirements.

[0030] In one embodiment, the device further includes:

[0031] A third determination module, configured to determine, for any chip in any of the preset basic modules, the chip importance information corresponding to the chip according to at least one of the number of connection relationships corresponding to the chip, the power consumption corresponding to the chip, and the function information of the chip;

[0032] A fourth determination module, configured to determine, for the connection relationship between any two chips in any of the preset basic modules, the first importance information corresponding to the connection relationship according to the chip importance information corresponding to the two chips and the type of transmission signal corresponding to the connection relationship.

[0033] In one embodiment, the second determination module is further configured to:

[0034] Determine a plurality of splitting strategies for the basic module to be split, and respectively determine the connection relationships to be split corresponding to each of the splitting strategies;

[0035] For any one of the splitting strategies, determine the strategy score corresponding to the splitting strategy according to the first importance information corresponding to each of the connection relationships to be split in the splitting strategy;

[0036] According to the strategy scores corresponding to each of the splitting strategies, determine a target splitting strategy from each of the splitting strategies, and split the basic module to be split into at least two target basic modules according to the target splitting strategy.

[0037] In one embodiment, the second determination module is further configured to:

[0038] Based on the number of chips included in each of the target basic modules and / or the signal integrity requirements corresponding to each of the target basic modules, respectively determine the second importance information of each of the target basic modules;

[0039] Based on the second importance information of each of the target basic modules, determine the basic module to be split from each of the target basic modules.

[0040] In one embodiment, each preset basic module corresponds to a preset layout design, and the generation module is further configured to:

[0041] Classify each of the target basic modules into a first basic module and a second basic module according to the second importance information of each of the target basic modules;

[0042] Perform layout on each of the first basic modules based on the preset layout design to obtain a basic layout design;

[0043] Generate at least one alternative layout design for the target system based on the basic layout design, each of the second basic modules, and the additional chips.

[0044] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the above-mentioned method is implemented.

[0045] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned method is implemented.

[0046] Fifth aspect, the present application also provides a computer program product. The computer program product includes a computer program which, when executed by a processor, implements any one of the above methods.

[0047] In the above method, device, computer device, storage medium, and computer program product for generating a chip module layout design, the chips in the chip module are integrated into preset basic modules. When it is necessary to adapt the chip module to a target system, first determine the target basic modules required by the target system in each preset basic module, and the additional chips required by the target system outside each target basic module, and perform layout on the target basic modules and the additional chips to obtain an alternative layout design. If each alternative layout design does not meet the design requirements of the chip module, split one or more target basic modules, and re-perform layout design on each module and the additional chips obtained after splitting until a target layout design that meets the design requirements of the target system for the chip module is obtained. In the embodiments of the present application, the chips are pre-integrated into preset basic modules with set layouts. When adapting the chip module to a target system, perform layout on each target basic module and each additional chip according to the functional requirements of the target system, and no longer need to consider the layout of the chips inside the target basic module. Therefore, the design efficiency of the chip module can be improved. Description of the Drawings

[0048] Figure 1 It is a flowchart of the method for generating a chip module layout design in an embodiment;

[0049] Figure 2 It is a flowchart of the process for determining the basic module to be split in an embodiment;

[0050] Figure 3 It is a flowchart of the process for determining the first importance information in an embodiment;

[0051] Figure 4 It is a flowchart of the process for splitting the basic module to be split in an embodiment;

[0052] Figure 5 It is a flowchart of step 104 in an embodiment;

[0053] Figure 6 It is a structural block diagram of the device for generating a chip module layout design in an embodiment;

[0054] Figure 7 It is an internal structure diagram of a computer device in an embodiment. Detailed Embodiments

[0055] In order to make the objectives, technical solutions, and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0056] In one embodiment, as Figure 1 shown, a method for generating a chip module layout design is provided. In this embodiment, an example is given where this method is applied to a server. It can be understood that this method can also be applied to a terminal, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0057] Step 102, according to the functional requirements of the target system for the chip module, determine the respective target basic modules corresponding to the target system in each preset basic module, and determine the additional chips corresponding to the target system; the preset basic module is composed of at least one chip.

[0058] In the embodiments of the present application, the target system is the system that the chip module needs to adapt to. For example, when the chip module is a vehicle-mounted cellular communication module, the target system can be a certain in-vehicle system.

[0059] The preset basic module is obtained by integrating some of the chips in the chip module. For example, when the chip module is a cellular communication module, the chips related to communication in the cellular communication module can be integrated into a radio frequency module, and the chips related to storage can be integrated into a storage module. Specifically, which chips are to form a preset basic module can be set by those skilled in the art according to actual needs, and the embodiments of the present application do not make specific limitations in this regard.

[0060] After integrating the chips into the preset basic module, one or more optimal layout methods can be determined in advance for the chips in the preset basic module. When subsequently laying out each target basic module and additional chips, these pre-set layout methods can be applied. Further, a unified external interface can also be set for the preset basic module. When it is necessary to make the chip module adapt to the target system, the pin definition of the external interface can be set according to the peripheral circuit to which the preset basic module needs to be connected.

[0061] The preset basic modules required to implement the functional requirements can be determined according to the functional requirements of the target system for the chip module, and these preset basic modules are used as the target basic modules. For example, when the preset basic modules include a radio frequency module and a positioning module, and the target system only requires a communication function and does not require a positioning function, the radio frequency module can be used as the target basic module corresponding to the target system.

[0062] An additional chip refers to a chip that may need to be added to the chip module in order to meet the functional requirements, in addition to the chips included in each preset basic module of the target system. For example, since different target systems usually use different SoC chips (System on Chip), it is generally impossible to design and integrate the SoC chips in advance. Therefore, the additional chips may include the SoC chips corresponding to the target system. Those skilled in the art can also set other additional chips according to actual needs, and the embodiments of the present application do not make specific limitations in this regard.

[0063] Step 104: Generate at least one alternative layout design for the target system based on each target basic module and each additional chip.

[0064] In the embodiments of the present application, after determining each target basic module and each additional chip, any chip layout software can be used to layout each target basic module and each additional chip to generate at least one alternative layout design available for the target system.

[0065] When performing the layout, the layout method of each chip within the target basic module may not be adjusted, or each chip may only be slightly displaced on the basis of maintaining the integrity of the signal path between the chips, and the layout methods between each target basic module and between the target basic module and the additional chip are focused on designing, so as to improve the generation efficiency of the layout design.

[0066] Step 106: In the case where none of the alternative layout designs meet the design requirements of the target system for the chip module, determine the basic module to be split from each target basic module, and based on the first importance information of the connection relationship between the chips in the basic module to be split, split the basic module to be split into at least two target basic modules, and jump to the step of generating at least one alternative layout design for the target system based on each target basic module and each additional chip, until there is a target layout design that meets the design requirements of the target system for the chip module.

[0067] In the embodiments of the present application, the target system has certain design requirements for the chip module, such as: size requirements for the chip module (the size of the chip module should be less than a certain preset maximum size, etc.), heat dissipation requirements (the temperature of the chip module during operation should be less than a certain preset maximum temperature, and the temperature distribution during operation should be uniform, etc.), signal integrity requirements (the time delay and distortion during signal transmission in the chip module should be controlled within a preset range, etc.). Those skilled in the art can also set other design requirements according to actual needs.

[0068] If the chip layout software used supports inputting all the design requirements of the target system as constraint conditions into the chip layout software when generating a layout design, when the chip layout software can generate a layout design under the given constraint conditions, it can be determined that there is a target layout design that meets the design requirements. If the chip layout software cannot generate a layout design under the given constraint conditions, it can be determined that there is no target layout design that meets the design requirements. If some or all of the design requirements cannot be input into the chip layout software as constraint conditions, after the chip layout software generates each alternative layout design, a simulation software can be used for simulation and other methods to determine whether there is a target layout design.

[0069] If there is a target layout design that meets the design requirements among the alternative layout designs, the target layout design can be used as the chip module layout design corresponding to the target system. If there is no target layout design that meets the design requirements among the alternative layout designs, the target basic module can be split to try whether it is possible to obtain a target layout design that meets the design requirements by changing the layout of the chips in the target basic module.

[0070] One or more basic modules to be split can be selected from each target basic module according to a preset splitting strategy. The splitting strategy may include, but is not limited to, preferentially splitting target basic modules with lower importance (the importance can be determined according to the importance of the target basic module for realizing the functions of the chip module, the strictness of the requirements of each chip in the target basic module for signal delay and signal timing, the number of chips in the target basic module, etc.), preferentially splitting target basic modules with larger sizes, and so on.

[0071] In one embodiment, as Figure 2 shown, the following method is used to determine the basic module to be split from each target basic module:

[0072] Step 202, based on the number of chips included in each target basic module and / or the signal integrity requirements corresponding to each target basic module, respectively determine the second importance information of each target basic module;

[0073] Step 204, based on the second importance information of each target basic module, determine the basic module to be split from each target basic module.

[0074] In the embodiment of the present application, the second importance information of the target basic module can be determined according to the number of chips included in each target basic module and the signal integrity requirements corresponding to each target basic module, and then which target basic module to split can be specifically determined according to the second importance information.

[0075] The second importance information is used to characterize the magnitude of the impact on the chip module layout after splitting the target basic module. The more chips included in the target basic module, the more chips are affected when splitting the target basic module. Therefore, splitting the target basic module has a greater impact on the chip module layout. The higher the signal integrity requirement corresponding to the target basic module, the more layout content needs to be redesigned and verified after splitting the target basic module. At the same time, the more difficult it is to redesign the wiring method of each signal transmission path. Therefore, splitting the target basic module has a greater impact on the chip module layout. Those skilled in the art can also determine the second importance information according to other criteria, and the embodiments of the present application do not make specific limitations in this regard.

[0076] A second importance information threshold can be set, and when the second importance information does not meet the second importance information threshold (if the second importance information is an importance level, not meeting the threshold means that the importance level is lower than the threshold; if the second importance information is an importance score, not meeting the threshold means that the importance score is less than the threshold), the target basic module is used as the basic module to be split. Or, the target basic module with the lowest second importance information can also be selected as the basic module to be split. The embodiments of the present application do not make specific limitations in this regard.

[0077] The first importance information can be set in advance for the connection relationships between the chips in each preset basic module. The first importance information is used to characterize the impact of changing the wiring method corresponding to the connection relationship on the layout of the target basic module, and it can be any information such as an importance level, an importance score, etc. that can characterize the degree of importance. The higher the importance level of the connection relationship characterized by the first importance information, the more the splitting of the target basic module should avoid splitting along this connection relationship as much as possible, so as to avoid problems such as signal transmission between chips when the wiring method of some important connection relationships is changed, or in order to make up for the impact caused by the change of the wiring method, a large amount of layout content needs to be redesigned and verified, resulting in a decrease in the layout design efficiency.

[0078] The embodiments of the present application do not make specific limitations on how to set the first importance information. For example, since high-frequency signals have high requirements for transmission accuracy and timing strictness, the importance level of the connection relationship for transmitting high-frequency signals can be set relatively high; for another example, the impact is relatively small when the positions of some chips that do not involve the core function part of the target basic module are changed. Therefore, the importance level of the connection relationship between such chips and other chips can be set relatively low.

[0079] In one embodiment, as Figure 3 shown, the following method is used to set the first importance information for each connection relationship:

[0080] Step 302: For any chip in any preset basic module, determine the chip importance information corresponding to the chip according to at least one of the number of connection relationships corresponding to the chip, the power consumption corresponding to the chip, and the function information of the chip.

[0081] Step 304: For the connection relationship between any two chips in any preset basic module, determine the first importance information corresponding to the connection relationship according to the chip importance information corresponding to the two chips and the transmission signal type corresponding to the connection relationship.

[0082] In the embodiment of the present application, first, the chip importance information of each chip in the preset basic module is determined, and then, according to the chip importance information, the first importance information of the connection relationships between the chips is generated.

[0083] The chip importance information is used to characterize the magnitude of the impact on the layout of the target basic module after the chip is moved. The chip importance information can be an importance level, an importance score, etc. The higher the importance level or importance score, the greater the impact on the layout of the target basic module after the chip is moved.

[0084] The chip importance information can be determined according to at least one of the number of connection relationships of the chip, the power consumption corresponding to the chip, and the function information of the chip. When the number of connection relationships between a chip and other chips is larger, the more signal paths need to be redesigned and verified after the chip is moved. Therefore, moving this chip has a greater impact on the layout of the target basic module. When the chip power consumption is higher, the greater the possibility of redesigning the chip heat dissipation layout after the chip is moved. Therefore, moving this chip has a greater impact on the layout of the target basic module. Some chips need to be specially laid out due to specific functions. For example, the global navigation satellite system chip in the cellular communication module should maintain a certain distance from other chips to avoid other chips interfering with the global navigation satellite system chip and causing inaccurate positioning. Therefore, after moving these chips, more layout contents need to be redesigned and verified, resulting in a greater impact on the layout of the target basic module when moving these chips. Those skilled in the art can also determine the chip importance information according to other criteria, and the embodiments of the present application do not make specific limitations in this regard.

[0085] After determining the importance information of the chips, the first importance information of each connection relationship can be further determined. The higher the importance level or importance score represented by the importance information of the chips at both ends of the connection relationship, the higher the importance level or importance score represented by the first importance information of the connection relationship should be. Further, the first importance information can also be determined based on the type of transmission signal corresponding to the connection relationship. When the type of transmission signal requires higher transmission accuracy (for example, when the type of transmission signal is a high-frequency signal or a signal that is more susceptible to electromagnetic interference), the importance level or importance score represented by the first importance information should also be higher. An importance information and a corresponding weight can be set for the type of transmission signal, weights can be set for the importance information of the chips corresponding to both ends of the connection relationship respectively, and then the importance information of the chips and the importance information corresponding to the type of transmission signal are weighted to obtain the first importance information corresponding to the connection relationship.

[0086] After determining the basic module to be split and obtaining the first importance information of each connection relationship in the basic module to be split, the way to split the basic module to be split can be further determined based on the first importance information. For example, the basic module to be split can be split along the connection relationship with the lowest first importance information and so on.

[0087] In one embodiment, as Figure 4 shown, the basic module to be split can be split in the following way:

[0088] Step 402, determine multiple splitting strategies for the basic module to be split, and respectively determine the connection relationships to be split corresponding to each splitting strategy;

[0089] Step 404, for any splitting strategy, determine the strategy score corresponding to the splitting strategy according to the first importance information of the connection relationships to be split in the splitting strategy;

[0090] Step 406, according to the strategy scores corresponding to each splitting strategy, determine the target splitting strategy from each splitting strategy, and split the basic module to be split into at least two target basic modules according to the target splitting strategy.

[0091] In the embodiments of the present application, each splitting strategy represents a way to split the basic module to be split. For example, for the radio frequency module in the cellular communication module, splitting the chips related to radio frequency signal reception and the chips related to radio frequency signal transmission can be used as one splitting strategy, and splitting the chips that process radio frequency signals of different frequency bands can be used as another splitting strategy and so on. Specific splitting strategies can be set by those skilled in the art according to actual needs.

[0092] To improve the subsequent maintenance convenience of the chip module, the splitting strategy can be set as follows as much as possible: after splitting the basic module to be split based on the splitting strategy, each of the split modules has complete functionality. For example, when splitting the chips related to radio frequency signal reception and the chips related to radio frequency signal transmission as a splitting strategy, after splitting the radio frequency module according to this splitting strategy, the two resulting modules will respectively have the signal transmission function and the signal reception function. By setting the splitting strategy in this way, when maintaining the chip module subsequently, the effect of removing or upgrading certain functions can be achieved by removing certain modules or replacing certain modules. There is no need to open the module during maintenance, which improves the maintenance convenience.

[0093] The connection relationship to be split corresponding to each splitting strategy can be determined separately. The connection relationship to be split refers to the connection relationship between each target basic module obtained after splitting the basic module to be split according to the splitting strategy, that is, the connection relationship for which the wiring method needs to be redesigned after splitting the basic module to be split. Furthermore, the splitting strategy can be scored based on the first importance information of the connection relationship to be split to obtain a strategy score. It can be made such that the first importance information of each connection relationship to be split is negatively correlated with the strategy score. That is, when the first importance information indicates that the connection relationship to be split has a greater impact on the layout of the target basic module, the strategy score is lower. When the first importance information is an importance score, the strategy score can be obtained by taking the reciprocal of the sum or average of the first importance information of each connection relationship to be split. When the first importance information is an importance level, a strategy score can be assigned to each importance level (the higher the importance level, the lower the strategy score), and then the strategy scores of each first importance information are summed or averaged to obtain the strategy score of the splitting strategy.

[0094] Furthermore, the strategy score can also be calculated based on the number of target basic modules obtained after splitting according to the splitting strategy. It can be made such that the number of target basic modules obtained after splitting is negatively correlated with the strategy score, so that the splitting strategy that generates fewer target basic modules is more likely to become the target splitting strategy, reducing the layout complexity. A strategy score can be calculated based on the first importance information corresponding to each connection relationship to be split, and another strategy score can be calculated based on the number of target basic modules obtained after splitting. Then, the two strategy scores are weighted and summed according to a preset weight to obtain the strategy score of the splitting strategy.

[0095] The splitting strategy with the highest strategy score can be used as the target splitting strategy. Alternatively, a strategy score threshold can be set. When there is a splitting strategy with a strategy score exceeding the strategy score threshold, the splitting strategy with the highest strategy score is used as the target splitting strategy; or when there is no splitting strategy with a strategy score exceeding the strategy score threshold, the basic module to be split is re - determined. After determining the target splitting strategy, the basic module to be split can be split into at least two target basic modules according to the target splitting strategy.

[0096] After splitting the basic module to be split into at least two target basic modules, steps 104 to 106 are re - executed until a target layout design that meets the design requirements of the target system for the chip module is obtained. If the target layout design has not been obtained after the number of repetitions of steps 104 and 106 has reached a certain number, all target basic modules can be split into individual chips and chip - level layout can be performed. If the target layout design still cannot be obtained after performing the above steps, the above process can be aborted and the technician can be prompted to modify the design requirements of the target system for the chip module.

[0097] The method for generating a chip module layout design provided by the embodiments of the present application integrates the chips in the chip module into preset basic modules. When it is necessary to adapt the chip module to the target system, first, the target basic modules required by the target system in each preset basic module and the additional chips required by the target system outside each target basic module are determined, and a candidate layout design is obtained by arranging the target basic modules and the additional chips. If each candidate layout design does not meet the design requirements of the chip module, one or more target basic modules are split, and the split modules and the additional chips are re - arranged until a target layout design that meets the design requirements of the target system for the chip module is obtained. The embodiments of the present application pre - integrate the chips into preset basic modules with set layouts. When adapting the chip module to the target system, the target basic modules and the additional chips are arranged according to the functional requirements of the target system, and there is no need to consider the layout of the chips inside the target basic module, so the design efficiency of the chip module can be improved.

[0098] In one embodiment, as Figure 5 shown, each preset basic module corresponds to a preset layout design. In step 104, based on each target basic module and each additional chip, at least one candidate layout design for the target system is generated, including:

[0099] Step 502, classifying each target basic module into a first basic module and a second basic module according to the second importance information of each target basic module;

[0100] Step 504: Based on the preset layout design, perform layout on each first basic module to obtain a basic layout design;

[0101] Step 506: Based on the basic layout design, each second basic module, and the additional chip, generate at least one alternative layout design for the target system.

[0102] In the embodiments of the present application, one or more optimal preset layout designs can be generated in advance for each preset basic module. When generating at least one alternative layout design for the target system based on each target basic module and each additional chip, the preset layout design can be referred to for generating the alternative layout design to improve the quality of the alternative layout design.

[0103] Based on the second importance information of the target basic module, each target basic module can be classified into a first basic module and a second basic module. The first basic module can be a module with relatively higher second importance information, and the second basic module can be a module with relatively lower second importance information. For example, a second importance information threshold can be set. When the second importance information is higher than the second importance information threshold, the target basic module is classified into the first basic module. When the second importance information is lower than the second importance information threshold, the target basic module is classified into the second basic module.

[0104] Based on the preset layout design, a basic layout design for each first basic module can be generated first. For example, it can be made that the positions of each first basic module in the basic layout design are close to their positions in the preset layout design, and the routing methods between each first basic module in the basic layout design are close to their routing methods in the preset layout design, etc. Then, based on the basic layout design, the second basic module, and the additional chip, multiple alternative layout designs can be further generated, so that in the finally obtained alternative layout designs, the layouts of each relatively important first basic module can be close to their layouts in the optimal preset layout design, improving the quality of the alternative layout design.

[0105] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0106] Based on the same inventive concept, an embodiment of the present application further provides a generating device for a chip module layout design for implementing the generating method of the chip module layout design involved above. The solution provided by this device for solving problems is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the generating device for the chip module layout design provided below can refer to the limitations on the generating method of the chip module layout design in the above text, and will not be repeated here.

[0107] In one embodiment, as Figure 6 shown, a generating device 600 for a chip module layout design is provided, including: a first determination module 602, a generation module 604, a second determination module 606, and a processing module 608, where:

[0108] The first determination module 602 is configured to determine, according to the functional requirements of the target system for the chip module, each target basic module corresponding to the target system in each preset basic module, and determine the additional chips corresponding to the target system; the preset basic module is composed of at least one chip;

[0109] The generation module 604 is configured to generate at least one alternative layout design for the target system based on each of the target basic modules and each of the additional chips;

[0110] The second determination module 606, in the case that none of the alternative layout designs meet the design requirements of the target system for the chip module, determines a basic module to be split from each of the target basic modules, and based on the first importance information of the connection relationships between the chips in the basic module to be split, splits the basic module to be split into at least two target basic modules, and jumps to the step of generating at least one alternative layout design for the target system based on each of the target basic modules and each of the additional chips, until there is a target layout design that meets the design requirements of the target system for the chip module;

[0111] The processing module 608 is configured to use the target layout design as the chip module layout design corresponding to the target system.

[0112] The generating device for the chip module layout design provided by the embodiment of the present application integrates the chips in the chip module into preset basic modules. When it is necessary to adapt the chip module to the target system, first determine the target basic modules required by the target system in each preset basic module, and the additional chips required by the target system outside each target basic module, and perform layout on the target basic modules and the additional chips to obtain alternative layout designs. If each alternative layout design does not meet the design requirements of the chip module, split one or more target basic modules, and re-perform layout design on each module and the additional chips obtained after splitting until a target layout design that meets the design requirements of the target system for the chip module is obtained. The embodiment of the present application pre-integrates the chips into preset basic modules with set layouts. When adapting the chip module to the target system, perform layout on each target basic module and each additional chip according to the functional requirements of the target system, and no longer need to consider the layout of the chips inside the target basic module, so the design efficiency of the chip module can be improved.

[0113] In one embodiment, the design requirements of the target system for the chip module include at least one of size requirements, heat dissipation requirements, and signal integrity requirements.

[0114] In one embodiment, the device further includes:

[0115] A third determination module, configured to determine, for any chip in any of the preset basic modules, chip importance information corresponding to the chip according to at least one of the number of connection relationships corresponding to the chip, the power consumption corresponding to the chip, and the function information of the chip;

[0116] A fourth determination module, configured to determine, for the connection relationship between any two chips in any of the preset basic modules, first importance information corresponding to the connection relationship according to the chip importance information corresponding to the two chips and the transmission signal type corresponding to the connection relationship.

[0117] In one embodiment, the second determination module 606 is further configured to:

[0118] Determine a plurality of splitting strategies for the basic module to be split, and respectively determine the connection relationships to be split corresponding to each splitting strategy;

[0119] For any of the splitting strategies, determine a strategy score corresponding to the splitting strategy according to the first importance information corresponding to each connection relationship to be split in the splitting strategy;

[0120] Determine a target splitting strategy from each of the splitting strategies according to the strategy scores corresponding to the splitting strategies, and split the basic module to be split into at least two target basic modules according to the target splitting strategy.

[0121] In one embodiment, the second determination module 606 is further configured to:

[0122] Based on the number of chips included in each of the target basic modules and / or the signal integrity requirements corresponding to each of the target basic modules, respectively determine the second importance information of each of the target basic modules;

[0123] Based on the second importance information of each of the target basic modules, determine the basic module to be split from each of the target basic modules.

[0124] In one embodiment, each preset basic module corresponds to a preset layout design, and the generation module 604 is further configured to:

[0125] Classify each of the target basic modules into a first basic module and a second basic module according to the second importance information of each of the target basic modules;

[0126] Perform layout on each of the first basic modules based on the preset layout design to obtain a basic layout design;

[0127] Generate at least one alternative layout design for the target system based on the basic layout design, each of the second basic modules, and the additional chips.

[0128] Each module in the above device can be implemented in whole or in part by software, hardware, and their combination. Each of the above modules can be embedded in or independent of a processor in a computer device in the form of hardware, or stored in a memory in the computer device in the form of software, so as to facilitate the processor to call and execute the operations corresponding to each of the above modules.

[0129] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 7 shown. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a method for generating a layout design of a chip module.

[0130] Those skilled in the art can understand that Figure 7 The structure shown in Figure 7 is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0131] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0132] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0133] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0134] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data that have been authorized by the user or fully authorized by all parties.

[0135] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0136] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0137] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A method for generating a chip module layout design, characterized in that: The method comprises: According to the functional requirements of the target system for the chip module, determine the target basic modules corresponding to the target system in the preset basic modules, and determine the additional chips corresponding to the target system; the preset basic module is composed of at least one chip; Based on each of the target basic modules and each of the additional chips, generating at least one candidate layout design for the target system; In the case that none of the alternative layout designs meets the design requirements of the target system for the chip module, determining a basic module to be split from each of the target basic modules, splitting the basic module to be split into at least two target basic modules based on the first importance information of the connection relationship between the chips in the basic module to be split, and jumping to the step of generating at least one alternative layout design for the target system based on each of the target basic modules and each of the additional chips, until there is a target layout design that meets the design requirements of the target system for the chip module; The target layout design is used as a chip module layout design corresponding to the target system.

2. The method according to claim 1, characterized in that: The design requirements of the target system for the chip module include at least one of size requirements, heat dissipation requirements, and signal integrity requirements.

3. The method according to claim 1, characterized in that The method further comprises: For any chip in any of the preset basic modules, determining chip importance information corresponding to the chip according to at least one of the number of connection relationships corresponding to the chip, the power consumption corresponding to the chip, and the function information of the chip; For a connection relationship between any two chips in any of the preset basic modules, first importance information corresponding to the connection relationship is determined according to chip importance information corresponding to the two chips and a transmission signal type corresponding to the connection relationship.

4. The method according to claim 1 or 3, characterized in that: The step of splitting the basic module to be split into at least two target basic modules based on the first importance information of the connection relationship between the chips in the basic module to be split includes: Determine a plurality of splitting strategies for the basic module to be split, and respectively determine the connection relationship to be split corresponding to each of the splitting strategies; For any of the splitting strategies, determining a strategy score corresponding to the splitting strategy according to the first importance information corresponding to each of the to-be-split connection relationships in the splitting strategy; According to the strategy scores corresponding to the splitting strategies, a target splitting strategy is determined from the splitting strategies, and the basic module to be split is split into at least two target basic modules according to the target splitting strategy.

5. The method according to claim 1, characterized in that The step of determining the basic modules to be split from each of the target basic modules includes: Determine the second importance information of each target basic module based on the number of chips included in each target basic module and / or the signal integrity requirements corresponding to each target basic module; Based on the second importance information of each of the target basic modules, a basic module to be split is determined from each of the target basic modules.

6. The method according to claim 5, characterized in that Each preset basic module corresponds to a preset layout design, and generating at least one candidate layout design for the target system based on each of the target basic modules and each of the additional chips includes: Classifying each of the target basic modules into a first basic module and a second basic module according to the second importance information of each of the target basic modules; Laying out each of the first basic modules based on the preset layout design to obtain a basic layout design; At least one candidate layout design for the target system is generated based on the basic layout design, each of the second basic modules, and the additional chip.

7. A device for generating a chip module layout design, characterized in that: The device comprises: A first determination module is used to determine, according to the functional requirements of the target system for the chip module, the target basic modules corresponding to the target system in the preset basic modules, and determine the additional chip corresponding to the target system; the preset basic module is composed of at least one chip; A generating module, configured to generate at least one candidate layout design for the target system based on each of the target basic modules and each of the additional chips; a second determination module, in the case that none of the alternative layout designs satisfies the design requirements of the target system for the chip module, determining a basic module to be split from each of the target basic modules, splitting the basic module to be split into at least two target basic modules based on the first importance information of the connection relationship between the chips in the basic module to be split, and jumping to the step of generating at least one alternative layout design for the target system based on each of the target basic modules and each of the additional chips, until there is a target layout design that satisfies the design requirements of the target system for the chip module; The processing module is used to use the target layout design as the chip module layout design corresponding to the target system.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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