Packaging structure and memory

Abstract

The invention provides a packaging structure, the packaging structure comprises a packaging substrate, a ball grid array is distributed on the surface of the packaging substrate, and the ball grid array comprises a plurality of chip selection ball grids and a plurality of data ball grids; wherein any one of the ball selection grids and one of the data ball grids are located in the same column and are arranged at an interval of one row.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and particularly to a packaging structure and a memory. Background Art

[0002] Currently, with the development of the semiconductor field, the integration degree of the packaging structure has been continuously improved, the number of input and output ends of the circuit layout has increased accordingly, and the size of the packaging substrate has also increased to accommodate more ball grid arrays. When applying the packaging substrate to a PCB board, due to the large area occupied by the packaging substrate on the PCB board, it will cause difficulties in PCB board wiring. Summary of the Invention

[0003] The present disclosure provides a packaging structure and a memory.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a packaging structure, which includes a packaging substrate, and a ball grid array is distributed on the surface of the packaging substrate. The ball grid array includes a plurality of chip select ball grids and a plurality of data ball grids;

[0006] Wherein, for any one of the chip select ball grids, it is located in the same column as one of the data ball grids and arranged with a spacing of one row.

[0007] In some embodiments, the plurality of chip select ball grids are divided into a first group of chip select ball grids and a second group of chip select ball grids, and the first group of chip select ball grids and the second group of chip select ball grids are centrosymmetric about the center of the ball grid array;

[0008] The middle two rows of the ball grid array are referred to as the center rows, and the middle one column of the ball grid array is referred to as the center column;

[0009] The first group of chip select ball grids, the center rows, and the second group of chip select ball grids are arranged adjacent to each other along the second direction;

[0010] The first group of chip select ball grids, the center column, and the second group of chip select ball grids are arranged adjacent to each other along the first direction;

[0011] Wherein, the first direction refers to the row direction of the ball grid array, and the second direction refers to the column direction of the ball grid array.

[0012] In some embodiments, the first group of chip select ball grids includes two chip select ball grids arranged adjacent to each other along the diagonal, and the second group of chip select ball grids includes two chip select ball grids arranged adjacent to each other along the diagonal;

[0013] The other ball grids that are linearly adjacent to any one of the chip select ball grids are used to transmit ground signals or power supply signals.

[0014] In some embodiments, the ball grid array further includes a first group of clock ball grids and a second group of clock ball grids, and the first group of clock ball grids and the second group of clock ball grids are centrosymmetric about the center of the ball grid array;

[0015] One of the clock ball grids in the first group of clock ball grids is diagonally adjacent to one of the chip select ball grids in the first group of chip select ball grids, and one of the clock ball grids in the second group of clock ball grids is diagonally adjacent to one of the chip select ball grids in the second group of chip select ball grids.

[0016] In some embodiments, each group of clock ball grids includes 2 adjacent clock ball grids in the same row, and the rows where the first group of clock ball grids are located, the central row, and the rows where the second group of clock ball grids are located are arranged adjacent to each other along the second direction. One of the clock ball grids in each group of clock ball grids is located in the central column;

[0017] Other ball grids that are linearly adjacent to any one of the clock ball grids are used to transmit ground signals or power signals.

[0018] In some embodiments, a plurality of data ball grids are divided into a first group of data ball grids, a second group of data ball grids, a third group of data ball grids, and a fourth group of data ball grids; the first group of data ball grids, the second group of data ball grids, the third group of data ball grids, and the fourth group of data ball grids are centrosymmetric about the center of the ball grid array;

[0019] The first group of data ball grids, the central row, and the second group of data ball grids are arranged along the second direction;

[0020] The third group of data ball grids, the central row, and the fourth group of data ball grids are arranged along the second direction;

[0021] The first group of data ball grids, the central column, and the third group of data ball grids are arranged along the first direction;

[0022] The second group of data ball grids, the central column, and the fourth group of data ball grids are arranged along the first direction;

[0023] Wherein, each data ball grid is at least diagonally adjacent to another data ball grid, and other ball grids that are linearly adjacent to any one of the data ball grids are used to transmit ground signals and / or power signals.

[0024] In some embodiments, the ball grid array further includes a first group of command address ball grids and a second group of command address ball grids, and the first group of command address ball grids and the second group of command address ball grids are centrosymmetric about the center of the ball grid array;

[0025] The first group of data ball grids, the first group of command address ball grids, and the second group of data ball grids are arranged in sequence along the second direction. The third group of data ball grids, the second group of command address ball grids, and the fourth group of data ball grids are arranged in sequence along the second direction.

[0026] In some embodiments, in the first group of command address ball grids, one of the command address ball grids is located in the central row, and the remaining command address ball grids are symmetric about the central row; in the second group of command address ball grids, one of the command address ball grids is located in the central row, and the remaining command address ball grids are symmetric about the central row;

[0027] Wherein, each command address ball grid is at least diagonally adjacent to another command address ball grid, and the other ball grids linearly adjacent to any one of the command address ball grids are used to transmit ground signals and / or power supply signals.

[0028] In some embodiments, the ball grid array further includes: a first group of write clock ball grids, a second group of write clock ball grids, a third group of write clock ball grids, and a fourth group of write clock ball grids. The first group of write clock ball grids, the second group of write clock ball grids, the third group of write clock ball grids, and the fourth group of write clock ball grids are symmetric about the center of the ball grid array;

[0029] A first group of read data strobe ball grids, a second group of read data strobe ball grids, a third group of read data strobe ball grids, and a fourth group of read data strobe ball grids. The first group of read data strobe ball grids, the second group of read data strobe ball grids, the third group of read data strobe ball grids, and the fourth group of read data strobe ball grids are symmetric about the center of the ball grid array;

[0030] 4 mask flip control ball grids, located in the edge row of the ball grid array and symmetric about the center of the ball grid array; wherein,

[0031] For each group of the write clock ball grids, it includes 2 write clock ball grids arranged adjacent diagonally. The first write clock ball grid is also diagonally adjacent to 2 data ball grids and 1 read data strobe ball grid. The second write clock ball grid is also diagonally adjacent to 2 data ball grids, and the other ball grids linearly adjacent to any one of the write clock ball grids are used to transmit ground signals and / or power supply signals;

[0032] For each group of the read data strobe ball grids, it includes 2 read data strobe ball grids arranged adjacent diagonally. The first read data strobe ball grid is also diagonally adjacent to 2 data ball grids and 1 write clock ball grid. The second read data strobe ball grid is also diagonally adjacent to 1 data ball grid and 1 mask flip control ball grid, and the other ball grids linearly adjacent to any one of the read data strobe ball grids are used to transmit ground signals and / or power supply signals.

[0033] In some embodiments, the ball grid array further includes a plurality of multi-purpose ball grids, which are located in the edge rows and / or edge columns of the ball grid array. The plurality of multi-purpose ball grids include one or more of reserved ball grids, reset ball grids, disabled ball grids, or calibration control ball grids.

[0034] In some embodiments, the ball grid array has 18 rows and 13 columns; the number of ball grids for transmitting ground signals is 67, and the number of ball grids for transmitting power supply signals is 77;

[0035] The ball grids for transmitting power supply signals located in the central row are distributed on both sides of the central column, and the number thereof is 14. The ball grids for transmitting power supply signals located in the central column are distributed on both sides of the central row, and the number thereof is 10;

[0036] The number of ball grids for transmitting ground signals located in the central row is 10, and the number of ball grids for transmitting ground signals located in the central column but not in the central row is 4.

[0037] In some embodiments, in the first direction, the distance between any two adjacent ball grids in the ball grid array is 0.6 mm, and in the second direction, the distance between any two adjacent ball grids in the ball grid array is 0.65 mm;

[0038] Wherein, the first direction is the row direction of the ball grid array, and the second direction is the column direction of the ball grid array.

[0039] In some embodiments, the first part of the ball grid array coincides with the second part of the ball grid array after rotating 180 degrees; the first part of the ball grid array is located on one side of the central row, and the second part of the ball grid array is located on the other side of the central row.

[0040] In a second aspect, an embodiment of the present disclosure provides a memory, including the packaging structure as described in the first aspect.

[0041] An embodiment of the present disclosure provides a packaging structure and a memory. The packaging structure includes a packaging substrate, and the ball grid array distributed on the packaging substrate is arranged more closely. The packaging substrate has a smaller size, stronger product competitiveness, and wider application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of a packaging structure provided by an embodiment of the present disclosure;

[0043] Figure 2 It is a schematic diagram of a ball grid array provided by an embodiment of the present disclosure Figure 1 ;

[0044] Figure 3 Schematic of a ball grid array provided by an embodiment of the present disclosure Figure 2 ;

[0045] Figure 4 Schematic of a ball grid array provided by an embodiment of the present disclosure Figure 3 ;

[0046] Figure 5 Schematic of a ball grid array provided by an embodiment of the present disclosure Figure 4 ;

[0047] Figure 6 Schematic of a ball grid array provided by an embodiment of the present disclosure Figure 5 ;

[0048] Figure 7 Curves of signal integrity of 315B package substrate and 234B package substrate in different working scenarios;

[0049] Figure 8 Schematic structural diagram of a memory provided by an embodiment of the present disclosure Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. Additionally, it should be noted that for the sake of description, only parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be pointed out that the terms "first / second / third" related to the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than the illustrated or described order.

[0051] Static Random-Access Memory (SRAM);

[0052] Dynamic Random Access Memory (DRAM);

[0053] Synchronous Dynamic Random Access Memory (SDRAM);

[0054] Double Data Rate SDRAM (DDR);

[0055] Low Power DDR (LPDDR);

[0056] Fourth Generation LPDDR (4 th LPDDR, LP4);

[0057] Fifth Generation LPDDR (5 th LPDDR, LP5);

[0058] UFS-based Multichip Package (UMCP).

[0059] Before introducing the embodiments of the present disclosure, three directions for describing three-dimensional structures that may be used in the planes involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis directions (not involved in the embodiments of the present disclosure). The memory may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g., perpendicular) with the top surface and the bottom surface of the memory is defined as the third direction. In the direction of the top surface and the bottom surface of the memory (i.e., the plane where the memory is located), two intersecting directions are defined. For example, the row direction of the ball grid array may be defined as the first direction, and the column direction of the ball grid array may be defined as the second direction. Based on the first direction and the second direction, the plane direction of the memory can be determined. In the embodiments of the present disclosure, the first direction and the second direction may be perpendicular to each other pairwise. In other embodiments, the first direction and the second direction may not be perpendicular.

[0060] Additionally, as used herein in connection with a ball grid array, the term "linearly adjacent" means and includes the ball grids directly above, directly below, directly to the left, and directly to the right of a given ball grid when the ball grid array is parallel to the plane of the drawing; the term "diagonal adjacent arrangement" as used herein in connection with a ball grid array means and includes the ball grids in the upper right, lower right, upper left, and lower left of a given ball grid when the ball grid array is parallel to the plane of the drawing; the term "around a ball grid" as used herein in connection with a ball grid array means and includes the ball grids directly above, directly below, directly to the left, directly to the right, in the upper right, lower right, upper left, and lower left of a given ball grid when the ball grid array is parallel to the plane of the drawing. The term "ball grid A is adjacent to ball grid B along the first direction" as used herein in connection with a ball grid array only includes that ball grid A and ball grid B are adjacent when the ball grid array is parallel to the plane of the drawing, and ball grid A is directly above or directly below ball grid B. The term "ball grid A is adjacent to ball grid B along the second direction" as used herein in connection with a ball grid array only includes that ball grid A and ball grid B are adjacent when the ball grid array is parallel to the plane of the drawing, and ball grid A is directly to the left or directly to the right of ball grid B.

[0061] In particular, the diagrams presented in this disclosure are not meant to be actual views of any specific microelectronic device package, ball grid array, or its components, but are merely idealized representations for describing illustrative embodiments. Therefore, the diagrams are not necessarily to scale.

[0062] Currently, with the development of the semiconductor field, the integration level of packaging structures has been continuously improved, the number of input and output terminals of circuit layouts has increased accordingly, and the size of packaging substrates has also increased to accommodate more ball grids. When applying a packaging substrate to a PCB board, since the area occupied by the packaging substrate on the PCB board is relatively large, it will cause difficulties in PCB board routing.

[0063] Taking LP5 as an example for illustration, the size of the LP4 discrete packaging substrate is, for example, 10 mm × 15 mm, the size of the uMCP packaging substrate is, for example, 11.5 mm × 13 mm or 13 mm × 14 mm, and the size of the LP5 discrete packaging substrate is, for example, 12.4 mm × 15 mm. Compared with the LP4 discrete packaging substrate and the uMCP packaging substrate, the larger size limits the application of the LP5 discrete packaging substrate. For example, with the development of technology, compared with 4G mobile phones, the area occupied by antennas and the gaps between antennas on the PCB board of 5G mobile phones is larger. However, when the existing LP5 discrete packaging substrate with a large size is applied to the PCB board of 5G mobile phones, it further causes a serious shortage of the remaining area on the PCB board, resulting in difficulties in PCB board routing. Therefore, there is an urgent need to provide a packaging substrate with a smaller size.

[0064] Based on this, the embodiments of the present disclosure propose the following technical solutions.

[0065] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0066] In one embodiment of the present disclosure, refer to Figure 1 , which shows a schematic diagram of a packaging structure 10 provided by an embodiment of the present disclosure. As Figure 1 shown, the packaging structure 10 includes a packaging substrate 11, and a ball grid array 20 is distributed on the surface of the packaging substrate 11.

[0067] It should be noted that the packaging structure 10 provided by the embodiment of the present disclosure can be applied to at least LPDDR, such as LP5. The above does not constitute a limitation to the embodiment of the present disclosure. After adaptively adjusting DDR, SDRAM, and SRAM, the embodiment of the present disclosure can be adopted.

[0068] It should be noted that in Figure 1 , the distribution position of the ball grid array 20 on the packaging substrate 11 is only for illustration and does not constitute a limitation. In fact, the surface of the packaging substrate 11 is not necessarily a completely regular rectangle, and the ball grid array 20 can be distributed in any area on the surface of the packaging substrate 11.

[0069] In the following description, the first direction is the row direction of the ball grid array 20, and the second direction is the column direction of the ball grid array 20.

[0070] As Figure 1 shown, the ball grid array 20 includes a plurality of chip select ball grids ( Figure 1 only part of which is shown in Figure 1 , namely 201, 202) and a plurality of data ball grids (

[0071] only part of which is shown in

[0072] In some embodiments, such as Figure 2As shown, multiple chip select ball grids (201-204) are divided into a first group of chip select ball grids (201, 202) and a second group of chip select ball grids (203, 204). The first group of chip select ball grids (201, 202) and the second group of chip select ball grids (203, 204) are symmetric about the center AA of the ball grid array 20. The middle two rows of the ball grid array 20 are called the center rows, and the middle one column of the ball grid array 20 is called the center column. The first group of chip select ball grids (201, 202), the center rows, and the second group of chip select ball grids (203, 204) are arranged adjacent to each other along the second direction. The first group of chip select ball grids (201, 202), the center column, and the second group of chip select ball grids (203, 204) are arranged adjacent to each other along the first direction. In the embodiments of the present disclosure, the chip select ball grids (201-204) are all distributed on both sides of the center column rather than in the center column, which is convenient for reducing the number of columns of the center column when performing ball grid layout.

[0073] In some embodiments, the first group of chip select ball grids (201, 202) includes two chip select ball grids arranged adjacent to each other along the diagonal, and the second group of chip select ball grids (203, 204) includes two chip select ball grids arranged adjacent to each other along the diagonal.

[0074] In some embodiments, the ball grid array 20 has 18 rows (row numbers are sequentially A, B... V) and 13 columns (column numbers are sequentially 1, 2... 13). The rows numbered J and K are called the center rows, and the column numbered 7 is called the center column. In a specific embodiment, for the first group and the second group of chip select ball grids (201-204), the chip select ball grid 201 is located at (H, 5), the chip select ball grid 202 is located at (G, 6), the chip select ball grid 203 is located at (L, 9), and the chip select ball grid 204 is located at (M, 8). The chip select ball grid 201 and the chip select ball grid 203 are symmetric about the center AA of the ball grid array 20, and the chip select ball grid 202 and the chip select ball grid 204 are symmetric about the center AA of the ball grid array 20.

[0075] Exemplarily, referring to Figure 6 , the first group of chip select ball grids (201, 202) respectively transmit a pair of chip select signals CS0 and CS1. The second group of chip select ball grids (203, 204) respectively transmit another pair of chip select signals CS0 and CS1. In particular, at most only one of the pair of chip select signals CS0 and CS1 is valid.

[0076] In one embodiment, as Figure 2 or Figure 6 shown, the other ball grids linearly adjacent to any chip select ball grid are used to transmit the ground signal VSS or the power supply signal VDD. As Figure 2As shown, in a specific embodiment, for the first set of chip select ball grids (201, 202), the chip select ball grid 201 is linearly adjacent to 2 ball grids for transmitting the ground signal VSS and 2 ball grids for transmitting the power supply signal VDD; the chip select ball grid 202 is linearly adjacent to 3 ball grids for transmitting the ground signal VSS and 1 ball grid for transmitting the power supply signal VDD. For the second set of chip select ball grids (203, 204), the chip select ball grid 203 is linearly adjacent to 2 ball grids for transmitting the ground signal VSS and 2 ball grids for transmitting the power supply signal VDD; the chip select ball grid 204 is linearly adjacent to 3 ball grids for transmitting the ground signal VSS and 1 ball grid for transmitting the power supply signal VDD. The ball grids for transmitting the ground signal VSS that are linearly adjacent to the chip select ball grids (201-204) can improve the signal interference problem.

[0077] As Figure 3 shown, in some embodiments, the multiple data ball grids (401-432) are divided into a first set of data ball grids (401-408), a second set of data ball grids (409-416), a third set of data ball grids (417-424), and a fourth set of data ball grids (425-432); the first set of data ball grids (401-408), the second set of data ball grids (409-416), the third set of data ball grids (417-424), and the fourth set of data ball grids (425-432) are symmetric about the center AA of the ball grid array 20. In a specific embodiment, the first set of data ball grids (401-408) and the fourth set of data ball grids (425-432) are symmetric about the center AA of the ball grid array 20; the second set of data ball grids (409-416) and the third set of data ball grids (417-424) are symmetric about the center AA of the ball grid array 20; for the first set of data ball grids (401-408), it is mirror symmetric with the second set of data ball grids (409-416) about the center row and mirror symmetric with the third set of data ball grids (417-424) about the center column; for the fourth set of data ball grids (425-432), it is mirror symmetric with the second set of data ball grids (409-416) about the center column and mirror symmetric with the third set of data ball grids (417-424) about the center row, so that the vias can be shared when performing the front and back pasting design on the PCB.

[0078] In some embodiments, the first group of data ball grids (401-408), the center row, and the second group of data ball grids (409-416) are arranged along the second direction; the third group of data ball grids (417-424), the center row, and the fourth group of data ball grids (425-432) are arranged along the second direction; the first group of data ball grids (401-408), the center column, and the third group of data ball grids (417-424) are arranged along the first direction; the second group of data ball grids (409-416), the center column, and the fourth group of data ball grids (425-432) are arranged along the first direction. In a specific embodiment, the row where the first group of data ball grids (401-408) is located, the row where the first group of chip select ball grids (201, 202) is located, the center row, the row where the second group of chip select ball grids (203, 204) is located, and the row where the second group of data ball grids (409-416) is located are arranged adjacent to each other in sequence along the second direction; the row where the third group of data ball grids (417-424) is located, the row where the first group of chip select ball grids (201, 202) is located, the center row, the row where the second group of chip select ball grids (203, 204) is located, and the row where the fourth group of data ball grids (425-432) is located are arranged adjacent to each other in sequence along the second direction.

[0079] Exemplarily, referring to Figure 6 , the first group of data ball grids (401-408) is used to transmit data signals (DQ0-DQ7), the second group of data ball grids (409-416) is used to transmit data signals (DQ8-DQ15), the third group of data ball grids (417-424) is used to transmit data signals (DQ8-DQ15), and the fourth group of data ball grids (425-432) is used to transmit data signals (DQ0-DQ7).

[0080] In one embodiment, each data ball grid is at least diagonally adjacent to another data ball grid, and the other ball grids that are linearly adjacent to any data ball grid are used to transmit the ground signal VSS and / or the power supply signal VDD.

[0081] Particularly, there are multiple power supply signals VDD with different functions, types, and voltages in the same chip. Therefore, there are VDDs filled with different patterns in the drawings. However, the distribution rule of the VDDs filled with different patterns in the drawings is only an example and does not constitute a corresponding limitation.

[0082] Referring again to Figure 2, in a specific embodiment, data ball grid 405 is located at (F, 5), data ball grid 406 is located at (E, 6), data ball grid 431 is located at (P, 8), and data ball grid 432 is located at (N, 9); chip select ball grid 201 and data ball grid 405 are in the same column and arranged with a one-row interval; chip select ball grid 202 and data ball grid 406 are in the same column and arranged with a one-row interval; chip select ball grid 203 and data ball grid 432 are in the same column and arranged with a one-row interval; chip select ball grid 204 and data ball grid 431 are in the same column and arranged with a one-row interval.

[0083] In some embodiments, such as Figure 2 shown, the ball grid array 20 further includes a first group of clock ball grids (301, 302) and a second group of clock ball grids (303, 304). The first group of clock ball grids (301, 302) and the second group of clock ball grids (303, 304) are symmetric about the center AA of the ball grid array 20; one clock ball grid in the first group of clock ball grids (301, 302) is diagonally adjacent to one chip select ball grid in the first group of chip select ball grids (201, 202), and one clock ball grid in the second group of clock ball grids (303, 304) is diagonally adjacent to one chip select ball grid in the second group of chip select ball grids (203, 204). In this way, the first group of clock ball grids (301 - 302) and the first group of chip select ball grids (201, 202) are closer and arranged more closely, and the second group of clock ball grids (303, 304) and the second group of chip select ball grids (203, 204) are closer and arranged more closely, which can overall reduce the number of ball grids of the ball grid array 20, thereby reducing the substrate area.

[0084] In some embodiments, each group of clock ball grids includes 2 adjacent clock ball grids in the same row. The rows where the first group of clock ball grids (301, 302) are located, the central row, and the rows where the second group of clock ball grids (303, 304) are located are arranged adjacent to each other along the second direction, and one of the clock ball grids in each group of clock ball grids is located in the central column.

[0085] Here, the two clock ball grids in each group of clock ball grids are in the same row and adjacent to each other, which can overall reduce the number of rows of ball grids of the ball grid array 20 and reduce the substrate area occupied; at the same time, one of the clock ball grids in each group of clock ball grids is located in the central column, that is, one clock ball grid in the first group of clock ball grids (301, 302) and one clock ball grid in the second group of clock ball grids (303, 304) are in the same column. In this way, the number of columns of ball grids of the ball grid array 20 can be reduced, further reducing the substrate area occupied.

[0086] It should be noted that in a specific embodiment, for the first and second groups of clock ball grids (301 - 304), clock ball grid 301 is located at (H, 7), clock ball grid 302 is located at (H, 8), clock ball grid 303 is located at (L, 6), clock ball grid 304 is located at (L, 7). Clock ball grid 301 and chip select ball grid number 202 are arranged adjacent to each other along the diagonal. Clock ball grid 304 and chip select ball grid 204 are arranged adjacent to each other along the diagonal. Clock ball grid 301 and clock ball grid 304 are located in the central column.

[0087] It should also be noted that as Figure 6 shown, the first group of clock ball grids (301, 302) respectively transmit a pair of clock signals CK_T and CK_C; the second group of clock ball grids (303, 304) respectively transmit another pair of clock signals CK_C and CK_T. In particular, a pair of clock signals CK_T and CK_C are differential signals.

[0088] In an embodiment, as Figure 2 or Figure 6 shown, the other ball grids that are linearly adjacent to any clock ball grid are used to transmit the ground signal VSS or the power supply signal VDD. As Figure 2 shown, in a specific embodiment, for the first group of clock ball grids (301, 302), clock ball grid 301 is linearly adjacent to 3 ball grids for transmitting the ground signal VSS, and clock ball grid 302 is linearly adjacent to 2 ball grids for transmitting the power supply signal VDD and 1 ball grid for transmitting the ground signal VSS; for the second group of clock ball grids (303, 304), clock ball grid 304 is linearly adjacent to 3 ball grids for transmitting the ground signal VSS, and clock ball grid 303 is linearly adjacent to 2 ball grids for transmitting the power supply signal VDD and one ball grid for transmitting the ground signal VSS.

[0089] For clock ball grids 301 and 304, the three ball grids that are linearly adjacent to them are all used to transmit the ground signal VSS, which maximally reduces signal perturbation; for clock ball grids 302 and 303, although they are linearly adjacent to 2 ball grids for transmitting the power supply signal VDD, the ball grids for transmitting the ground signal VSS that are also linearly adjacent can improve the signal interference problem and at the same time save the area occupied by the clock ball grids as much as possible.

[0090] In some embodiments, as Figure 4As shown, the ball grid array 20 further includes a first group of command address ball grids (501 - 507) and a second group of command address ball grids (508 - 514). The first group of command address ball grids (501 - 507) and the second group of command address ball grids (508 - 514) are symmetric about the center AA of the ball grid array 20. The multiple command address ball grids (501 - 514) are used to transmit command address signals CA. The first group of data ball grids (401 - 408), the first group of command address ball grids (501 - 507), and the second group of data ball grids (409 - 416) are arranged in sequence along the second direction. The third group of data ball grids (417 - 424), the second group of command address ball grids (508 - 514), and the fourth group of data ball grids (425 - 432) are arranged in sequence along the second direction.

[0091] In some embodiments, among the first group of command address ball grids (501 - 507), one of the command address ball grids is located in the center row, and the remaining command address ball grids are symmetric about the center row. Among the second group of command address ball grids (508 - 514), one of the command address ball grids is located in the center row, and the remaining command address ball grids are symmetric about the center row. Wherein, each command address ball grid is at least diagonally adjacent to another command address ball grid, and the other ball grids that are linearly adjacent to any command address ball grid are used to transmit ground signal VSS and / or power supply signal VDD. In the embodiments of the present disclosure, each command address ball grid is at least diagonally adjacent to another command address ball grid. Thus, the multiple command address ball grids (501 - 514) are arranged more densely in the ball grid array 20, and the number of ball grids of the ball grid array 20 can be reduced as a whole.

[0092] It should be noted that in a specific embodiment, for the first group of command address ball grids (501 - 507), the command address ball grid 501 is located at (G, 2), the command address ball grid 502 is located at (G, 4), the command address ball grid 503 is located at (H, 3), the command address ball grid 504 is located at (K, 4), the command address ball grid 505 is located at (M, 2), the command address ball grid 506 is located at (M, 4), the command address ball grid 507 is located at (L, 3), the command address ball grid 504 is located in the center row, and the command address ball grids (501 - 503) are respectively symmetric with the command address ball grids (505 - 507) about the center row. For the second group of command address ball grids (508 - 514), the command address ball grid 508 is located at (M, 12), the command address ball grid 509 is located at (M, 10), the command address ball grid 510 is located at (L, 11), the command address ball grid 511 is located at (J, 10), the command address ball grid 512 is located at (G, 12), the command address ball grid 513 is located at (G, 10), the command address ball grid 514 is located at (H, 11), the command address ball grid 511 is located in the center row, and the command address ball grids (508 - 510) are respectively symmetric with the command address ball grids (512 - 514) about the center row

[0093] In the embodiments of the present disclosure, the columns where the first group of command address ball grids (501-507) are located are between the first column of the ball grid array 20 and the columns where the first group of chip select ball grids (201, 202) are located, and the second group of command address ball grids (508-514) are between the last column of the ball grid array 20 and the columns where the second group of chip select ball grids (203, 204) are located. Moreover, there are 2 or 3 command address ball grids arranged on the column where any command address ball grid is located. In this way, it is possible to minimize the distribution breadth of the command address ball grids in the first direction. On the one hand, the signal transmission distance is shortened, better ensuring the signal integrity. On the other hand, the number of ball grid columns of the ball grid array 20 can be reduced as a whole.

[0094] In some embodiments, as Figure 5 shown, the ball grid array 20 further includes: the first group of write clock ball grids (601, 602), the second group of write clock ball grids (603, 604), the third group of write clock ball grids (605, 606), and the fourth group of write clock ball grids (607, 608). The first group of write clock ball grids (601, 602), the second group of write clock ball grids (603, 604), the third group of write clock ball grids (605, 606), and the fourth group of write clock ball grids (607, 608) are symmetric about the center AA of the ball grid array 20; the first group of read data strobe ball grids (701, 702), the second group of read data strobe ball grids (703, 704), the third group of read data strobe ball grids (705, 706), and the fourth group of read data strobe ball grids (707, 708). The first group of read data strobe ball grids (701, 702), the second group of read data strobe ball grids (703, 704), the third group of read data strobe ball grids (705, 706), and the fourth group of read data strobe ball grids (707, 708) are symmetric about the center AA of the ball grid array 20; 4 mask flip control ball grids (801-804), and the 1st, 2nd, 3rd, and 4th mask flip control ball grids are symmetric about the center AA of the ball grid array 20.

[0095] In a specific embodiment, for each group of write clock ball grids, it includes 2 write clock ball grids arranged adjacent diagonally. The first write clock ball grid is also diagonally adjacent to 2 data ball grids and 1 read data strobe ball grid. The second write clock ball grid is also diagonally adjacent to 2 data ball grids, and the other ball grids linearly adjacent to any write clock ball grid are used to transmit the ground signal VSS and / or the power supply signal VDD; for each group of read data strobe ball grids, it includes 2 read data strobe ball grids arranged adjacent diagonally. The first read data strobe ball grid is also diagonally adjacent to 2 data ball grids and 1 write clock ball grid. The second read data strobe ball grid is also diagonally adjacent to 1 data ball grid and 1 mask flip control ball grid, and the other ball grids linearly adjacent to any read data strobe ball grid are used to transmit the ground signal VSS and / or the power supply signal VDD.

[0096] It should be noted that, as Figure 6 shown, any one of the first group of write clock ball grids (601, 602), the second group of write clock ball grids (603, 604), the third group of write clock ball grids (605, 606), and the fourth group of write clock ball grids (607, 608) transmits a pair of write clock signals WCK_T and WCK_C respectively. In particular, a pair of write clock signals WCK_T and WCK_C are differential signals. Any one of the first group of read data strobe ball grids (701, 702), the second group of read data strobe ball grids (703, 704), the third group of read data strobe ball grids (705, 706), and the fourth group of read data strobe ball grids (707, 708) transmits a pair of read data strobe signals RDQS_T and RDQS_C respectively; in particular, a pair of read data strobe signals RDQS_T and RDQS_C are differential signals; 4 mask flip control ball grids (801 - 804) are used to transmit mask flip control signal DMI.

[0097] In some embodiments, the 4 mask flip control ball grids (801 - 804) are respectively located in the first row and the last row of the ball grid array 20, and the other ball grids that are linearly adjacent to any one of the mask flip control ball grids are used to transmit ground signal VSS and / or power supply signal VDD.

[0098] In some embodiments, as Figure 6 shown, the ball grid array 20 further includes a plurality of multi - purpose ball grids. The multi - purpose ball grids are located in the edge rows and / or edge columns of the ball grid array 20. The plurality of multi - purpose ball grids include one or more of reserved ball grid RFU, reset ball grid RESET, non - enabled ball grid NC, or calibration control ball grid ZQ. Here, the edge rows of the ball grid array 20 include the first row and the last row, and the edge columns include the first column and the last column. In the embodiments of the present disclosure, setting the multi - purpose ball grids in the edge rows and edge columns of the ball grid array 20 can overall reduce the number of ball grids of the ball grid array 20, thereby reducing the size of the package substrate 11.

[0099] In a specific embodiment, the ball grid array 20 is provided with: (1) 2 reserved ball grids RFU. The reserved ball grids RFU have no defined meaning, and each manufacturer or customer can enable and define them according to requirements; (2) 12 non - enabled ball grids NC. The non - enabled ball grids NC refer to the ball grids that are not connected and can play a mechanical support role; (3) 1 reset ball grid Reset_N; (4) 1 calibration control ball grid ZQ.

[0100] In actual operation, the ball grid array 20 can support chips with 2 Channels. Generally, the upper half of the ball grid array 20 (rows 1 to 9) is used to package the signals of 1 Channel, and the lower half of the ball grid array 20 (rows 10 to 18) is used to package the signals of the other 1 Channel. At the same time, the entire ball grid array 20 is centrosymmetric, so that the internal circuits of each Channel can be designed to be the same. That is to say, the first part of the ball grid array 20 coincides with the second part after rotating 180 degrees; the first part of the ball grid array 20 is on one side of the central row, and the second part of the ball grid array 20 is on the other side of the central row.

[0101] Of course, in other embodiments, the left half of the ball grid array (columns 1 to 6) can be used to package the signals of 1 Channel, and the right half of the ball grid array (columns 8 to 13) can be used to package the signals of 1 Channel.

[0102] In some embodiments, as Figure 6 shown, the number of ball grids for transmitting the ground signal VSS is 67, and the number of ball grids for transmitting the power supply signal VDD is 77. In a specific embodiment, the ball grids for transmitting the power supply signal VDD located in the central row are distributed on both sides of the central column, and the number thereof is 14. The ball grids for transmitting the power supply signal VDD located in the central column are distributed on both sides of the central row, and the number thereof is 10. The number of ball grids for transmitting the ground signal VSS located in the central row is 10, and the number of ball grids for transmitting the ground signal VSS located in the central column but not in the central row is 4. Compared with the conventional packaging substrate of LP5, the ball grid array 20 in the packaging structure provided by the embodiments of the present disclosure deletes some ball grids for transmitting the power supply signal VDD and the ground signal VSS, especially deletes some ball grids for transmitting the power supply signal VDD and the ground signal VSS located in the central row and the central column, thereby reducing the number of rows and columns of the ball grid array 20, and further reducing the size of the packaging substrate 11.

[0103] In some embodiments, in the first direction, the distance between any two adjacent ball grids in the ball grid array 20 is 0.6 mm, and in the second direction, the distance between any two adjacent ball grids in the ball grid array 20 is 0.65 mm. Here, by reducing the distance between two linearly adjacent ball grids, the soldering reliability (SJR) of the ball grids is improved, and at the same time, the traces on the packaging substrate 11 are shortened, which helps to improve the signal integrity (SI) in the circuit system.

[0104] It can be seen that in the embodiments of the present disclosure, by deleting some of the ball grid arrays in the ball grid array 20 (such as the ball grid arrays for transmitting the power signal VDD and the ground signal VSS, and the reserved ball grid RFU), and adjusting the distribution positions of some of the ball grid arrays (such as the ball grid arrays for transmitting the chip select signal CS, the clock signal CLK, and the command address signal CA), and by reducing the distance between two linearly adjacent ball grid arrays, the number of rows and columns of the ball grid array 20 and the size of the packaging substrate 11 are reduced. In some embodiments, the size of the packaging substrate 11 is approximately 8.2 mm × 12.4 mm, which is reduced by 4.3 mm × 2.6 mm compared to the conventional packaging size of LP5.

[0105] The ball grid array 20 provided by the embodiments of the present disclosure has a total of 18 rows and 13 columns, and the number of ball grid arrays is 234. Therefore, the packaging substrate 11 provided by the embodiments of the present disclosure can be referred to as a 234B packaging substrate. The ball grid array in the conventional packaging substrate of LP5 usually has 21 rows and 15 columns, and the number of ball grid arrays is 315. Therefore, it can be referred to as a 315B packaging substrate. Figure 7 shows the signal integrity curve graphs of the 315B packaging substrate and the 234B packaging substrate when transmitting signals; among them, Figure 7 in figure (1) is the signal integrity curve graph of the two packaging substrates when transmitting write data signals in a scenario with a working frequency of 6400 Mbps, Figure 7 in figure (2) is the signal integrity curve graph of the two packaging substrates when transmitting read data signals in a scenario with a working frequency of 6400 Mbps, Figure 7 in figure (3) is the signal integrity curve graph of the two packaging substrates when transmitting write data signals in a scenario with a working frequency of 7500 Mbps, Figure 7 in figure (4) is the signal integrity curve graph of the two packaging substrates when transmitting read data signals in a scenario with a working frequency of 7500 Mbps, and Figure 7 figures (1) to (4) respectively provide the signal integrity data of 8 data ball grid arrays (DQ0 to DQ7). It can be seen that in different working scenarios, the signal integrity trends of the 234B packaging substrate and the 315B packaging substrate are the same, indicating that the signal integrity of the packaging substrate 11 provided by the embodiments of the present disclosure is not greatly affected when transmitting signals.

[0106] In another embodiment of the present disclosure, refer to Figure 8 , which shows a schematic structural diagram of a memory 90 provided by the embodiments of the present disclosure. As Figure 8 shown, the memory 90 at least includes the aforementioned packaging structure 10.

[0107] The above are only the preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element. The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the superiority or inferiority of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A packaging structure, characterized in that, it includes: a packaging substrate, on the surface of which a ball grid array is distributed, and the ball grid array includes a plurality of chip select ball grids and a plurality of data ball grids; wherein, for any one of the chip select ball grids, it is in the same column as one of the data ball grids and arranged with a spacing of one row.

2. The packaging structure according to claim 1, characterized in that, the plurality of chip select ball grids are divided into a first group of chip select ball grids and a second group of chip select ball grids, and the first group of chip select ball grids and the second group of chip select ball grids are centrosymmetric about the center of the ball grid array; the middle two rows of the ball grid array are called the center rows, and the middle one column of the ball grid array is called the center column; the first group of chip select ball grids, the center rows, and the second group of chip select ball grids are arranged adjacent to each other along the second direction; the first group of chip select ball grids, the center column, and the second group of chip select ball grids are arranged adjacent to each other along the first direction; wherein, the first direction refers to the row direction of the ball grid array, and the second direction refers to the column direction of the ball grid array.

3. The packaging structure according to claim 2, characterized in that, the first group of chip select ball grids includes 2 chip select ball grids arranged adjacent to each other along the diagonal, and the second group of chip select ball grids includes 2 chip select ball grids arranged adjacent to each other along the diagonal; the other ball grids linearly adjacent to any one of the chip select ball grids are used to transmit ground signals or power supply signals.

4. The packaging structure according to claim 2 or 3, characterized in that, the ball grid array further includes a first group of clock ball grids and a second group of clock ball grids, and the first group of clock ball grids and the second group of clock ball grids are centrosymmetric about the center of the ball grid array; one of the clock ball grids in the first group of clock ball grids is diagonally adjacent to one of the chip select ball grids in the first group of chip select ball grids, and one of the clock ball grids in the second group of clock ball grids is diagonally adjacent to one of the chip select ball grids in the second group of chip select ball grids.

5. The packaging structure according to claim 4, characterized in that, each group of clock ball grids includes 2 clock ball grids in the same row and adjacent to each other, the rows where the first group of clock ball grids is located, the center rows, and the rows where the second group of clock ball grids is located are arranged adjacent to each other along the second direction, and one of the clock ball grids in each group of clock ball grids is located in the center column; the other ball grids linearly adjacent to any one of the clock ball grids are used to transmit ground signals or power supply signals.

6. The packaging structure according to claim 2, characterized in that, the plurality of data ball grids are divided into a first group of data ball grids, a second group of data ball grids, a third group of data ball grids, and a fourth group of data ball grids; the first group of data ball grids, the second group of data ball grids, the third group of data ball grids, and the fourth group of data ball grids are centrosymmetric about the center of the ball grid array; the first group of data ball grids, the center rows, and the second group of data ball grids are arranged along the second direction; the third group of data ball grids, the center rows, and the fourth group of data ball grids are arranged along the second direction; the first group of data ball grids, the center column, and the third group of data ball grids are arranged along the first direction; The second group of data ball grids, the central column, and the fourth group of data ball grids are arranged in a first direction; wherein, each of the data ball grids is at least diagonally adjacent to another data ball grid, and the other ball grids that are linearly adjacent to any one of the data ball grids are used to transmit ground signals and / or power supply signals.

7. The packaging structure according to claim 6, characterized in that the ball grid array further includes a first group of command address ball grids and a second group of command address ball grids, and the first group of command address ball grids and the second group of command address ball grids are centrosymmetric about the center of the ball grid array; the first group of data ball grids, the first group of command address ball grids, and the second group of data ball grids are arranged in sequence in a second direction, and the third group of data ball grids, the second group of command address ball grids, and the fourth group of data ball grids are arranged in sequence in a second direction.

8. The packaging structure according to claim 7, characterized in that in the first group of command address ball grids, one of the command address ball grids is located in the central row, and the remaining command address ball grids are symmetric about the central row; in the second group of command address ball grids, one of the command address ball grids is located in the central row, and the remaining command address ball grids are symmetric about the central row; wherein, each command address ball grid is at least diagonally adjacent to another command address ball grid, and the other ball grids that are linearly adjacent to any one of the command address ball grids are used to transmit ground signals and / or power supply signals.

9. The packaging structure according to claim 2, characterized in that the ball grid array further includes: a first group of write clock ball grids, a second group of write clock ball grids, a third group of write clock ball grids, and a fourth group of write clock ball grids, and the first group of write clock ball grids, the second group of write clock ball grids, the third group of write clock ball grids, and the fourth group of write clock ball grids are centrosymmetric about the center of the ball grid array; a first group of read data strobe ball grids, a second group of read data strobe ball grids, a third group of read data strobe ball grids, and a fourth group of read data strobe ball grids, and the first group of read data strobe ball grids, the second group of read data strobe ball grids, the third group of read data strobe ball grids, and the fourth group of read data strobe ball grids are centrosymmetric about the center of the ball grid array; 4 mask flip control ball grids, located at the edge row of the ball grid array and centrosymmetric about the center of the ball grid array; wherein, for each group of the write clock ball grids, it includes 2 write clock ball grids arranged adjacent diagonally, the first write clock ball grid is also diagonally adjacent to 2 data ball grids and 1 read data strobe ball grid, the second write clock ball grid is also diagonally adjacent to 2 data ball grids, and the other ball grids that are linearly adjacent to any one of the write clock ball grids are used to transmit ground signals and / or power supply signals; For each set of the read data strobe ball grid arrays, which includes 2 read data strobe ball grid arrays arranged adjacent to each other along the diagonal, the first read data strobe ball grid array is also diagonally adjacent to 2 data ball grid arrays and 1 write clock ball grid array, and the second read data strobe ball grid array is also diagonally adjacent to 1 data ball grid array and 1 mask flip control ball grid array, and the other ball grid arrays that are linearly adjacent to any one of the read data strobe ball grid arrays are used to transmit ground signals and / or power supply signals.

10. The package structure according to claim 1, wherein, the ball grid array further includes a plurality of multi-purpose ball grid arrays, the multi-purpose ball grid arrays are located in the edge rows and / or edge columns of the ball grid array, and the plurality of multi-purpose ball grid arrays include one or more of reserved ball grid arrays, reset ball grid arrays, disabled ball grid arrays or calibration control ball grid arrays.

11. The package structure according to claim 2, wherein, the ball grid array has 18 rows and 13 columns; the number of ball grid arrays for transmitting ground signals is 67, and the number of ball grid arrays for transmitting power supply signals is 77; the ball grid arrays for transmitting power supply signals located in the central row are distributed on both sides of the central column, and the number thereof is 14, and the ball grid arrays for transmitting power supply signals located in the central column are distributed on both sides of the central row, and the number thereof is 10; the number of ball grid arrays for transmitting ground signals located in the central row is 10, and the number of ball grid arrays for transmitting ground signals located in the central column but not in the central row is 4.

12. The package structure according to claim 1, wherein, in the first direction, the distance between any two adjacent ball grid arrays in the ball grid array is 0.6 mm, and in the second direction, the distance between any two adjacent ball grid arrays in the ball grid array is 0.65 mm; wherein, the first direction is the row direction of the ball grid array, and the second direction is the column direction of the ball grid array.

13. The package structure according to claim 2, wherein, the first part of the ball grid array coincides with the second part of the ball grid array after rotating 180 degrees; the first part of the ball grid array is located on one side of the central row, and the second part of the ball grid array is located on the other side of the central row.

14. A memory, wherein, it includes the package structure according to any one of claims 1-13.

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