Evaporation device, display panel and preparation method thereof

Abstract

Embodiments of the present application provide an evaporation device, a display panel and a preparation method thereof. The evaporation device comprises a plurality of evaporation sources, a carrier table having a bearing surface facing the plurality of evaporation sources, and a shielding mask plate located between the bearing surface and the plurality of evaporation sources. The bearing surface is used for carrying a mother board. The shielding mask plate has a main body portion and a plurality of evaporation openings formed by the main body portion. At least one second alignment mark is arranged on the main body portion and corresponds to at least one first alignment mark on the mother board. After the at least one second alignment mark is matched with the at least one first alignment mark, a panel portion is exposed from a corresponding evaporation opening and is opposite to at least part of the plurality of evaporation sources. Embodiments of the present application can reduce the positional alignment deviation between the evaporation sources and the mother board, thereby improving the alignment accuracy of the light-emitting device and further improving the display effect of the display panel.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of evaporation technology, and in particular to an evaporation device, a display panel, and a method for manufacturing the same. Background Art

[0002] Traditional display panel manufacturing typically uses a fine metal mask (FMM) to pattern luminous pixels. FMM technology is mature and boasts extensive mass production experience. However, FMM also suffers from limitations such as limited precision, high development costs, and long development cycles. FMM-free technology eliminates the limitations of traditional OLED (organic light-emitting diode) processes on display size, resolution, and other performance characteristics, offering the advantages of high performance, full-scale scalability, and agile delivery.

[0003] Patent applications CN118251982A, CN115666161A, CN116648095A, CN117062489A, CN118678742A, CN118785761A, CN115224220A, CN118678729A, CN118660529A, and CN118660589A record relevant content of the fine metal mask-free technology for reference.

[0004] The manufacturing process of the display panel includes an evaporation process, which requires an evaporation device. However, the existing evaporation device needs to be improved. Summary of the Invention

[0005] In view of this, embodiments of the present application provide an evaporation device, a display panel, and a method for manufacturing the same, to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, an evaporation device is provided. The evaporation device is used for evaporating a motherboard of a display panel. The motherboard includes a blank portion and a plurality of panel portions, at least two adjacent panel portions are separated by a blank portion, and the blank portion is provided with at least one first alignment mark. The evaporation device includes a plurality of evaporation sources, a carrier and a shielding mask. The carrier has a bearing surface facing the plurality of evaporation sources. The bearing surface is used to bear the motherboard. The shielding mask is located between the bearing surface and the plurality of evaporation sources, and has a main body portion and a plurality of evaporation openings formed by the main body portion. The main body portion is provided with at least one second alignment mark corresponding to the at least one first alignment mark. Wherein, after the at least one second alignment mark is aligned with the at least one first alignment mark, the panel portion is exposed from the corresponding evaporation opening and is at least partially opposite to the plurality of evaporation sources.

[0007] In some embodiments, the at least one first alignment mark includes a plurality of first alignment marks, the blank portion includes a plurality of first corner regions, and the plurality of first alignment marks are disposed in the plurality of first corner regions. The at least one second alignment mark includes a plurality of second alignment marks, the main portion includes a plurality of second corner regions corresponding to the plurality of first corner regions, and the plurality of second alignment marks are disposed in the plurality of second corner regions corresponding to the plurality of first alignment marks.

[0008] In some embodiments, after a plurality of second alignment marks are aligned with a plurality of first alignment marks, a first shape formed by the orthographic projections of the outer edges of the first alignment marks on the carrying surface has a first area, a second shape formed by the orthographic projections of the outer edges of the second alignment marks on the carrying surface has a second area, and the orthographic projection of the panel portion on the carrying surface has a third area, wherein: the first area is smaller than the third area, the second area is smaller than the third area, and the first area is smaller than the second area.

[0009] In some embodiments, the number of multiple first alignment marks and the number of multiple second alignment marks are equal, the first alignment marks have a first pattern, and the second alignment marks have a first opening that matches the first pattern of the corresponding first alignment mark. After at least one second alignment mark is aligned with at least one first alignment mark, the first pattern is exposed from the corresponding first opening.

[0010] In some embodiments, an orthographic projection area of ​​the first opening on the carrying surface is smaller than an orthographic projection area of ​​the evaporation opening on the carrying surface.

[0011] In some embodiments, the plurality of first alignment marks include at least a first sub-alignment mark and a second sub-alignment mark, and the plurality of second alignment marks include at least a third sub-alignment mark corresponding to the first sub-alignment mark and a fourth sub-alignment mark corresponding to the second sub-alignment mark, wherein:

[0012] The shape of the first pattern corresponding to the first sub-alignment mark is different from the shape of the first pattern corresponding to the second sub-alignment mark;

[0013] The shape of the orthographic projection of the first opening corresponding to the third sub-alignment mark on the carrying surface is different from the shape of the orthographic projection of the first opening corresponding to the fourth sub-alignment mark on the carrying surface.

[0014] In some embodiments, the plurality of first alignment marks include at least a first sub-alignment mark and a second sub-alignment mark, and the plurality of second alignment marks include at least a third sub-alignment mark corresponding to the first sub-alignment mark and a fourth sub-alignment mark corresponding to the second sub-alignment mark, wherein:

[0015] The width of the first pattern corresponding to the first sub-alignment mark is smaller than the width of the first pattern corresponding to the second sub-alignment mark;

[0016] The width of the orthographic projection of the first opening corresponding to the third sub-alignment mark on the carrying surface is smaller than the width of the orthographic projection of the first opening corresponding to the fourth sub-alignment mark on the carrying surface.

[0017] In some embodiments, the number of the multiple first alignment marks, the multiple second alignment marks, the multiple first corner areas, and the multiple second corner areas are all 4, the first alignment marks are set in the corresponding first corner areas, and the second alignment marks are set in the corresponding second corner areas.

[0018] In some embodiments, the first pattern is at least one of a cross, a tic-tac-toe, and a rectangle, and the orthographic projection of the first opening corresponding to the first pattern on the bearing surface is at least one of a cross, a tic-tac-toe, and a rectangle.

[0019] In some embodiments, the number of the plurality of first alignment marks is smaller than the number of the plurality of second alignment marks, the plurality of first alignment marks include at least one fifth sub-alignment mark, and the plurality of second alignment marks include at least a plurality of sixth sub-alignment marks corresponding to the fifth sub-alignment mark, wherein:

[0020] The fifth sub-alignment mark has a second pattern, and the sixth sub-alignment mark has second openings matched with the second pattern. After the fifth sub-alignment mark and the sixth sub-alignment mark are matched and aligned, parts of the second pattern are exposed from the plurality of second openings.

[0021] In some embodiments, after the fifth sub-alignment mark and the sixth sub-alignment mark are aligned, the orthographic projection area of ​​the second pattern on the carrying surface is larger than the total area of ​​the shape enclosed by the orthographic projections of the outer edges of the plurality of second openings on the carrying surface.

[0022] In some embodiments, the blank portion is provided with a plurality of test terminals, and the test terminals are electrically connected to corresponding panel portions, wherein:

[0023] After the at least one second alignment mark is aligned with the at least one first alignment mark, the main body separates the plurality of test terminals from the plurality of evaporation sources.

[0024] In some embodiments, a plurality of test devices are disposed in the blank portion. The test devices are disposed beside the corresponding panel portion and include a dummy pixel circuit, a dummy isolation structure, and a dummy first electrode. The dummy isolation structure encloses an isolation opening, and a portion of the dummy first electrode is exposed from the isolation opening and is electrically connected to the dummy pixel circuit.

[0025] After the at least one second alignment mark is aligned with the at least one first alignment mark, the main body separates the plurality of test devices from the plurality of evaporation sources.

[0026] In some embodiments, after at least one second alignment mark is aligned with at least one first alignment mark, the orthographic projection of the main body on the carrying surface covers the orthographic projections of multiple test terminals on the carrying surface, and the orthographic projection of the main body on the carrying surface covers the orthographic projections of multiple test devices on the carrying surface.

[0027] In some embodiments, the width of the main body portion located between the plurality of evaporation openings is smaller than the width of the main body portion located beside the plurality of evaporation openings.

[0028] According to a second aspect of an embodiment of the present application, a method for manufacturing a display panel is provided. The method for manufacturing a display panel comprises: moving a motherboard of a display panel onto a carrying surface of a carrier of a vapor deposition device as described above, wherein the motherboard comprises a blank portion and a plurality of panel portions, at least two adjacent panel portions are separated by the blank portion, and the blank portion is provided with at least one first alignment mark;

[0029] Moving the shielding mask to align the at least one second alignment mark with the at least one first alignment mark so that the panel portion is exposed from the corresponding evaporation opening and faces at least part of the plurality of evaporation sources;

[0030] The evaporation material ejected from the plurality of evaporation sources is used to perform evaporation on the plurality of panel portions of the motherboard.

[0031] In some embodiments, the blank portion is provided with a plurality of test terminals and a plurality of test devices, the test terminals being electrically connected to the corresponding panel portion, the test device being provided beside the corresponding panel portion and including a dummy pixel circuit, a dummy isolation structure, and a dummy first electrode, the dummy isolation structure enclosing an isolation opening, a portion of the dummy first electrode being exposed from the isolation opening and electrically connected to the dummy pixel circuit;

[0032] In the step of performing vapor deposition on the plurality of panel portions of the motherboard, the main body separates the plurality of test terminals from the plurality of vapor deposition sources, and the main body separates the plurality of test devices from the plurality of vapor deposition sources;

[0033] After the step of performing evaporation deposition on the plurality of panel portions of the motherboard, the method further comprises:

[0034] Use the test terminal to perform lighting test on the corresponding panel part;

[0035] Perform cathode bonding impedance test on the corresponding panel part using the test device.

[0036] In some embodiments, after the step of performing a cathode bonding impedance test on the corresponding panel portion using a test device, the method further includes:

[0037] Cutting the blank portion to separate the plurality of panel portions after vapor deposition from each other to obtain a plurality of display panels, each display panel including the corresponding panel portions after vapor deposition;

[0038] In the process of separating the plurality of panel portions after vapor deposition, the test terminals are separated from the corresponding panel portions after vapor deposition, and the test devices are separated from the corresponding panel portions after vapor deposition.

[0039] According to a third aspect of the embodiments of the present application, a display panel is provided. The display panel is manufactured using the method of any of the above embodiments.

[0040] In some embodiments, a display panel includes a substrate, an isolation structure, and multiple light-emitting devices. The isolation structure is located on one side of the substrate and encloses multiple isolation openings. Portions of the light-emitting devices are located within corresponding isolation openings. The light-emitting devices include a first electrode, a light-emitting functional layer, and a second electrode, sequentially arranged in a direction away from the substrate. The second electrode overlaps the isolation structure.

[0041] According to the solution provided in the embodiment of the present application, a shielding mask is set between the evaporation source and the carrier, and the second alignment mark on the shielding mask is aligned with the first alignment mark on the motherboard, which can reduce the position alignment deviation between the evaporation source and the motherboard, so that the evaporation material can be accurately evaporated at the corresponding position of the motherboard, so as to improve the alignment accuracy of the film layer pattern of the motherboard, thereby improving the alignment accuracy of the light-emitting device and further improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0043] Figure 1 This is a schematic diagram of an exemplary structure of a display device provided in an embodiment of the present application;

[0044] Figure 2 A schematic diagram of an exemplary structure of a display panel provided in an embodiment of the present application;

[0045] Figure 3 for Figure 2 Enlarged view of point A in the middle;

[0046] Figure 4 for Figure 3 A sectional view taken along section line B1-B2;

[0047] Figure 5 A schematic diagram of an exemplary structure of a motherboard provided in an embodiment of the present application;

[0048] Figure 6Schematic diagram of the structure of the evaporation device in some examples;

[0049] Figure 7 This is a schematic diagram of an exemplary structure of an evaporation device provided in an embodiment of the present application;

[0050] Figure 8 A schematic diagram of an exemplary structure of a shielding mask provided in an embodiment of the present application;

[0051] Figure 9 This is a schematic diagram of an exemplary structure after alignment of a motherboard and a blocking mask provided in an embodiment of the present application;

[0052] Figure 10 A flow chart of a method for preparing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0054] The terms used in the embodiments of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the embodiments of this application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in the embodiments of this application refers to and includes any or all possible combinations of one or more associated listed items.

[0055] It should be understood that in the description of the embodiments of the present application, the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the scheme of the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0056] In addition, when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0057] The terms first, second, etc. are used to describe various elements, components, regions, layers and / or sections, but these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section.

[0058] Unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," and the like should be interpreted broadly. For example, they may refer to fixed or detachable connections, or integration; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0059] The specific implementation of the embodiment of the present application is further explained below in conjunction with the accompanying drawings of the embodiment of the present application.

[0060] Figure 1 This is a schematic diagram of an exemplary structure of a display device provided in an embodiment of the present application.

[0061] See also Figure 1 In an embodiment of the present application, a display device 1000 is provided. The display device 1000 is an electronic device having an image display function (including static images or dynamic images, where the dynamic image may be a video). For example, the display device 1000 may be any one of, but not limited to, a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a large-area wall, a home appliance, an information query device (such as a business query device for e-government, banks, hospitals, power departments, etc.), a monitor, an electronic screen, a virtual reality (VR) display device, an augmented reality (AR) display device, and an in-vehicle display.

[0062] Continue to see Figure 1The display device 1000 may include a display panel 100. The display panel 100 may be any one of an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Mini LED or Micro LED) display panel and a liquid crystal display (LCD) panel. The embodiments of the present application do not limit the type of the display panel 100.

[0063] Figure 2 This is a schematic diagram of an exemplary structure of a display panel provided in an embodiment of the present application. Figure 3 for Figure 2 Enlarged view of point A in the middle.

[0064] For the convenience of the following description, an XYZ coordinate system is established. Figure 2 The third direction Z represents the thickness direction of the display panel 100 (or the thickness direction of the display device). The first direction X and the second direction Y are perpendicular to each other and are both perpendicular to the third direction Z.

[0065] See also Figure 2 The display panel 100 has a display area AA and a non-display area SA. The display area AA is the area of ​​the display panel 100 used to display images, and the non-display area SA is the area of ​​the display panel 100 other than the display area AA. The non-display area SA may be located on at least one side (e.g., one side or multiple sides) of the display area AA. For example, the non-display area SA may be arranged around the display area AA.

[0066] The display area AA includes a plurality of pixel units P. Figure 3 , each pixel unit P includes a plurality of sub-pixels 101, and the sub-pixel 101 is the smallest unit for displaying an image in the display panel 100. The luminous colors of the plurality of sub-pixels 101 are different. Exemplarily, each pixel unit P includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel respectively emit three primary colors of light. For example, the first sub-pixel can emit red light, the second sub-pixel can emit green light, and the third sub-pixel can emit blue light. The arrangement of the plurality of sub-pixels 101 in the display area AA can be any arrangement such as a standard RGB arrangement, a Delta pixel arrangement, a Pentile arrangement, a diamond-like arrangement, or the like.

[0067] Figure 4 for Figure 3 A sectional view taken along section line B1-B2.

[0068] Referring to Figure 4 The display panel 100 includes a substrate 10, a display functional layer, a pixel definition layer 20, and an isolation structure (VSS) 40.

[0069] The substrate 10 includes a substrate substrate 11. The substrate substrate 11 supports other structures in the display panel 100. The substrate substrate 11 can be set according to actual needs. Exemplarily, the substrate substrate 11 can be a rigid substrate, and also exemplarily, the substrate substrate 11 can be a flexible substrate. The substrate 10 can further include a driving circuit layer 12, which is located on one side of the substrate substrate 11, coupled with a plurality of light emitting devices (which will be described in detail below), and configured to provide an electrical signal to each light emitting device so that the light emitting device emits light with a corresponding brightness. The driving circuit layer 12 includes a plurality of pixel driving circuits, each of which is electrically connected to a sub-pixel 101 for driving the sub-pixel to emit light. The pixel driving circuit can include a plurality of electronic elements such as transistors and capacitors, for example, each pixel driving circuit can include three transistors and one capacitor, forming a 3T1C (i.e., one driving transistor, two switching transistors, and one capacitor), and can also include more than three transistors and at least one capacitor, such as 4T1C, 5T1C, or 7T1C, etc. Among them, the transistor can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics.

[0070] The pixel definition layer 20 is located on one side of the substrate 10. The pixel definition layer 20 includes a pixel limiting portion 21 and a plurality of pixel openings 22 formed by the pixel limiting portion 21, that is, the surface of the pixel definition layer 20 away from the substrate 10 side has a plurality of openings.

[0071] The display function layer is located on the substrate 10 and includes a plurality of light-emitting devices 30, at least partially (e.g., partially or completely) located within the pixel openings 22. A light-emitting device 30 is an electronic device capable of emitting light. One light-emitting device 30 corresponds to one sub-pixel, and one light-emitting device 30 corresponds to one pixel opening 22. The light-emitting device 30 can be any of an OLED device, a QLED device, an LED device, or a micro-light-emitting diode (Mini LED or Micro LED) device. The light-emitting device 30 includes a first electrode 31, a light-emitting function layer 32, and a second electrode 33, stacked in a direction away from the substrate 10. The first electrode 31 is located on one side of the substrate 10, with each first electrode 31 corresponding to a pixel opening 22. The pixel opening 22 exposes a portion of the corresponding first electrode 31, and the pixel defining portion 21 covers the gaps between adjacent first electrodes 31. The light-emitting function layer 32 covers the exposed first electrodes 31. The side of the light-emitting function layer 32 that is closer to the substrate 10 is connected to the first electrode 31, and the side farther from the substrate 10 is connected to the second electrode 33. One of the first electrode 31 and the second electrode 33 is an anode, and the other is a cathode. Exemplarily, the first electrode 31 is an anode, and the second electrode 33 is a cathode. Furthermore, exemplary embodiments include the first electrode 31 as a cathode and the second electrode 33 as an anode. The light-emitting functional layer 32 may include a light-emitting layer (EML) and a functional material layer. For example, the functional material layer may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). The specific configuration depends on actual needs and is not limited in this embodiment.

[0072] The isolation structure 40 is located on one side of the substrate 10, specifically, on the side of the pixel definition layer 20 away from the substrate 10, and is used to isolate the light-emitting functional layer 32 of the adjacent light-emitting device 30. Specifically, the isolation structure 40 is located on the side of the pixel definition portion 21 away from the substrate 10. The isolation structure 40 can be a multi-layer structure. Exemplarily, the isolation structure 40 includes a first isolation layer 41, a second isolation layer 42 and a third isolation layer 43 stacked in sequence in a direction away from the substrate 10, and the second electrode 33 overlaps the first isolation layer 41. The isolation structure 40 encloses a plurality of isolation openings. The isolation openings are connected to the pixel opening 21, and part of the light-emitting device 30 is located in the corresponding isolation opening. The isolation structure 40 is electrically connected to the light-emitting device 30, specifically, the isolation structure 40 overlaps the second electrode 33.

[0073] The display panel 100 may further include a first encapsulation layer 50, which is located on the side of the display function layer away from the substrate 10. Exemplarily, the first encapsulation layer 50 is composed of multiple encapsulation units that respectively cover the isolation openings. The first encapsulation layer 50 covers at least the light-emitting devices 30. The first encapsulation layer 50 forms a dense thin film (e.g., a film having only a closed outline) above the light-emitting devices 30 to prevent the entry of moisture and oxygen from the outside into the light-emitting devices and protect the film layers of the light-emitting devices 30. To achieve a better sealing effect, the material of the first encapsulation layer 50 may include an inorganic insulating material, such as one or more of silicon oxide, silicon nitride, and titanium oxide. The first encapsulation layer 50 can be formed using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0074] The display panel 100 may further include a second encapsulation layer 60 and a third encapsulation layer 70 to further enhance the encapsulation effect. The second encapsulation layer 60 is located on the side of the first encapsulation layer 50 away from the substrate 10, and the third encapsulation layer 70 is located on the side of the second encapsulation layer 60 away from the substrate 10, covering the isolation opening and isolation structure 40. The second encapsulation layer 60 and the third encapsulation layer 70 can extend from the display area AA to the non-display area SA, in which case their outlines are located in the non-display area SA. The second encapsulation layer 60 is an organic layer, and the third encapsulation layer 70 is an inorganic layer.

[0075] Figure 5 This is a schematic diagram of an exemplary structure of a motherboard provided in an embodiment of the present application.

[0076] The display panel 100 is formed by cutting the motherboard 100m. Figure 5 The motherboard 100m includes a plurality of panel portions 101 and blank portions 102, wherein at least two adjacent panel portions 101 are separated by the blank portion 102. When forming the display panel 100, the blank portion of the motherboard 100m is cut so that the panel portions 101 form the display panel 100.

[0077] In some embodiments, the blank portion 102 is provided with a plurality of test terminals 1021 for light on inspection (LOI) and CT testing. The test terminals 1021 are electrically connected to corresponding panel portions 101 .

[0078] In some embodiments, the blank portion 102 is further provided with a plurality of test devices 1022, which serve as a test element group (TEG) for cathode bonding impedance testing. The test devices 1022 are disposed adjacent to the corresponding panel portion 101 and include a dummy pixel circuit, a dummy isolation structure, and a dummy first electrode. The dummy isolation structure encloses an isolation opening, and a portion of the dummy first electrode is exposed through the isolation opening and electrically connected to the dummy pixel circuit.

[0079] The process steps for preparing the motherboard 100m include at least the following: G1. Forming an isolation structure on a substrate, wherein the isolation structure encloses a plurality of isolation openings. G2. Forming a plurality of light-emitting devices, wherein portions of the light-emitting devices are located within corresponding isolation openings. The formed light-emitting devices include a first electrode, a light-emitting functional layer, and a second electrode sequentially arranged in a direction away from the substrate, wherein the second electrode overlaps the isolation structure. When forming a pixel driving circuit in the substrate, a virtual pixel circuit can be formed simultaneously. When forming an isolation structure on the substrate, a virtual isolation structure can be formed simultaneously. When forming the first electrode, a virtual first electrode can be formed simultaneously.

[0080] The formation of multiple light-emitting devices is carried out using an evaporation process in an evaporation device.

[0081] Figure 6 Schematic diagram of the structure of the evaporation device in some examples.

[0082] For some examples, see Figure 6 The evaporation device 200A includes an evaporation source 201A and a carrier 202A. The carrier 202A has a carrying surface 2021A facing the evaporation source 201A, and the motherboard 100m is placed on the carrying surface 2021A. In the process of preparing the motherboard 100m, the evaporation material is sprayed onto the motherboard 100m by the evaporation source 201A to complete the evaporation process. During the evaporation process, the motherboard 100m is placed on the carrier 202A, and the position alignment of the evaporation source 201A and the motherboard 100m deviates, resulting in the evaporation material not being accurately evaporated at the corresponding position of the motherboard 100m, causing the position of the light-emitting device of the motherboard 100m to deviate, affecting the light-emitting effect, thereby resulting in poor display effect of the formed display panel 100.

[0083] In order to solve the above technical problems, an embodiment of the present application provides an evaporation device, which adds a positioning system to improve the alignment accuracy between the evaporation source and the motherboard.

[0084] Figure 7 This is a schematic diagram of an exemplary structure of an evaporation device provided in an embodiment of the present application. Figure 8 A schematic diagram of an exemplary structure of a blocking mask provided in an embodiment of the present application.

[0085] See also Figure 7The evaporation device includes multiple evaporation sources 201, a carrier 202 and a shielding mask 203.

[0086] The evaporation source 201 can accommodate evaporation materials and can be applied to the evaporation process in the display panel manufacturing process, that is, in a vacuum chamber, by heating, the evaporation material is sublimated into molecular-level vapor and uniformly adhered to the motherboard 100m according to the preset device structure. Evaporation materials can be divided into packaging layer materials (including light extraction materials and crystal packaging materials), cathode evaporation materials, electron transport layer materials, hole blocking layer materials, light-emitting layer materials, electron blocking layer materials, hole transport layer materials, hole injection layer materials, etc. according to their functions. The evaporation source 210 can be a point evaporation source, a line evaporation source or a surface evaporation source. For example, the evaporation source 10 can be a crucible. The embodiment of the present application does not specifically limit the shape and size of the evaporation source, as long as it can accommodate the evaporation material and heat it.

[0087] The carrier 202 has a carrying surface 2021 facing the plurality of evaporation sources 201, and the carrying surface 2021 is used to carry the motherboard 100m. Figure 5 The blank portion 102 of the motherboard 100m is provided with at least one (eg, one, or multiple) first alignment mark G1.

[0088] See also Figure 7 and Figure 8 The shielding mask 203 is located between the carrying surface 2021 and the multiple evaporation sources 201, and has a main body 2031 and a plurality of evaporation openings 2032 formed by the main body 2031. At least one second alignment mark G2 corresponding to at least one first alignment mark G1 is provided on the main body 2031. After the at least one second alignment mark G2 is aligned with the at least one first alignment mark G1, illustratively, one second alignment mark G2 is aligned with one first alignment mark G1. In another exemplary embodiment, each second alignment mark G2 is aligned with one first alignment mark G1. The panel portion 101 is exposed from the corresponding evaporation opening 2032 and is at least partially opposite to the multiple evaporation sources 201.

[0089] Figure 9 This is a schematic diagram of an exemplary structure after alignment of a motherboard and a blocking mask provided in an embodiment of the present application.

[0090] During the operation of the evaporation device 200, there is no obstruction between the first alignment mark G1 and the second alignment mark G2. Figure 9The second alignment mark G2 on the shielding mask plate 203 is aligned with the first alignment mark G1 on the mother board 100m, the panel part 101 of the mother board 100m corresponds to the evaporation opening 2032 of the shielding mask plate 203, the panel part 101 is exposed from the evaporation opening 2032, the evaporation material in the evaporation source 201 is evaporated on the panel part 101 through the evaporation opening 2032, a corresponding film layer on the mother board 100m is formed, and the evaporation process is completed. By aligning the first alignment mark G1 and the second alignment mark G2, the position alignment deviation of the evaporation source 201 and the mother board 100m can be reduced, so that the evaporation material is accurately evaporated on the corresponding position of the mother board 100m after being heated to form vapor in the evaporation source 201 and being sprayed along the side of the bearing surface 2021 of the third square Z direction carrier 202, thereby improving the alignment accuracy of the film layer pattern of the mother board 100m, improving the alignment accuracy of the light emitting device, and further improving the display effect of the display panel 100.

[0091] In some embodiments, continuing to refer to Figure 5 , the at least one first alignment mark G1 includes a plurality of (for example, two, and for example, more than two) first alignment marks G1, and the blank part 102 includes a plurality of (for example, two, and for example, more than two) first corner areas Q1. For example, the first corner area Q1 can be located at a region where the right angles of the mother board 100m are located. The plurality of first alignment marks G1 are arranged in the plurality of first corner areas Q1. In this way, the range of the mother board 100m covered by the plurality of first alignment marks G1 after being connected is larger, that is, the plurality of first alignment marks G1 can improve the range of the alignment mark and perform high-precision positioning in a wider area of the mother board 100m, so as to reduce the alignment error caused by shielding or environmental interference and improve the stability and reliability of the alignment.

[0092] Continuing to refer to Figure 8 , the at least one second alignment mark G2 includes a plurality of (for example, two, and for example, more than two) second alignment marks G2. The main body part 2031 includes a plurality of second corner areas Q2 corresponding to the plurality of first corner areas Q1, and the plurality of second alignment marks G2 are arranged in the plurality of second corner areas Q2 corresponding to the plurality of first alignment marks G1. In this way, the first corner area Q1 corresponds to the second corner area Q2, the plurality of first alignment marks G1 correspond to the plurality of second alignment marks G2, and the alignment marks at two or more corresponding positions correspond to each other, so as to improve the alignment accuracy between the mother board 100m and the shielding mask plate 203 and reduce the alignment error.

[0093] In some embodiments, after a plurality of second alignment marks G2 are aligned with a plurality of first alignment marks G1, a first shape formed by the orthographic projection of the outer edge of the first alignment mark G1 on the carrying surface 2021 has a first area, a second shape formed by the orthographic projection of the outer edge of the second alignment mark G2 on the carrying surface 2021 has a second area, and the orthographic projection of the panel portion 101 on the carrying surface 2021 has a third area.

[0094] The first area is smaller than the third area, that is, the orthographic projection of the outer edge of the first alignment mark G1 on the bearing surface 2021 is smaller than the orthographic projection of the panel portion 101 on the bearing surface 2021. The first alignment mark G1 is smaller than the panel portion 101, and the movable range of the first alignment mark G1 is smaller. Compared with directly using the panel portion 101 for alignment, the absolute error between the actual position and the target position of the first alignment mark G1 during the alignment process is smaller, and the alignment accuracy is greater than the alignment accuracy of the panel portion 101. Therefore, using the first alignment mark G1 for alignment can improve the alignment accuracy of the motherboard 100m.

[0095] The second area is smaller than the third area, that is, the orthographic projection of the outer edge of the second alignment mark G2 on the bearing surface 2021 is smaller than the orthographic projection of the panel part 101 on the bearing surface 2021. The second alignment mark G2 is smaller than the panel part 101, and the movable range of the second alignment mark G2 is smaller. Compared with directly using the panel part 101 for alignment, the absolute error between the actual position and the target position of the second alignment mark G2 during the alignment process is smaller, and the alignment accuracy is greater than the alignment accuracy of the panel part 101. Therefore, using the second alignment mark G2 for alignment can improve the alignment accuracy of the motherboard 100m.

[0096] The first area is smaller than the second area. In other words, the orthographic projection of the outer edge of the first alignment mark G1 on the support surface 2021 is smaller than the orthographic projection of the second alignment mark G2 on the support surface 2021. During alignment, the first alignment mark G1 can be moved to within the corresponding second alignment mark G2 before fine-tuning to improve alignment efficiency. Furthermore, during alignment, the alignment accuracy between the motherboard 100m and the mask plate 203 can be monitored by detecting whether the first alignment mark G1 is covered by the second alignment mark G2, thereby reducing alignment errors.

[0097] In some embodiments, see Figure 9The number of the plurality of first alignment marks G1 and the number of the plurality of second alignment marks G2 are equal, for example, the number of the first alignment marks G1 is four, and the first alignment marks G1 are respectively located at the four corners of the mother board 100m, and the number of the second alignment marks G2 is also four, and the second alignment marks G2 are respectively located at the four corners of the shielding mask plate 203. The first alignment marks G1 have a first pattern, and the second alignment marks G2 have a first opening matched with the first pattern of the corresponding first alignment mark G1, and the first pattern is exposed from the corresponding first opening after at least one second alignment mark is matched with at least one first alignment mark. The number of the first alignment marks G1 and the number of the second alignment marks G2 are equal, and each first pattern is respectively exposed from the corresponding first opening, and the plurality of positions of the first alignment marks G1 and the second alignment marks G2 are matched one by one, which can improve the alignment accuracy of the position of each alignment mark, and further improve the alignment accuracy of the whole mother board 100m and the whole shielding mask plate 203, reduce the alignment error, and thus improve the display effect.

[0098] In some embodiments, continuing to refer to Figure 8 The area of the orthographic projection of the first opening K1 on the bearing surface 2021 is smaller than the area of the orthographic projection of the evaporation opening 2032 on the bearing surface 2021. The first opening K1 is smaller than the evaporation opening 2032, and the second alignment mark G2 has a smaller active range. Compared with directly using the evaporation opening 2032 for alignment, the absolute error between the actual position and the target position of the second alignment mark G2 during alignment is smaller, and the alignment accuracy is greater than the alignment accuracy of the evaporation opening 2032. Therefore, using the first opening K1 of the second alignment mark G2 for alignment can improve the alignment accuracy of the mother board 100m.

[0099] In some embodiments, the plurality of first alignment marks G1 at least includes a first sub-alignment mark and a second sub-alignment mark, and the plurality of second alignment marks at least includes a third sub-alignment mark corresponding to the first sub-alignment mark and a fourth sub-alignment mark corresponding to the second sub-alignment mark.

[0100] The shape of the first pattern corresponding to the first sub-alignment mark is different from the shape of the first pattern corresponding to the second sub-alignment mark, and the shape of the orthographic projection of the first opening corresponding to the third sub-alignment mark on the bearing surface is different from the shape of the orthographic projection of the first opening corresponding to the fourth sub-alignment mark on the bearing surface. The shape of the first sub-alignment mark in the first alignment mark G1 can be the same as the shape of the third sub-alignment mark or the fourth sub-alignment mark, and the shape of the second sub-alignment mark can be the same as the shape of the third sub-alignment mark or the fourth sub-alignment mark. That is, the shape of the first alignment mark G1 has at least two kinds, and the shape of the second alignment mark G2 has at least two kinds. In the matching alignment process, the plurality of sub-alignment marks of different shapes of the mother board 100m are respectively aligned with the plurality of sub-alignment marks of different shapes of the shielding mask plate 203, and the alignment positions are different, which can improve the alignment accuracy and reduce the alignment error.

[0101] In some embodiments, the plurality of first alignment marks include at least a first sub-alignment mark and a second sub-alignment mark, and the plurality of second alignment marks include at least a third sub-alignment mark corresponding to the first sub-alignment mark and a fourth sub-alignment mark corresponding to the second sub-alignment mark.

[0102] The width of the first pattern corresponding to the first sub-alignment mark is smaller than the width of the first pattern corresponding to the second sub-alignment mark. That is, the size of the first sub-alignment mark is different from the size of the second sub-alignment mark. In this way, the first sub-alignment mark and the second sub-alignment mark have different alignment positions during the alignment process, which can improve the alignment accuracy and reduce the alignment error.

[0103] The width of the orthographic projection of the first opening corresponding to the third sub-alignment mark on the support surface is smaller than the width of the orthographic projection of the first opening corresponding to the fourth sub-alignment mark on the support surface. In other words, the size of the third sub-alignment mark is different from the size of the fourth sub-alignment mark. As a result, the third sub-alignment mark and the fourth sub-alignment mark are aligned at different positions during the alignment process, which can improve alignment accuracy and reduce alignment errors.

[0104] In some embodiments, see Figure 9 The number of the multiple first alignment marks G1, the multiple second alignment marks G2, the multiple first corner areas Q1, and the multiple second corner areas Q2 is four each. The first alignment marks G1 are located in corresponding first corner areas Q1, and the second alignment marks G2 are located in corresponding second corner areas Q2. During the alignment process, the first corner areas Q1 and the second corner areas Q2 are aligned one by one, and the first alignment marks G1 and the second alignment marks G2 are aligned one by one. As a result, the first alignment marks G1 are located in the four first corner areas Q1, and the lines connecting the first alignment marks G1 cover the entire motherboard 100m. The second alignment marks G2 are located in the four second corner areas Q2, and the lines connecting the second alignment marks G2 cover the entire shielding mask 203. The first alignment marks G1 and the second alignment marks G2 can expand the alignment range, enabling high-precision positioning within a wider area of ​​the motherboard 100m and the shielding mask 203, reducing alignment errors caused by occlusion or environmental interference, and improving alignment stability and reliability.

[0105] In some embodiments, the first pattern is at least one of a cross, a tic-tac-toe, and a rectangle, and the shape of the orthographic projection of the first opening corresponding to the first pattern on the bearing surface is at least one of a cross, a tic-tac-toe, and a rectangle. The shapes of the orthographic projections of the first pattern and the first opening on the bearing surface may be the same or different. Exemplarily, the first pattern is a cross, and the shape of the orthographic projection of the first opening on the bearing surface may also be a cross. When a specific position on the cross of the first pattern is aligned with a specific position on the cross of the first opening, it indicates that the first alignment mark G1 and the second alignment mark G2 are aligned. Another exemplary embodiment is that the first pattern is a cross, and the shape of the orthographic projection of the first opening on the bearing surface may be a rectangle. When a specific position on the cross of the first pattern is aligned with a specific position on the rectangle of the first opening, it indicates that the first alignment mark G1 and the second alignment mark G2 are aligned.

[0106] In some embodiments, the number of the plurality of first alignment marks G1 is less than the number of the plurality of second alignment marks G2. In other words, the number of alignment marks on the motherboard 100m is less than the number of alignment marks on the mask 203. The plurality of first alignment marks G1 includes at least one fifth sub-alignment mark, and the plurality of second alignment marks G2 includes at least a plurality of sixth sub-alignment marks corresponding to the fifth sub-alignment mark.

[0107] The fifth sub-alignment mark has a second pattern, and the sixth sub-alignment mark has a second opening that matches the second pattern. After the fifth sub-alignment mark and the sixth sub-alignment mark are aligned, portions of the second pattern are exposed through the multiple second openings. One fifth sub-alignment mark corresponds to multiple sixth sub-alignment marks, and one fifth sub-alignment mark is aligned with at least two sixth sub-alignment marks. In other words, one first alignment mark G1 is aligned with at least two second alignment marks G2. One alignment mark on the motherboard 100m is positioned using the multiple alignment marks on the shielding mask 203, further improving the alignment accuracy between the motherboard 100m and the shielding mask 203. During the evaporation process, the spray range of the evaporation material is more precise, and the position of the film pattern on the motherboard 100m is more accurate, further improving the display quality of the display panel.

[0108] In some embodiments, after the fifth sub-alignment mark is aligned with the sixth sub-alignment mark, the orthographic projection of the second pattern on the support surface is greater than the total area of ​​the shape enclosed by the orthographic projections of the outer edges of the plurality of second openings on the support surface. The fifth sub-alignment mark can overlap one second opening, and using at least two second openings to position the fifth sub-alignment mark can improve alignment accuracy.

[0109] In some examples, when forming each sub-pixel of each color on the motherboard 100m, a light-emitting layer of the corresponding color is formed by evaporating and encapsulating the corresponding pixel opening, removing the sub-pixels of that color (VEE yellow light) formed at the pixel openings of other colors, and then performing dry etching (DE), wet etching (WE), and removing the photoresist. Then, the test terminal 1021 of the blank portion 102 is electrically connected to the panel portion 101, and a cathode bonding impedance test is performed to confirm whether the second electrode of the light-emitting device and the isolation structure are bonded. To protect the test terminal 1021 from damage by DE and WE, a photoresist (PR) layer covers the test terminal 1021 of the motherboard 100m. Before the bonding impedance test, the photoresist layer is removed to expose the test terminal 1021 for testing.

[0110] If the overlap impedance test passes, it indicates that the second electrode of the light-emitting device overlaps the isolation structure. If the overlap impedance test fails, a new photoresist layer must be formed to cover test terminal 1021. The evaporation parameters (e.g., evaporation angle) in the evaporation device must be changed before the evaporation process is repeated. The photoresist layer covering test terminal 1021 is then removed and the overlap impedance test is repeated. This process is repeated until the test passes. This process of forming and removing the photoresist layer requires a longer overlap impedance test, extending the evaporation cycle, and thus the display panel production cycle and reducing production efficiency.

[0111] In order to solve the above problems, in some embodiments, see Figure 7 and Figure 9 After at least one second alignment mark G2 is aligned with at least one first alignment mark G1, the main body 2031 separates the multiple test terminals 2021 from the multiple evaporation sources 201. The main body 2031 is located between the test terminals 2021 and the evaporation sources 201. It can block the evaporation material within the evaporation sources 201 from being sprayed onto the test terminals 2021. During processes such as VEE yellow light, dry etching (DE), wet etching (WE), and photoresist removal, the test terminals 1021 no longer need to be covered with a photoresist layer and are directly protected by the shielding mask 203 to prevent damage to the DE and WE layers. Prior to performing a cathode bonding impedance test, there is no need to remove the photoresist layer. After the evaporation process, the cathode bonding impedance test can be performed directly. This reduces the time required to confirm the evaporation effect, increases the efficiency of changing evaporation process parameters, and facilitates the introduction of optimized conditions, shortening the evaporation cycle and improving production efficiency.

[0112] In some examples, after the overlap impedance test is completed, it is necessary to ship to the OLED factory for LOI testing to confirm the luminous effect of the sub-pixels of the same color. In order to protect the test device 1022 from being damaged by DE and WE, the photoresist (PR) layer covers the test device 1022 of the motherboard 100m. Before the LOI test, the photoresist layer needs to be removed to expose the test device 1022 for testing. If the LOI test passes, it means that the sub-pixels of the same color emit light well. If the LOI test fails, it is necessary to re-form the photoresist layer to cover the test device 1022, change the evaporation parameters in the evaporation process, etc., and re-perform the LOI test. Repeat the above steps until the test passes. The evaluation cycle of a color evaporation is as short as 3-4 days and as long as 6-8 days. If the test result fails, re-evaporation will delay a lot of time, which will also affect the preparation cycle of the display panel.

[0113] In order to solve the above problems, in some embodiments, see Figure 7 and Figure 9 After at least one second alignment mark G2 is aligned with at least one first alignment mark G1, the main body 2031 separates the multiple test devices 2022 from the multiple evaporation sources 201. The main body 2031 is located between the test devices 2022 and the evaporation sources 201. The main body 2031 can block the evaporation material in the evaporation sources 201 from being sprayed onto the test devices 2022. During the LOI test, the test devices 2022 no longer need to be covered with a photoresist layer and are directly protected by the shielding mask 203. Before performing the LOI test, there is no need to remove the photoresist layer from the test devices 2022. After the evaporation process, the LOI test can be performed directly. This shortens the time required to confirm the evaporation effect, increases the efficiency of changing evaporation process parameters, and quickly optimizes the conditions, shortening the evaporation cycle and improving production efficiency.

[0114] In some embodiments, see Figure 9 After the at least one second alignment mark G2 is aligned with the at least one first alignment mark G1, the orthographic projection of the main body 2031 on the carrying surface 2021 covers the orthographic projections of the multiple test terminals 1021 on the carrying surface 2021, and the orthographic projection of the main body 2031 on the carrying surface 2021 covers the orthographic projections of the multiple test devices 2022 on the carrying surface 2021. The main body 2031 completely covers the test terminals 1021 and the test devices 2022, shielding them between the evaporation source 201 and the motherboard 100m. This prevents the evaporation source 201 from directly facing the motherboard 100m, which could damage the test terminals 1021 and the test devices 2022 during the evaporation process and reduce testing efficiency.

[0115] In some embodiments, see Figure 8The width of the main body 2031 located between the plurality of evaporation openings 2032 is smaller than the width of the main body 2031 located beside the plurality of evaporation openings 2032. The first alignment mark G1 is located on the main body 2031 beside the plurality of evaporation openings 2032. The wider width of the main body 2031 facilitates the formation of the first alignment mark G1 and prevents a larger first alignment mark G1 from entering the evaporation openings 2032 and affecting the evaporation process.

[0116] An embodiment of the present application further provides a method for preparing a display panel, wherein a shielding mask is added to an evaporation device for preparing the display panel.

[0117] Figure 10 The flowchart of a method for manufacturing a display panel provided in an embodiment of the present application is shown below.

[0118] See also Figure 10 The above-mentioned method for preparing the display panel includes: S1-S3.

[0119] S1. Move the motherboard 100m of the display panel onto the carrying surface 2021 of the carrying platform 202 of the evaporation device 100 as described in any of the above embodiments. The structure of the motherboard 100m can be found in the above description and will not be repeated here.

[0120] S2. Continue to see Figure 7 and Figure 9 The shielding mask 203 is moved to align the at least one second alignment mark G2 with the at least one first alignment mark G1, so that the panel portion 101 is exposed through the corresponding evaporation opening 2032 and at least partially faces the multiple evaporation sources 201. The structure of the shielding mask 203 can be found in the above description and will not be repeated here.

[0121] S3 . Using the evaporation material ejected from the plurality of evaporation sources 201 , evaporation is performed on the plurality of panel portions 101 of the motherboard 100 m .

[0122] The embodiment of the present application utilizes the first alignment mark G1 of the motherboard 100m and the second alignment mark G2 of the shielding mask 203 to align the motherboard 100m with the shielding mask 203, so that the evaporation material can be accurately sprayed on the corresponding position of the panel portion 101 to form the corresponding film layer pattern of the display panel, thereby improving the evaporation accuracy and thereby improving the display effect of the display panel.

[0123] In some embodiments, during the step of performing vapor deposition on the plurality of panel portions 101 of the motherboard 100m, the main body portion 2031 separates the plurality of test terminals 1021 from the plurality of vapor deposition sources 201, and the main body portion 2031 separates the plurality of test devices 1022 from the plurality of vapor deposition sources 201. In this way, the shielding mask 203 protects the test terminals 1021 and the test devices 1022.

[0124] After the step of performing evaporation deposition on the plurality of panel portions 101 of the motherboard 100m, the method for preparing a display panel further includes:

[0125] S4 (optional): perform a lighting test on the corresponding panel unit 101 using the test terminal 1021 .

[0126] The test terminal 1021 is electrically connected to the corresponding panel portion 101 , and a lighting test is performed directly after the vapor deposition process.

[0127] S5 (optional): perform a cathode bonding impedance test on the corresponding panel portion 101 using the test device 1022 .

[0128] The test device 1022 is positioned adjacent to the corresponding panel portion 101 and includes a dummy pixel circuit, a dummy isolation structure, and a dummy first electrode. The dummy isolation structure forms an isolation opening, with a portion of the dummy first electrode exposed through the isolation opening and electrically connected to the dummy pixel circuit. After the evaporation process, the cathode bonding impedance test is performed directly.

[0129] In some implementations, the cathode bonding impedance test may be performed on the corresponding panel portion 101 using the test device 1022 first, and then the lighting test may be performed on the corresponding panel portion 101 using the test terminal 1021 .

[0130] In some embodiments, the method for preparing a display panel further includes:

[0131] S6. Cutting is performed in the blank portion 102 to separate the plurality of panel portions 101 after evaporation to obtain a plurality of display panels 100. The display panel 100 includes corresponding panel portions 101 after evaporation. The structure of the display panel 100 can be found in the above description and will not be repeated here.

[0132] In the process of separating the plurality of panel portions 101 after vapor deposition, the test terminals 1021 are separated from the corresponding panel portions 101 after vapor deposition, and the test devices 1022 are separated from the corresponding panel portions 101 after vapor deposition.

[0133] The display panel provided in the embodiment of the present application is manufactured using the method described in any of the above embodiments. The structure of the display panel can refer to the description of the display panel above and will not be repeated here.

[0134] The above implementation methods are only used to illustrate the embodiments of the present application, and are not intended to limit the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. A vapor deposition device, characterized in that: A motherboard for evaporating a display panel, the motherboard comprising a blank portion and a plurality of panel portions, at least two adjacent panel portions being separated by the blank portion, the blank portion being provided with a plurality of first alignment marks and a plurality of test terminals, the test terminals being electrically connected to the corresponding panel portions, the plurality of first alignment marks including at least one fifth sub-alignment mark, the fifth sub-alignment mark having a second pattern, the evaporation device comprising: Multiple evaporation sources; a carrier, having a carrying surface facing the plurality of evaporation sources, the carrying surface being used to carry the motherboard; a shielding mask, located between the carrying surface and the plurality of evaporation sources, comprising a main body and a plurality of evaporation openings enclosed by the main body, the main body being provided with a plurality of second alignment marks corresponding to at least one first alignment mark, the number of the plurality of first alignment marks being less than the number of the plurality of second alignment marks, the plurality of second alignment marks at least including a plurality of sixth sub-alignment marks corresponding to the fifth sub-alignment mark, the sixth sub-alignment mark having a second opening matched with the second pattern; Wherein, after the plurality of second alignment marks are aligned with the plurality of first alignment marks: The panel portion is exposed from the corresponding evaporation opening and is at least partially opposite to the plurality of evaporation sources, so that the evaporation materials in the plurality of evaporation sources are sprayed onto the panel portion during the evaporation process; The second opening is provided near at least one of the plurality of test terminals, portions of the second pattern are exposed from the plurality of second openings, and an orthographic projection area of ​​the second pattern on the carrying surface is larger than a total area of ​​a shape enclosed by orthographic projections of outer edges of the plurality of second openings on the carrying surface; and The main body separates the plurality of test terminals from the plurality of evaporation sources to block the evaporation material from being sprayed onto the test terminals, so that the test terminals are exposed after the evaporation process is completed and before the yellow light process begins.

2. The evaporation device according to claim 1, characterized in that The blank portion includes a plurality of first corner areas, and the plurality of first alignment marks are respectively provided in the plurality of first corner areas; The main body includes a plurality of second corner areas corresponding to the plurality of first corner areas, and the plurality of second alignment marks are respectively arranged in the plurality of second corner areas corresponding to the plurality of first alignment marks.

3. The evaporation device according to claim 2, characterized in that After the plurality of second alignment marks are aligned with the plurality of first alignment marks, a first shape formed by orthographic projections of outer edges of the first alignment marks on the carrying surface has a first area, a second shape formed by orthographic projections of outer edges of the second alignment marks on the carrying surface has a second area, and an orthographic projection of the panel portion on the carrying surface has a third area, wherein: The first area is smaller than the third area, the second area is smaller than the third area, and the first area is smaller than the second area.

4. The evaporation device according to claim 2, wherein The number of the multiple first alignment marks and the multiple second alignment marks is equal, the first alignment marks have a first pattern, and the second alignment marks have a first opening that matches the first pattern of the corresponding first alignment mark. After the at least one second alignment mark is aligned with the at least one first alignment mark, the first pattern is exposed from the corresponding first opening.

5. The evaporation device according to claim 4, characterized in that An orthographic projection area of ​​the first opening on the carrying surface is smaller than an orthographic projection area of ​​the evaporation opening on the carrying surface.

6. The evaporation device according to claim 4, characterized in that The plurality of first alignment marks include at least a first sub-alignment mark and a second sub-alignment mark, and the plurality of second alignment marks include at least a third sub-alignment mark corresponding to the first sub-alignment mark and a fourth sub-alignment mark corresponding to the second sub-alignment mark, wherein: A shape of the first pattern corresponding to the first sub-alignment mark is different from a shape of the first pattern corresponding to the second sub-alignment mark; A shape of an orthographic projection of the first opening corresponding to the third sub-alignment mark on the carrying surface is different from a shape of an orthographic projection of the first opening corresponding to the fourth sub-alignment mark on the carrying surface.

7. The evaporation device according to claim 4, characterized in that The plurality of first alignment marks include at least a first sub-alignment mark and a second sub-alignment mark, and the plurality of second alignment marks include at least a third sub-alignment mark corresponding to the first sub-alignment mark and a fourth sub-alignment mark corresponding to the second sub-alignment mark, wherein: A width of the first pattern corresponding to the first sub-alignment mark is smaller than a width of the first pattern corresponding to the second sub-alignment mark; A width of an orthographic projection of the first opening corresponding to the third sub-alignment mark on the carrying surface is smaller than a width of an orthographic projection of the first opening corresponding to the fourth sub-alignment mark on the carrying surface.

8. The vapor deposition device according to claim 4, wherein The number of the multiple first alignment marks, the multiple second alignment marks, the multiple first corner areas and the multiple second corner areas are all 4, the first alignment marks are set in the corresponding first corner areas, and the second alignment marks are set in the corresponding second corner areas.

9. The evaporation device according to claim 4, characterized in that The first pattern is at least one of a cross, a tic-tac-toe, and a rectangle, and the orthographic projection of the first opening corresponding to the first pattern on the bearing surface is in the shape of at least one of a cross, a tic-tac-toe, and a rectangle.

10. The vapor deposition device according to claim 1, wherein The blank portion is provided with a plurality of test devices, which are arranged beside the corresponding panel portion and include a dummy pixel circuit, a dummy isolation structure, and a dummy first electrode. The dummy isolation structure encloses an isolation opening, and a portion of the dummy first electrode is exposed from the isolation opening and is electrically connected to the dummy pixel circuit, wherein: After the at least one second alignment mark is aligned with the at least one first alignment mark, the main body separates the plurality of test devices from the plurality of evaporation sources.

11. The evaporation device according to claim 10, wherein: After the at least one second alignment mark is aligned with the at least one first alignment mark, the orthographic projection of the main body on the carrying surface covers the orthographic projection of the multiple test terminals on the carrying surface, and the orthographic projection of the main body on the carrying surface covers the orthographic projection of the multiple test devices on the carrying surface.

12. The evaporation device according to claim 1, wherein The width of the main body portion located between the plurality of vapor deposition openings is smaller than the width of the main body portion located beside the plurality of vapor deposition openings.

13. A method for preparing a display panel, characterized in that: The method comprises: Moving a motherboard of a display panel onto the carrying surface of the carrier of the evaporation device according to any one of claims 1 to 12, wherein the motherboard comprises a blank portion and a plurality of panel portions, at least two adjacent panel portions are separated by the blank portion, and the blank portion is provided with at least one first alignment mark; Moving the shielding mask to align the at least one second alignment mark with the at least one first alignment mark so that the panel portion is exposed from the corresponding evaporation opening and faces at least part of the plurality of evaporation sources; The plurality of panel portions of the motherboard are subjected to vapor deposition using the vapor deposition material ejected from the plurality of vapor deposition sources.

14. The method according to claim 13, wherein: The blank portion is provided with a plurality of test terminals and a plurality of test devices, the test terminals being electrically connected to the corresponding panel portion, the test device being provided beside the corresponding panel portion and comprising a dummy pixel circuit, a dummy isolation structure, and a dummy first electrode, the dummy isolation structure enclosing an isolation opening, a portion of the dummy first electrode being exposed from the isolation opening and electrically connected to the dummy pixel circuit; In the step of performing evaporation deposition on the plurality of panel portions of the motherboard, the main body separates the plurality of test terminals from the plurality of evaporation sources, and the main body separates the plurality of test devices from the plurality of evaporation sources; After the step of performing evaporation deposition on the plurality of panel portions of the motherboard, the method further includes: Performing a lighting test on the corresponding panel portion using the test terminal; and, The cathode bonding impedance test is performed on the corresponding panel portion using the test device.

15. The method according to claim 14, characterized in that The method further comprises: Cutting the blank portion to separate the plurality of panel portions after vapor deposition from each other to obtain a plurality of display panels, each of which includes the corresponding panel portions after vapor deposition; In the process of separating the plurality of panel portions after vapor deposition, the test terminals are separated from the corresponding panel portions after vapor deposition, and the test devices are separated from the corresponding panel portions after vapor deposition.

16. A display panel, characterized in that: Prepared by the method according to any one of claims 13 to 15.

17. The display panel according to claim 16, wherein: The display panel includes: substrate; An isolation structure is located on one side of the substrate, and the isolation structure encloses a plurality of isolation openings; A plurality of light-emitting devices, parts of the light-emitting devices are located in the corresponding isolation openings, the light-emitting devices include a first electrode, a light-emitting functional layer and a second electrode arranged in sequence in a direction away from the substrate, and the second electrode is overlapped with the isolation structure.

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