Mask plate assembly for manufacturing alignment mark and manufacturing method of alignment mark
By designing mask components for lithography processes, using similar graphic dislocation arrangements on the mask units, the problem of poor signal caused by over-grinding of traditional alignment marks is solved, and the high recognition rate of alignment marks and the improvement of substrate sheet yield is achieved.
Patent Information
- Application Number
- CN202311698081.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-11
- Publication Date
- 2025-06-13
AI Technical Summary
In traditional lithography processes, the alignment mark of the substrate sheet is poor in the subsequent process due to overgrinding, causing the exposure machine to withdraw the film, which in turn leads to the scrapping of the substrate sheet, affecting the yield.
A mask assembly for making alignment marks is designed, including a plurality of mask units, alternately arranged lithographic pattern areas and etched pattern areas, and reduce the groove size on the alignment marks of the final support by similar graphic dislocation arrangements on adjacent mask units.
By reducing the trench size on the alignment mark, the possibility of excessive wear is reduced, the probability of alignment marks is improved, the probability of scrapping of the substrate sheet is reduced, and the yield of the substrate sheet is improved.
Smart Images
Figure CN120143542A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of lithography technology, and more particularly, to a mask plate assembly for manufacturing alignment marks and a method for manufacturing alignment marks. Background Art
[0002] When performing a lithography process, generally, alignment marks are recognized to enable the patterns on the current mask plate to be aligned with the patterns on the underlying film layer. Therefore, the alignment marks will directly affect the alignment deviation between each film layer in the lithography process. In the manufacturing process of semiconductor wafers, in the traditional process, the tungsten (W) of the alignment marks on the wafer is over-polished, causing the alignment marks to be recessed. This will result in poor signal during wafer alignment in subsequent processes, causing the exposure machine to reject the wafer, and ultimately scrapping the wafer. Therefore, it is necessary to fabricate a new alignment mark to improve the recognition rate of the alignment mark. Summary of the Invention
[0003] The purpose of the present disclosure is to provide a mask plate assembly for manufacturing alignment marks and a method for manufacturing alignment marks, so as to improve the recognition rate of the alignment marks, thereby improving the yield of wafers.
[0004] To achieve the above object, the present disclosure provides a mask plate assembly for manufacturing alignment marks, including a plurality of mask plate units. A plurality of lithography pattern areas and a plurality of etching pattern areas are alternately arranged on the mask plate units, and the mask plate assembly is arranged such that when a plurality of mask plate units are stacked, the lithography pattern area of one mask plate unit is located in the etching pattern area of an adjacent mask plate unit.
[0005] Optionally, both the lithography pattern area and the etching pattern area are in a strip-like structure.
[0006] Optionally, the etching pattern area includes a first etching pattern area disposed between two adjacent lithography pattern areas and a second etching pattern area selectively disposed at the edge of the mask plate unit, wherein the area of the second etching pattern area is not greater than the area of the first etching pattern area.
[0007] Optionally, the number of mask plate units is n, where 2 ≤ n ≤ 4, and the width of a single first etching pattern area is 2n - 1 times the width of a single lithography pattern area.
[0008] Optionally, the lithography pattern area and the etching pattern area extend in the same direction.
[0009] Optionally, when a plurality of mask plate units are stacked, all the lithography pattern areas are arranged at intervals along the arrangement direction of the lithography pattern areas.
[0010] Optionally, the dimension of the mask template unit in the width direction is 8 μm, and the lithography pattern regions and the etching pattern regions are arranged alternately along the width direction of the mask template unit.
[0011] According to still another aspect of the present disclosure, there is provided a method for manufacturing an alignment mark. The manufacturing method uses the above-mentioned mask template assembly for manufacturing an alignment mark, and the manufacturing method includes:
[0012] Coating a photoresist on a substrate wafer to form a photoresist layer;
[0013] Placing a mask template unit above the photoresist layer, and etching the lithography pattern region to corresponding positions on the photoresist layer and the substrate wafer;
[0014] Etching the substrate wafer between two adjacent lithography pattern regions; and
[0015] Replacing the mask template unit, and repeating the above steps.
[0016] Optionally, in the step of placing a mask template unit above the photoresist layer and etching the lithography pattern region to corresponding positions on the photoresist layer and the substrate wafer, the manufacturing method further includes:
[0017] While etching the lithography pattern region to the photoresist layer, exposing and developing the photoresist between two adjacent lithography pattern regions on the photoresist layer.
[0018] Optionally, before the step of coating a photoresist on a substrate wafer to form a photoresist layer, the manufacturing method includes:
[0019] Coating an anti-reflection material on the substrate wafer to form an anti-reflection coating.
[0020] Through the above technical solution, by arranging the same type of patterns on adjacent mask template units in a staggered manner, the size of the grooves on the alignment mark of the final support is reduced, thereby reducing the possibility of excessive wear caused by too large a size of the grooves, improving the recognition probability of the alignment mark, reducing the scrap probability of the substrate wafer, and improving the production yield of the substrate wafer.
[0021] Other features and advantages of the present disclosure will be described in detail in the subsequent specific implementation section. Brief Description of the Drawings
[0022] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following specific implementation, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:
[0023] Figure 1Schematic diagram of a mask unit in a mask assembly according to an embodiment of the present disclosure.
[0024] Figure 2 Schematic diagram of a mask unit in a mask assembly according to another embodiment of the present disclosure.
[0025] Figure 3 Schematic diagram of an alignment mark fabricated according to a method for fabricating an alignment mark according to an embodiment of the present disclosure.
[0026] Figure 4 Schematic diagram after the first coating of photoresist on a substrate wafer in a method for fabricating an alignment mark according to an embodiment of the present disclosure.
[0027] Figure 5 Schematic diagram after the first exposure and development of photoresist on a substrate wafer in a method for fabricating an alignment mark according to an embodiment of the present disclosure.
[0028] Figure 6 Schematic diagram after the first etching of the substrate wafer in a method for fabricating an alignment mark according to an embodiment of the present disclosure.
[0029] Figure 7 Schematic diagram after the second exposure and development of photoresist on a substrate wafer in a method for fabricating an alignment mark according to an embodiment of the present disclosure.
[0030] Figure 8 Schematic diagram after the second etching of the substrate wafer in a method for fabricating an alignment mark according to an embodiment of the present disclosure.
[0031] Figure 9 Flowchart of a method for fabricating an alignment mark according to an embodiment of the present disclosure.
[0032] Figure 10 Flowchart of a method for fabricating an alignment mark according to another embodiment of the present disclosure.
[0033] Description of reference numerals
[0034] 1 - Mask unit; 11 - Lithography pattern area; 12 - Etching pattern area; 121 - First etching pattern area; 122 - Second etching pattern area; 2 - Substrate wafer; 3 - Photoresist layer; 4 - Anti - reflection coating; 5 - Groove; 51 - First groove; 52 - Second groove. Detailed description of specific embodiments
[0035] The following provides a detailed description of the specific embodiments of the present disclosure with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustrating and explaining the present disclosure, and are not intended to limit the present disclosure.
[0036] In this disclosure, unless otherwise stated, the orientation terms such as "inner" and "outer" are defined with respect to the contour of the corresponding component. The terms "first", "second", etc. are used to distinguish different components and do not have an order or importance. In addition, in the following description, when referring to the drawings, unless otherwise explained, the same reference numerals in different drawings represent the same or similar elements.
[0037] According to an embodiment of the present disclosure, as Figures 1 to 8 shown, a mask plate assembly for manufacturing alignment marks may be provided, which may include a plurality of mask plate units 1. A plurality of lithography pattern areas 11 and a plurality of etching pattern areas 12 are alternately arranged on the mask plate unit 1, and the mask plate assembly may be arranged such that when the plurality of mask plate units 1 are stacked, the lithography pattern area 11 of one mask plate unit 1 is located in the etching pattern area 12 of an adjacent mask plate unit.
[0038] Through the above technical solution, by arranging the same type of patterns on adjacent mask plate units 1 in a staggered manner, the size of the groove 52 on the alignment mark of the final support is reduced, thereby reducing the possibility of excessive wear caused by the too large size of the groove 52, improving the recognition probability of the alignment mark, reducing the scrap probability of the substrate wafer 2, and improving the production yield of the substrate wafer.
[0039] It should be noted that the dimension of the mask plate unit 1 in the width direction may be 8 μm, or may be other dimensions such as 14 μm, 64 μm, etc. The present disclosure does not limit this. In addition, the lithography pattern area 11 and the etching pattern area 12 may also be alternately arranged along the width direction of the mask plate unit 1 to coincide with the recognition direction of the alignment mark, thereby improving the recognition probability of the alignment mark.
[0040] Furthermore, as Figures 1 to 3 shown, both the lithography pattern area 11 and the etching pattern area 12 may be in a long strip structure. The long strip structure is easier to be recognized compared with circular, elliptical, and dot-like structures, etc., so as to reduce the film ejection of the exposure machine caused by poor recognition of the alignment mark and improve the yield of the substrate wafer 2. It should be noted that in this arrangement, the extending directions of the lithography pattern area 11 and the etching pattern area 12 may be the same. In this way, the lithography pattern area 11 and the etching pattern area 12 can be arranged alternately without gaps. In this way, when the plurality of mask plate units 1 are stacked, while ensuring that there is no overlap of the lithography pattern area 11 mentioned below, the number of the lithography pattern areas 11 can be made larger, so that the number of grooves 52 of the finally manufactured alignment mark is more and the width is smaller, reducing the possibility of its over-grinding and improving the recognition probability of the alignment mark.
[0041] Furthermore, as Figure 1 and Figure 2As shown, the etched pattern area 12 can include a first etched pattern area 121 disposed between two adjacent lithographic pattern areas 11 and a second etched pattern area 122 selectively disposed at the edge of the mask unit 1, wherein the area of the second etched pattern area 122 is not greater than the area of the first etched pattern area 121. The reduction in the area of the second etched pattern area 122 is to cooperate with the lithographic pattern area 11 in the adjacent mask unit 1 while keeping the sizes of the mask units 1 equal. In this way, when performing multiple lithography processes, different mask units 1 can be placed at the same position for exposure without additional position adjustment.
[0042] Furthermore, the number of mask units 1 can be n, where 2 ≤ n ≤ 4, and the width of a single first etched pattern area 121 is 2 n -1 times the width of a single lithographic pattern area 11. That is, when the number of mask units 1 is 2, the width of a single first etched pattern area 121 is 3 times the width of a single lithographic pattern area 11; when the number of mask units 1 is 3, the width of a single first etched pattern area 121 is 7 times the width of a single lithographic pattern area 11; when the number of mask units 1 is 4, the width of a single first etched pattern area 121 is 15 times the width of a single lithographic pattern area 11. This can ensure that when all the mask units 1 are stacked, the lithographic pattern areas 11 of all the mask units 1 do not overlap and are in a misaligned arrangement. It can also ensure that when using the alignment marks of this mask assembly, the width of each trench 52 is equal to the gap between two adjacent trenches 52, so as to increase the recognition probability of the alignment marks.
[0043] According to an embodiment of the present disclosure, as Figures 1 to 3 shown, the lithographic pattern areas 11 and the etched pattern areas 12 of all the mask units 1 can be misaligned. In this way, when multiple mask units 1 are stacked, all the lithographic pattern areas 11 are arranged at intervals along the arrangement direction of the lithographic pattern areas 11. This can make the number of trenches 5 of the finally fabricated alignment marks more, and the width dimension of each trench 5 smaller. The smaller the width dimension of the trench 5, the smaller the possibility of overgrinding. Therefore, arranging all the lithographic pattern areas 11 at intervals along the arrangement direction of the lithographic pattern areas 11 can effectively increase the probability of successful recognition of the alignment marks, thereby improving the yield of the substrate wafer.
[0044] According to another aspect of the present disclosure, as Figures 3 to 9As shown, a method for fabricating alignment marks is provided. The fabrication method can use the above-mentioned mask plate assembly for fabricating alignment marks. The fabrication method can include step 901. First, a photoresist is coated on the substrate wafer 2 to form a photoresist layer 3. After the coating of the photoresist layer 3 is completed, step 902 is then performed. A mask plate unit 1 is placed above the photoresist layer 3, and the lithography pattern area 11 is etched onto the corresponding positions of the photoresist layer 3 and the substrate wafer 2. After the pattern of the lithography pattern area 11 is etched onto the photoresist layer 3, step 903 can be performed, that is, the substrate wafer 2 between two adjacent lithography pattern areas 11 is etched. After the etching, step 904 is performed, that is, the mask plate unit 1 is replaced. After the replacement, the above steps are repeatedly executed until the patterns on the lithography pattern areas 11 on the mask plate units 1 in the mask plate assembly are all etched onto the substrate wafer 2, and the gaps between the lithography pattern areas 11 on the substrate wafer 2 are all etched. After the pattern on each lithography pattern area 11 on a mask plate unit 1 is etched, an etching step needs to be performed in sequence. That is to say, when using the mask plate assembly in the present disclosure to fabricate alignment marks, the steps of lithography (referring to the step of etching the lithography pattern area 11 onto the photoresist layer 3) - etching - lithography - etching need to be repeatedly performed until each mask plate unit 1 is used. Since the adjacent grooves 52 on the finally fabricated alignment marks come from different mask plate units 1 and their lithography sequences are different, and lithography will cause different degrees of loss of the photoresist layer 3. If the process of first completing the lithography steps of all mask plate units 1 and then performing an etching at the end is used, the loss of the photoresist layer 3 will be gradually superimposed according to the number of lithography times. The loss degree of the photoresist layer 3 will have an impact on the etching depth of the subsequent etching steps, which will result in inconsistent depths of the grooves 52 at different steps, increasing the probability that the alignment marks cannot be recognized. However, alternating the lithography steps and the etching steps can effectively average the loss degree of the photoresist layer 3, so that the depths of different grooves 52 of the finally fabricated alignment marks tend to be consistent, improving the recognition rate of the alignment marks and reducing the scrap probability of the substrate wafer 2.
[0045] Further, as Figure 10 shown, in the step of placing a mask plate unit 1 above the photoresist layer 3 and etching the lithography pattern area 11 onto the corresponding positions of the photoresist layer 3 and the substrate wafer 2, the fabrication method can further include step 1001, that is, when placing a mask plate unit 1 above the photoresist layer 3 and etching the lithography pattern area 11 onto the photoresist layer 3, the photoresist between two adjacent lithography pattern areas 11 on the photoresist layer 3 is exposed and developed. It can also be that the photoresist on the lithography pattern area 11 on the photoresist layer 3 is exposed and developed, and the position on the substrate wafer 2 corresponding to the lithography pattern area 11 is etched. The present disclosure does not make any limitation in this regard.
[0046] According to an embodiment of the present disclosure, as Figure 10As shown, before the step of coating the photoresist on the substrate wafer 2 to form the photoresist layer 3, the manufacturing method includes step 1002 of coating the substrate wafer 2 with an anti-reflection material to form an anti-reflection coating 4. The anti-reflection coating 4 can effectively reduce the degree of light reflection and effectively improve the clarity of the photolithographic pattern area 11 during engraving. The anti-reflection coating 4 can also be coated on the side of the substrate wafer 2 away from the photoresist coating, and the present disclosure does not limit this.
[0047] Taking the mask assembly as an example of two mask units, during manufacturing, it can be as Figure 4 shown. First, coat the photoresist and the anti-reflection material on the substrate wafer 2 to form the photoresist layer 3 and the anti-reflection coating 4. After coating, place the first mask unit 1 above the photoresist layer 3, and while engraving the photolithographic pattern area 11 onto the corresponding positions of the photoresist layer 3 and the substrate wafer 2, as Figure 5 shown, expose and develop the photoresist between two adjacent photolithographic pattern areas 11. After the photoresist is exposed and developed, etch the substrate wafer 2 between two adjacent photolithographic pattern areas 11 and remove the remaining photoresist and anti-reflection material until as Figure 6 shown. At this time, due to the etching of the substrate wafer 2, a plurality of first grooves 51 will be etched at intervals on the substrate wafer 2. After the first grooves 51 are etched on the substrate wafer 2, continue to coat the photoresist and the anti-reflection material to form the photoresist layer 3 and the anti-reflection coating 4. After coating, place the second mask unit 1 above the photoresist layer 3, and while engraving the photolithographic pattern area 11 onto the photoresist layer 3, as Figure 7 shown, expose and develop the photoresist between two adjacent photolithographic pattern areas 11. After the photoresist is exposed and developed, etch the substrate wafer 2 between two adjacent photolithographic pattern areas 11. It should be noted that the two adjacent photolithographic pattern areas 11 here are the pattern areas after the first photolithography and the second photolithography respectively. After etching, remove the remaining photoresist and anti-reflection material until as Figure 8 shown. At this time, due to the etching of the substrate wafer 2, a plurality of second grooves 52 will be etched at intervals on the basis of the first grooves 51 on the substrate wafer 2 to complete the production of the alignment marks.
[0048] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0049] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure does not separately describe various possible combination methods.
[0050] In addition, any combination can be made among various different embodiments of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A mask plate assembly for manufacturing alignment marks, characterized in that, it includes a plurality of mask plate units, on which a plurality of lithography pattern areas and a plurality of etching pattern areas are alternately arranged, and the mask plate assembly is arranged such that when a plurality of mask plate units are stacked, the lithography pattern area of one mask plate unit is located in the etching pattern area of an adjacent mask plate unit.
2. The mask plate assembly for manufacturing alignment marks according to claim 1, characterized in that, both the lithography pattern area and the etching pattern area are in a strip-shaped structure.
3. The mask plate assembly for manufacturing alignment marks according to claim 2, characterized in that, the etching pattern area includes a first etching pattern area disposed between two adjacent lithography pattern areas and a second etching pattern area selectively disposed at the edge of the mask plate unit, wherein the area of the second etching pattern area is not greater than the area of the first etching pattern area.
4. The mask plate assembly for manufacturing alignment marks according to claim 3, characterized in that, The number of the mask pattern units is n, where 2 ≤ n ≤ 4, and the width of a single first etching pattern area is 2 n -1 times the width of a single lithography pattern area.
5. The mask plate assembly for manufacturing alignment marks according to claim 2, characterized in that, the lithography pattern area and the etching pattern area extend in the same direction.
6. The mask plate assembly for manufacturing alignment marks according to claim 1, characterized in that, when a plurality of mask plate units are stacked, all the lithography pattern areas are arranged at intervals along the arrangement direction of the lithography pattern areas.
7. The mask plate assembly for manufacturing alignment marks according to claim 1, characterized in that, the dimension of the mask plate unit in the width direction is 8 μm, and the lithography pattern area and the etching pattern area are alternately arranged along the width direction of the mask plate unit.
8. A method for manufacturing alignment marks, characterized in that, the manufacturing method uses the mask plate assembly for manufacturing alignment marks according to any one of claims 1 - 7, and the manufacturing method includes: coating a photoresist on a substrate wafer to form a photoresist layer; placing a mask plate unit above the photoresist layer, and etching the lithography pattern area to the corresponding positions of the photoresist layer and the substrate wafer; etching the substrate wafer between two adjacent lithography pattern areas; and replacing the mask plate unit and repeating the above steps.
9. The method for manufacturing alignment marks according to claim 8, characterized in that, in the step of placing a mask plate unit above the photoresist layer and etching the lithography pattern area to the corresponding positions of the photoresist layer and the substrate wafer, the manufacturing method further includes: while etching the lithography pattern area to the photoresist layer, exposing and developing the photoresist between two adjacent lithography pattern areas on the photoresist layer.
10. The method for manufacturing alignment marks according to claim 8, characterized in that, before the step of coating a photoresist on a substrate wafer to form a photoresist layer, the manufacturing method includes: coating an anti-reflection material on the substrate wafer to form an anti-reflection coating.