Multi-node server with power consumption adjusting function

Abstract

A multi-node server is mainly characterized in that a power switch generates an output voltage according to a working current, a comparison unit generates a first logic signal according to a first partial voltage and a first reference voltage, the comparison unit generates a second logic signal according to a second partial voltage and the first reference voltage, and the logic unit is electrically connected with the comparison unit. The logic unit is used for receiving the first logic signal, the second logic signal and a setting signal, and the logic unit is used for carrying out logic operation according to the setting signal, the first logic signal and the second logic signal to generate a power control signal; when the output voltage is increased and the first partial voltage is greater than the first reference voltage, the power control signal is used for triggering the chip module to reduce the power consumption so as to reduce the working current.

Description

Technical Field

[0001] The present invention relates to a server technology, and particularly to a multi-node server with a power consumption adjustment function to achieve a current protection function. Background Art

[0002] The existing single-node server uses a baseboard management controller (a professional microcontroller embedded in most Intel server motherboards, hereinafter referred to as BMC). The BMC on the motherboard (hereinafter referred to as MB) communicates with the power supply unit (hereinafter referred to as PSU), and reads relevant information of the PSU through the Power Management Bus (hereinafter referred to as PMBus, a communication line connecting the MB and the PSU). The new Intel CPUs all support Turbo Boost (a technology that increases the CPU frequency when the program's utilization of CPU resources increases to meet the computing power requirements), which improves performance, but at the same time increases the power consumption and temperature of the CPU. Therefore, it is necessary to increase the air volume to reduce the temperature, which further increases the power consumption. Thus, a larger PSU is required to solve these problems. Therefore, Intel proposed a new PSU specification, allowing the BMC on the MB to adjust the over-current protection point of the PSU through the PMBus, to avoid shutdown caused by excessive PSU power consumption due to Turbo Boost. This approach can make the single-node server achieve the best performance without the need for a larger PSU, but this method is not applicable to multi-node servers. Summary of the Invention

[0003] Therefore, an object of the present invention is to provide a multi-node server with a power consumption adjustment function that can overcome the shortcomings of the prior art.

[0004] Thus, the multi-node server includes a power supply unit and multiple node motherboards. The power supply unit is used to provide multiple working currents. The multiple node motherboards are electrically connected to the power supply unit to respectively receive these working currents. Each node motherboard includes a power switch, a protection device, and a chip module. The power switch is electrically connected to the power supply unit and the chip module to receive the corresponding working current, and generates an output voltage according to the working current. The change of the output voltage is positively correlated with the change of the working current, and the power switch transmits the working current to the chip module, so that the change of the working current is positively correlated with the power consumption of the chip module. The protection device has a comparison unit and a logic unit. The comparison unit is electrically connected to the power switch to receive the output voltage, and divides the output voltage to generate a first divided voltage and a second divided voltage. Among them, the value of the first divided voltage is greater than the value of the second divided voltage. The comparison unit generates a first logic signal according to the first divided voltage and a first reference voltage, and the comparison unit generates a second logic signal according to the second divided voltage and the first reference voltage. The logic unit is electrically connected to the comparison unit to receive the first logic signal, the second logic signal, and a setting signal. And the logic unit performs a logic operation according to the setting signal, the first logic signal, and the second logic signal to generate a power control signal. The power control signal switches between a power consumption suppression level and a non-power consumption suppression level. The chip module is electrically connected to the logic unit to receive the power control signal. When the working current increases as the power consumption of the chip module rises, causing the output voltage to increase so that the first divided voltage is greater than the first reference voltage, the power control signal is at the power consumption suppression level to trigger the chip module to reduce power consumption, so as to reduce the working current.

[0005] Specifically, the comparison unit includes a first comparator and a first voltage divider for dividing the output voltage to generate the first divided voltage. The first comparator has a non-inverting input terminal electrically connected to the first voltage divider to receive the first divided voltage, an inverting input terminal receiving the first reference voltage, and an output terminal outputting the first logic signal. When the first divided voltage is greater than the first reference voltage, the first logic signal is logic 1. When the first divided voltage is less than the first reference voltage, the first logic signal is logic 0.

[0006] Specifically, the comparison unit further includes a second comparator and a second voltage divider for dividing the output voltage to generate the second divided voltage. The second comparator has an inverting input terminal electrically connected to the second voltage divider to receive the second divided voltage, a non-inverting input terminal receiving the first reference voltage, and an output terminal outputting the second logic signal. When the second divided voltage is greater than the first reference voltage, the second logic signal is logic 0. When the second divided voltage is less than the first reference voltage, the second logic signal is logic 1.

[0007] In particular, it further includes a power setting unit for generating the setting signal. Among them, the logic unit includes a logic operation circuit electrically connected to the power setting unit to receive the setting signal. The logic operation circuit is electrically connected to the first comparator and the second comparator to respectively receive the first logic signal and the second logic signal, and generates a logic output according to the first logic signal, the second logic signal and the setting signal. Among them, a logic function of the logic operation circuit is: L = H &!(G &!C), where the parameter L is the logic level of the logic output, the parameter G is the logic level of the first logic signal, the parameter C is the logic level of the second logic signal, the definition of the parameter! is inversion, and the definition of the parameter & is AND gate.

[0008] In particular, the logic unit further includes a complex programmable logic device. The complex programmable logic device is electrically connected to the logic operation circuit to receive the logic output, and delays the logic output according to a default time to generate the power control signal. Among them, the logic level of the power control signal is equal to that of the logic output.

[0009] In particular, the chip module includes a buck converter electrically connected to the power switch, a central processing unit electrically connected to the buck converter and the logic unit, and a graphics processing unit electrically connected to the power switch and the logic unit. The buck converter steps down the voltage from the power switch and then supplies it to the central processing unit. The central processing unit and the graphics processing unit receive the power control signal and adjust the power consumption according to the power control signal.

[0010] Another object of the present invention is to provide a multi-node server capable of overcoming the disadvantages of the prior art.

[0011] The multi-node server includes a power supply unit for providing a plurality of working currents and a plurality of node motherboards. The plurality of node motherboards are electrically connected to the power supply unit to respectively receive the working currents. Each node motherboard includes a power switch, a protection device, and a chip module. The power switch is electrically connected to the power supply unit and the chip module to receive the corresponding working current, and the power switch transmits the working current to the chip module, such that the change in the working current is positively correlated with the power consumption of the chip module. The protection device has a detection unit and a judgment unit. The detection unit is electrically connected between the power switch and the chip module to detect the change in the working current to generate a detection voltage proportional to the working current. The judgment unit is electrically connected to the detection unit to receive the detection voltage and receive a setting signal, and generates a selection voltage according to the setting signal and the detection voltage, and compares the selection voltage with a third reference voltage to generate a power control signal. The power control signal switches between a power consumption suppression level and a non-power consumption suppression level. The chip module is electrically connected to the judgment unit to receive the power control signal. When the working current increases as the power consumption of the chip module rises, such that the detection voltage increases and the selection voltage is greater than the third reference voltage, the power control signal is at the power consumption suppression level to trigger the chip module to reduce power consumption to reduce the working current.

[0012] Specifically, the detection unit has a detection resistor and an operational amplifier. The working current flows through both ends of the detection resistor to generate a voltage across, and the operational amplifier is electrically connected to both ends of the detection resistor to receive the voltage across and amplify the voltage across to generate the detection voltage, and the detection voltage is proportional to the voltage across.

[0013] Specifically, it further includes a power setting unit for generating the setting signal. Among them, the judgment unit has a voltage divider selector electrically connected to the power setting unit to receive the setting signal. The voltage divider selector is electrically connected to the operational amplifier to receive the detection voltage, divides the detection voltage to generate a third divided voltage and a fourth divided voltage, and selects one of the third divided voltage and the fourth divided voltage as the selection voltage according to the setting signal.

[0014] Specifically, the judgment unit further has a third comparator and a complex programmable logic device. The third comparator has an inverting input terminal electrically connected to the voltage divider selector to receive the selection voltage, a non-inverting input terminal receiving the third reference voltage, and an output terminal providing a comparison signal. The complex programmable logic device is electrically connected to the third comparator to receive the comparison signal and delays the comparison signal according to a default time to generate the power control signal. Among them, the logic level of the power control signal is the same as that of the comparison signal.

[0015] Compared with the prior art, the multi-node server of the present invention has a power consumption adjustment function, and individual current limiting protection is performed on each node motherboard to protect the system from accidentally triggering overcurrent and causing the entire server to shut down. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein:

[0017] Figure 1 is a system diagram of a first embodiment of the multi-node server with a power consumption adjustment function of the present invention;

[0018] Figure 2 is a timing diagram of the first embodiment;

[0019] Figure 3 is a system diagram of a second embodiment of the multi-node server of the present invention;

[0020] Figure 4 is a timing diagram of the second embodiment;

[0021] Figure 5 is a system diagram of a third embodiment of the multi-node server of the present invention; and

[0022] Figure 6 is a timing diagram of the third embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

[0024] Refer to Figure 1 and Figure 2 , which is a first embodiment of applying the multi-node server with a power consumption adjustment function of the present invention, including a power supply unit 1 and a plurality of node motherboards 2.

[0025] The power supply unit 1 is used to provide a plurality of working currents, and the plurality of node motherboards 2 are electrically connected to the power supply unit 1 to respectively receive these working currents. Each node motherboard 2 includes a power switch 3, a protection device 6, a chip module 5, and a power setting unit 4. The power setting unit 4 is used to generate a setting signal. Among them, the setting signal C is at logic 0 when set to 500W and at logic 1 when set to 600W. The power switch 3 receives a setting signal and is electrically connected to the power supply unit 1 and the chip module 5 to receive the corresponding working current, and generates an output voltage according to the working current. The change of the output voltage is positively correlated with the change of the working current, and the power switch 3 transmits the working current to the chip module 5, so that the change of the working current is positively correlated with the power consumption of the chip module 5. Here, actual data is used for illustration. Refer toFigure 2 , in this embodiment, when the setting signal C is logic 0 and under the condition of normal power consumption (at this time, the upper limit of power consumption allowed according to the setting signal is 500W), the voltage E from the power switch 3 is 12V. When the chip module 5 draws too much working current resulting in an increase in power consumption, the working current will first pass through an internal resistor (not shown in the figure) of the power switch 3 and then be supplied to the chip module 5. Since the increase in current causes the voltage across the internal resistor to rise, that is, the internal resistor consumes part of the voltage, the voltage E supplied to the chip module 5 will drop to 11.6V. An operational amplifier (not shown in the figure) of the power switch 3 will generate an operation result according to the increase in the voltage across the internal resistor. This operation result causes the output voltage D to change from a normal value to increase to 3.58V. The definition of this normal value is 2.15V < normal value < 3.58V. When the setting signal C is logic 1 and under the condition of normal power consumption (at this time, the upper limit of power consumption is 600W), the voltage E from the power switch 3 is 12V. When the chip module 5 draws too much working current resulting in an increase in power consumption, the voltage E will drop to 11.6V. Also, because the upper limit of power consumption setting is increased from 500W to 600W, the change in the output voltage D increases to 4.63V.

[0026] The protection device 6 has a comparison unit 7 and a logic unit 8. The comparison unit 7 is electrically connected to the power switch 3 to receive the output voltage, and divides the output voltage to generate a first divided voltage and a second divided voltage. Among them, the value of the first divided voltage is greater than the value of the second divided voltage. The comparison unit 7 generates a first logic signal according to the first divided voltage and a first reference voltage, and the comparison unit 7 generates a second logic signal according to the second divided voltage and the first reference voltage. The logic unit 8 is electrically connected to the comparison unit 7 to receive the first logic signal, the second logic signal and a setting signal. And the logic unit 8 performs a logic operation according to the setting signal, the first logic signal and the second logic signal to generate a power control signal. The power control signal switches between a power consumption suppression level and a non-power consumption suppression level. In this embodiment, the power consumption suppression level is defined as logic 0, and the non-power consumption suppression level is defined as logic 1. The comparison unit 7 includes a first comparator OP1, a first voltage divider 71 for dividing the output voltage to generate the first divided voltage, a second comparator OP2, and a second voltage divider 72 for dividing the output voltage to generate the second divided voltage. The first comparator OP1 has a non-inverting input terminal (+) electrically connected to the first voltage divider 71 to receive the first divided voltage, an inverting input terminal (−) for receiving the first reference voltage, and an output terminal for outputting the first logic signal. When the first divided voltage is greater than the first reference voltage, the first logic signal is logic 1. When the first divided voltage is less than the first reference voltage, the first logic signal is logic 0. The second comparator OP2 has an inverting input terminal (−) electrically connected to the second voltage divider 72 to receive the second divided voltage, a non-inverting input terminal (+) for receiving the first reference voltage, and an output terminal for outputting the second logic signal. When the second divided voltage is greater than the first reference voltage, the second logic signal is logic 0. When the second divided voltage is less than the first reference voltage, the second logic signal is logic 1. The logic unit 8 includes a logic operation circuit 81 for receiving the setting signal and a complex programmable logic device (abbreviated as CPLD) 82. The logic operation circuit 81 is electrically connected to the first comparator OP1 and the second comparator OP2 to receive the first logic signal and the second logic signal respectively, and generates a logic output according to the first logic signal, the second logic signal and the setting signal. Among them, a logic function of the logic operation circuit 81 is: L = H &!(G &!C), where the parameter L is the logic level of the logic output, the parameter G is the logic level of the first logic signal, the parameter C is the logic level of the second logic signal, the definition of the parameter! is inversion (NOT), and the definition of the parameter & is AND gate. The complex programmable logic device 82 is electrically connected to the logic operation circuit 81 to receive the logic output, and delays the logic output according to a default time to generate the power control signal. Among them, the logic level of the power control signal is the same as that of the logic output. Refer toFigure 2 The first reference voltage is 0.4V. First, look at the first half of the timing diagram. When the set power is 500W, that is, when C = 0 and the output voltage D changes to 3.58V, the first voltage division D1 is 0.431V. Since it is greater than 0.4V, the first logic signal G changes to logic 1. The second voltage division D2 is 0.32V. Since it is less than 0.4V, the second logic signal H remains at logic 1. Since C = 0, G = 1, and H = 0, the power control signal L changes to logic 0 after a delay time. When the set power is 600W, that is, when C = 1 and the output voltage D changes to 4.63V, the first voltage division D1 is 0.557V. Since it is greater than 0.4V, the first logic signal G changes to logic 1. The second voltage division D2 is 0.42V. Since it is greater than 0.4V, the second logic signal H changes to logic 0. Since C = 1, G = 1, and H = 0, the power control signal L changes to logic 0 after a delay of 1 unit of time.

[0027] The chip module 5 is electrically connected to the logic unit 8 to receive the power control signal. When the operating current increases as the power consumption of the chip module 5 rises, causing the output voltage D to increase and the first voltage division to be greater than the first reference voltage, the power control signal is the power consumption suppression level used to trigger the chip module to reduce power consumption, so as to reduce the operating current. The chip module 5 includes a buck converter 51 electrically connected to the power switch 3, a central processing unit (abbreviated as CPU) 52 electrically connected to the buck converter 51 and the logic unit 8, and a graphics processing unit 53 electrically connected to the power switch 3 and the logic unit 8. The buck converter 51 steps down the voltage from the power switch 3 and then supplies it to the central processing unit 52. An overheat protection pin 54 of the central processing unit 52 and an overcurrent protection pin 55 of the graphics processing unit 53 receive the power control signal and reduce the power consumption according to the power control signal. Among them, the way the central processing unit 52 reduces power consumption is not to completely turn off the current, but only to reduce the current value. Also, when the central processing unit 52 overheats itself, it will also notify the CPLD82, and then the CPLD82 will perform the following subsequent actions. For example, the CPLD of the node motherboard 2 with the overheated CPU issues a notice to the CPLDs of other node motherboards 2 (not shown in the figure). The notice is to indicate that the overcurrent protection can be postponed for processing, or the CPLD notifies the baseboard management controller (abbreviated as BMC, not shown in the figure) of the same node motherboard to write the CPU overheat event into a log file (System Event Log). Refer to Figure 2, when the power setting is 500W, that is, C = logic 0, since the power control signal L = logic 0 triggers the overheat protection of the central processing unit 52 and the overcurrent protection of the graphics processing unit 53 to reduce the required current, the working current from the power supply unit 1 is reduced, the voltage E starts to rise, and when the power switch 3 detects the reduction of the working current and the output voltage D first drops to 2.15V and then returns to the normal value (for example, in this case, the change of the working current is 50mA → 100mA → 0mA → 50mA, where when L = 0, the working current changes from 100mA → 0mA, resulting in D dropping to 2.15V first), both the first voltage division D1 and the second voltage division D2 drop below 0.4V, causing the first logic signal G to change back from logic 1 to logic 0, and the second logic signal H remains logic 1. Since C = 0, G = 0, and H = 1, the power control signal L changes back to logic 1 after a delay of 2 unit times, stopping the triggering of the overheat protection of the central processing unit 52 and the overcurrent protection of the graphics processing unit 53. When the power setting is 600W, that is, C = logic 1, since the power control signal L = logic 0 triggers the overheat protection of the central processing unit 52 and the overcurrent protection of the graphics processing unit 53 to reduce the required current, the working current from the power supply unit 1 is reduced, the voltage E starts to rise, and when the power switch 3 detects the reduction of the working current and the output voltage D first drops to 2.15V and then returns to the normal value, both the first voltage division D1 and the second voltage division D2 drop below 0.4V, causing the first logic signal G to change back from logic 1 to logic 0, and the second logic signal H changes from logic 0 to logic 1. Since C = 1, G = 0, and H = 1, the power control signal L changes back to logic 1 after a delay of 2 unit times, stopping the triggering of the overheat protection of the central processing unit 52 and the overcurrent protection of the graphics processing unit 53.

[0028] Refer to Figure 3 and Figure 4 , which is a second embodiment of applying the multi-node server of the present invention, including a power supply unit 1 and a plurality of node motherboards 2 (for convenience of description, only one is drawn in this embodiment).

[0029] The power supply unit 1 is used to provide a plurality of working currents. The plurality of node motherboards 2 are electrically connected to the power supply unit 1 to respectively receive these working currents. Each node motherboard 2 includes a power switch 3, a protection device 6, and a chip module 5. The power switch 3 is electrically connected to the power supply unit 1 and the chip module 5 to receive the corresponding working current, and the power switch 3 transmits the working current to the chip module 5, making the change of the working current positively correlated with the power consumption of the chip module 5.

[0030] The protection device 6 has a detection unit 61 and a judgment unit 62. The detection unit 61 is electrically connected between the power switch 3 and the chip module 5 to detect the change in the working current to generate a detection voltage proportional to the working current. The detection unit 61 has a detection resistor R and an operational amplifier OP. The working current flows through both ends of the detection resistor R to generate a voltage across, and the operational amplifier OP is electrically connected to both ends of the detection resistor R to receive the voltage across and amplify the voltage across to generate the detection voltage, and the detection voltage is proportional to the voltage across.

[0031] The judgment unit 62 is electrically connected to the detection unit 61 to receive the detection voltage and receive a setting signal, and generates a selection voltage according to the setting signal and the detection voltage, and compares the selection voltage with a third reference voltage (0.6V in this embodiment) to generate a power control signal. The power control signal switches between a power consumption suppression level and a non-power consumption suppression level. The judgment unit 62 has a voltage division selector 9, a third comparator OP3, and a complex programmable logic device 82. The voltage division selector 9 receives the setting signal and is electrically connected to the operational amplifier OP to receive the detection voltage, divides the detection voltage to generate a third divided voltage and a fourth divided voltage, and selects one of the third divided voltage and the fourth divided voltage as the selection voltage according to the setting signal. The third comparator OP3 has an inverting input terminal electrically connected to the voltage division selector 9 to receive the selection voltage, a non-inverting input terminal receiving the third reference voltage (0.6V), and an output terminal providing a comparison signal. The complex programmable logic device 82 is electrically connected to the third comparator OP3 to receive the comparison signal and delays the comparison signal according to a default time to generate the power control signal. Among them, the logic level of the power control signal is the same as that of the comparison signal. The chip module 5 is electrically connected to the judgment unit 62 to receive the power control signal. When the working current increases as the power consumption of the chip module 5 rises, such that the detection voltage increases and the selection voltage is greater than the third reference voltage, then the power control signal is the power consumption suppression level to trigger the chip module 5 to reduce power consumption to reduce the working current. Refer to Figure 4, it is further explained herein that when the set signal C = logic 0, it means the power setting is 500W. When the working current increases, causing the voltage to drop from the original normal 12V to 11.6V and the detection voltage D to increase to 1.025 (when the set signal C = logic 1, it means the power setting is 600W. Except that the detection voltage D increases to 1.3125V, the other operations are the same as those for 500W), the selected voltage F = 0.61V. Since it is greater than the third reference voltage of 0.6V, the power control signal L becomes logic 0 after a delay of 1 unit time. Since the power control signal L = logic 0 triggers the overheat protection of the central processing unit 52 and the overcurrent protection of the graphics processing unit 53 to reduce the required current, the working current from the power supply unit 1 decreases, and the voltage E starts to rise. When the detection unit 61 detects that the working current decreases and the output voltage D first drops to 0.615V and then returns to the normal value, the selected voltage F drops below 0.6V. Therefore, the power control signal L becomes logic 1 again after a delay of 2 unit time, stopping the triggering of the overheat protection of the central processing unit 52 and the overcurrent protection of the graphics processing unit 53.

[0032] Refer to Figure 5 and Figure 6 , which is a third embodiment of applying the multi-node server of the present invention. The difference from the second embodiment is that the third reference voltage = 0.4V, and when the working current increases, causing the voltage E to drop from the original normal 12V to 11.6V, the selected voltage F = 0.41V. The other operations are the same as those of the second embodiment and will not be repeated.

[0033] In summary, the above embodiments are applied in a multi-node server, and can perform individual current limiting protection on each node motherboard to protect the system from accidentally triggering overcurrent and causing the entire server to shut down, effectively solving the deficiencies of the prior art.

[0034] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A multi-node server with a power consumption adjustment function, characterized in that, it includes: A power supply unit for providing a plurality of working currents; A plurality of node motherboards electrically connected to the power supply unit to respectively receive these working currents, and each of the node motherboards includes a power switch, a protection device, and a chip module; The power switch is electrically connected to the power supply unit and the chip module to receive the corresponding working current, and generates an output voltage according to the working current. The change of the output voltage is positively correlated with the change of the working current, and the power switch transmits the working current to the chip module, so that the change of the working current is positively correlated with the power consumption of the chip module; The protection device has a comparison unit and a logic unit; The comparison unit is electrically connected to the power switch to receive the output voltage, and divides the output voltage to generate a first divided voltage and a second divided voltage. Among them, the value of the first divided voltage is greater than the value of the second divided voltage. The comparison unit generates a first logic signal according to the first divided voltage and a first reference voltage, and the comparison unit generates a second logic signal according to the second divided voltage and the first reference voltage; The logic unit is electrically connected to the comparison unit to receive the first logic signal, the second logic signal and a setting signal, and the logic unit performs a logic operation according to the setting signal, the first logic signal and the second logic signal to generate a power control signal, and the power control signal switches between a power consumption suppression level and a non-power consumption suppression level; and The chip module is electrically connected to the logic unit to receive the power control signal. When the working current increases as the power consumption of the chip module rises, causing the output voltage to increase so that the first divided voltage is greater than the first reference voltage, the power control signal is the power consumption suppression level to trigger the chip module to reduce power consumption to reduce the working current.

2. The multi-node server with a power consumption adjustment function according to claim 1, characterized in that, The comparison unit includes a first comparator and a first voltage divider for dividing the output voltage to generate the first divided voltage. The first comparator has a non-inverting input terminal electrically connected to the first voltage divider to receive the first divided voltage, an inverting input terminal receiving the first reference voltage, and an output terminal for outputting the first logic signal. When the first divided voltage is greater than the first reference voltage, the first logic signal is logic 1. When the first divided voltage is less than the first reference voltage, the first logic signal is logic 0.

3. The multi-node server with a power consumption adjustment function according to claim 2, characterized in that, The comparison unit further includes a second comparator and a second voltage divider for dividing the output voltage to generate the second divided voltage. The second comparator has an inverting input terminal electrically connected to the second voltage divider to receive the second divided voltage, a non-inverting input terminal receiving the first reference voltage, and an output terminal for outputting the second logic signal. When the second divided voltage is greater than the first reference voltage, the second logic signal is logic 0. When the second divided voltage is less than the first reference voltage, the second logic signal is logic 1.

4. The multi-node server with power consumption adjustment function according to claim 3, characterized in that, it further includes a power setting unit for generating the setting signal. Wherein, the logic unit includes a logic operation circuit electrically connected to the power setting unit to receive the setting signal. The logic operation circuit is electrically connected to the first comparator and the second comparator to respectively receive the first logic signal and the second logic signal, and generates a logic output according to the first logic signal, the second logic signal and the setting signal. Wherein, a logic function of the logic operation circuit is: L = H &!(G &!C), where the parameter L is the logic level of the logic output, the parameter G is the logic level of the first logic signal, the parameter C is the logic level of the second logic signal, the definition of the parameter! is inversion, and the definition of the parameter & is AND gate.

5. The multi-node server with power consumption adjustment function according to claim 1, characterized in that, the logic unit further includes a complex programmable logic device. The complex programmable logic device is electrically connected to the logic operation circuit to receive the logic output, and delays the logic output according to a default time to generate the power control signal. Wherein, the logic level of the power control signal is the same as that of the logic output.

6. The multi-node server with power consumption adjustment function according to claim 1, characterized in that, the chip module includes a buck converter electrically connected to the power switch, a central processing unit electrically connected to the buck converter and the logic unit, and a graphics processing unit electrically connected to the power switch and the logic unit. The buck converter steps down the voltage from the power switch and then supplies it to the central processing unit. The central processing unit and the graphics processing unit receive the power control signal and adjust the power consumption according to the power control signal.

7. A multi-node server with power consumption adjustment function, characterized in that, it includes: a power supply unit for providing a plurality of working currents; a plurality of node motherboards electrically connected to the power supply unit to respectively receive the working currents. Each node motherboard includes a power switch, a protection device, and a chip module; the power switch is electrically connected to the power supply unit and the chip module to receive the corresponding working current, and the power switch transmits the working current to the chip module, so that the change of the working current is positively correlated with the power consumption of the chip module; the protection device has a detection unit and a judgment unit; the detection unit is electrically connected between the power switch and the chip module to detect the change of the working current and generate a detection voltage proportional to the working current; the judgment unit is electrically connected to the detection unit to receive the detection voltage and receive a setting signal, and generates a selection voltage according to the setting signal and the detection voltage, and compares the selection voltage with a third reference voltage to generate a power control signal. The power control signal switches between a power consumption suppression level and a non-power consumption suppression level; and The chip module is electrically connected to the judgment unit to receive the power control signal. When the working current increases as the power consumption of the chip module rises, causing the detection voltage to increase such that the selection voltage is greater than the third reference voltage, the power control signal is the power consumption suppression level used to trigger the chip module to reduce power consumption, thereby reducing the working current.

8. The multi-node server with a power consumption adjustment function according to claim 7, wherein, the detection unit has a detection resistor and an operational amplifier. The working current flows through both ends of the detection resistor to generate a voltage across it. The operational amplifier is electrically connected to both ends of the detection resistor to receive the voltage across it, and amplifies the voltage across it to generate the detection voltage, and the detection voltage is proportional to the voltage across it.

9. The multi-node server with a power consumption adjustment function according to claim 8, wherein, it further includes a power setting unit for generating the setting signal. Among them, the judgment unit has a voltage division selector electrically connected to the power setting unit to receive the setting signal. The voltage division selector is electrically connected to the operational amplifier to receive the detection voltage, divides the detection voltage to generate a third divided voltage and a fourth divided voltage, and selects one of the third divided voltage and the fourth divided voltage as the selection voltage according to the setting signal.

10. The multi-node server with a power consumption adjustment function according to claim 9, wherein, the judgment unit further has a third comparator and a complex programmable logic device. The third comparator has an inverting input terminal electrically connected to the voltage division selector to receive the selection voltage, a non-inverting input terminal receiving the third reference voltage, and an output terminal providing a comparison signal. The complex programmable logic device is electrically connected to the third comparator to receive the comparison signal, and delays the comparison signal according to a default time to generate the power control signal, wherein the logic level of the power control signal is the same as that of the comparison signal.

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