Threshold voltage test circuit, test chip, test method and readable storage medium

Abstract

The invention relates to a threshold voltage test circuit, a test chip, a test method and a readable storage medium. The threshold voltage test circuit comprises a storage unit, a switch module and a digital signal output module, the storage unit comprises a plurality of transistors; the storage unit is respectively connected to the test voltage signal and digital signal output module through the switch module; the switch module is used for selecting a target transistor from the storage unit; the test voltage signal is used for respectively providing test voltage for the grid electrode, the source electrode and / or the drain electrode of the target transistor; and the digital signal output module is used for converting the drain current of the target transistor into a digital signal. The threshold voltage fluctuation condition of the storage unit can be monitored under the condition that the structure of the storage unit is not damaged, the threshold voltage fluctuation is converted into the digital signal to be output to detect changes, the influence of the threshold voltage fluctuation on the storage unit can be evaluated more easily, and therefore the working yield of the storage unit is improved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design and manufacturing, and particularly relates to a threshold voltage test circuit, a test chip, a test method, and a readable storage medium. Background Art

[0002] Threshold voltage deviation caused by process fluctuations will seriously affect the working stability of a static random access memory (SRAM) circuit. Monitoring the threshold voltage of SRAM memory cells and avoiding using cells with large threshold voltage mismatches before a failure occurs provides an effective reference for improving the SRAM yield and identifying process defects.

[0003] To accurately monitor the threshold voltages of transistors at various positions in an SRAM memory cell, existing solutions usually adopt the constant current method and monitor by applying a voltage to the transistor under test and comparing the current. Among them, the method of applying and sensing voltages to each node in the SRAM memory cell to measure the threshold voltage of the selected transistor has relatively accurate test results, but this method requires changing the layout of the SRAM memory array and destroys the tight structure of the SRAM memory array. For the current conversion method, existing solutions usually use current comparators and other methods for processing, but such circuit solutions are relatively complex and will introduce additional circuit errors. In addition, there are also solutions that improve the accuracy of threshold voltage monitoring by changing the layout of the memory cell, but this method will destroy the storage function of the SRAM itself and affect its normal operation.

[0004] On the other hand, current test circuit technologies can only be applied to the monitoring of the standard threshold voltage V th and cannot achieve high stability and high precision for monitoring the linear threshold voltage V tlin . With the engineering test requirements for the linear threshold voltage V tlin , higher requirements are put forward for the threshold voltage test circuit. The linear threshold voltage is the threshold voltage used to describe the device when it operates in a low electric field or a linear region in the MOSFET model, and it is different from the standard threshold voltage V th and is mainly used to more accurately simulate the characteristics of the MOSFET in different operating regions.

[0005] Therefore, it is necessary to provide a circuit that can meet the new test requirements for the threshold voltage and support the testing of the linear threshold voltage V tlin . Summary of the Invention

[0006] The present invention provides a threshold voltage test circuit, an addressable threshold voltage test circuit, an on-chip self-adjusting threshold voltage test circuit, an addressable multifunctional test circuit, a threshold voltage test method, a test chip, and its computer-readable storage to solve all or part of the above-mentioned existing technical problems.

[0007] In order to achieve the above object, in a first aspect, the present invention provides a threshold voltage test circuit, including a storage unit, a switch module, and a digital signal output module; The storage unit includes a plurality of transistors; The storage unit is respectively connected to the digital signal output module and at least one test voltage signal through the switch module; The switch module is configured to select a target transistor from the storage unit; The test voltage signal is configured to respectively provide test voltages to the gate, source, and / or drain of the target transistor; The digital signal output module is configured to convert the drain current of the target transistor into a digital signal.

[0008] In some embodiments, the digital signal output module is implemented by a frequency output module, wherein the digital signal is a frequency signal.

[0009] In some embodiments, the threshold voltage test circuit further includes a frequency comparator; The frequency comparator is configured to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage based on a preset reference frequency and the frequency signal.

[0010] In some embodiments, the threshold voltage test circuit further includes: Automatically adjust the test voltage signal applied to the gate of the target transistor based on the magnitude relationship fed back by the frequency comparator.

[0011] In some embodiments, the frequency output module includes a current conversion module and a voltage-controlled oscillator module; The current conversion module is configured to convert the drain current of the target transistor into a voltage signal for driving the voltage-controlled oscillator module; The voltage-controlled oscillator module is configured to convert the driving voltage output by the current conversion module into a frequency signal for output.

[0012] In some embodiments, the frequency output module includes a regulated current replication module and a frequency conversion module; The regulated current replication module is configured to use the input voltage clamping and voltage regulation of an operational amplifier, and drive at least two transistors through the same output voltage of the operational amplifier to generate the same current signal, so as to accurately replicate the drain current of the target transistor; The frequency conversion module is configured to convert the current signal output by the current replication module into a voltage signal, and drive a voltage-controlled oscillator to oscillate by using the voltage signal, so as to output a digital frequency signal.

[0013] In some embodiments, the frequency output module includes two circuit groups arranged in a mirror image of each other, and each circuit group includes a regulated current replication module and a frequency conversion module; The two circuit groups are respectively configured to provide the drain currents of different types of target transistors in the storage unit to be connected to corresponding circuits.

[0014] In a second aspect, the present invention provides an addressable threshold voltage test circuit designed based on the threshold voltage test circuit described in the first aspect. The addressable threshold voltage test circuit includes a storage unit array, a first control module, and a plurality of first drive modules; The first control module is configured to provide the address signal and / or control signal required by the first drive module; The first drive module includes a first multiplexer module, a switch module, and a digital signal output module; Wherein, the first multiplexer module is configured to select a target storage unit from the storage unit array based on the address signal of the first control module; The switch module is configured to select a target transistor from the target storage unit based on the address signal and / or control signal of the first control module, and connect the target transistor to the digital signal output module and at least one test voltage signal; The test voltage signal is configured to provide test voltages to the gate, source, and / or drain of the target transistor respectively; The digital signal output module is configured to convert the drain current of the target transistor into a digital signal.

[0015] In some embodiments, the first drive module includes a first word line drive module and a first bit line drive module; The first word line drive module includes a word line switch module; The first bit line drive module includes a first multiplexer module, a bit line switch module, and a frequency output module; the digital signal output module is implemented by using the frequency output module, and wherein the digital signal is a frequency signal; The switch module includes the word line switch module and the bit line switch module; the word line switch module is configured to select the word line where the target transistor is located based on the address signal and / or control signal of the first control module, and connect the target transistor to at least one test voltage signal; the bit line switch module is configured to select the bit line where the target transistor is located based on the address signal and / or control signal of the first control module, and connect the target transistor to the frequency output module and at least one test voltage signal.

[0016] In some embodiments, the first bit line driving module further includes a frequency comparator; the frequency comparator is configured to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage based on a preset reference frequency and the frequency signal; The first control module determines whether the threshold voltage test of the target transistor is completed based on the magnitude relationship fed back by the frequency comparator: If it is determined that the test is completed, the address signal is adjusted to control the first driving module to select the next target transistor to be tested until the threshold voltage tests of all the transistors to be tested in the memory cell array are completed.

[0017] In a third aspect, the present invention provides an on-chip self-adjusting threshold voltage test circuit designed based on the threshold voltage test circuit described in the first aspect. The on-chip self-adjusting threshold voltage test circuit includes a memory cell, a switch module, a digital signal output module, and a test voltage generation module; The memory cell includes a plurality of transistors; The memory cell is respectively connected to the test voltage generation module and the digital signal output module through the switch module; The switch module is configured to select a target transistor from the memory cell; The test voltage generation module is configured to provide at least one test voltage signal to the target transistor; the test voltage generation module includes a sweep frequency voltage output for generating at least one per-cycle adjustment; wherein, the test voltage signal is configured to provide test voltages to the gate, source, and / or drain of the target transistor respectively; The digital signal output module is configured to convert the drain current of the target transistor into a digital signal.

[0018] In some embodiments, the source and drain of the target transistor are respectively connected to an initial voltage, and the gate is connected to a sweep frequency voltage.

[0019] In some embodiments, the on-chip self-adjusting threshold voltage test circuit further includes a frequency comparator; The digital signal output module is implemented by a frequency output module, where the digital signal is a frequency signal; The frequency comparator is configured to compare the frequency signal with a preset reference frequency to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage, and then control the test voltage generation module to adjust the swept-frequency voltage on a per-cycle basis.

[0020] In some embodiments, the on-chip self-adjusting threshold voltage test circuit further includes a voltage stabilizing module; The voltage stabilizing module is configured to provide a stable power supply voltage to the frequency output module.

[0021] In a fourth aspect, the present invention provides an addressable multi-functional test circuit, including the addressable threshold voltage test circuit described in the second aspect, as well as a second control module and a plurality of second driving modules; The second control module is configured to provide the address signal and / or control signal required by the second driving module; The second driving module includes a second multiplexer module and a peripheral circuit; Wherein, the second multiplexer module is configured to select a target storage unit from the storage unit array based on the address signal of the second control module, and connect the target storage unit to the peripheral circuit and at least one read / write test signal; The peripheral circuit includes a data input circuit and a data output circuit, and is configured to perform read / write tests on the target storage unit.

[0022] In some embodiments, the second driving module includes a second word line driving module and a second bit line driving module; The second bit line driving module includes a second multiplexer module and a peripheral circuit; The second word line driving module is configured to select the word line where the target storage unit is located based on the address signal and / or control signal of the second control module, and connect the target storage unit to at least one read / write test signal; The data output circuit includes a sense amplifier, and is configured to compare and amplify different bit line voltages.

[0023] In a fifth aspect, the present invention provides a threshold voltage test method, designed based on the threshold voltage test circuit described in the first aspect, and the threshold voltage test method includes the steps: Step S1: Control the switch module to select a target transistor, and respectively provide initial voltages to the gate, source, and drain of the target transistor; Step S2: Through the switch module, provide a swept-frequency voltage to the gate of the target transistor; Step S3: Determine the magnitude relationship between the current voltage signal applied to the gate of the target transistor and the threshold voltage through the digital signal of the digital signal output module, thereby controlling the per-cycle adjustment of the swept voltage and determining whether the threshold voltage test of the target transistor is completed.

[0024] In some embodiments, the digital signal output module is implemented by a frequency output module, wherein the digital signal is a frequency signal; In step S3, determining the magnitude relationship between the current voltage signal applied to the gate of the target transistor and the threshold voltage through the frequency signal of the frequency output module includes: If F out < F ref , then the gate-source voltage applied to the target transistor is less than the linear threshold voltage; If F out ≈ F ref , then the gate-source voltage applied to the target transistor is approximately equal to the linear threshold voltage; If F out > Fr ef , then the gate-source voltage applied to the target transistor is greater than the linear threshold voltage; wherein the F ref refers to the reference frequency output by the frequency output module under the drive of the reference current I ref of the target transistor; The F out refers to the frequency signal generated by the frequency output module for output; The gate-source voltage refers to the voltage difference between the gate voltage and the source voltage on the target transistor.

[0025] In a sixth aspect, the present invention provides a test chip, including the threshold voltage test circuit described in the first aspect.

[0026] In a seventh aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the threshold voltage test method described in the fifth aspect.

[0027] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The present application provides a threshold voltage test circuit: 1) It can monitor the threshold voltage fluctuation of a memory cell (bitcell) without damaging the memory cell structure, which is more beneficial for evaluating the impact of threshold voltage fluctuation on the memory cells in the array, thereby improving the working yield of the memory cells; 2) It can monitor the threshold voltages of the transistors at various positions in the memory cells at different positions in the memory array through a switching module, thereby further improving the working yield of the memory cells; 3) It can convert the threshold voltage fluctuation into a digital signal for output to detect the change. Preferably, the output frequency is used to detect the change. The output digital signal (especially the frequency signal) is easier to monitor, does not rely on precise amplification and comparison circuits, reduces the circuit complexity, and is easier for subsequent judgment and processing, simplifying the detection process of the threshold voltage fluctuation; 4) It is applicable to the V tlin measurement in engineering practice and meets its requirements for the four-terminal voltage of the device under test.

[0028] 2. Based on the foregoing threshold voltage test circuit, the present application provides an addressable threshold voltage test circuit. While having the beneficial effects of the threshold voltage test circuit, it can perfectly meet the requirement of not damaging the tight structure of the memory cell storage array and supports monitoring the addressable threshold voltage fluctuation of the target memory cell and the target transistor therein in the memory cell array, which is more beneficial for evaluating the impact of threshold voltage fluctuation on the memory cells in the array, thereby improving the working yield of the memory cell array.

[0029] 3. Based on the foregoing threshold voltage test circuit, the present application provides an on-chip self-adjusting threshold voltage test circuit. While having the beneficial effects of the threshold voltage test circuit, it can provide a test circuit with an on-chip self-adjusting assignment potential to each terminal of the target transistor according to the threshold voltage monitoring process, and no longer relies on an external instrument to generate a stepped signal that changes periodically (i.e., the swept voltage in the test voltage signal). Since the test voltage signal does not need to be input externally, the number of external interfaces of the on-chip circuit can be saved, and the external interfaces can be reserved for other test requirements.

[0030] 4. Based on the foregoing addressable threshold voltage test circuit, the present application provides an addressable multi-functional test circuit. While having the beneficial effects of the addressable threshold voltage test circuit, it can switch between the read-write performance test mode and the threshold voltage test mode, support monitoring the working margin of the memory cell from multiple dimensions, and at the same time does not damage the normal storage function of the memory cell circuit.

[0031] 5. Based on the aforementioned threshold voltage test circuit, the present application provides a threshold voltage test method. While having the beneficial effects of the threshold voltage test circuit, it automatically determines the threshold voltage fluctuation by detecting the change in the output of a digital signal (especially a frequency signal), making it easier to perform subsequent judgments and processing, and simplifying the detection process of threshold voltage fluctuation.

[0032] 6. Based on the aforementioned threshold voltage test circuit, the present application further provides a test chip, which has the beneficial effects of the threshold voltage test circuit.

[0033] 7. Based on the aforementioned threshold voltage test method, the present application further provides a computer-readable storage medium, which has the beneficial effects of the threshold voltage test method. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0035] Figure 1 Schematic diagram of a threshold voltage test circuit provided in Embodiment 1 of the present application.

[0036] Figure 2 Schematic diagram of a threshold voltage test circuit implemented by a frequency output module as the digital signal output module provided in Embodiment 1 of the present application.

[0037] Figure 3 Another schematic diagram of a threshold voltage test circuit provided in Embodiment 1 of the present application.

[0038] Figure 4 Specific circuit diagram of a threshold voltage test circuit provided in Embodiment 1 of the present application.

[0039] Figure 5 Timing diagram of Embodiment 1 of the present application.

[0040] Figure 6 Timing diagram of Embodiment 1 of the present application.

[0041] Figure 7 Timing diagram of Embodiment 1 of the present application.

[0042] Figure 8 Specific circuit diagram of another threshold voltage test circuit provided in Embodiment 1 of the present application.

[0043] Figure 9Schematic diagram of an on-chip self-adjusting threshold voltage test circuit provided in Embodiment 3 of this application.

[0044] Figure 10 Schematic diagram of an addressable multi-functional test circuit provided in Embodiment 4 of this application. Detailed implementation manners

[0045] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to relevant accompanying drawings. Embodiments of this application are shown in the accompanying drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by those with ordinary skills in the technical field to which this application belongs. In this application, words such as "a", "an", "one kind", "the", "these", etc. do not indicate a limitation in quantity and can be singular or plural. The terms "including", "comprising", "having" and any variants thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device including a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The terms "connected", "coupled", etc. involved in this application do not limit to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "multiple" involved in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " represents an "or" relationship between the associated objects before and after. The terms "first", "second", "third", etc. involved in this application only distinguish similar objects and do not represent a specific sorting of the objects.

[0048] Embodiment 1 This embodiment provides a threshold voltage test circuit as Figure 1 shown, including a storage unit, a switch module, and a digital signal output module; The memory cell includes a plurality of transistors; The memory cell is respectively connected to a digital signal output module and at least one test voltage signal through a switching module; The switching module is used to select a target transistor from the memory cell; The test voltage signal is used to respectively provide test voltages to the gate, source and / or drain of the target transistor; The digital signal output module is used to convert the drain current of the target transistor into a digital signal.

[0049] Specifically, the digital signal output module can convert the current into a digital signal based on application requirements, such as frequency, codeword (0101010), etc., which is not specifically limited in this application.

[0050] Specifically, in this embodiment, the gate, source and drain of the target transistor are respectively connected to their respective test voltage signals to respectively provide test voltages; however, in other embodiments, the source or drain of the target transistor, or even the source and drain, can be supplied with voltage by an external VS / VD (power supply voltage / ground voltage).

[0051] The threshold voltage test circuit of this embodiment: can monitor the threshold voltage fluctuation of the memory cell (bitcell) without damaging the memory cell structure, which is more beneficial to evaluating the impact of the threshold voltage fluctuation on the memory cells in the array, thereby improving the working yield of the memory cell; can monitor the threshold voltages of the transistors at various positions in the memory cells at different positions in the memory array through the switching module, thereby further improving the working yield of the memory cell; can convert the threshold voltage fluctuation into a digital signal output for detection, and the output digital signal is easier to monitor, does not rely on precise amplification and comparison circuits, reduces the circuit complexity, and is easier to perform subsequent judgment and processing, simplifying the detection process of the threshold voltage fluctuation.

[0052] In some of these embodiments, the digital signal output module is preferably implemented by a frequency output module, and the digital signal is a frequency signal; the digital signal is preferably a frequency signal, which is easier to monitor and further reduces the circuit complexity.

[0053] Specifically, reference can be made to, for example Figure 2The schematic diagram of the circuit structure shown uses an SRAM bitcell as the storage unit. The test voltage signals include FORCE_VD, FORCE_VS, FORCE_WL, FORCE_BL, and FORCE_BLB, which respectively provide voltage assignments for the nodes VD, VS, WL, BL, and BLB of the SRAM bitcell. The digital signal output module is implemented using a frequency output module (VCO module). The switch control module in the figure refers to the switch module.

[0054] In some of these embodiments, the threshold voltage test circuit further includes a frequency comparator; the frequency comparator is used to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage based on a preset reference frequency and the frequency signal. Implementing the frequency comparison circuit on-chip reduces the dependence on the accuracy of external instruments.

[0055] In some of these embodiments, the threshold voltage test circuit further includes: automatically adjusting the test voltage signal applied to the gate of the target transistor based on the magnitude relationship fed back by the frequency comparator.

[0056] Specifically, automatically adjusting the test voltage signal applied to the gate of the target transistor can be a per-cycle feedback adjustment, which can be implemented by other on-chip control circuits or off-chip control software. The on-chip self-regulation method can save the number of external interfaces of the circuit and further reduce the dependence on the accuracy of external instruments.

[0057] In some of these embodiments, the frequency output module includes a current conversion module and a voltage-controlled oscillator module; the current conversion module is used to convert the drain current of the target transistor into a voltage signal for driving the voltage-controlled oscillator module; the voltage-controlled oscillator module is used to convert the driving voltage output by the current conversion module into a frequency signal for output.

[0058] Specifically, reference can be made to Figure 3 the schematic diagram of the circuit structure shown. The storage unit uses an SRAM bitcell, and the frequency output module is implemented using a current conversion module and a VCO module (voltage-controlled oscillator module) to output a frequency for test monitoring. The switch control module in the figure refers to the switch module.

[0059] To further illustrate the working principle of the threshold voltage test circuit of this design, the following will be described in detail with an embodiment in a specific application scenario. As Figure 4 shown, the threshold voltage test circuit mainly includes four modules: an SRAM bitcell (selected bitcell, that is, the selected storage unit), a switch module, a current conversion module, and a voltage-controlled oscillator module.

[0060] The SRAM bitcell includes six transistors. According to the different positions of the transistors in a bitcell unit, the six transistors to be tested can be divided into a PD (Pull-Down, drive transistor), a PG (Pass-Gate, access transistor), and a PU transistor (Pull-Up, load transistor) on the BL side, and a PD, a PG, and a PU transistor on the BLB side.

[0061] The source of the PU transistor on the BLB side is connected to the VD node; the drain of the PG transistor on the BLB side is connected to the BLB node, and the gate is connected to the WL node; the source of the PD transistor on the BLB side is connected to the VS node; the gates of the PU transistor and the PD transistor on the BLB side are connected together and connected to the Q node; the drains of the PU transistor on the BLB side, the source of the PG transistor on the BLB side, and the drain of the PD transistor on the BLB side are all commonly connected to the QB node; The source of the PU transistor on the BL side is connected to the VD node; the drain of the PG transistor on the BL side is connected to the BL node, and the gate is connected to the WL node; the source of the PD transistor on the BL side is connected to the VS node; the gates of the PU transistor and the PD transistor on the BL side are connected together and connected to the QB node; the drains of the PU transistor on the BL side, the source of the PG transistor on the BL side, and the drain of the PD transistor on the BL side are all commonly connected to the Q node.

[0062] The switch S0 is used to control the conduction or cut-off between the VD node and the test voltage signal FORCE_VD; the switch S1 is used to control the conduction or cut-off between the VS node and the test voltage signal FORCE_VS; the switch S2 is used to control the conduction or cut-off between the WL node and the test voltage signal FORCE_WL; the switch S3 is used to control the conduction or cut-off between the BL node and the test voltage signal FORCE_BL; the switch S4 is used to control the conduction or cut-off between the BLB node and the test voltage signal FORCE_BLB. In addition, the switch S5 is used to control the conduction or cut-off between the BL node and the input end of the current conversion module, and the switch S6 is used to control the conduction or cut-off between the BLB node and the input end of the current conversion module.

[0063] The switch module includes switches S0 - S10 in the figure, which are mainly used to control the current conversion module to select transistors at different positions in the bitcell for monitoring. The switch control signals are provided by the output of a decoder (Decoder) in this embodiment and are controlled by the control signal CTRL<3:0> and the address signals BL addr and WL addr input to the decoder. Additionally, since switches S0 and S1 do not need to be specifically connected to test voltage signals and can both be supplied with voltage by the external VS / VD (power supply voltage / ground voltage), and switch S2 does not need to be connected to a swept voltage in the current mode (switch S2 needs to be connected to a scanned voltage signal in the PG mode) and can be provided with an initial voltage at a fixed point, for the convenience of drawing, the connection methods of switches S0, S1, and S2 are not specifically shown in the circuit diagram, and only the voltage signals they are connected to are simply indicated below the circuit diagram.

[0064] Current conversion module: It includes a group of NMOS current mirrors, a group of PMOS current mirrors, an NMOS precharge transistor, and a PMOS precharge transistor. Among them, the part on the side of switch S7 is the PMOS current mirror part. The gate and drain of the first transistor are connected together and connected to one end of switch S7; the source of the first transistor, the gate and drain of the second transistor are connected together and connected to one end of switch S9; the source of the second transistor is connected to the VDD node; the drain of the third transistor is connected to switch S9 and the voltage - controlled oscillator module, the gate of the third transistor is connected to the PRE node, and the source of the third transistor is connected to the VSS node. The part on the side of switch S8 is the NMOS current mirror part, which is symmetrically arranged with the above - mentioned PMOS current mirror part. Among them, switches S9 and S10 are used to control the conduction or cut - off of the current conversion module and the voltage - controlled oscillator module. The PRE node is connected to a precharge control signal, which is used to provide the initial voltage of the input transistor of the voltage - controlled oscillator module.

[0065] In this embodiment, the implementation method of this current conversion module directly uses the current mirror method to convert the current signal into a voltage and input it into the VCO. In other embodiments, other current conversion implementation methods can also be adopted according to different application requirements, and this application does not make specific limitations.

[0066] Voltage - controlled oscillator module: It includes a group of PMOS voltage - controlled input transistors, a group of NMOS voltage - controlled input transistors, and a ring oscillator circuit connected to the voltage - controlled input transistors. Among them, the part on the side of switch S9 is the PMOS voltage - controlled input transistor part. The gates of the input transistors are commonly connected to the drain of the NMOS precharge transistor in the current conversion module, the sources of the input transistors are commonly connected to the VDD node, and the drains of the input transistors are connected to the sources of the PMOS transistors in the ring oscillator. The part on the side of switch S10 is the NMOS voltage - controlled input transistor part, which is symmetrically arranged with the above - mentioned PMOS voltage - controlled input transistor part.

[0067] The implementation method of the voltage-controlled oscillation module in this embodiment mainly functions to convert the input voltage into the output frequency. In other embodiments, other VCO circuits can also be used according to different application requirements, and this application does not make specific limitations.

[0068] For these six transistors to be measured, this circuit can be switched to six states correspondingly: the PD mode, PG mode, and PU mode on the BL side, and the PD mode, PG mode, and PU mode on the BLB side, to detect the transistors at the corresponding positions respectively.

[0069] Taking the PD mode, PG mode, and PU mode on the BL side as examples: PD mode: S6, S8, and S10 in the switch module are all set to low level, S0, S1, and S2 are all set to high level, S3 and S5 are opposite signals to each other, and the signals of S5, S7, and S9 are consistent. As Figure 5 shown in the timing embodiment diagram of the PD mode on the BL side, within one detection period, the signals of S6, S8, S10, and PRE are all set to low level, the signals of S0, S1, S2, and S4 are all set to high level, FORCE_VD = FORCE_VS = 0V, FORCE_WL = 1V, the signal of S3 is first set to high level and then to low level, and S4 is constantly set to high level; the current conversion module selects the PMOS current mirror part, and the voltage-controlled oscillator module starts to output frequency after being enabled. PG mode: S6, S8, and S10 in the switch module are all set to low level, S0, S1, and S2 are all set to high level, S3 and S5 are opposite signals to each other, and the signals of S5, S7, and S9 are consistent. As Figure 6 shown in the timing embodiment diagram of the PG mode on the BL side, within one detection period, the signals of S6, S8, S10, and PRE are all set to low level, the signals of S0, S1, S2, and S4 are all set to high level, FORCE_VD = VDD, FORCE_VS = 0V, FORCE_BLB = VDD, the signal of S3 is first set to high level and then to low level, and S4 is constantly set to high level; the current conversion module selects the PMOS current mirror part, and the voltage-controlled oscillator module starts to output frequency after being enabled.

[0070] PU mode: S6, S7, and S9 in the switch module are all set to low level, S0, S1, and S2 are all set to high level, S3 and S5 are opposite signals to each other, and the signals of S5, S8, and S10 are consistent. As Figure 7The timing example diagram of the BL-side PU mode shown. During a detection cycle, the signals S6, S7, and S9 are all set to low level; the signals S0, S1, S2, S4, and PRE are all set to high level, FORCE_VD = FORCE_VS = VDD, FORCE_WL = 1V, the signal S3 is first set to high level and then to low level, and S4 is constantly set to high level; the current conversion module selects the NMOS current mirror part, and the voltage-controlled oscillator module starts to output frequency after being enabled.

[0071] Taking the monitoring of three transistors on the BL side as an example, namely the PD mode, PG mode, and PU mode on the BL side, the potential assignment situations of different ports in each mode are shown in Table 1.

[0072] Table 1 Potential assignment situations of different ports / nodes

[0073] Taking the PD mode on the BL side as an example: The switch module controls the circuit to switch to the corresponding monitoring mode. During a detection cycle: First, the signals BL, BLB, WL, VD, and VS are assigned to the initial voltages (the initial values are set differently at different process nodes and can be determined by simulation), and then it enters the monitoring stage. The current signal on BL (since it is a transistor on the BL side, the current signal at the BL terminal is connected to the current conversion module. If it is a transistor on the BLB side, the current at the BLB terminal is connected) is connected to the current conversion module, and the current signal is converted into a voltage signal; finally, the frequency is output through the voltage-controlled oscillator module.

[0074] Subsequently, the output frequencies can be compared. The comparison includes: comparing the output frequency with the reference frequency under the drive of the reference current I ref ; comparing with the reference frequency under the drive of the reference current I. According to the two implementation methods of on-chip and off-chip, it can be self-driven internally or compared externally; the comparison result will determine whether the voltage signal at the BLB terminal needs to be increased or decreased in the next clock cycle; the comparison result is determined by the acceptable error range. Similarly, when the PG mode and PU mode are working, stages such as pressurizing and assigning initial values, current conversion, frequency output, and comparison will also be carried out successively.

[0075] In some of the embodiments, the frequency output module includes a regulated current replication module and a frequency conversion module; the regulated current replication module is used to clamp and regulate the input voltage of the operational amplifier and drive at least two transistors through the same output voltage of the operational amplifier to generate the same current signal, so as to accurately replicate the drain current of the target transistor; the frequency conversion module is used to convert the current signal output by the current replication module into a voltage signal and drive the voltage-controlled oscillator to oscillate with the voltage signal to output a digital frequency signal.

[0076] Specifically, it can be referred to asFigure 8 The schematic diagram of the circuit structure shown, where the storage unit uses an SRAM bitcell, and the frequency output module is implemented by a regulated current replication module (i.e., the analog current conversion module marked in the figure) and a frequency conversion module (i.e., the digital frequency output module marked in the figure), and the output frequency is used for test monitoring.

[0077] To further illustrate the working principle of the threshold voltage test circuit of this design, the following will be described in detail in combination with an embodiment in a specific application scenario. As Figure 8 shown, the threshold voltage test circuit mainly includes four modules: an SRAM bitcell (selected bitcell, i.e., the selected storage unit), a switch module, an analog current conversion module, and a digital frequency output module.

[0078] The internal connection relationship of the storage unit will not be elaborated and can be referred to the description in Figure 4 . The switch module includes the switches on each branch in the figure and is mainly used to complete the assignment and selection method of the PD / PG / PU transistors. The switch control signal is provided by the output of a decoder (Decoder) in this embodiment and is controlled by the control signal CTRL<3:0> input to the decoder and the address signals BL addr and WL addr. The address signals are used to select the target storage unit selected bitcell. In addition, since switches S0 and S1 do not need to be specifically connected to the test voltage signal and can both be supplied with voltage by the external VS / VD (power supply voltage / ground voltage), and switch S2 does not need to be connected to the swept frequency voltage in the current mode (switch S2 needs to be connected to the scanned voltage signal in the PG mode) and can be provided by an initial voltage at a fixed point, for the convenience of drawing, the connection methods of switches S0, S1, and S2 are not specifically shown in the circuit diagram, and only the voltage signals they are connected to are simply indicated below the circuit diagram.

[0079] In the analog current conversion module, the input end of the operational amplifier performs voltage clamping to ensure that the voltage of the branch where switch S10 is located is the same as FORCE_BL / BLB, so as to accurately replicate the current of the selected transistor; the output end of the amplifier drives a group of identical PMOS transistors to generate the same current, and this current signal is transmitted to the digital frequency output module for processing.

[0080] Analog current conversion module: It includes an operational amplifier and at least two transistors; the positive input terminal of the operational amplifier is connected to the test voltage signal that provides a potential to the drain of the target transistor through switch S9 or switch S8; the negative input terminal is connected to the drain current output terminal of the target transistor through switch S7; the output terminal of the operational amplifier is connected to the gates of the at least two transistors (at least including the first transistor and the second transistor); the drain current output terminal of the target transistor is connected to the drain of the first transistor through switch S10; the drain of the second transistor, as the output terminal of the regulated current replication module, is connected to the frequency conversion module; the sources of the at least two transistors are all commonly connected to the VDD node; in the regulated current replication module, in the path where the drain current output terminal of the target transistor is connected to the drain of the first transistor through switch S10, a resistor is also connected. Among them, switch S8 is used to control the conduction or cutoff between FORCE_BLB and the input terminal of the operational amplifier; S9 is used to control the conduction or cutoff between FORCE_BL and the input terminal of the operational amplifier; switch S10 is used to control the conduction or cutoff of the PMOS current mirror and the NMOS current mirror (not shown in the figure because it belongs to the circuit group not shown due to mirroring).

[0081] In this implementation manner of the regulated current replication module in this embodiment, the LDO-like connection method is adopted, and the operational amplifier is used for clamping and voltage regulation, which can realize the test of the threshold voltage in the linear region and solve the problem that the existing circuits for measuring the threshold voltage cannot perform the test currently; in other embodiments, other implementation manners of the regulated current replication can also be adopted according to different application requirements, and the present application does not make specific limitations.

[0082] Digital frequency output module: It includes a ring oscillator and a group of voltage-controlled input transistors. The drain and gate of one of the voltage-controlled input transistors are commonly connected together and are connected to the analog current conversion module through a switch; the gates of the remaining voltage-controlled input transistors are commonly connected together and are connected to the analog current conversion module through a switch, and the drains of the remaining voltage-controlled input transistors are connected to the source of the NMOS transistor in the ring oscillator. The sources of the group of voltage-controlled input transistors are all commonly connected to the VSS node.

[0083] The digital frequency output module in this embodiment is mainly composed of a voltage-controlled oscillator (VCO). The input current signal is converted into a voltage signal to drive the VCO circuit to oscillate, and then a digital frequency is output. In other embodiments, other VCO circuits can also be adopted according to different application requirements, and the present application does not make specific limitations.

[0084] The design of the frequency output module in this embodiment is applicable to V in engineering practice tlinMeasurement meets its requirements for the four-terminal voltage of the tube to be measured, including using a regulated connection method to effectively stabilize the bit line voltage to control the four-terminal voltage of the transistor to be measured, especially dealing with the stabilization of the drain voltage to achieve the effective measurement of V tlin The current test circuit technology can only be applied to the monitoring of the standard threshold voltage V th and cannot achieve the high stability and high precision required for monitoring the linear threshold voltage V tlin .

[0085] In some of these embodiments, the frequency output module includes two circuit groups arranged in a mirror image of each other. The circuit group includes a regulated current replication module and a frequency conversion module. The two circuit groups are respectively used to provide the drain currents of different types of target transistors in the storage unit to be connected to the corresponding circuits.

[0086] Specifically, PMOS\NMOS are different transistor types under one division method. For example, due to the differences between PMOS\NMOS, different voltages need to be provided at some ports of the circuit group. Therefore, they are arranged in the form of mirror-image circuit groups, with PMOS connected to the upper circuit group and NMOS connected to the lower circuit group, which is convenient for providing different voltage levels at the mirror-image ports in the two circuit groups.

[0087] Specifically, reference can be made to Figure 8 As shown, two circuit groups arranged in a mirror image of each other are actually set in this circuit. Figure 8 For the convenience of drawing, only the circuit groups corresponding to the PD and PG detection modes are drawn (that is, including the analog current conversion module and the digital frequency output module marked in the figure), and the circuit group corresponding to the PU mode is symmetric to it (not drawn for simplicity).

[0088] Based on the threshold voltage test circuit of this embodiment, the present application also provides a threshold voltage test method, which specifically includes the following steps: Step S1: Control the switch module to select the target transistor and provide initial voltages to the gate, source, and drain of the target transistor respectively. Step S2: Provide a swept-frequency voltage to the gate of the target transistor through the switch module. Step S3: Determine the magnitude relationship between the current voltage signal applied to the gate of the target transistor and the threshold voltage through the digital signal of the digital signal output module, and then control the swept-frequency voltage to be adjusted period by period and determine whether the threshold voltage test of the target transistor is completed.

[0089] Specifically, the control of the switch module in step S2 includes changing from the initial voltage applied to the gate of the target transistor to the test mode. Subsequently, the switch connected to the frequency output module needs to be turned on, and the switch supplying the drain potential of the transistor is turned off.

[0090] In some of these embodiments, the digital signal output module is implemented using a frequency output module, where the digital signal is a frequency signal. In step S3, by using the frequency signal of the frequency output module, determining the magnitude relationship between the current voltage signal applied to the gate of the target transistor and the threshold voltage includes: If F out < F ref , then the gate-source voltage applied to the target transistor is less than the linear threshold voltage. If F out ≈ F ref , then the gate-source voltage applied to the target transistor is approximately equal to the linear threshold voltage. If F out > F ref , then the gate-source voltage applied to the target transistor is greater than the linear threshold voltage. Wherein, the Fref refers to the reference frequency output by the frequency output module under the drive of the reference current I ref of the target transistor; I ref =(W / L)*IDT, the constant current IDT changes according to different process nodes, and W and L respectively represent the width and length of the bitcell. In the case where the process and application scenario are determined, this is a fixed value. The F out refers to the frequency signal generated by the frequency output module for output. The gate-source voltage refers to the voltage difference between the gate voltage and the source voltage on the target transistor.

[0091] It should be noted that in this test scenario, the source of the target transistor is generally grounded or connected to 0 potential. Therefore, the gate-source voltage will numerically be equal to the gate voltage here.

[0092] Combined with the threshold voltage test circuit and the above-mentioned monitoring circuit in this embodiment, taking the PD transistor on the BL side of the transistor to be measured in the storage unit as an example, the specific steps of the threshold voltage monitoring method include: Figure 4 Step 1: Switch the overall circuit to the SRAM VT MONITOR mode, select the transistor to be measured and clarify the PD mode, and assign the node voltages of BL, BLB, WL, VDD, and VSS to the corresponding potentials according to different modes. Step 1: Switch the overall circuit to the SRAM VT MONITOR mode, select the transistor to be measured and clarify the PD mode, and assign the node voltages of BL, BLB, WL, VDD, and VSS to the corresponding potentials according to different modes. Step 2: Through the switch control module, adjust the voltage applied to the BLB terminal cycle by cycle, and measure the current I flowing through the BL terminal BL Reflect the magnitude of the potential applied to the BLB terminal and the threshold voltage of the transistor under test. The specific judgment basis is as follows: If I BL <I ref , it indicates that the potential applied to the BLB terminal is less than the threshold voltage of the transistor under test; If I BL ≈ I ref , it indicates that the potential applied to the BLB terminal is approximately equal to the threshold voltage of the transistor under test; If I BL >I ref , it indicates that the potential applied to the BLB terminal is greater than the threshold voltage of the transistor under test; Among them, the reference current I ref =(W / L)*IDT; W and L respectively refer to the width and length of the bitcell, and the constant current IDT changes according to different process nodes; and the reference frequency F out refers to the frequency F ref of the output driven by the reference current I ref .

[0093] Step 3: Through the switch control module, select the corresponding current conversion module to convert the current signal on the BL into a voltage signal to drive the VCO module; Step 4: Through the voltage-controlled oscillator module, convert the corresponding driving voltage into an output frequency, and indirectly reflect the relationship between the potential applied to the BLB terminal and the threshold voltage of the transistor under test by monitoring the magnitude relationship between the output frequency in the monitoring mode and the output frequency under the drive of I ref .

[0094] Furthermore, taking the PG, PD, and PU transistors on the BL side as an example, the truth table of the connections is shown in Table 2 below. The following is the situation within a single cycle ("invalid" state, x in the control signal Ctrl[0] means it can be 0 or 1).

[0095] Table 2 Truth Table

[0096] As Figure 8 shown, it contains at least four control signals Ctrl[3:0]. Among them, Ctrl[3] is used to select whether the measured transistor is on the BL side / BLB side, Ctrl[2:1] is used to select whether the measured transistor is at the PU / PD / PG position, and Ctrl[0] is used to determine whether the circuit is in the initial assignment / measurement stage within a cycle. Among them, Ctrl[3]=1 means selecting the transistor on the BL side, and vice versa for the BLB side.

[0097] Without changing the compact structure of the SRAM memory array, this solution uses the constant current method (a common method for VT measurement). Through the switch control module, the power supply conditions of the VD, VS, WL, BL, and BLB ports in the memory array are changed (currently, the switch control module only controls the power supply conditions of the WL, BL, and BLB ports. The VD and VS ports are not shown in the circuit diagram. VD and VS supply power to the memory cells in the BCA uniformly. It should be noted here that the VD and VS mentioned in this document refer to the voltage signals inside the BCA, rather than the voltage signals of the entire circuit). The conduction current of the transistors at each position in the SRAM memory cell is controlled to change, and the current fluctuation is converted into a frequency change through an external current conversion module and a voltage-controlled oscillator module. The threshold voltage fluctuation is determined through the frequency range.

[0098] Embodiment 2 Based on the threshold voltage test circuit of Embodiment 1, this embodiment provides an addressable threshold voltage test circuit, which includes a memory cell array, a first control module, and a plurality of first driver modules; The first control module is used to provide the address signal and / or control signal required by the first driver module; The first driver module includes a first multiplexer module, a switch module, and a digital signal output module; Among them, the first multiplexer module is used to select a target memory cell from the memory cell array based on the address signal of the first control module; The switch module is used to select a target transistor from the target memory cell based on the address signal and / or control signal of the first control module, and connect the target transistor to the digital signal output module and at least one test voltage signal; The test voltage signal is used to provide test voltages to the gate, source, and / or drain of the target transistor respectively; The digital signal output module is used to convert the drain current of the target transistor into a digital signal.

[0099] The addressable threshold voltage test circuit of this embodiment, while having the beneficial effects of the threshold voltage test circuit, can perfectly meet the requirement of not destroying the compact structure of the memory cell array, and supports monitoring the addressable threshold voltage fluctuation conditions of the target memory cell and the target transistor in the memory cell array, which is more beneficial to evaluating the impact of threshold voltage fluctuation on the memory cells in the array, thereby improving the working yield of the memory cell array.

[0100] In some of these embodiments, the first driver module includes a first word line driver module and a first bit line driver module; The first word line driver module includes a word line switch module; The first bit line driving module includes a first multiplexer module, a bit line switch module, and a frequency output module; the digital signal output module is implemented by the frequency output module, wherein the digital signal is a frequency signal. The switch module includes the word line switch module and the bit line switch module; the word line switch module is configured to select the word line where the target transistor is located based on the address signal and / or control signal of the first control module, and connect the target transistor to at least one test voltage signal; the bit line switch module is configured to select the bit line where the target transistor is located based on the address signal and / or control signal of the first control module, and connect the target transistor to the frequency output module and at least one test voltage signal.

[0101] Specifically, the first word line driving module can directly adopt 128 groups of switch modules without a word line multiplexer, or can be implemented by using a "word line multiplexer and a word line switch module".

[0102] In some of the embodiments, the first bit line driving module further includes a frequency comparator; the frequency comparator is configured to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage based on a preset reference frequency and the frequency signal. The first control module determines whether the threshold voltage test of the target transistor is completed based on the magnitude relationship fed back by the frequency comparator. If it is determined that the test is completed, the address signal is adjusted to control the first driving module to select the next target transistor to be tested until the threshold voltage tests of all the transistors to be tested in the memory cell array are completed.

[0103] Specifically, when adjusting the address signal, for example, in the patent "An Addressable Test Chip Test System (201721911051.5)", it is disclosed that a function generator and a multi-purpose address register combination are used to generate the address signal. This multi-purpose address register has two functions of a counter and a shift register, and can support two addressing methods: (1) continuous addressing, in this method, each address is incremented by 1, and continuous address signals can be generated, which is the core for realizing continuous and fast measurement; (2) fixed-point addressing, in this method, through a specific communication protocol, the required address is transmitted to the chip. This method can arbitrarily change the address in the chip, but only one address can be changed each time.

[0104] Embodiment 3 According to the different ways of assigning potentials to each end of the selected transistor during the threshold voltage monitoring process, the circuit can be further divided into two working modes, namely, off-chip voltage input type and on-chip self-regulation type. The circuit structure of the off-chip voltage input type is used to measure Figure 4Taking the threshold voltage of the PD transistor on one side of the BL in the middle as an example, the off-chip voltage input type circuit adjusts the voltage signal on one side of the BLB cycle by cycle through the direct input of the external voltage, and determines the fluctuation of the target transistor threshold voltage according to the relationship between the output frequency and the reference frequency. The off-chip voltage input type circuit can more directly control the voltage change through an external instrument, and the internal circuit is relatively simple, but it depends on the accuracy of the external instrument and requires more external interfaces to adjust the voltage of each port.

[0105] Based on the threshold voltage test circuit of Embodiment 1, this embodiment provides an on-chip self-adjusting type circuit, which can provide the BLB voltage signal through an on-chip adjustable DAC module; the on-chip self-adjusting type circuit no longer depends on an external instrument to generate a step signal that changes cycle by cycle, and can save the number of external interfaces of the circuit through the on-chip self-adjusting method.

[0106] This embodiment provides an on-chip self-adjusting threshold voltage test circuit, which includes a storage unit (SRAM bit cell), a switch module, a digital signal output module, and a test voltage generation module (DAC module); The storage unit includes a plurality of transistors; The storage unit is respectively connected to the test voltage generation module and the digital signal output module through the switch module; The switch module is used to select a target transistor from the storage unit; The test voltage generation module is used to provide at least one test voltage signal to the target transistor; the test voltage generation module includes a swept-frequency voltage output for generating at least one adjustment per cycle; wherein, the test voltage signal is used to provide test voltages to the gate, source, and / or drain of the target transistor respectively; The digital signal output module is used to convert the drain current of the target transistor into a digital signal.

[0107] Specifically, the DAC module is a module that generates different analog voltages under the control of a code word (digital signal), and is mainly used to generate voltage signals cycle by cycle to provide corresponding voltages to the ports that need to be in the SWEEP state in the unit.

[0108] The on-chip self-adjusting threshold voltage test circuit of this embodiment, while having the beneficial effects of the threshold voltage test circuit, can provide a test circuit with an on-chip self-adjusting type assignment potential to each end of the target transistor according to the threshold voltage monitoring process, and no longer depends on an external instrument to generate a step signal that changes cycle by cycle (that is, the swept-frequency voltage in the test voltage signal). Because the test voltage signal does not need to be input from the outside, the number of external interfaces of the on-chip circuit can be saved, and the external interface can be left for other test requirements.

[0109] In some of these embodiments, the source and drain of the target transistor are respectively connected to an initial voltage, and the gate is connected to a swept-frequency voltage.

[0110] Specifically, the connection method in this embodiment may include direct connection or indirect connection through other components such as other transistors.

[0111] In some of these embodiments, the on-chip self-adjusting threshold voltage test circuit further includes a frequency comparator; The digital signal output module is implemented by a frequency output module (VCO module), where the digital signal is a frequency signal; The frequency comparator is used to compare the frequency signal with a preset reference frequency to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage, and then control the test voltage generation module to adjust the swept-frequency voltage cycle by cycle.

[0112] In some of these embodiments, the on-chip self-adjusting threshold voltage test circuit further includes a voltage stabilizing module (LDO module); the voltage stabilizing module is used to provide a stable power supply voltage to the frequency output module, so as to supply AVDDP (stable voltage) internally after passing AVDD (externally input voltage) through the voltage stabilizing module.

[0113] Specifically, the voltage stabilizing module here is mainly used to provide a stable power supply voltage, stabilize the voltage for the VCO, frequency comparator and other peripheral circuits, reduce the detection error caused by the voltage sensitivity of the peripheral circuits, and ensure the stability of the output result.

[0114] Reference may be made to an on-chip self-adjusting threshold voltage test circuit provided in this embodiment as Figure 9 shown, which includes a storage unit, a switch module, a frequency output module (VCO module), a frequency comparator, a test voltage generation module (DAC module) and a voltage stabilizing module (LDO module).

[0115] The on-chip self-adjusting threshold voltage test circuit of this embodiment can support the free selection of the implementation modes of off-chip input type circuits and on-chip self-adjusting type circuits.

[0116] Embodiment 4 This embodiment provides an addressable multi-functional test circuit, including the addressable threshold voltage test circuit of Embodiment 2, as well as a second control module and a plurality of second driving modules; The second control module is used to provide the address signal and / or control signal required by the second driving module; The second driving module includes a second multiplexer module and a peripheral circuit; Wherein, the second multiplexer module is configured to select a target storage cell from the storage cell array based on the address signal of the second control module, and connect the target storage cell to the peripheral circuit and at least one read / write test signal; The peripheral circuit includes a data input circuit and a data output circuit, and is configured to perform read / write tests on the target storage cell.

[0117] The addressable multi-functional test circuit of this embodiment can switch between two modes of operation. One is the normal read / write performance test mode, and the other is the threshold voltage test mode, thereby providing multi-dimensional monitoring means for SRAM; it supports monitoring the operating margin of storage cells from multiple dimensions without disrupting the normal storage function of the storage cell circuit.

[0118] In some of these embodiments, the second driving module includes a second word line driving module and a second bit line driving module; The second bit line driving module includes a second multiplexer module and a peripheral circuit; The second word line driving module is configured to select the word line where the target storage cell is located based on the address signal and / or control signal of the second control module, and connect the target storage cell to at least one read / write test signal; The data output circuit includes a sense amplifier, and is configured to compare and amplify different bit line voltages.

[0119] Next, in combination with the specific implementation method as follows Figure 10 shown, the addressable multi-functional test circuit of this embodiment will be described in detail. The architecture of an addressable multi-functional test circuit of this embodiment is as follows Figure 10 shown. The circuit includes at least one storage cell array (SRAM bitcell array, i.e., SRAM BCA), two parts of control modules (the first control module VTCTRL, the second control module CTRL), as well as two parts of word line driving modules (the first word line driving module VT_WLDRIVER, the second word line driving module WLDRIVER) and two parts of bit line driving modules (the first bit line driving module VT_BLDRIVER, the second bit line driving module BLDRIVER). This circuit can switch between two modes of operation. One is the normal SRAM TQV mode (read / write performance test mode), and the other is the SRAM VT MONITOR mode (threshold voltage test mode), thereby providing multi-dimensional monitoring means for SRAM.

[0120] Control modules (CTRL, VT CTRL) are used to provide control signals / address signals required in word line driver modules (WLDRIVER, VT_WLDRIVER) and bit line driver modules (BLDRIVER, VT_BLDRIVER).

[0121] The word line driver module includes MUX8 and a switch control module, which are used to provide power supply for the WL port. The bit line driver module is used to provide power supply for ports including BL and BLB. As Figure 4 shown, for monitoring each transistor selected in a bitcell unit, the switch control module includes switch controls from S0 to S10. In this embodiment, S2 belongs to the switch control module in the word line driver module, and the remaining 10 switches belong to the switch control module in the bit line driver module.

[0122] The circuit is divided into two bit line driver modules (BLDRIVER, VT_BLDRIVER) according to different working modes. Each bit line driver module is further divided into multiple groups of bit line driver circuits according to the BCA scale. As Figure 10 taking the 128*128 BCA as an example, each bit line driver module is divided into 16 groups of bit line driver circuits, which are arranged in sequence in the bit line direction; each group of bit line driver circuits corresponds to 8 bitcells (memory cells), which is determined based on the selected MUX8.

[0123] When the circuit operates in the SRAM TQV mode, the BLDRIVER module starts to work. Each bit line driver circuit is composed of modules such as MUX8 (the second multiplexer module), DATA_OUT (data output circuit), and DATA_IN (data input circuit). Here, MUX8 is used as the connection between the BCA and SA modules to select the corresponding bit line for read and write operations, which can realize the multiplexing of peripheral circuits such as SA and avoid waste of additional circuit resources. MUX8 is a multiplexer. Here, an 8-to-1 multiplexer is selected. For each group of bit line driver circuits, it corresponds to 8 bitcells (memory cells), and other specifications of multiplexers can also be selected. DATA_OUT (SA) and DATA_IN modules both belong to peripheral circuits, and each group of bit line driver circuits has its own DATA_OUT (SA) and DATA_IN circuits. DATA_OUT: data output circuit, which is mainly used for driving during the data readout stage. SA is an important module in DATA_OUT. SA: It can also be called a sense amplifier, a sense amplifier circuit, etc. in Chinese, and is mainly used for comparing and amplifying different bit line voltages during the data readout stage. DATA_IN: data input circuit, which is mainly used for driving during the data write stage.

[0124] Similarly, when the circuit switches to the SRAM VT MONITOR mode, the VT_BLDRIVER module is activated. Each bit line driver circuit consists of a MUX8, a switch control module, a current conversion module, and a voltage controlled oscillator module (VCO). It is connected to the BCA through the MUX8 circuit (the first multiplexer module) to achieve the gating of the corresponding bit line and the multiplexing of the peripheral circuit module. The MUX8 circuit here is jointly determined by the bitcell size, peripheral circuit size, etc. in the BCA and can be changed according to the BCA array scale, peripheral circuit size, transmission loss, etc. Similarly, it can be changed to circuits such as MUX4 and MUX16. In this SRAM VT MONITOR mode, the switch control module, current conversion module, and voltage controlled oscillator module are all peripheral functional circuit modules, and each bit line driver circuit has its own set of switch control modules, current conversion modules, and voltage controlled oscillator modules.

[0125] In the SRAM VT MONITOR mode, the bitcell at a specified position in the BCA module can be selected through the control of a part of the VT CTRL circuit. The part of the VT CTRL circuit is implemented by providing an address signal to the mux in the VT_BLDRIVER module. Generally, a decoder can be selected; that is, the corresponding bitcell is first selected through the mux.

[0126] The addressable multi-functional test circuit of this embodiment can switch between the SRAM TQV mode and the SRAM VT MONITOR mode, can monitor the SRAM operating margin from multiple dimensions, and does not damage the normal storage function of the SRAM circuit at the same time.

[0127] Furthermore, this embodiment provides a test chip including the threshold voltage test circuit described in the first aspect.

[0128] Furthermore, this embodiment provides a computer-readable storage medium with a computer program stored thereon. When the computer program is executed by a processor, the foregoing threshold voltage test method is implemented.

[0129] It should be understood that the specific embodiments described here are only used to explain this application, rather than to limit it. According to the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of this application.

[0130] Obviously, the accompanying drawings are only some examples or embodiments of the present application. For those of ordinary skill in the art, the present application can also be applied to other similar situations based on these drawings without creative efforts. Additionally, it can be understood that although the work done during the development process may be complex and time-consuming, for those of ordinary skill in the art, certain design, manufacturing, or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be regarded as insufficient disclosure of the present application.

[0131] The term "embodiment" in the present application means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various positions in the specification and does not necessarily mean the same embodiment, nor does it mean independence or alternative to other embodiments that are mutually exclusive. Those of ordinary skill in the art can clearly or implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0132] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A threshold voltage test circuit, characterized in that: It includes a storage unit, a switch module and a digital signal output module; The memory cell comprises a plurality of transistors; The storage unit is respectively connected to the digital signal output module and at least one test voltage signal through the switch module; The switch module is used to select a target transistor from the storage unit; The test voltage signal is used to provide a test voltage to the gate, source and / or drain of the target transistor respectively; The digital signal output module is used to convert the drain current of the target transistor into a digital signal.

2. A threshold voltage test circuit according to claim 1, characterized in that: The digital signal output module is implemented by a frequency output module, wherein the digital signal is a frequency signal.

3. A threshold voltage test circuit according to claim 2, characterized in that: Also included is a frequency comparator; The frequency comparator is used to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage based on a preset reference frequency and the frequency signal.

4. A threshold voltage test circuit according to claim 3, characterized in that: Also includes: Based on the magnitude relationship of the frequency comparator feedback, the test voltage signal applied to the gate of the target transistor is automatically adjusted.

5. A threshold voltage test circuit according to claim 2, characterized in that: The frequency output module includes a current conversion module and a voltage-controlled oscillator module; The current conversion module is used to convert the drain current of the target transistor into a voltage signal for driving the voltage-controlled oscillator module; The voltage-controlled oscillator module is used to convert the driving voltage output by the current conversion module into a frequency signal output.

6. A threshold voltage test circuit according to claim 2, characterized in that: The frequency output module includes a voltage-stabilized current replication module and a frequency conversion module; The voltage-stabilized current replication module is used to utilize the voltage clamping of the input terminal of the operational amplifier to stabilize the voltage, and to drive at least two transistors to generate the same current signal through the same output voltage of the operational amplifier, so as to achieve accurate replication of the drain current of the target transistor; The frequency conversion module is used to convert the current signal output by the current replication module into a voltage signal, and use the voltage signal to drive the voltage-controlled oscillator to oscillate, so as to output a digital frequency signal.

7. A threshold voltage test circuit according to claim 6, characterized in that: The frequency output module includes two circuit groups that are mirror images of each other, and the circuit groups include a voltage-stabilizing current replication module and a frequency conversion module; The two circuit groups are respectively used to provide drain current connections for different types of target transistors in the memory cell.

8. An addressable threshold voltage test circuit, based on the threshold voltage test circuit design according to any one of claims 1 to 7, characterized in that: The addressable threshold voltage test circuit includes a storage cell array, a first control module and a plurality of first driving modules; The first control module is used to provide an address signal and / or a control signal required by the first driving module; The first driving module includes a first multiplexer module, a switch module and a digital signal output module; Wherein, the first multiplexer module is used to select a target storage unit from the storage unit array based on the address signal of the first control module; The switch module is used to select a target transistor from the target storage unit based on the address signal and / or the control signal of the first control module, and connect the target transistor to the digital signal output module and at least one test voltage signal; The test voltage signal is used to provide a test voltage to the gate, source and / or drain of the target transistor respectively; The digital signal output module is used to convert the drain current of the target transistor into a digital signal.

9. The addressable threshold voltage test circuit according to claim 8, characterized in that: The first driving module includes a first word line driving module and a first bit line driving module; The first word line driving module includes a word line switch module; The first bit line driving module includes a first multiplexer module, a bit line switch module and a frequency output module; the digital signal output module is implemented by the frequency output module, wherein the digital signal is a frequency signal; The switch module includes the word line switch module and the bit line switch module; the word line switch module is used to select the word line where the target transistor is located based on the address signal and / or control signal of the first control module, and connect the target transistor to at least one test voltage signal; the bit line switch module is used to select the bit line where the target transistor is located based on the address signal and / or control signal of the first control module, and connect the target transistor to the frequency output module and at least one test voltage signal.

10. The addressable threshold voltage test circuit according to claim 9, characterized in that: The first bit line driving module further includes a frequency comparator; the frequency comparator is used to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage based on a preset reference frequency and the frequency signal; The first control module determines whether the threshold voltage test of the target transistor is completed based on the magnitude relationship of the feedback from the frequency comparator: If the determination is completed, the address signal is adjusted to control the first driving module to select the next target transistor to be tested until the threshold voltage test of all transistors to be tested in the memory cell array is completed.

11. An on-chip self-adjusting threshold voltage test circuit, based on the threshold voltage test circuit design according to any one of claims 1 to 7, characterized in that: The on-chip self-adjusting threshold voltage test circuit comprises a storage unit, a switch module, a digital signal output module and a test voltage generation module; The memory cell comprises a plurality of transistors; The storage unit is respectively connected to the test voltage generation module and the digital signal output module through the switch module; The switch module is used to select a target transistor from the storage unit; The test voltage generating module is used to provide at least one test voltage signal to the target transistor; the test voltage generating module includes a module for generating at least one swept-frequency voltage output adjusted cycle by cycle; wherein the test voltage signal is used to provide a test voltage to the gate, source and / or drain of the target transistor respectively; the digital signal output module is used to convert the drain current of the target transistor into a digital signal.

12. The on-chip self-adjusting threshold voltage test circuit according to claim 11, characterized in that: The source and drain of the target transistor are respectively connected to the initial voltage, and the gate of the target transistor is connected to the sweep voltage.

13. The on-chip self-adjusting threshold voltage test circuit according to claim 12, characterized in that: Also included is a frequency comparator; The digital signal output module is implemented by a frequency output module, wherein the digital signal is a frequency signal; The frequency comparator is used to compare the frequency signal with a preset reference frequency to determine the magnitude relationship between the test voltage signal applied to the gate of the target transistor and the threshold voltage, and then control the test voltage generation module to adjust the sweep voltage cycle by cycle.

14. The on-chip self-adjusting threshold voltage test circuit according to claim 13, characterized in that: It also includes a voltage regulator module; The voltage stabilizing module is used to provide a stable power supply voltage to the frequency output module.

15. An addressable multifunctional test circuit, characterized in that: The addressable threshold voltage test circuit according to claim 8, as well as a second control module and a plurality of second driving modules; The second control module is used to provide an address signal and / or a control signal required by the second driving module; The second driving module includes a second multiplexer module and a peripheral circuit; Wherein, the second multiplexer module is used to select a target memory cell from the memory cell array based on the address signal of the second control module, and connect the target memory cell to the peripheral circuit and at least one read / write test signal; The peripheral circuit includes a data input circuit and a data output circuit, which are used to perform a read and write test on the target storage unit.

16. The addressable multifunctional test circuit according to claim 15, characterized in that: The second driving module includes a second word line driving module and a second bit line driving module; The second bit line driver module includes a second multiplexer module and a peripheral circuit; The second word line driving module is used to select the word line where the target storage unit is located based on the address signal and / or control signal of the second control module, and connect the target storage unit to at least one read-write test signal; The data output circuit includes a sense amplifier for comparing and amplifying different bit line voltages.

17. A threshold voltage test method, based on the threshold voltage test circuit design according to any one of claims 1 to 7, characterized in that: The threshold voltage testing method comprises the steps of: Step S1: controlling the switch module to select a target transistor and providing initial voltages to the gate, source and drain of the target transistor respectively; Step S2: providing a swept frequency voltage to the gate of the target transistor through a switch module; Step S3: Determine the magnitude relationship between the current voltage signal applied to the gate of the target transistor and the threshold voltage through the digital signal of the digital signal output module, thereby controlling the cycle-by-cycle adjustment of the sweep voltage and determining whether the threshold voltage test of the target transistor is completed.

18. A threshold voltage testing method according to claim 17, characterized in that: The digital signal output module is implemented by a frequency output module, wherein the digital signal is a frequency signal; In the step S3, judging the magnitude relationship between the current voltage signal applied to the gate of the target transistor and the threshold voltage by using the frequency signal of the frequency output module includes: If F out <F ref , then the gate-source voltage applied to the target transistor is less than the linear threshold voltage; If F out ≈F ref , then the gate-source voltage applied to the target transistor is approximately equal to the linear threshold voltage; If F out >F ref , then the gate-source voltage applied to the target transistor is greater than the linear threshold voltage; Among them, the F ref It refers to the reference current I of the frequency output module in the target transistor ref The reference frequency of the output under the drive; The F out It means that the frequency output module generates a frequency signal for output; The gate-source voltage refers to the voltage difference between the gate voltage and the source voltage on the target transistor.

19. A test chip, characterized in that: A threshold voltage test circuit comprising any one of claims 1 to 7.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the threshold voltage testing method according to any one of claims 17 to 18 is implemented.

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