Tray and carrying device

Abstract

The invention provides a conveying method in a substrate processing system. The conveying method in the substrate processing system comprises a tray feeding step, a measuring step, an adjusting step, a substrate carrying step and a tray discharging step. In the tray feeding step, a tray on which a semiconductor substrate and an edge ring can be mounted is fed into a mounting chamber provided with a mounting table. In the measuring step, the position of the edge ring placed on the tray is measured to acquire position information of the edge ring. In the adjusting step, the position of the semiconductor substrate is adjusted based on the obtained position information. In the substrate placing step, the semiconductor substrate after position adjustment is placed on a tray. In the tray feeding step, the tray on which the semiconductor substrate and the edge ring are placed is fed from the placement chamber. The present invention enables a semiconductor substrate to be arranged at a correct position with respect to an edge ring.

Description

[0001] This case is a divisional application of the application named "Transportation Method in a Substrate Processing System" with an application date of August 3, 2020 and an application number of 202010766400.9. Technical Field

[0002] The present invention relates to a tray and a mounting device. Background Art

[0003] Sometimes, in the plasma processing of semiconductor substrates, an edge ring (also called a focusing ring) is arranged along the outer periphery of the semiconductor substrate arranged in a chamber (processing container) having a predetermined degree of vacuum. By arranging the edge ring, the plasma at the outer peripheral portion of the semiconductor substrate can be controlled, so that the processing can be uniformly performed at the outer peripheral portion and the central portion of the semiconductor substrate. At this time, the positional relationship between the semiconductor substrate and the edge ring becomes important. Therefore, it is required to correctly transport the semiconductor substrate to the edge ring.

[0004] In addition, the edge ring is consumed by plasma processing, so it needs to be replaced regularly. The replacement of the edge ring is usually performed by opening the atmosphere in the chamber in which the edge ring is arranged. As a method of replacing the edge ring without opening the atmosphere in the chamber, a method has been proposed in which an edge ring storage chamber connected to a vacuum transfer chamber is provided, and the edge ring is transferred to the chamber using the transfer mechanism of the vacuum transfer chamber.

[0005] In addition, a technique is known in which a semiconductor substrate is mounted on a tray and transported into a chamber through each tray.

[0006] Prior Art Documents

[0007] Patent Documents

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-084872

[0009] Patent Document 2: Japanese Patent Application Laid-Open No. 2006-196691

[0010] Patent Document 3: Japanese Patent Application Laid-Open No. 2011-114178 Summary of the Invention

[0011] Technical Problem to be Solved by the Invention

[0012] Generally, a semiconductor substrate is transported into a chamber via an atmospheric transfer chamber, a load lock chamber, and a vacuum transfer chamber. Therefore, even if the transfer mechanism is controlled to correctly transfer the semiconductor substrate to the edge ring disposed in the chamber, there is a possibility that the semiconductor substrate may shift from the transfer mechanism and cannot be correctly transferred during the period until the semiconductor substrate is transferred into the chamber. In addition, when the edge ring is transferred into the chamber using the transfer mechanism of the vacuum transfer chamber, it is necessary to correctly transfer and place the edge ring on the placement table for placing the edge ring.

[0013] The present invention provides a technique capable of disposing a semiconductor substrate at a correct position relative to an edge ring.

[0014] Technical solution for solving technical problems

[0015] The transfer method in the substrate processing system according to one aspect of the present invention includes a tray feeding step, a measurement step, an adjustment step, a substrate placement step, and a tray discharging step. In the tray feeding step, a tray capable of placing a semiconductor substrate and an edge ring is fed into a placement chamber provided with a placement table. In the measurement step, the position of the edge ring placed on the tray is measured to obtain the position information of the edge ring. In the adjustment step, based on the obtained position information, the position of the semiconductor substrate is adjusted. In the substrate placement step, the semiconductor substrate with the adjusted position is placed on the tray. In the tray discharging step, the tray on which the semiconductor substrate and the edge ring are placed is discharged from the above placement chamber.

[0016] Advantages of the invention

[0017] According to the technique of the present invention, a semiconductor substrate can be disposed at a correct position relative to an edge ring. Brief description of the drawings

[0018] Figure 1 It is a diagram showing a structural example of a substrate processing system.

[0019] Figure 2 It is a diagram showing a structural example of a processing device.

[0020] Figure 3 It is a diagram showing an example of the shape of a tray.

[0021] Figure 4 It is a diagram showing an example of the shape of an edge ring placed on a tray.

[0022] Figure 5 It is a diagram showing an example of the shapes of an edge ring and a wafer placed on a tray.

[0023] Figure 6 It is a diagram showing a structural example of a placement device.

[0024] Figure 7It is a flowchart showing an example of the processing sequence of the conveying method.

[0025] Figure 8 It is a diagram showing an example of the conveying method.

[0026] Figure 9 It is a diagram showing an example of the conveying method.

[0027] Figure 10 It is a diagram showing an example of the conveying method.

[0028] Figure 11 It is a diagram showing an example of the conveying method.

[0029] Figure 12 It is a graph showing the relationship between the electrostatic capacitance per unit area and the attractive force per unit area of the electrostatic chuck of the processing apparatus.

[0030] Figure 13 It is a diagram showing the positional relationship between the rotation angle sensor and the horizontal position sensor.

[0031] Figure 14 It is a diagram showing the correct positional relationship between the edge ring and the wafer.

[0032] Figure 15 It is a diagram showing an example of the position adjustment of the wafer.

[0033] Figure 16 It is a diagram showing an example of the position adjustment of the wafer.

[0034] Figure 17 It is a diagram showing an example of the position adjustment of the wafer.

[0035] Figure 18 It is a diagram showing an example of the position adjustment of the wafer.

[0036] Figure 19 It is a diagram showing a structural example of a substrate processing system in which the tray storage unit 5 is connected to the vacuum transfer chamber.

[0037] Figure 20 It is a diagram showing an example of a tray in which the edge ring placement portion and the substrate placement portion are formed at the same height.

[0038] Figure 21 It is a diagram showing an example of applying a DC voltage to the tray body without using the lift pins.

[0039] Figure 22 It is a diagram showing another example of applying a DC voltage to the tray body without using the lift pins.

[0040] Figure 23 It is a diagram showing another example of applying a DC voltage to the tray body without using the lift pins.

[0041] Figure 24 This is a diagram showing an example of discharging the wafer W without using a lift pin.

[0042] Figure 25 This is a diagram showing another example of discharging the wafer W without using a lift pin.

[0043] Figure 26 This is a diagram showing an example of a tray that functions as a bipolar electrostatic chuck.

[0044] Figure 27 This is a diagram showing an example of a mounting device for mounting the mounting tray TR8.

[0045] Description of Reference Numerals

[0046] 100, 200 Substrate Processing System

[0047] 2 Edge Ring Storage Section

[0048] 3 Aligner

[0049] 4 Processing Device

[0050] 5 Tray Storage Section

[0051] 11 Atmospheric Transfer Chamber

[0052] 12 Load Lock Chamber

[0053] 13 Vacuum Transfer Chamber

[0054] 14 FOUP

[0055] 15 First Transfer Mechanism

[0056] 16 Second Transfer Mechanism. Detailed Embodiment

[0057] Hereinafter, embodiments of the technology of the present invention will be described based on the drawings. In the following embodiments, the same reference numerals are assigned to the same structures, and repeated descriptions are omitted.

[0058] <Structure of Substrate Processing System>

[0059] Figure 1 This is a diagram showing an example of the structure of a substrate processing system.

[0060] In Figure 1In this case, the substrate processing system 100 includes a FOUP 14, an atmospheric transfer chamber 11, an edge-ring stocker 2, a tray stocker 5, an aligner 3, a load lock room 12, a vacuum transfer chamber 13, a processing device 4, a first transfer mechanism 15, and a second transfer mechanism 16.

[0061] The FOUP 14 is a container capable of accommodating semiconductor substrates (hereinafter sometimes referred to as "wafers") and has an openable and closable lid. When the FOUP 14 accommodating wafers is assembled in the atmospheric transfer chamber 11, the lid of the FOUP 14 engages with the gate door GT of the atmospheric transfer chamber 11 and the latch of the lid of the FOUP 14 is released, bringing it into a state where the lid of the FOUP 14 can be opened. In this state, by opening the gate GT, the lid of the FOUP 14 moves together with the gate GT and the lid of the FOUP 14 opens, allowing the inside of the FOUP 14 to communicate with the inside of the atmospheric transfer chamber 11.

[0062] The atmospheric transfer chamber 11 is maintained in an atmospheric atmosphere and is connected to the edge-ring stocker 2 and the tray stocker 5 via an openable and closable opening / closing member 23. A plurality of edge rings are stored in the edge-ring stocker 2. A plurality of trays are stored in the tray stocker 5. In addition, the atmospheric transfer chamber 11 is connected to the aligner 3 via an opening 22. Further, a first transfer mechanism 15 is provided in the atmospheric transfer chamber 11, and the first transfer mechanism 15 transfers wafers, edge rings, and trays between the FOUP 14, the edge-ring stocker 2, the tray stocker 5, the aligner 3, and the load lock room 12. The first transfer mechanism 15 includes a base 15a, an articulated arm 15b, and a picker 15c. The proximal end side of the arm 15b is connected to the base 15a, and the distal end side of the arm 15b is connected to the picker 15c. The base 15a is capable of moving in the arrow direction (the long side direction of the atmospheric transfer chamber 11) within the atmospheric transfer chamber 11. The picker 15c is formed in a U shape and supports wafers, edge rings, and trays. When the picker 15c takes out an edge ring from the edge-ring stocker 2, the opening / closing member 23 between the edge-ring stocker 2 and the atmospheric transfer chamber 11 is opened, and when the picker 15c takes out a tray from the tray stocker 5, the opening / closing member 23 between the tray stocker 5 and the atmospheric transfer chamber 11 is opened.

[0063] The atmospheric transfer chamber 11 and the vacuum transfer chamber 13 are connected via the load lock chamber 12. The inside of the vacuum transfer chamber 13 is maintained in a vacuum atmosphere. The atmospheric transfer chamber 11 and the load lock chamber 12, as well as the vacuum transfer chamber 13 and the load lock chamber 12, are separated by gate valves G. Normally, the gate valves G are closed. When the wafer, edge ring or tray is transferred from the atmospheric transfer chamber 11 into the load lock chamber 12 by the first transfer mechanism 15, the gate valve G provided between the atmospheric transfer chamber 11 and the load lock chamber 12 is opened. In addition, when the tray carrying the edge ring and wafer is taken out from the load lock chamber 12 and transferred into the vacuum transfer chamber 13 by the second transfer mechanism 16, the gate valve G provided between the load lock chamber 12 and the vacuum transfer chamber 13 is opened.

[0064] A vacuum pump (not shown) serving as an exhaust mechanism and a leak valve (not shown) for restoring the pressure to atmospheric pressure are provided in the load lock chamber 12, and the inside of the load lock chamber 12 can be switched between an atmospheric atmosphere and a vacuum atmosphere. When the wafer, edge ring or tray is transferred from the atmospheric transfer chamber 11 into the load lock chamber 12 by the first transfer mechanism 15, the inside of the load lock chamber 12 is switched to an atmospheric atmosphere. When the tray carrying the wafer and edge ring is taken out from the load lock chamber 12 and transferred into the vacuum transfer chamber 13 by the second transfer mechanism 16, the inside of the load lock chamber 12 is switched to a vacuum atmosphere.

[0065] The second transfer mechanism 16 is provided inside the vacuum transfer chamber 13. The second transfer mechanism 16 exchanges the tray carrying the wafer and edge ring between the load lock chamber 12 and the processing device 4. The second transfer mechanism 16 has a base 16a, an articulated arm 16b, and a picker 16c. The root end side of the arm 16b is connected to the base 16a, and the front end side of the arm 16b is connected to the picker 16c. The base 16a can move in the arrow direction (the long side direction of the vacuum transfer chamber 13) inside the vacuum transfer chamber 13. The picker 16c is formed in a U shape and supports the tray carrying the wafer and edge ring.

[0066] The vacuum transfer chamber 13 and the processing device 4 are separated by a gate valve G. Normally, the gate valve G is closed. When the tray carrying the wafer and edge ring is transferred from the vacuum transfer chamber 13 into the processing device 4 by the second transfer mechanism 16, the gate valve G provided between the vacuum transfer chamber 13 and the processing device 4 is opened.

[0067] The processing device 4 processes the wafer as the object to be processed in a vacuum atmosphere. The processing device 4 performs processes such as etching and film formation on the wafer placed on the tray.

[0068] <Structure of the processing device>

[0069] Figure 2 It is a diagram showing a structural example of the processing device. Figure 2The processing device 4 shown constitutes a parallel-plate substrate processing device of a capacitive coupling type.

[0070] exist Figure 2 In the embodiment, the processing apparatus 4 includes a processing container, that is, a chamber 10, which is made of a metal such as aluminum or stainless steel. The chamber 10 is securely grounded.

[0071] A disc-shaped susceptor 12 is horizontally arranged in the chamber 10. A tray TR1 carrying a wafer W and an edge ring ER is placed on the susceptor 12. The susceptor 12 also functions as a lower electrode. A gate valve G for opening and closing a wafer W inlet and outlet is installed on the side wall of the chamber 10. The susceptor 12 is made of a metal such as aluminum, and is supported by an insulating cylindrical support 14 extending vertically upward from the bottom of the chamber 10.

[0072] An annular exhaust passage 18 is formed between a conductive cylindrical support portion (inner wall portion) 16 extending vertically upward from the bottom of the chamber 10 along the outer circumference of the cylindrical support portion 14 and the side wall of the chamber 10. An exhaust port 22 is provided at the bottom of the exhaust passage 18.

[0073] The exhaust port 22 is connected to an exhaust device 26 via an exhaust pipe 24. The exhaust device 26 includes a vacuum pump such as a turbomolecular pump and can reduce the pressure of the processing space PS in the chamber 10 to a desired vacuum level. The chamber 10 is preferably maintained at a constant pressure in the range of 10 mTorr to 3500 mTorr.

[0074] On the susceptor 12, a wafer W as a substrate processing target is placed via the tray TR1, and an edge ring ER is arranged to surround the wafer W. The edge ring ER is made of a conductive material such as Si, SiC, or SiO. 2 It is made of insulating materials such as , and is placed on the upper surface of the tray TR1.

[0075] In addition, an electrostatic chuck 40 for wafer adsorption is provided on the upper surface of the susceptor 12. The electrostatic chuck 40 is formed by sandwiching a sheet-like or mesh-like conductor between a film-like or plate-like dielectric. The conductor in the electrostatic chuck 40 is electrically connected to a DC power supply 42 disposed outside the chamber 10 via a switch 44 and a power supply line 46. The wafer W is electrostatically adsorbed to the electrostatic chuck 40 via the tray TR1 by utilizing the Coulomb force generated in the electrostatic chuck 40 by the DC voltage applied from the DC power supply 42 to the electrostatic chuck 40 when the switch 44 is turned on.

[0076] An annular coolant chamber 48 extending in the circumferential direction is provided inside the susceptor 12. A coolant (e.g., cooling water) at a predetermined temperature is circulated and supplied to the coolant chamber 48 from a cooling unit (not shown) via pipes 50 and 52. By controlling the temperature of the coolant, the temperature of the wafer W can be controlled. Furthermore, in order to improve the accuracy of the temperature of the wafer W, a heat transfer gas (e.g., He gas) from a heat transfer gas supply unit (not shown) is supplied between the tray TR1 and the wafer W via a gas supply pipe 51 and a gas passage 56 in the susceptor 12.

[0077] A disk-shaped upper electrode 60 is provided on the top of the chamber 10 so as to be parallel to (ie, face) the susceptor 12. The upper electrode 60 is mounted on the top of the chamber 10 via a ring-shaped insulator 98 made of, for example, ceramic.

[0078] The upper electrode 60 includes: an electrode plate 64 that is exactly face-to-face with the base 12; and an electrode support 66 that can detachably support the electrode plate 64 from the back (top) of the electrode plate 64. As the material of the electrode plate 64, a conductive material such as Si or Al is preferred. The electrode support 66 is composed of, for example, aluminum that has been subjected to an acid-resistant aluminum treatment. As described above, in the processing device 4, the disc-shaped base 12 (i.e., the lower electrode) and the disc-shaped upper electrode 60 are arranged parallel to each other.

[0079] The gas supply unit 76 supplies the processing gas to the chamber 10. In order to supply the processing gas to the processing space PS set between the upper electrode 60 and the susceptor 12, the upper electrode 60 is used as a shower head. In more detail, a gas diffusion chamber 72 is provided inside the electrode support 66, and a large number of gas release holes 74 that penetrate from the gas diffusion chamber 72 to the susceptor 12 side are formed in the electrode support 66 and the electrode plate 64. The gas inlet port 72a provided at the upper part of the gas diffusion chamber 72 is connected to the gas supply pipe 78 extending from the gas supply unit 76.

[0080] The upper electrode 60 is connected to the first RF (Radio Frequency) power supply 150 via the first matcher 152. The first matcher 152 can match the impedance of the first RF power supply 150 side with the impedance of the load (mainly the electrode, plasma, chamber) side. The first RF power supply 150 can apply a high-frequency voltage for plasma generation having a frequency in the range of 30 to 150 MHz to the upper electrode 60. By applying a high-frequency voltage to the upper electrode 60 in this way, plasma can be generated in a preferred dissociated state and at a high density in the processing space PS, and plasma processing can be performed under lower pressure conditions. The frequency of the output voltage of the first RF power supply 150 is preferably 50 to 80 MHz, and is typically adjusted to a frequency of 60 MHz or thereabouts.

[0081] The base 12 serving as the lower electrode is connected to the second RF power supply 160 via the second matcher 162 and the connecting rod 36. The second matcher 162 can match the impedance on the second RF power supply 160 side with the impedance on the load (mainly the electrode, plasma, chamber) side. The second RF power supply 160 can apply a high-frequency voltage for bias with a frequency in the range of several hundred kHz to several tens of MHz to the base 12. The frequency of the output voltage of the second RF power supply 160 is typically adjusted to 2 MHz or 13.56 MHz, etc.

[0082] <Shape of the tray, edge ring, and wafer>

[0083] Figure 3 It is a diagram showing an example of the shape of the tray. Figure 4 It is a diagram showing an example of the shape of the edge ring placed on the tray. Figure 5 It is a diagram showing an example of the shape of the edge ring and wafer placed on the tray.

[0084] As Figure 3 shown, the tray TR1 has a disk shape and includes: a conductive tray body 101; a dielectric film 102 formed so as to cover the periphery of the tray body 101; a lift pin contact portion 103; and through holes 104, 105, 106. The through hole 104 is a through hole for supplying a heat transfer gas between the tray TR1 and the wafer W via a gas passage 56 ( Figure 2 ) in the processing apparatus 4. The through hole 105 is a through hole for a lift pin for lifting the wafer W. The through hole 106 is a through hole for a lift pin for lifting the edge ring ER. The lift pin contact portion 103 is a part of the back surface of the tray body 101 where the lift pin for lifting the tray TR1 contacts, and the dielectric film 102 is not formed. The lift pin contact portion 103 can be formed as a concave portion corresponding to the shape of the lift pin. In addition, a substrate placement portion 108 capable of placing the wafer W and an edge ring placement portion 107 capable of placing the edge ring ER are formed on the upper surface of the tray TR1. The edge ring placement portion 107 is provided around the substrate placement portion 108. That is, each of the substrate placement portion 108 and the edge ring placement portion 107 has: a conductive tray body 101; and a dielectric film 102 formed so as to cover the periphery of the tray body 101. In addition, the edge ring placement portion 107 is formed at a position lower than the substrate placement portion 108. In addition, the dielectric film 102 only needs to be formed on at least the upper surface of the tray body 101.

[0085] In addition, as Figure 4As shown, the edge ring ER has an annular shape. The outer peripheral portion of the edge ring ER is circular. In contrast, a flat portion FL having a flat shape is formed in a part of the inner peripheral portion of the edge ring ER. The edge ring ER is placed on the edge ring placement portion 107 on the upper surface of the tray TR1. In addition, the inner peripheral portion of the edge ring ER is formed thinner than the outer peripheral portion of the edge ring ER. That is, the inner peripheral portion of the edge ring ER is formed such that when the edge ring ER is placed on the edge ring placement portion 107, the upper surface of the inner peripheral portion of the edge ring ER is substantially at the same height as the upper surface of the substrate placement portion 108 or lower than the upper surface of the substrate placement portion 108. In addition, the outer peripheral portion of the edge ring ER is formed such that when the wafer W is placed on the substrate placement portion 108 on the upper surface of the tray TR1, the upper surface of the outer peripheral portion of the edge ring ER is substantially at the same height as the upper surface of the wafer W or higher than the upper surface of the wafer W.

[0086] In addition, as Figure 5 shown, the wafer W has a disk shape, and a V-shaped notch NT is formed in a part of the outer periphery of the wafer W. The wafer W is placed on the substrate placement portion 108 on the upper surface of the tray TR1. When the wafer W is placed on the substrate placement portion 108, the wafer W is placed such that the notch NT overlaps with the flat portion FL of the edge ring ER. As described above, the substrate placement portion 108 includes: a support surface that supports the back surface of the wafer W; and through holes 104 and 105 that penetrate the tray body 101 and the dielectric film 102. In addition, the area of the substrate placement portion 108 is smaller than the area of the wafer W. That is, when the wafer W is placed, the outer peripheral portion of the wafer W having the notch NT is located at a position outside the outer periphery of the substrate placement portion 108 and on the inner peripheral portion of the edge ring ER.

[0087] As described above, the wafer W and the edge ring ER can be placed on the tray TR1.

[0088] <Structure of the placement device>

[0089] Figure 6 is a diagram of a structural example of the placement device. In the present embodiment, as Figure 6 shown, the placement device 12A is used as the load lock chamber 12. In Figure 6In [the device], the placement device 12A includes a container 201, a rotation angle sensor 202, a horizontal position sensor 203, a placement table 204, a first lifting pin 205, a second lifting pin 206, a third lifting pin 207, a DC power supply 208, and a switch 209. The rotation angle sensor 202 is provided on the upper wall of the container 201, and the horizontal position sensor 203 is provided on the side wall of the container 201. The placement table 204 is accommodated in the conductive container 201. In addition, the placement device 12A includes: a first lifting mechanism (not shown) that raises and lowers the first lifting pin 205; a second lifting mechanism (not shown) that raises and lowers the second lifting pin 206 independently of the first lifting pin 205; and a third lifting mechanism (not shown) that raises and lowers the third lifting pin 207 independently of the first lifting pin 205 and the second lifting pin 206. The first lifting pin 205, the second lifting pin 206, and the third lifting pin 207 are made of a conductive material (such as Ni, Al, etc.). The first lifting pin 205 is connected to the DC power supply 208 via the switch 209. The second lifting pin 206 and the third lifting pin 207 are grounded. In addition, a vacuum pump (not shown) and a leak valve (not shown) are provided in the placement device 12A. The vacuum pump serves as an exhaust mechanism capable of making the pressure inside the container 201 lower than the atmospheric pressure, and the leak valve is used to restore the pressure inside the container 201 to the atmospheric pressure.

[0090] <Transport Method in a Substrate Processing System>

[0091] Figure 7 It is a flowchart showing an example of the processing sequence of the transport method. Figures 8 - 11 It is a diagram showing an example of the transport method.

[0092] In Figure 7 first, through step S1, the tray TR1 is transported to the load lock chamber 12 using the first transport mechanism 15. The tray TR1 is stored in the tray storage unit 5 connected to the atmospheric transport chamber 11. The tray TR1 is sent out from the tray storage unit 5 by the first transport mechanism 15, and the tray TR1 placed on the picker 15c is sent into the load lock chamber 12 (inside the placement device 12A). At this time, the pressure inside the load lock chamber 12 becomes the atmospheric pressure.

[0093] Next, through step S2, the tray TR1 is placed on the placement table 204 inside the load lock chamber 12. As Figure 8 shown, the first lifting pin 205 is raised to separate the tray TR1 from the picker 15c (i.e., raise the tray TR1). At this time, the first lifting pin 205 contacts the lifting pin contact portion 103 on the back surface of the tray body 101.

[0094] Next, while maintaining the position of the first lifting pin 205 at the position shown in Figure 8 the picker 15c is withdrawn from the load lock chamber 12.

[0095] Next, by lowering the first lifting pin 205 (i.e., lowering the tray TR1), the tray TR1 is placed on the placement table 204.

[0096] Next, in step S3, the edge ring ER is conveyed to the load lock chamber 12 by the first conveying mechanism 15. The edge ring ER is stored in the edge ring storage unit 2 connected to the atmospheric conveying chamber 11. The edge ring ER is sent out from the edge ring storage unit 2 by the first conveying mechanism 15, and the edge ring ER placed on the pick-up 15c is sent into the load lock chamber 12.

[0097] Next, in step S4, the edge ring ER is placed on the tray TR1 of the placement table 204 placed in the load lock chamber 12. As Figure 9 shown, the third lifting pin 207 is raised to separate the edge ring ER from the pick-up 15c (i.e., raise the edge ring ER). At this time, the third lifting pin 207 contacts the back surface of the edge ring ER through the through hole 106 of the tray TR1. Since the third lifting pin 207 is grounded, the edge ring ER can be discharged by the front end of the third lifting pin 207 contacting the back surface of the edge ring ER.

[0098] Next, while maintaining the position of the third lifting pin 207 at the Figure 9 position shown, the pick-up 15c is withdrawn from the load lock chamber 12.

[0099] Next, by lowering the third lifting pin 207 (i.e., lowering the edge ring ER), the edge ring ER is placed on the tray TR1.

[0100] Next, in step S5, the position of the edge ring ER placed on the tray TR1 is measured. As Figure 10As shown, the position of the edge ring ER placed on the tray TR1 is measured using the rotation angle sensor 202 and the horizontal position sensor 203, and the position information of the edge ring ER is obtained. The signal representing the obtained position information is transmitted to the aligner 3. The rotation angle sensor 202 can be implemented using, for example, a CCD (Charge-Coupled Device). By photographing the flat portion FL from above the edge ring ER, the rotation angle RA of the edge ring ER relative to a predetermined reference position RP is measured, and the rotation angle information RAI representing the rotation angle RA is obtained as the first position information of the edge ring ER. The horizontal position sensor 203 can be implemented using, for example, a laser that irradiates the edge ring ER from the side of the edge ring ER. By measuring the distance between the horizontal position sensor 203 and the outer periphery of the edge ring ER, the horizontal position deviation HP of the edge ring ER in the horizontal direction relative to the predetermined reference position RP is measured, and the horizontal position information HPI representing the position deviation HP is obtained as the second position information of the edge ring ER. Thus, the position information transmitted from the load lock chamber 12 to the aligner 3 includes the rotation angle information RAI of the edge ring ER and the horizontal position information HPI of the edge ring ER.

[0101] Next, through step S6, the position of the wafer W is adjusted in the aligner 3. The wafer W is transported from the FOUP 14 to the inside of the aligner 3 by the first transport mechanism 15. Then, the aligner 3 adjusts the position of the wafer W based on the position information transmitted from the load lock chamber 12. That is, the aligner 3 rotates the wafer W based on the rotation angle information RAI of the edge ring ER, and on the other hand, adjusts the horizontal position of the wafer W based on the horizontal position information HPI of the edge ring ER. The details of adjusting the position of the wafer W will be described later.

[0102] Next, through step S7, the wafer W is transported to the load lock chamber 12 using the first transport mechanism 15. The wafer W after position adjustment is placed on the picker 15c of the first transport mechanism 15, sent out from the aligner 3, and sent into the load lock chamber 12 above the stage 204.

[0103] Next, through step S8, the wafer W is placed on the tray TR1 of the stage 204 placed in the load lock chamber 12. As Figure 11 shown, the second lift pin 206 is raised to separate the wafer W from the picker 15c (i.e., raise the wafer W). At this time, the second lift pin 206 contacts the back surface of the wafer W through the through hole 105 of the tray TR1. Since the second lift pin 206 is grounded, the wafer W can be discharged by the front end of the second lift pin 206 contacting the back surface of the wafer W.

[0104] Next, while maintaining the position of the second lift pin 206 at Figure 11In the state of the position shown, the picker 15c is withdrawn from the load lock chamber 12.

[0105] Next, by lowering the second lift pin 206 (i.e., lowering the wafer W), the wafer W is placed on the tray TR1.

[0106] Next, in step S9, a DC voltage is applied to the tray body 101. The inside of the container 201 is evacuated with a vacuum pump, and the first lift pin 205 contacts the lift pin contact portion 103. By turning on the switch 209 to connect the first lift pin 205 to the DC power supply 208, the DC power supply 208 applies a positive DC voltage to the first lift pin 205. By applying a positive DC voltage to the first lift pin 205, a positive DC voltage can be applied to the tray body 101 from the DC power supply 208 via the first lift pin 205 and the lift pin contact portion 103. Due to the Coulomb force generated in the tray TR1 by the DC voltage applied to the tray body 101, the wafer W is electrostatically adsorbed to the tray TR1. In addition, when the material of the edge ring ER is a conductive material such as Si or SiC, for example, the edge ring ER is also electrostatically adsorbed to the tray TR1. As described above, the wafer W is adsorbed to the tray TR1 by the action of bringing the first lift pin 205 into contact with the back surface of the tray body 101 and applying a DC voltage to the tray body 101 via the first lift pin 205.

[0107] Next, in step S10, the tray TR1 on which the edge ring ER and the wafer W are placed is sent into the processing apparatus 4. By turning off the switch 209 to stop applying the DC voltage to the tray body 101, on the other hand, the first lift pin 205 is raised in a state where the tip of the first lift pin 205 contacts the back surface of the tray TR1. After stopping the application of the DC voltage to the tray body 101, the tray TR1 is also in a charged state, so that the wafer W can be adsorbed and held on the tray TR1.

[0108] Next, the tray TR1 is sent out by the second transfer mechanism 16 in the vacuum transfer chamber 13. The picker 16c of the second transfer mechanism 16 is inserted into the load lock chamber 12 so that the picker 16c is located below the tray TR1 lifted by the first lift pin 205.

[0109] Next, by lowering the first lift pin 205, the tray TR1 is placed on the picker 16c. Then, the picker 16c is withdrawn from the load lock chamber 12, and the tray TR1 on which the wafer W and the edge ring ER are placed is transferred from the load lock chamber 12 to the processing apparatus 4 by the second transfer mechanism 16.

[0110] During the time when the tray TR1 carrying the wafer W and the edge ring ER is transported from the load lock chamber 12 to the processing apparatus 4, the tray TR1 is still in a charged state, so the wafer W after position adjustment continues to be adsorbed on the tray TR1. Thus, the position of the wafer W after position adjustment can be prevented from shifting during the process of transporting the wafer W from the load lock chamber 12 to the processing apparatus 4.

[0111] In addition, the edge ring ER is generally heavier than the wafer W. Therefore, when the tray TR1 is transported from the load lock chamber 12 to the processing device 4, the edge ring ER is less likely to shift than the wafer W. Therefore, even if the edge ring ER is made of SiO 2 However, when the edge ring ER is made of a conductive material such as Si or SiC, not only the wafer W but also the edge ring ER can be attracted to the tray TR1, which is more effective.

[0112] The tray TR1 transported to the processing device 4 is placed on the susceptor 12 (electrostatic chuck 40) in the processing device 4. The susceptor 12 is provided with lifting pins (not shown), and the tray TR1 is placed on the susceptor 12 (electrostatic chuck 40) in the same order as step S2. After the tray TR1 is placed on the electrostatic chuck 40, the switch 44 is turned on, and a DC voltage is applied to the electrostatic chuck 40 by the DC power supply 42. As a result, the wafer W is attracted to the electrostatic chuck 40 via the tray TR1.

[0113] Next, in step S11 , plasma processing such as etching is performed.

[0114] After the plasma treatment is completed, the tray TR1 carrying the edge ring ER and the wafer W is sent out from the processing device 4 in step S12. The tray TR1 sent out from the processing device 4 is placed on the placement table 204 in the load lock chamber 12. After the pressure in the load lock chamber 12 is restored to atmospheric pressure using a leak valve (not shown), the wafer W is sent out from the load lock chamber 12 by the first transport mechanism 15. The sent out wafer W is stored in the FOUP 14.

[0115] The edge ring ER and the tray TR1 may be stored in the edge ring storage unit 2 and the tray storage unit 5, respectively, or may not be stored. A new wafer W may be introduced while the edge ring ER and the tray TR1 are placed on the stage 204 in the load lock chamber 12. That is, the next process may be started from step S5 or step S6. In addition, when replacing the consumed edge ring ER, the consumed edge ring ER may be stored in the edge ring storage unit 2 and a new edge ring ER may be introduced. That is, the next process may be started from step S3.

[0116] <Attraction of electrostatic chuck>

[0117] The tray TR1 carried into the processing apparatus 4 in step S10 is placed on the electrostatic chuck 40. Therefore, the wafer W is not placed directly on the electrostatic chuck 40 but is placed via the tray TR1. Figure 12 This is a graph showing the relationship between the electrostatic capacitance per unit area and the attraction force per unit area of ​​the electrostatic chuck of the processing device. For example, when the thickness of the dielectric layer above the electrode built into the electrostatic chuck is 0.3 mm, the thickness of the dielectric film 102 on the upper surface of the tray body 101 and the dielectric film 102 on the lower surface of the tray body 101 are 0.1 mm, and the relative dielectric constant of each dielectric is 8.5, the electrostatic capacitance of the tray TR1 is 0.124 μF / m 2 In this case, when a DC voltage of 5 kV is applied to the electrostatic chuck 40 by the DC power supply 42, a Coulomb force of attraction of about 170 Torr per unit area can be obtained in the electrostatic chuck 40. Thus, when a heat-conducting gas is supplied between the tray TR1 mounted on the electrostatic chuck 40 and the wafer W in the processing apparatus 4, a sufficient attraction force can be obtained by utilizing the pressure of the heat-conducting gas to prevent the wafer W from leaving.

[0118] <Adjustment of Wafer Position>

[0119] Figure 13 is a diagram showing the positional relationship between the rotation angle sensor and the horizontal position sensor. Figure 13 As shown, in the placement device 12A, the edge ring ER is placed on the tray TR1 so that the flat portion FL is located below the rotation angle sensor 202. In addition, in the placement device 12A, horizontal position sensors 203 are provided at three locations around the edge ring ER placed on the tray TR1.

[0120] Figure 14 This is a diagram showing the correct positional relationship between the edge ring and the wafer. Figure 14 As shown, in the correct positional relationship between the edge ring ER and the wafer W, the center of the edge ring ER coincides with the center of the wafer W, and the apex of the concave portion of the notch NT of the wafer W is located at the center of the flat portion FL of the edge ring ER. Therefore, in order to set the correct positional relationship between the edge ring ER and the wafer W, a straight reference line L1 and a straight reference line L2 are set in advance. The reference position RP is defined by the horizontal reference line L1 and the vertical reference line L2. The reference line L1 and the reference line L2 intersect each other perpendicularly. In the correct positional relationship between the edge ring ER and the wafer W, the intersection of the reference line L1 and the reference line L2 coincides with the center of the edge ring ER and the center of the wafer W, and on the reference line L1, the apex of the concave portion of the notch NT is located at the center of the flat portion FL.

[0121] Figures 15 - 18 This is a diagram showing an example of wafer position adjustment. Figure 15 and Figure 17 Indicates the position of the edge ring ER placed on the tray TR1, Figure 16 and Figure 18 The position of the wafer W after position adjustment is shown.

[0122] The edge ring ER placed on the tray TR1 is measured by using the horizontal position sensor 203. Figure 15 As shown in FIG. 1 , the horizontal positional offset HP relative to the reference position RP defined by the reference line L1 and the reference line L2 is measured. In the measurement of the positional offset HP, as shown in FIG. Figure 15 As shown in FIG. 1 , a horizontal straight line LA and a vertical straight line LB are set relative to the edge ring ER placed on the tray TR1. The straight lines LA and LB intersect each other perpendicularly, the intersection of the straight lines LA and LB coincides with the center of the edge ring ER, and the center of the flat portion FL is located on the straight line LA. Then, the horizontal position sensor 203 is used to measure the direction and amount of deviation of the intersection of the straight lines LA and LB relative to the intersection of the reference line L1 and the reference line L2 as the position deviation HP. Then, in the adjustment of the horizontal position of the wafer W performed in the aligner 3, as shown in FIG. Figure 16 As shown in FIG. 1 , the center position of the wafer W is moved from the intersection of the reference line L1 and the reference line L2 by the amount of the position offset HP. Thus, the center of the edge ring ER placed on the tray TR1 can be moved by the amount of the position offset HP to coincide with the center of the wafer W, so that the gap between the inner periphery of the edge ring ER and the outer periphery of the wafer W arranged in the edge ring ER can be constant over the entire periphery.

[0123] In addition, the edge ring ER placed on the tray TR1 is measured using the rotation angle sensor 202. Figure 17 The rotation angle RA is measured relative to the reference position RP defined by the reference line L1 and the reference line L2 as shown in FIG. Figure 17 As shown, a horizontal straight line LC and a vertical straight line LD are set relative to the edge ring ER placed on the tray TR1. The straight line LC and the straight line LD intersect each other perpendicularly, and the intersection of the straight line LC and the straight line LD coincides with the center of the edge ring ER and the intersection of the reference line L1 and the reference line L2, and the center of the flat portion FL is located on the straight line LC. Therefore, the rotation angle RA of the straight line LC relative to the reference line L1 is measured by the rotation angle sensor 202. Then, by rotating the wafer W in the aligner 3, the wafer W is rotated from the reference position RP by the rotation angle RA. As a result, as shown in FIG. Figure 18 As shown, the wafer W can be placed on the flat portion FL by shifting the rotation angle RA so that the apex of the recessed portion of the notch NT of the wafer W is located at the center of the flat portion FL of the edge ring ER placed on the tray TR1.

[0124] In this embodiment, the edge ring ER and the wafer W are placed on the tray TR1 in the load lock chamber 12 and conveyed to the processing device 4. The placement position of the edge ring ER is measured in the load lock chamber 12, and based on the measurement result, the position of the wafer W is adjusted, and the wafer W is placed on the tray TR1. Therefore, even if there is a deviation in the placement position of the edge ring ER, the wafer W can be conveyed to a relatively correct position relative to the edge ring ER. In addition, the tray TR1 can electrostatically adsorb the wafer W and the edge ring ER, so that the edge ring ER and the wafer W placed on the tray TR1 can be prevented from shifting in the load lock chamber 12, and thus they are conveyed to the processing device 4. Moreover, when the wafer W is conveyed to the edge ring ER disposed in the processing device 4, the relative position of the edge ring ER and the wafer W will shift due to the error generated when the wafer W is conveyed from the load lock chamber 12 to the processing device 4. However, in this embodiment, the wafer W is conveyed to the edge ring ER in the load lock chamber 12. Therefore, the relative position of the edge ring ER and the wafer W will not shift due to the conveyance error from the load lock chamber 12 to the processing device 4. That is, in this embodiment, the wafer W can be conveyed to a relatively correct position relative to the edge ring ER in the load lock chamber 12, and they are conveyed from the load lock chamber 12 to the processing device 4 while maintaining the relative position of the wafer W and the edge ring ER. Therefore, uniform plasma processing can be performed on the wafer W in the processing device 4.

[0125] The embodiments of the present invention are illustrative in all respects and should not be considered restrictive. In fact, the above embodiments can be specifically implemented in various ways. In addition, the above embodiments can be omitted, replaced, and changed in various ways without departing from the scope and spirit of the claims.

[0126] For example, in the above embodiment, the example in which the tray storage unit 5 is connected to the atmospheric conveyance chamber 11 is described, but it can also be as Figure 19 shown, the tray storage unit 5 is connected to the vacuum conveyance chamber 13. Figure 19 FIG. is a structural example of a substrate processing system in which the tray storage unit 5 is connected to the vacuum conveyance chamber. In addition, the edge ring storage unit 2 can also be connected to the vacuum conveyance chamber 13. In the above case, the edge ring and / or the tray are sent into the load lock chamber 12 by the second conveyance mechanism 16.

[0127] In addition, in the above embodiment, the edge ring and the wafer are placed on the tray in the load lock chamber 12, but it can also be performed outside the load lock chamber 12. For example, a placement device 12A different from the load lock chamber 12 can be connected to the atmospheric conveyance chamber 11, and the tray on which the edge ring and the wafer are placed in the placement device 12A is sent into the load lock chamber 12.

[0128] In addition, in the above-described embodiment, in step S2, the tray TR1 was placed on the placement table 204, but it may not be placed. It is also possible to lower the first lifting pin 205 in step S3 to a level where the edge ring ER can be fed, and perform the processing after step S3 while supporting the tray TR1 with the first lifting pin 205.

[0129] In addition, in the above-described embodiment, the trays are stored in the tray storage unit 5, and the edge rings are stored in the edge ring storage unit 2, and they are respectively fed into the load lock chamber 12. However, it is also possible to store the trays on which the edge rings are pre-placed in the tray storage unit 5. In this case, the processing of step S3 and step S4 can be omitted. In addition, the edge ring storage unit 2, the third lifting pin 207 of the placement device 12A for lifting the edge ring, and the through hole 106 of the tray TR1 through which the third lifting pin 207 passes can be omitted.

[0130] In addition, in the above-described embodiment, an example in which an edge ring with an inner peripheral portion located below the outer peripheral portion of the wafer W is used has been described, but the inner peripheral portion of the edge ring may not be located below the outer peripheral portion of the wafer W. That is, in the tray TR1, the edge ring placement portion 107 is formed at a position lower than the substrate placement portion 108, but the edge ring placement portion may also be formed at a position higher than the substrate placement portion or at the same position as the substrate placement portion.

[0131] Figure 20 FIG. is a diagram showing an example of a tray in which the edge ring placement portion and the substrate placement portion are formed at the same height. In Figure 20 , the tray TR2 has a disk shape and includes: a conductive tray main body 251; a dielectric film 252 formed so as to cover the periphery of the tray main body 251; an annular groove 253; an annular protection member 254 housed in the groove 253; a lift pin contact portion 255; and through holes 256 and 257. In addition, the dielectric film 252 may be formed on at least the upper surface of the tray main body 251. The through hole 256 is a through hole for supplying a heat transfer gas between the tray TR2 and the wafer W through a gas passage 56 ( Figure 2 ) in the processing apparatus 4. In addition, the through hole 257 is a through hole for a lift pin for lifting the wafer W. In addition, a through hole for a lift pin for lifting the edge ring ER is not provided in the tray TR2, but such a through hole may be provided. In addition, a substrate placement portion 259 on which the wafer W can be placed and an edge ring placement portion 258 on which the edge ring ER can be placed are formed on the upper surface of the tray TR2. The edge ring placement portion 258 is provided around the substrate placement portion 259. The substrate placement portion 259 and the edge ring placement portion 258 are formed in the same plane.

[0132] In the tray TR2, the outer peripheral portion of the wafer W does not overlap with the inner peripheral portion of the edge ring ER. Therefore, during plasma processing, the dielectric film between the wafer W and the edge ring ER is exposed to the plasma. Thus, it is considered that the wafer W is contaminated due to the dielectric film or the material constituting the tray main body that is exposed due to the consumption of the dielectric film. Therefore, in the tray TR2, a protection member 254 is provided between the substrate placement portion 259 and the edge ring placement portion 258. The protection member 254 is housed in a groove 253 provided between the substrate placement portion 259 and the edge ring placement portion 258. The material of the protection member 254 is preferably the same as that of the edge ring ER. In the tray TR2, the shapes of the edge ring ER and the tray TR2 can be simplified.

[0133] In addition, in the above-described embodiment, a DC voltage is applied to the tray main body 101 by the first lifting pin 205 connected to the DC power supply 208. However, a DC voltage can also be applied to the tray main body 101 without using the lifting pin.

[0134] Figure 21 It is a diagram showing an example of applying a DC voltage to the tray main body without using a lifting pin. Figure 21 The mounting device 12B shown is used as the load lock chamber 12. For parts Figure 6 repeated with the mounting device 12A shown, the description and / or illustration are omitted. In Figure 21 , the mounting device 12B includes a conductive mounting table 352, an insulating support portion 351, a DC power supply 353, and a conductive lifting pin 501. The lifting pin 501 is grounded. The tray TR3 is placed on the mounting table 352. The edge ring ER and the wafer W are placed on the tray TR3. The wafer W is placed on the tray TR3 by the lifting of the lifting pin 501. Thus, the wafer W is discharged when lifted by the lifting pin 501.

[0135] In the tray TR3, a dielectric film 361 is formed laminated on the conductive tray main body 362. In the tray TR3, the dielectric film 361 is formed only on the upper surface of the tray main body 362, and the lower surface of the tray main body 362 is not covered with the dielectric film, which is different from Figure 3 the tray TR1 shown. That is, on the lower surface of the tray TR3, the conductive tray main body 362 is exposed. Thus, in a state where the tray TR3 on which the edge ring ER and the wafer W are placed is placed on the mounting table 352, a DC voltage is applied to the mounting table 352 by the DC power supply 353, and thus a DC voltage can be applied to the tray main body 362. Thereby, a Coulomb force is generated in the tray TR3, and the wafer W is electrostatically adsorbed to the tray TR3.

[0136] Figure 22 It is a diagram showing another example of applying a DC voltage to the tray main body without using a lifting pin. Figure 22The placement device 12C shown is used as the load lock chamber 12. For parts that are repeated with the Figure 21 placement device 12B shown, the description and / or illustration are omitted. The placement device 12C is different from the Figure 21 placement device 12B shown in that a conduction terminal 361 is provided on the upper surface of the conductive placement table 352. The conduction terminal 361 can be formed by protruding a part of the conductive placement table 352, or can be formed by a component different from the placement table 352. For example, the conduction terminal 361 can be formed by a spring.

[0137] A tray TR4 is placed on the placement table 352. The tray TR4 includes: a conductive tray main body 451; a dielectric film 452 formed so as to cover the periphery of the tray main body 451; and a DC power supply connection part 453. The DC power supply connection part 453 is a part of the back surface of the tray main body 451 where the conduction terminal 361 contacts, and the dielectric film 452 is not formed. The DC power supply connection part 453 can be formed as a recess corresponding to the shape of the conduction terminal 361. In the tray TR4, the DC power supply connection part 453 is provided, which is different from the Figure 3 tray TR1 shown. When the tray TR4 on which the edge ring ER and the wafer W are placed is placed on the placement table 352, the conduction terminal 361 of the placement table 352 contacts the tray main body 451 via the DC power supply connection part 453. Thereby, in a state where the tray TR4 on which the edge ring ER and the wafer W are placed is placed on the placement table 352, a DC voltage is applied to the placement table 352 by the DC power supply 353, and thereby a DC voltage can be applied to the tray main body 451. Thereby, a Coulomb force is generated in the tray TR4, and the wafer W is electrostatically adsorbed to the tray TR4.

[0138] Figure 23 FIG. is a diagram showing another example of applying a DC voltage to the tray main body without using a lift pin. Figure 23 The placement device 12D shown is used as the load lock chamber 12. For parts that are repeated with the Figure 22 placement device 12C shown, the description and / or illustration are omitted. In the placement device 12D, the placement table 371 is made of an insulating component, and the DC power supply 355 is not connected to the placement table 371, which is different from the Figure 22 placement device 12C shown. A conductive conduction terminal 361 is provided on the upper surface of the placement table 371, and the conduction terminal 361 is directly connected to the DC power supply 355. A tray TR5 is placed on the placement table 371.

[0139] Regarding the tray TR5, similar to the tray TR4, it includes: a conductive tray body 471; a dielectric film 472 formed so as to cover the periphery of the tray body 471; and a DC power supply connection part 473. When the tray TR5 on which the edge ring ER and the wafer W are placed is placed on the placement table 371, the conduction terminal 361 of the placement table 371 contacts the tray body 471 via the DC power supply connection part 473. Thus, in a state where the tray TR5 on which the edge ring ER and the wafer W are placed is placed on the placement table 371, a DC voltage can be applied to the tray body 471 by the DC power supply 355. Thus, due to the DC voltage applied to the tray body 471, a Coulomb force is generated in the tray TR5, and the wafer W is electrostatically adsorbed to the tray TR5.

[0140] In addition, in the above-described embodiment, the wafer W was discharged using a grounded conductive lift pin. However, the wafer W can also be discharged without using the lift pin.

[0141] Figure 24 It is a diagram showing an example of discharging the wafer W without using a lift pin. Figure 24 The placement device 12E shown is used as the load lock chamber 12. For parts that are repeated with the Figure 21 placement device 12B shown, the description and / or illustration are omitted. In Figure 24 , the placement device 12E has a grounding member 354. The placement device 12E discharges the wafer W using the grounding member 354 instead of the grounded lift pin 501, which is different from the placement device 12B. The grounding member 354 is electrically connected to the grounded container 201. The grounding member 354 is configured to be able to contact the wafer W placed on the tray TR6. In addition, it can also be configured to be able to contact not only the wafer W but also the edge ring ER.

[0142] As Figure 24 shown, by bringing the grounding member 354 into contact with the wafer W, the wafer W is grounded and discharged. In a state where the tray TR6 on which the edge ring ER and the wafer W are placed is placed on the placement table 352, a DC voltage is applied to the placement table 352 by the DC power supply 353. Thus, due to the DC voltage applied to the placement table 352, a Coulomb force is generated in the tray TR6, and the wafer W is electrostatically adsorbed to the tray TR6.

[0143] Figure 25 It is a diagram showing another example of discharging the wafer W without using a lift pin. Figure 25 The placement device 12F shown is used as the load lock chamber 12. For parts that are repeated with the Figure 22 placement device 12C shown, the description and / or illustration are omitted. In Figure 25 , the placement device 12F has an RF power supply 392 connected to the conductive placement table 382.

[0144] When the tray TR7 on which the edge ring ER and the wafer W are placed is placed on the placement table 382, the DC power supply 391 is connected to the tray main body 481 via the DC power supply connection portion 483. In a state where the DC power supply 391 is connected to the tray main body 481, a DC voltage is applied to the tray main body 481 by the DC power supply 391. In addition, the RF power supply 392 applies a high-frequency voltage for plasma generation having a frequency in the range of 30 to 150 MHz to the placement table 382. By applying a high-frequency voltage to the placement table 382 in this way, plasma PLS can be generated in the container 201. Then, the edge ring ER and the wafer W are grounded via the plasma PLS generated in the container 201. Thereby, a Coulomb force is generated in the tray TR7 by the DC voltage applied to the tray main body 481, and the wafer W is electrostatically adsorbed to the tray TR7.

[0145] In addition, in the above-described embodiment, the tray is configured to function as a unipolar electrostatic chuck, but it may also be configured to function as a bipolar electrostatic chuck.

[0146] Figure 26 It is a diagram showing an example of a tray that functions as a bipolar electrostatic chuck. In Figure 26 the tray TR8 has a disk shape and includes: a conductive first tray main body 302; a conductive second tray main body 301; a dielectric film 303 formed so as to cover the periphery of the first tray main body 302 and the second tray main body 301; an insulating layer 304; lift pin contact portions 305, 306; and through holes 307, 308. In the tray TR8, the tray main body is divided into the first tray main body 302 and the second tray main body 301 by the insulating layer 304, and lift pin contact portions are provided on the first tray main body 302 and the second tray main body 301, which are different from the tray TR1. The insulating layer 304 electrically separates the first tray main body 302 and the second tray main body 301 in the horizontal direction. The through hole 307 is a through hole for supplying a heat conductive gas between the tray TR2 and the wafer W via a gas passage 56 ( Figure 2 ) in the processing apparatus 4. The through hole 308 is a through hole for the lift pin.

[0147] Figure 27 It is a diagram showing an example of a placement device for placing the tray TR8. Figure 27 The placement device 12G shown is used as the load lock chamber 12. In Figure 27 the placement device 12G includes a first lift pin 401, an insulating second lift pin 409, a first DC power supply 407, a second DC power supply 405, and switches 406, 408, which is different from Figure 6is different from the placement device 12A shown. The first lift pin 401 includes a conductive first pin 404, a conductive second pin 403, and an insulating support portion 402 that connects the first pin 404 and the second pin 403. In addition, the placement device 12G includes: a first lift mechanism (not shown) that lifts and lowers the first lift pin 401; and a second lift mechanism (not shown) that lifts and lowers the second lift pin 409 independently of the first lift pin 401. The first pin 404 is connected to the first DC power supply 407 via the switch 408, and the second pin 403 is connected to the second DC power supply 405 via the switch 406.

[0148] As Figure 27 shown, the tray TR9 on which the wafer W and the edge ring ER are placed is placed on the placement table 204. The first pin 404 and the second pin 403 are in contact with the lift pin contact portions 305 and 306. By turning on the switch 408, the first pin 404 is connected to the first DC power supply 407, and the first DC power supply 407 applies a positive DC voltage to the first pin 404. By applying a positive DC voltage to the first pin 404, a positive DC voltage is applied to the first tray body 302 from the first DC power supply 407 via the first pin 404 and the lift pin contact portion 306. In addition, by turning on the switch 406, the second pin 403 is connected to the second DC power supply 405, and the second DC power supply 405 applies a negative DC voltage to the second pin 403. By applying a negative DC voltage to the second pin 403, a negative DC voltage is applied to the second tray body 301 from the second DC power supply 405 via the second pin 403 and the lift pin contact portion 305. Using the Coulomb force generated in the tray TR2 due to the DC voltages applied to the first tray body 302 and the second tray body 301, the wafer W is electrostatically adsorbed to the tray TR2. In addition, in the case where the material of the edge ring ER is a conductive material such as Si or SiC, for example, the edge ring ER is also electrostatically adsorbed to the tray TR2.

[0149] In the above-described embodiment, in step S6, the aligner 3 rotates the wafer W and adjusts the horizontal position of the wafer W. However, the adjustment of the horizontal position of the wafer W can also be performed by controlling the first transfer mechanism 15 based on the horizontal position information HPI of the edge ring ER. That is, based on the horizontal position information HPI of the edge ring ER, the wafer W is transferred above the placement table 204 by the first transfer mechanism 15, thereby adjusting the horizontal position of the wafer W so that the center of the edge ring ER coincides with the center of the wafer W.

[0150] In addition, the respective operations of the respective components of the substrate processing systems 100 and 200 and the operations (processing sequences) of the substrate processing systems 100 and 200 as a whole are controlled by a control unit (not shown). As an example of the control unit, a microcomputer can be cited.

[0151] In addition, the embodiments of the present invention are illustrative in all aspects and should not be considered restrictive. In fact, the above embodiments can be specifically implemented in various ways. Further, the above embodiments can be omitted, replaced, or changed in various ways without departing from the scope and spirit of the claims. For example, in the above description, as an example of substrate processing, etching was described, but the substrate processing to which the technology of the present invention can be applied is not limited to etching. For example, by changing the degree of vacuum and the processing gas in the processing space PS to those suitable for film formation, the technology of the present invention can also be applied to film formation, which is one of the substrate processes.

[0152] Regarding the above embodiments, the following supplementary notes are also disclosed.

[0153] (Supplementary Note 1)

[0154] A tray capable of mounting a semiconductor substrate, comprising:

[0155] A substrate mounting portion capable of mounting the above semiconductor substrate; and

[0156] An edge ring mounting portion provided around the above substrate mounting portion, which is capable of mounting an edge ring,

[0157] The above substrate mounting portion and the above edge ring mounting portion include:

[0158] A conductive tray body; and

[0159] A dielectric film formed on at least the upper surface of the above tray body.

[0160] (Supplementary Note 2)

[0161] In the tray described in Supplementary Note 1,

[0162] The above edge ring mounting portion is formed at a position lower than the above substrate mounting portion.

[0163] (Supplementary Note 3)

[0164] In the tray described in Supplementary Note 2,

[0165] The area of the above substrate mounting portion is smaller than the area of the above semiconductor substrate.

[0166] (Supplementary Note 4)

[0167] In the tray described in Supplementary Note 1,

[0168] The above substrate mounting portion and the above edge ring mounting portion are formed on the same plane.

[0169] (Supplementary Note 5)

[0170] In the tray described in Supplementary Note 4,

[0171] A protective member is provided between the substrate placement portion and the edge ring placement portion.

[0172] (Supplementary Note 6)

[0173] In the tray described in Supplementary Note 5,

[0174] the protective member is housed in a groove provided between the substrate placement portion and the edge ring placement portion.

[0175] (Supplementary Note 7)

[0176] In the tray described in Supplementary Note 1,

[0177] the substrate placement portion includes:

[0178] a support surface for supporting the back surface of the semiconductor substrate; and

[0179] a through hole that penetrates the tray main body and the dielectric film.

[0180] (Supplementary Note 8)

[0181] In the tray described in Supplementary Note 1,

[0182] It further includes an insulating layer that electrically separates the tray main body in the horizontal direction.

[0183] (Supplementary Note 9)

[0184] A placement device, comprising:

[0185] a placement table;

[0186] a first lifting pin for lifting and lowering the tray placed on the placement table;

[0187] a second lifting pin for lifting and lowering the semiconductor substrate placed on the tray;

[0188] a first lifting mechanism for lifting and lowering the first lifting pin;

[0189] a second lifting mechanism for lifting and lowering the second lifting pin independently of the first lifting pin; and

[0190] a voltage application unit for applying a voltage to the tray.

[0191] (Supplementary Note 10)

[0192] In the placement device described in Supplementary Note 9,

[0193] the voltage application unit is a DC power supply connected to the placement table.

[0194] (Supplementary Note 11)

[0195] In the placing device described in Supplementary Note 9,

[0196] The placing table has a conduction terminal that electrically contacts the tray with the placing table.

[0197] (Supplementary Note 12)

[0198] In the placing device described in Supplementary Note 9,

[0199] The voltage application unit is a first DC power source connected to the first lifting pin.

[0200] (Supplementary Note 13)

[0201] In the placing device described in Supplementary Note 9,

[0202] The second lifting pin is grounded.

[0203] (Supplementary Note 14)

[0204] In the placing device described in Supplementary Note 12,

[0205] The first lifting pin includes:

[0206] A first pin;

[0207] A second pin; and

[0208] An insulating support portion connecting the first pin and the second pin,

[0209] The first DC power source is connected to the first pin,

[0210] The placing device further includes a second DC power source connected to the second pin.

[0211] (Supplementary Note 15)

[0212] In the placing device described in Supplementary Note 9,

[0213] It further includes a third lifting pin for lifting the edge ring placed on the tray.

[0214] (Supplementary Note 16)

[0215] In the placing device described in Supplementary Note 15,

[0216] The third lifting pin is grounded.

[0217] (Supplementary Note 17)

[0218] In the placing device described in Supplementary Note 9, it further includes:

[0219] A container for housing the placing table; and

[0220] An exhaust mechanism capable of making the pressure inside the container lower than the atmospheric pressure.

[0221] (Appendix 18)

[0222] In the mounting device described in Appendix 9,

[0223] it further includes an RF power supply connected to the above-mentioned mounting table.

Claims

1. A tray capable of mounting a semiconductor substrate, characterized in that, it includes: a substrate mounting portion capable of mounting the semiconductor substrate; and an edge ring mounting portion provided around the substrate mounting portion, which is capable of mounting an edge ring, the substrate mounting portion and the edge ring mounting portion include: a conductive tray body; and a dielectric film formed on at least the upper surface of the tray body.

2. The tray according to claim 1, characterized in that: the edge ring mounting portion is formed at a position lower than the substrate mounting portion.

3. The tray according to claim 2, characterized in that: the area of the substrate mounting portion is smaller than the area of the semiconductor substrate.

4. The tray according to claim 1, characterized in that: the substrate mounting portion and the edge ring mounting portion are formed on the same plane.

5. The tray according to claim 4, characterized in that: a protection member is provided between the substrate mounting portion and the edge ring mounting portion.

6. The tray according to claim 5, characterized in that: the protection member is received in a groove provided between the substrate mounting portion and the edge ring mounting portion.

7. The tray according to claim 1, characterized in that: the substrate mounting portion includes: a support surface for supporting the back surface of the semiconductor substrate; and a through hole penetrating the tray body and the dielectric film.

8. The tray according to claim 1, characterized in that: it further includes an insulating layer for electrically separating the tray body in the horizontal direction.

9. The tray according to claim 1, characterized in that: the thickness of the dielectric film is 0.3 mm or less.

10. A mounting device, characterized in that, it includes: a mounting table; a first lifting pin for lifting the tray mounted on the mounting table; a second lifting pin for lifting the semiconductor substrate mounted on the tray; a first lifting mechanism for lifting the first lifting pin; a second lifting mechanism for lifting the second lifting pin independently of the first lifting pin; and a voltage application unit for applying a voltage to the tray.

11. The mounting device according to claim 10, characterized in that: the voltage application unit is a DC power supply connected to the mounting table.

12. The mounting device according to claim 10, characterized in that: the mounting table has a conduction terminal for making the tray in electrical contact with the mounting table.

13. The mounting device according to claim 10, characterized in that: the voltage application unit is a first DC power supply connected to the first lifting pin.

14. The mounting device according to claim 10, characterized in that: the second lifting pin is grounded.

15. The mounting device according to claim 13, characterized in that: the first lifting pin includes: a first pin; a second pin; and an insulating support portion connecting the first pin and the second pin, the first DC power supply is connected to the first pin, the mounting device further includes a second DC power supply connected to the second pin.

16. The mounting device according to claim 10, characterized in that: it further includes a third lifting pin for lifting the edge ring mounted on the tray.

17. The mounting device according to claim 16, wherein: the third lifting pin is grounded.

18. The mounting device according to claim 10, wherein, further comprising: a container for accommodating the mounting table; and an exhaust mechanism capable of making the pressure inside the container lower than the atmospheric pressure.

19. The mounting device according to claim 10, wherein: further comprising an RF power supply connected to the mounting table.

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