Method of forming pattern and method of manufacturing integrated circuit device using the same

Abstract

Methods of forming patterns and methods of manufacturing integrated circuit devices may be provided. The method of forming a pattern includes: forming an etch target layer on a substrate including a first region and a second region; forming a hard mask structure on the etching target layer; forming a first photoresist layer on the hard mask structure; forming a first photoresist pattern and a first dummy pattern; forming a hard mask pattern corresponding to the first photoresist pattern and a second dummy pattern corresponding to the first dummy pattern; forming a second photoresist layer on the second dummy pattern and the hard mask pattern; forming a second photoresist pattern covering the second dummy pattern and exposing the hard mask pattern; and forming the resulting pattern from the etching target layer by using the hard mask pattern as an etching mask.

Description

Technical Field

[0001] The inventive concept relates to a method of forming a pattern and a method of manufacturing an integrated circuit device, and more particularly, to a method of forming a pattern in a plurality of regions having different pattern densities and a method of manufacturing an integrated circuit device by using the method of forming a pattern. Background Art

[0002] Recently, with the rapid development of semiconductor memory devices in terms of size reduction, the feature size of semiconductor memory devices has become more minute, and the line width of patterns constituting the semiconductor memory devices has gradually decreased. Accordingly, the difficulty of a process of simultaneously forming patterns having various shapes, sizes, and densities required for semiconductor memory devices is increasing. Summary of the Invention

[0003] The inventive concept provides a method of forming a pattern and a method of manufacturing an integrated circuit device, in which a critical dimension (CD) deviation of a pattern can be reduced.

[0004] In addition, the technical objectives of the inventive concept are not limited to the above objectives, and other objectives will be clearly understood by those skilled in the art from the following description.

[0005] According to an aspect of the inventive concept, a method of forming a pattern may include: forming an etch target layer on a substrate, the substrate including a first region and a second region; forming a hard mask structure on the etch target layer; forming a first photoresist layer on the hard mask structure; forming a first photoresist pattern and a first dummy pattern by exposing and developing the first photoresist layer; forming a hard mask pattern corresponding to the first photoresist pattern and a second dummy pattern corresponding to the first dummy pattern by etching at least a portion of the hard mask structure by using the first photoresist pattern and the first dummy pattern; forming a second photoresist layer on the second dummy pattern and the hard mask pattern; forming a second photoresist pattern covering the second dummy pattern and exposing the hard mask pattern by exposing and developing the second photoresist layer; and forming a resultant pattern from the etch target layer by using the hard mask pattern as an etch mask, wherein, in a plane, one of the first region and the second region surrounds the other of the first region and the second region.

[0006] According to another aspect of the inventive concept, a method of forming a pattern may include: forming an etch target layer on a substrate including a first region and a second region adjacent to the first region; forming a hard mask structure on the etch target layer, the hard mask structure including a plurality of hard mask layers; forming a first photoresist pattern and a first dummy pattern on the hard mask structure according to a design pattern of a design layout, each of the first photoresist pattern and the first dummy pattern including a metal oxide resist (MOR); forming a hard mask pattern and a second dummy pattern by etching at least one of the plurality of hard mask layers using the first photoresist pattern and the first dummy pattern as an etch mask; and forming a resultant pattern from the etch target layer using the hard mask pattern as an etch mask, wherein a pattern density of the design pattern of the design layout is greater than a pattern density of the resultant pattern on the substrate.

[0007] According to another aspect of the inventive concept, a method of manufacturing an integrated circuit device may include: forming an etch target layer on a substrate including a memory cell region and a peripheral circuit region surrounding the memory cell region; forming a hard mask structure on the etch target layer in the memory cell region and the peripheral circuit region; forming a first photoresist layer including a metal material on the hard mask structure in the memory cell region and the peripheral circuit region; forming a first dummy pattern in the memory cell region and a first photoresist pattern in the peripheral circuit region by exposing and developing the first photoresist layer according to a design layout; forming a second dummy pattern corresponding to the first dummy pattern in the memory cell region and a hard mask pattern corresponding to the first photoresist pattern in the peripheral circuit region; forming a second photoresist layer covering the hard mask pattern and the second dummy pattern in the memory cell region and the peripheral circuit region; forming a second photoresist pattern in the memory cell region by exposing and developing the second photoresist layer; and forming a resultant pattern from the etch target layer using the hard mask pattern and the second photoresist pattern, wherein a pattern density of the design pattern included in the design layout and a pattern density of the resultant pattern on the substrate are different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a layout diagram of an integrated circuit device formed by a method of manufacturing an integrated circuit device according to an example embodiment;

[0010] Figures 2 to 9 is a cross-sectional view of a method of forming a pattern according to an example embodiment;

[0011] Figure 10 shows Figure 1 a schematic plan view of main components of the memory cell region shown;

[0012] Figure 11 is a plan view showing an example arrangement of a plurality of conductive patterns arranged in the peripheral circuit region shown; and Figure 1 a cross-sectional view showing a method of manufacturing an integrated circuit device according to an example embodiment.

[0013] Figures 12A to 15B is a layout view of an integrated circuit device 1 formed by a method of manufacturing an integrated circuit device according to an example embodiment. DETAILED DESCRIPTION

[0014] Hereinafter, some example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and repeated descriptions thereof are omitted.

[0015] Although the terms "same", "equal", or "identical" are used in the description of the example embodiments, it should be understood that there may be some inaccuracies. Therefore, when an element is referred to as being the same as another element, it should be understood that within the desired manufacturing or operating tolerance range (e.g., ±10%), one element or value is the same as another element or value.

[0016] When the terms "about", "substantially", or "approximately" are used in this specification in conjunction with a numerical value, it means that the relevant numerical value includes the manufacturing or operating tolerance around the stated numerical value (e.g., ±10%). In addition, when the words "about", "substantially", or "approximately" are used in conjunction with a geometric shape, it means that geometric precision is not required, but rather the tolerance of the shape is within the scope of the present disclosure. Furthermore, whether or not a numerical value or shape is modified by "about" or "substantially", it should be understood that these numerical values and shapes should be interpreted as including the manufacturing or operating tolerance around the stated numerical value or shape (e.g., ±10%).

[0017] Figure 1 is a layout view of an integrated circuit device 1 formed by a method of manufacturing an integrated circuit device according to an example embodiment.

[0018] Referring Figure 1 , the integrated circuit device 1 may include a substrate 110, and the substrate 110 includes a memory cell area MCA and a peripheral circuit area PCA. The peripheral circuit area PCA may surround the memory cell area MCA.

[0019] The memory cell area MCA may be an array area of volatile memory cells of a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA may be a core area or a peripheral circuit area of the DRAM device. For example, the peripheral circuit area PCA may include peripheral circuit transistors for transmitting signals and / or power to the memory cell array included in the memory cell area MCA.

[0020] In some example embodiments, the peripheral circuit transistors may form various circuits, such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and data input / output circuits.

[0021] The memory cell area MCA and the peripheral circuit area PCA may have different pattern densities. In an example embodiment, in the memory cell area MCA, a plurality of patterns having a relatively small width may be separated from each other to form a regular arrangement, and may be repeatedly formed at a relatively small pitch. In the peripheral circuit area PCA, a plurality of patterns having non-constant widths and lengths may be repeatedly formed at a non-constant pitch. Reference is made below Figure 10 and Figure 11 to describe the patterns formed in each of the memory cell area MCA and the peripheral circuit area PCA.

[0022] Figures 2 to 9 is a cross-sectional view showing a method of forming a pattern according to an example embodiment. The first region AR1 and the second region AR2 may refer to different regions on the substrate 110 that do not overlap each other. In Figures 2 to 9 the first region AR1 may refer to one of the memory cell area MCA and the peripheral circuit area PCA, and the second region AR2 may refer to the other of the memory cell area MCA and the peripheral circuit area PCA.

[0023] Reference is made to Figure 2 wherein a lower structure 120 is formed on the substrate 110. The upper surface of the lower structure 120 may be at substantially the same or similar level in the first region AR1 and the second region AR2. Here, the term "level" refers to the height extending in the vertical direction (Z direction) from the upper surface of the substrate 110. An etch target layer 130 is formed on the lower structure 120.

[0024] The substrate 110 may include a semiconductor element (such as silicon (Si) or germanium (Ge)) or a compound semiconductor (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). The lower structure 120 may include an insulating layer, a conductive layer, or a combination thereof. For example, the lower structure 120 may include a structure including at least one conductive region. The conductive region may include a doped structure, a doped semiconductor layer, a metal layer, or a combination thereof. The lower structure 120 may include conductive regions (such as a wiring layer, a contact plug, a transistor, etc.) and an insulating layer for insulating the conductive regions from each other. In an example embodiment, the etch target layer 130 may include an insulating pattern, a conductive pattern, or a combination thereof. In an example embodiment, the etch target layer 130 may include a doped semiconductor, a metal, a conductive metal nitride, or a combination thereof.

[0025] Reference is made to Figure 3, a hard mask structure 140 including a plurality of hard mask layers is formed on an etching target layer 130, and a first photoresist layer 150 is formed on the hard mask structure 140. The first photoresist layer 150 may cover the upper surface of the hard mask structure 140.

[0026] The hard mask structure 140 may be disposed in a first region AR1 and a second region AR2. The hard mask structure 140 may include a first hard mask layer 141, a second hard mask layer 142, and a third hard mask layer 143 sequentially stacked on the etching target layer 130. The first hard mask layer 141, the second hard mask layer 142, and the third hard mask layer 143 may include different materials, each having an etching selectivity different from that of the other layers adjacent to each of the first hard mask layer 141, the second hard mask layer 142, and the third hard mask layer 143 at its lower and upper portions.

[0027] In an exemplary embodiment, the first hard mask layer 141 may include a silicon oxide layer, a silicon nitride layer, or an amorphous carbon layer (ACL). The second hard mask layer 142 may include a spin-on hard mask (SOH) layer including a hydrocarbon or its derivative having a relatively high carbon content of about 85 wt% to about 99 wt%. The third hard mask layer 143 may include silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, titanium, titanium dioxide, titanium nitride, chromium oxide, carbon, an organic anti-reflective coating (ARC) material, or a combination thereof.

[0028] The first photoresist layer 150 may include a resist for extreme ultraviolet (EUV) (13.5 nm), a resist for krypton fluoride (KrF) excimer laser (248 nm), a resist for argon fluoride (ArF) excimer laser (193 nm), and / or a resist for fluorine (F 2 ) excimer laser (157 nm).

[0029] In an exemplary embodiment, the first photoresist layer 150 may include a metal material and an inorganic material. For example, the first photoresist layer 150 may include a metal oxide resist (MOR). The first photoresist layer 150 may be formed by a deposition process and / or a spin-on process.

[0030] Hereinafter, for example, a description will be provided under the assumption that the first photoresist layer 150 includes a negative photoresist material. The first photoresist layer 150 may be disposed in the first region AR1 and the second region AR2. Accordingly, the upper surface of the hard mask structure 140 in each of the first region AR1 and the second region AR2 may not be exposed to the outside.

[0031] Reference Figure 3 and Figure 4, by exposing and developing the first photoresist layer 150, a first photoresist pattern 150P and a first dummy pattern DP1 can be formed from the first photoresist layer 150. During the exposure of the first photoresist layer 150, according to the design layout, the first photoresist pattern 150P can be formed in the first region AR1, and the first dummy pattern DP1 can be formed in the second region AR2.

[0032] The design patterns included in the design layout can have the same (or similar) pattern density in the first region AR1 and the second region AR2. The pattern density of the first photoresist pattern 150P in the first region AR1 can be the same (or similar) to the pattern density of the first dummy pattern DP1 in the second region AR2.

[0033] According to an exemplary embodiment, according to the method of forming a pattern, the first photoresist pattern 150P can be transferred to the resulting pattern, and the first dummy pattern DP1 can not be transferred to the resulting pattern and can be deleted during the pattern formation process. When forming a pattern by exposing the first photoresist layer 150, the first dummy pattern DP1 can be a component for making the pattern densities of the respective regions the same (or similar). The following reference Figure 8 provides a detailed description in this regard.

[0034] The first photoresist layer 150 can be exposed to light having a first wavelength λ 1 that has passed through the first mask MK1. For example, the first wavelength λ 1 can be 13.5 nm. That is, the light having the first wavelength λ 1 can be EUV. The first photoresist pattern 150P can be formed by EUV lithography.

[0035] The first mask MK1 can be opened in at least a part of the first region AR1 and at least a part of the second region AR2. Mask closed means that the light incident on the mask does not pass through the mask, and mask open means that the light incident on the mask passes through the mask.

[0036] Since the first photoresist layer 150 includes a negative photoresist material, the unexposed portion of the first photoresist layer 150 can be removed by a developing process. Thus, the first photoresist pattern 150P can be formed in the region corresponding to the region in the first region AR1 where the first mask MK1 is open, and the first dummy pattern DP1 can be formed in the region corresponding to the region in the second region AR2 where the first mask MK1 is open.

[0037] By forming the first photoresist pattern 150P and the first dummy pattern DP1, at least a part of the upper surface of the hard mask structure 140 in the first region AR1 and at least a part of the upper surface of the hard mask structure 140 in the second region AR2 can be exposed. The exposure rate of the upper surface of the hard mask structure 140 in the first region AR1 can be the same (or similar) to the exposure rate of the upper surface of the hard mask structure 140 in the second region AR2.

[0038] Reference Figure 4 and Figure 5 , in the first region AR1, the first photoresist pattern 150P can be used as an etching mask, and a hard mask pattern 140P can be formed, and the shape of the first photoresist pattern 150P is transferred to the hard mask pattern 140P. The hard mask pattern 140P can include a third hard mask pattern 143P and a second hard mask pattern 142P. In the process of forming the hard mask pattern 140P, the third hard mask layer 143 and the second hard mask layer 142 can be sequentially etched, and the third hard mask pattern 143P and the second hard mask pattern 142P corresponding to the first photoresist pattern 150P can be formed.

[0039] In the second region AR2, the first dummy pattern DP1 can be used as an etching mask, and a second dummy pattern DP2 can be formed, and the shape of the first dummy pattern DP1 is transferred to the second dummy pattern DP2. The second dummy pattern DP2 can include a third hard mask dummy pattern 143DP and a second hard mask dummy pattern 142DP. In the process of forming the second dummy pattern DP2, the third hard mask layer 143 and the second hard mask layer 142 can be sequentially etched, and the third hard mask dummy pattern 143DP and the second hard mask dummy pattern 142DP corresponding to the first dummy pattern DP1 can be formed. Regarding the patterns formed on the first hard mask layer 141, the pattern density in the first region AR1 and the pattern density in the second region AR2 can be the same (or similar) to each other.

[0040] Reference Figure 6 , a second photoresist layer 160 can be formed in the first region AR1 and the second region AR2. The second photoresist layer 160 can be formed on the hard mask pattern 140P and the second dummy pattern DP2. The second photoresist layer 160 can cover the hard mask pattern 140P in the first region AR1, and can cover the second dummy pattern DP2 in the second region AR2.

[0041] The second photoresist layer 160 can include a resist for EUV (13.5 nm), a resist for KrF excimer laser (248 nm), a resist for ArF excimer laser (193 nm), and / or a resist for F 2A resist for excimer laser (157 nm). The second photoresist layer 160 may include a metal material and an inorganic material. For example, the second photoresist layer 160 may include MOR. The second photoresist layer 160 may be formed by a deposition process and / or a spin coating process.

[0042] Hereinafter, for example, a description will be provided under the assumption that the second photoresist layer 160 includes a negative photoresist material.

[0043] Reference Figure 6 and Figure 7 and, by exposing and developing the second photoresist layer 160, a second photoresist pattern 160P can be formed. The second photoresist layer 160 may be exposed to light having a second wavelength λ 2 that has passed through the second mask MK2. For example, the second wavelength λ 2 may be about 157 nm, about 193 nm, and / or about 248 nm. The second wavelength λ 2 may be longer than the first wavelength λ 1 . The second photoresist layer 160 may be exposed by a KrF excimer laser (248 nm), an ArF excimer laser (193 nm), or an F 2 excimer laser (157 nm). That is, in an exemplary embodiment, considering the process difficulty, the process of exposing the second photoresist layer 160 may be performed by using light having a wavelength different from the light used in the process of exposing the first photoresist layer 150.

[0044] The second mask MK2 may be closed in the first region AR1 and may be open in the second region AR2. As described above, since the second photoresist layer 160 includes a negative photoresist material, the unexposed portion of the second photoresist layer 160 may be removed by a developing process.

[0045] The second photoresist layer 160 may be removed in the first region AR1 corresponding to the region where the second mask MK2 is closed, and the second photoresist layer 160 may form a second photoresist pattern 160P in the second region AR2 corresponding to the region where the second mask MK2 is open. Accordingly, the second photoresist pattern 160P may cover the second dummy pattern DP2 and may expose the hard mask pattern 140P. The second photoresist pattern 160P may cover the upper surface and the side surface of the second dummy pattern DP2 in the second region AR2, and the upper surface of the third hard mask pattern 143P may be exposed in the first region AR1.

[0046] Reference Figure 7 and Figure 8, by using the hard mask pattern 140P as an etching mask, the resulting pattern 130P can be formed from the etching target layer 130.

[0047] In the first region AR1, by using the second hard mask pattern 142P and the third hard mask pattern 143P as etching masks, a portion of the first hard mask layer 141 can be removed to form the first hard mask pattern 141P, and a portion of the etching target layer 130 can be removed to form the resulting pattern 130P. During the formation of the resulting pattern 130P, the first hard mask pattern 141P and the etching target layer 130 can be sequentially etched, and the resulting pattern 130P corresponding to the hard mask pattern 140P can be formed.

[0048] In the second region AR2, since the second photoresist pattern 160P is formed, the first hard mask layer 141 and the etching target layer 130 may not be removed. Since the second photoresist pattern 160P covers the upper surface of the second dummy pattern DP2 and the upper surface of the first hard mask layer 141, the etching target layer 130 may not be etched in the second region AR2.

[0049] Reference Figure 8 and Figure 9 , the first hard mask pattern 141P, the second hard mask pattern 142P, and the third hard mask pattern 143P can be removed in the first region AR1, and the first hard mask layer 141, the second hard mask pattern 142P, the third hard mask pattern 143P, and the second photoresist pattern 160P can be removed in the second region AR2. Reference Figure 9 , the resulting pattern 130P can be formed from the etching target layer 130 in the first region AR1, and the upper surface of the etching target layer 130 in the second region AR2 can be flat.

[0050] Summary reference Figures 2 to 9 Provided the description, in the method of forming a pattern, according to an exemplary embodiment, the etching target layer 130, the hard mask structure 140, and the first photoresist layer 150 can be formed on the substrate 110 on which a first region AR1 and a second region AR2 are defined. Thereafter, according to the design layout, the first photoresist pattern 150P can be formed in the first region AR1, and the first dummy pattern DP1 can be formed in the second region AR2. The first photoresist pattern 150P can be transferred to the hard mask pattern 140P, which is subsequently used as an etching mask to form the resulting pattern 130P. The first dummy pattern DP1 can be transferred to the second dummy pattern DP2, but may not subsequently appear as the resulting pattern 130P.

[0051] In the exposure of the first photoresist layer 150, the first dummy pattern DP1 can be used to maintain uniform pattern density on the substrate 110. Specifically, when the first photoresist layer 150 includes MOR, due to the compositional characteristics of MOR, the critical dimension (CD) deviation of the pattern caused by the pattern density difference will increase. In various exemplary embodiments, in the exposure of the first photoresist layer 150, by forming the first dummy pattern DP1 in a region with a relatively low pattern density to compensate for the density, the CD deviation of the pattern can be reduced.

[0052] According to an exemplary embodiment, a method of forming a pattern may include forming a second photoresist pattern 160P that covers a second dummy pattern DP2 formed by the first dummy pattern DP1. The second photoresist pattern 160P may cover the second dummy pattern DP2 while exposing the hard mask pattern 140P. Accordingly, the first photoresist pattern 150P (or the hard mask pattern 140P) may be transferred to the resulting pattern 130P, and the first dummy pattern DP1 (or the second dummy pattern DP2) may not be transferred to the resulting pattern 130P.

[0053] That is, in the method of forming a pattern, according to an exemplary embodiment, in order to make the pattern density uniform in each region, in the exposure of the first photoresist layer 150, the first dummy pattern DP1 may be formed, but the first dummy pattern DP1 that is not the target pattern may not be transferred to the resulting pattern 130P. That is, in the exposure of the first photoresist layer 150, the pattern density of the design pattern included in the design layout may be greater than the pattern density of the resulting pattern 130P.

[0054] According to the reference Figures 2 to 9 In the described exemplary embodiment, the first photoresist pattern 150P may be formed in the first region AR1, and the first dummy pattern DP1 may be formed in the second region AR2. To compensate for the pattern density with the first dummy pattern DP1, the design pattern included in the design layout may have the same (or similar) pattern density in the first region AR1 and the second region AR2. Thereafter, the first photoresist pattern 150P in the first region AR1 may be transferred to the resulting pattern 130P, and the first dummy pattern DP1 in the second region AR2 may not be transferred to the resulting pattern 130P, such that the resulting pattern 130P may have different pattern densities in the first region AR1 and the second region AR2. Accordingly, the pattern density difference between the first region AR1 and the second region AR2 in the design pattern included in the design layout may be smaller than the pattern density difference between the first region AR1 and the second region AR2 in the resulting pattern 130P.

[0055] In Figures 2 to 9Among them, the first region AR1 can refer to one of the memory cell area MCA (see Figure 1 ) and the peripheral circuit area PCA (see Figure 1 ), and the second region AR2 can refer to the other of the memory cell area MCA (see Figure 1 ) and the peripheral circuit area PCA (see Figure 1 ).

[0056] Figures 2 to 9 A method is shown, in which, when the first region AR1 is the memory cell area MCA (see Figure 1 ) and the second region AR2 is the peripheral circuit area PCA (see Figure 1 ), a dummy pattern is added to the peripheral circuit area PCA (see Figure 1 ), and the resulting pattern 130P is formed in the memory cell area MCA (see Figure 1 ). Figures 2 to 9 A method is shown, in which, when the first region AR1 is the peripheral circuit area PCA (see Figure 1 ) and the second region AR2 is the memory cell area MCA (see Figure 1 ), a dummy pattern is added to the memory cell area MCA (see Figure 1 ), and the resulting pattern 130P is formed in the peripheral circuit area PCA (see Figure 1 ).

[0057] In addition, Figures 2 to 9 An example is shown in which the first region AR1 and the second region AR2 are respectively one and the other of the memory cell area MCA (see Figure 1 ) and the peripheral circuit area PCA (see Figure 1 ), but the inventive concept is not limited thereto. The first region AR1 and the second region AR2 can refer to two different regions defined on the substrate 110 (see Figure 1 ).

[0058] Figure 10 is a schematic plan view showing the main components of the memory cell area MCA shown in Figure 1 .

[0059] Referring to Figure 10 , the memory cell area MCA can include a plurality of cell active regions A1. Each of the plurality of cell active regions A1 can have a main axis in an oblique direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction). A plurality of word lines WL can extend parallel to each other in the first horizontal direction (X direction) across the plurality of cell active regions A1. A plurality of bit lines BL can extend parallel to each other in the second horizontal direction (Y direction) on the plurality of word lines WL.

[0060] Multiple bit lines BL can be connected to multiple cell active regions A1 through direct contacts DC. Multiple buried contacts BC can be formed between two adjacent bit lines BL among the multiple bit lines BL. The multiple buried contacts BC can be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Multiple conductive landing pads LP can be formed on the multiple buried contacts BC. The multiple buried contacts BC and the multiple conductive landing pads LP can connect a lower electrode (not shown) of a capacitor formed above the multiple bit lines BL to the cell active region A1. Each of the multiple conductive landing pads LP can partially overlap the buried contact BC.

[0061] Figure 11 is a plan view showing an exemplary arrangement of multiple conductive patterns CNP arranged in Figure 1 the peripheral circuit region PCA shown.

[0062] Reference Figure 11 , multiple conductive patterns CNP can be arranged in Figure 1 the peripheral circuit region PCA of the integrated circuit device 1 shown. Some of the multiple conductive patterns CNP can extend parallel to each other. Some of the multiple conductive patterns CNP can be used as conductive pads for connecting a lower conductive region and an upper conductive region to each other. The multiple conductive patterns CNP can be separated from each other in a horizontal direction (e.g., the first horizontal direction (X direction) or the second horizontal direction (Y direction)), with spaces of various sizes therebetween. In some peripheral circuit regions PCA, the minimum separation distance between two adjacent conductive patterns CNP can be the minimum feature size of the integrated circuit device 1. In some other peripheral circuit regions PCA, the minimum separation distance between two adjacent conductive patterns CNP can be several times to dozens of times the minimum feature size of the integrated circuit device 1.

[0063] The horizontal width of each of the multiple conductive patterns CNP (e.g., the width in the first horizontal direction (X direction) and the width in the second horizontal direction (Y direction)) and the horizontal separation distance between each pair of conductive patterns among the multiple conductive patterns CNP (e.g., the separation distance in the first horizontal direction (X direction) and the separation distance in the second horizontal direction (Y direction)) can vary.

[0064] Figure 10 the multiple conductive landing pads LP and the direct contacts DC shown, and Figure 11 the multiple conductive patterns CNP shown can be formed through a series of processes including multiple exposure processes. In some example embodiments, for forming Figure 10 the multiple conductive landing pads LP and the direct contacts DC shown, and Figure 11A series of processes for the multiple conductive patterns CNP shown may include one exposure process using an EUV light source and one exposure process using a KrF excimer laser (248 nm), an ArF excimer laser (193 nm), and / or an F 2 excimer laser (157 nm) light source. The exposure process may include the method of forming a pattern described above with reference to Figures 2 to 9 description.

[0065] Figures 12A to 15B is a cross-sectional view showing a method of manufacturing an integrated circuit device 1 according to an exemplary embodiment. Figure 12A 、 Figure 13A 、 Figure 14A and Figure 15A are cross-sectional views of the memory cell area MCA, Figure 12B 、 Figure 13B 、 Figure 14B and Figure 15B are cross-sectional views of the peripheral circuit area PCA. Figures 12A to 15B shows a process of forming a pattern only in the peripheral circuit area PCA. Figures 12A to 15B shows a wiring process of the integrated circuit device 1.

[0066] Referring to Figure 12A and Figure 12B , in the memory cell area MCA and the peripheral circuit area PCA, a substrate 210, a first insulating layer pattern 212, a second insulating layer pattern 214, a peripheral device isolation layer 215, a device isolation layer 216, a word line 220, a buried insulating layer 224, a bit line structure 240, insulating spacers 250, and an insulating fence 280 may be formed. The substrate 210 may correspond to Figure 2 the substrate 110 of

[0067] First, in the memory cell area MCA, a device isolation layer trench 216T penetrating the substrate 210 may be formed, and the device isolation layer 216 may be formed inside the device isolation layer trench 216T. Thereafter, a gate dielectric layer 222, a lower word line 220a, and an upper word line 220b may be sequentially stacked on the substrate 210. The buried insulating layer 224, the first insulating layer pattern 212, and the second insulating layer pattern 214 may be sequentially stacked on the word line 220.

[0068] Thereafter, on the second insulating layer pattern 214, a conductive semiconductor pattern 232, a first metal-based conductive pattern 245, a second metal-based conductive pattern 246, and an insulating cover line 248 may be sequentially stacked, and first to third insulating spacers 252, 254, and 256 may be formed around the sidewalls of each of the conductive semiconductor pattern 232, the first metal-based conductive pattern 245, the second metal-based conductive pattern 246, and the insulating cover line 248.

[0069] Thereafter, an insulating fence 280 that penetrates at least a portion of each of the first insulating layer pattern 212, the second insulating layer pattern 214, and the buried insulating layer 224 may be formed adjacent to the insulating spacer 250. A preliminary insulating material layer 298P may be formed on the insulating fence 280. The preliminary insulating material layer 298P may correspond to Figure 2 the etch target layer 130.

[0070] In the peripheral circuit area PCA, a peripheral device isolation layer trench 215T that penetrates at least a portion of the substrate 210 may be formed, and a peripheral device isolation layer 215 may be formed inside the peripheral device isolation layer trench 215T. Thereafter, the first insulating layer pattern 212 and the second insulating layer pattern 214 may be sequentially stacked on the substrate 210.

[0071] Thereafter, a gate line structure 240P may be formed on the peripheral active region 217. The gate line structure 240P may include a gate line 247P, an insulating cover line 248 covering the gate line 247P, and a gate insulating spacer 250P covering the sidewalls of the gate line 247P and the insulating cover line 248. That is, the gate line 247P may have a stacked structure of a first metal-based conductive pattern 245 and a second metal-based conductive pattern 246. A gate insulating layer pattern 242 may be disposed between the gate line 247P and the peripheral active region 217. In some example embodiments, the gate line structure 240P may further include a conductive semiconductor pattern 232 disposed between the gate insulating layer pattern 242 and the first metal-based conductive pattern 245. Multiple gate lines 247P may constitute Figure 11 the plurality of conductive patterns CNP shown.

[0072] Thereafter, a first filling insulating layer 272 and a second filling insulating layer 274 may be formed on the sidewalls of the gate line structure 240P. Thereafter, a contact plug CP may be formed to penetrate at least a portion of each of the substrate 210, the first insulating layer pattern 212, the second insulating layer pattern 214, the first filling insulating layer 272, and the second filling insulating layer 274. A preliminary insulating material layer 298P may be formed on the second filling insulating layer 274, and the preliminary insulating material layer 298P may correspond to Figure 2 the etch target layer 130.

[0073] A hard mask structure HM and a first dummy pattern PR1_D may be formed on the preliminary insulating material layer 298P in the memory cell area MCA, and the hard mask structure HM covers the entire upper surface of the preliminary insulating material layer 298P. In addition, a hard mask structure HM and a first photoresist pattern PR1 may be formed on the preliminary insulating material layer 298P in the peripheral circuit area PCA. The hard mask structure HM may include first to third hard mask layers HM1, HM2, and HM3.

[0074] The first dummy pattern PR1_D in the memory cell region MCA and the first photoresist pattern PR1 in the peripheral circuit region PCA can be formed by exposing and developing the first photoresist layer. The first photoresist layer can be exposed according to the design layout. In an exemplary embodiment, the design patterns included in the design layout can have the same (or similar) pattern density in the memory cell region MCA and the peripheral circuit region PCA. The first photoresist layer can include a metal material and an inorganic material. For example, the first photoresist layer can include MOR.

[0075] When the first photoresist layer includes MOR, during pattern formation, due to the pattern density difference between regions, the CD distribution of the pattern may increase. In the manufacturing method according to the exemplary embodiment, by adding the first dummy pattern PR1_D during the process of exposing the first photoresist layer, the memory cell region MCA and the peripheral circuit region PCA can be formed to have a uniform pattern density.

[0076] At least a part of the upper surface of the hard mask structure HM in the memory cell region MCA can be covered by the first dummy pattern PR1_D, and at least a part of the upper surface of the hard mask structure HM in the peripheral circuit region PCA can be covered by the first photoresist pattern PR1.

[0077] In Figure 12A and Figure 12B the hard mask structure HM can correspond to Figure 4 the hard mask structure 140 of Figure 4 the first photoresist pattern PR1 can correspond to Figure 4 the first photoresist pattern 150P of

[0078] Referring to Figure 13A and Figure 13B in the memory cell region MCA, at least a part of the hard mask structure HM can be etched by using the first dummy pattern PR1_D as an etching mask, and in the peripheral circuit region PCA, at least a part of the hard mask structure HM can be etched by using the first photoresist pattern PR1 as an etching mask.

[0079] Therefore, in the memory cell region MCA, a second dummy pattern HMP_D corresponding to the position of the first dummy pattern PR1_D can be formed. The second dummy pattern HMP_D can include a second hard mask dummy pattern HM2P_D and a third hard mask dummy pattern HM3P_D. In the peripheral circuit region PCA, a hard mask pattern HMP corresponding to the position of the first photoresist pattern PR1 can be formed. The hard mask pattern HMP can include a second hard mask pattern HM2P and a third hard mask pattern HM3P.

[0080] In Figure 13A and Figure 13B the second dummy pattern HMP_D may correspond to the second dummy pattern DP2 of Figure 5 and the hard mask pattern HMP may correspond to the hard mask pattern 140P of Figure 5

[0081] Referring to Figure 14A and Figure 14B in the memory cell area MCA, a second photoresist pattern PR2 covering the second dummy pattern HMP_D may be formed. The second photoresist pattern PR2 may be formed by forming a second photoresist layer in the memory cell area MCA and the peripheral circuit area PCA and then performing an exposure and development process thereon. The second photoresist layer may be removed in the peripheral circuit area PCA, and the second photoresist layer may form the second photoresist pattern PR2 in the memory cell area MCA. The second photoresist pattern PR2 may correspond to the second photoresist pattern 160P of Figure 7

[0082] After forming the second photoresist pattern PR2 (e.g., after covering the second dummy pattern HMP_D in the memory cell area MCA), the first hard mask layer HM1 and the preliminary insulating material layer 298P may be etched by using the hard mask pattern HMP as an etching mask (see Figure 13B ). Accordingly, in the peripheral circuit area PCA, a plurality of peripheral bit line grooves 298R may be formed by removing a portion of the preliminary insulating material layer 298P (see Figure 13B ). By forming a plurality of peripheral bit line grooves 298R in the preliminary insulating material layer 298P (see Figure 13B ), a peripheral bit line insulating structure BPS may be formed.

[0083] The peripheral bit line insulating structure BPS in which a plurality of peripheral bit line grooves 298R are formed may correspond to the resulting pattern 130P of Figure 9

[0084] Referring to Figure 15A and Figure 15B in the memory cell area MCA, the second photoresist pattern PR2 and the second dummy pattern HMP_D may be removed. In an exemplary embodiment, in the memory cell area MCA, at least a portion of the preliminary insulating material layer 298P (see Figure 14A ) may be removed to form the insulating material layer 298. In another exemplary embodiment, the insulating material layer 298 may be formed without removing the preliminary insulating material layer 298P (see Figure 14A ​​​)。Thereafter, the capacitor dielectric layer 320 and the upper electrode 330 may be sequentially formed on the insulating material layer 298, thereby forming the integrated circuit device 1.

[0085] In the peripheral circuit area PCA, the hard mask pattern HMP may be removed, and a plurality of peripheral bit lines BLP may be formed in the plurality of peripheral bit line grooves 298R. Thereafter, a buried insulating layer 350 covering the plurality of peripheral bit lines BLP and the peripheral bit line insulating structure BPS may be formed, thereby forming the integrated circuit device 1.

[0086] Reference Figure 12A and Figure 15A , the first dummy pattern PR1_D is not transferred to the insulating material layer 298, and the first photoresist pattern PR1 is transferred to the peripheral bit line insulating structure BPS including the plurality of peripheral bit line grooves 298R. In the exposure of the first photoresist layer, the design pattern included in the design layout includes both the first dummy pattern PR1_D and the first photoresist pattern PR1. However, only the pattern corresponding to the first photoresist pattern PR1 can be formed as the resulting pattern in the preliminary insulating material layer 298P. That is, the pattern density of the design pattern included in the design layout may be greater than the pattern density of the resulting pattern.

[0087] Figures 12A to 15B A method of manufacturing an integrated circuit device is shown, which includes a method of forming a pattern, where the pattern is not formed in the memory cell area MCA but only in the peripheral circuit area PCA, but the exemplary embodiments are not limited thereto. Figures 12A to 15B A method is shown in which a dummy pattern is formed in the memory cell area MCA to compensate for the pattern density, and a pattern is formed in the peripheral circuit area PCA. However, in another exemplary embodiment, a dummy pattern may be formed in the peripheral circuit area PCA to compensate for the pattern density, and a pattern may be formed in the memory cell area MCA.

[0088] Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it is to be understood that various changes in form and detail may be made without departing from the spirit and scope of the claims.

[0089] This application is based on and claims priority to Korean Patent Application No. 10-2023-0181161, filed with the Korean Intellectual Property Office on December 13, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for forming a pattern, the method comprising: forming an etching target layer on a substrate, the substrate comprising a first region and a second region; forming a hard mask structure on the etching target layer; forming a first photoresist layer on the hard mask structure; forming a first photoresist pattern and a first dummy pattern by exposing and developing the first photoresist layer; forming a hard mask pattern corresponding to the first photoresist pattern and a second dummy pattern corresponding to the first dummy pattern by etching at least a portion of the hard mask structure using the first photoresist pattern and the first dummy pattern; forming a second photoresist layer on the second dummy pattern and the hard mask pattern; forming a second photoresist pattern covering the second dummy pattern and exposing the hard mask pattern by exposing and developing the second photoresist layer; as well as forming a resulting pattern from the etch target layer by using the hard mask pattern as an etch mask, Wherein, in a plan view, one of the first region and the second region surrounds the other of the first region and the second region. 2 . The method of claim 1 , wherein forming the first photoresist pattern and the first dummy pattern comprises forming the first photoresist pattern in the first region and forming the first dummy pattern in the second region. 3 . The method of claim 2 , wherein forming the second photoresist pattern comprises forming the second photoresist pattern over the entire second region on the upper surface of the substrate.

4. The method according to claim 2, wherein forming the first photoresist pattern and the first dummy pattern comprises exposing the first photoresist layer according to a design layout, The design pattern included in the design layout has the same pattern density in the first area and the second area.

5. The method according to claim 2, wherein: In forming the resultant pattern from the etch target layer, the resultant pattern has a greater pattern density in the first region than in the second region. 6 . The method of claim 1 , wherein a first wavelength of light used to expose the first photoresist layer is shorter than a second wavelength of light used to expose the second photoresist layer. 7 . The method of claim 1 , wherein the first photoresist pattern and the first dummy pattern each comprise a metal oxide photoresist (MOR).

8. The method according to claim 1, wherein: In forming the resultant pattern from the etch target layer, the etch target layer remains in a region overlapping with the second dummy pattern on the substrate and in a region overlapping with a region between a pair of adjacent second dummy patterns.

9. The method according to claim 1, wherein: The first region is a memory cell region of an integrated circuit device, and the second region is a peripheral circuit region of the integrated circuit device.

10. A method for forming a pattern, the method comprising: forming an etching target layer on a substrate, the substrate comprising a first region and a second region adjacent to the first region; forming a hard mask structure on the etch target layer, the hard mask structure comprising a plurality of hard mask layers; forming a first photoresist pattern and a first dummy pattern on the hard mask structure according to a design pattern of a design layout, the first photoresist pattern and the first dummy pattern each comprising a metal oxide photoresist (MOR); forming a hard mask pattern and a second dummy pattern by etching at least one of the plurality of hard mask layers using the first photoresist pattern and the first dummy pattern as an etching mask; as well as forming a resulting pattern from the etch target layer by using the hard mask pattern as an etch mask, wherein a pattern density of the design pattern of the design layout is greater than a pattern density of the resulting pattern on the substrate.

11. The method of claim 10, wherein a pattern density difference between the first region and the second region in the design pattern of the design layout is smaller than a pattern density difference between the first region and the second region in the resulting pattern on the substrate.

12. The method according to claim 10, wherein The first dummy pattern is located in the second region, and The second dummy pattern is formed by using the first dummy pattern as an etching mask in the second region. 13 . The method of claim 11 , wherein a pattern density of the resultant pattern in the first region is greater than a pattern density of the resultant pattern in the second region.

14. The method according to claim 11, further comprising: A second photoresist pattern is formed on the substrate to cover the entire second region where the second dummy pattern is located.

15. The method according to claim 14, wherein Each of the first photoresist pattern and the second photoresist pattern is formed by applying a photoresist layer and then performing exposure and development processes thereon, and The photoresist layer forming the first photoresist pattern includes tin (Sn).

16. The method according to claim 10, wherein: In forming the resultant pattern from the etch target layer, the etch target layer remains in a region overlapping with the second dummy pattern on the substrate and in a region overlapping with a region between a pair of adjacent second dummy patterns.

17. A method of manufacturing an integrated circuit device, the method comprising: forming an etching target layer on a substrate, the substrate comprising a memory cell region and a peripheral circuit region surrounding the memory cell region; forming a hard mask structure on the etching target layer in the memory cell region and the peripheral circuit region; forming a first photoresist layer on the hard mask structure in the memory cell region and the peripheral circuit region, wherein the first photoresist layer comprises a metal material; forming a first dummy pattern in the memory cell region and forming a first photoresist pattern in the peripheral circuit region by exposing and developing the first photoresist layer according to a design layout; forming a second dummy pattern corresponding to the first dummy pattern in the memory cell region, and forming a hard mask pattern corresponding to the first photoresist pattern in the peripheral circuit region; forming a second photoresist layer covering the hard mask pattern and the second dummy pattern in the memory cell region and the peripheral circuit region; forming a second photoresist pattern in the memory cell region by exposing and developing the second photoresist layer; as well as forming a resulting pattern from the etch target layer by using the hard mask pattern and the second photoresist pattern, Wherein a pattern density of a design pattern included in the design layout and a pattern density of the resultant pattern on the substrate are different from each other.

18. The method according to claim 17, wherein forming the first photoresist pattern by an exposure process using an extreme ultraviolet (EUV) light source, and The second photoresist pattern is formed by an exposure process using one of a krypton fluoride (KrF) light source and an argon fluoride (ArF) light source.

19. The method of claim 17, wherein the first photoresist pattern comprises a metal oxide photoresist (MOR).

20. The method of claim 17, wherein a pattern density difference between the memory cell region and the peripheral circuit region in the design pattern of the design layout is smaller than a pattern density difference between the memory cell region and the peripheral circuit region in the resulting pattern on the substrate.

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