Wafer bearing device and processing equipment

Abstract

The invention discloses a wafer bearing device and processing equipment, the wafer bearing device comprises a base, the top of the base is at least partially in a step shape with a first outer edge lower than a first inner edge; the tray is arranged on the first inner edge; at least part of the top of the tray is in a step shape with the second outer edge lower than the second inner edge. The edge protection ring is arranged above the first outer edge; the edge protection ring is arranged around the base; the top protection ring is arranged above the second outer edge and the edge protection ring; the top protection ring is arranged around the tray; when the second inner edge bears the wafer, the top protection ring, the edge protection ring and the wafer are matched to cover the upper surfaces and the outer circumferential surfaces of the tray and the base, and plasma can be prevented from bombarding the base and the tray under the condition that the tray and the base are not provided with plating layers.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a wafer carrier device and a processing equipment. Background Art

[0002] In a semiconductor processing equipment, a susceptor for carrying a wafer is disposed inside a reaction chamber; since the susceptor is usually directly exposed to a plasma environment, when the wafer is processed by plasma, the plasma located outside the wafer edge will directly bombard the susceptor below the wafer edge, resulting in damage to the susceptor, and even causing metal and particle contamination to the wafer or the reaction chamber.

[0003] Currently, a coating layer (such as nickel / anodization / yttrium oxide, etc.) is usually formed on the surface of the susceptor to prevent the susceptor from being directly exposed to the plasma environment; however, when the susceptor is heated to a relatively high temperature (greater than 300 °C), the coating layer may crack due to different thermal expansion coefficients from the susceptor, thereby exposing the susceptor, which will also cause damage to the susceptor and metal and particle contamination. Summary of the Invention

[0004] The purpose of the present invention is to provide a wafer carrier device and a processing equipment, in which a top protection ring, an edge protection ring and a wafer cooperate to cover the upper surface and the outer circumferential surface of a tray and a susceptor, so as to prevent plasma from bombarding the susceptor and the tray when there is no coating layer on the tray and the susceptor.

[0005] To achieve the above purpose, the present invention is realized by the following technical solutions:

[0006] A wafer carrier device, comprising:

[0007] A susceptor, at least part of the top of the susceptor is a stepped shape with a first outer edge lower than a first inner edge;

[0008] A tray, disposed on the first inner edge; at least part of the top of the tray is a stepped shape with a second outer edge lower than a second inner edge;

[0009] An edge protection ring, disposed above the first outer edge; and the edge protection ring surrounds the susceptor; and

[0010] A top protection ring, disposed above the second outer edge and the edge protection ring; and the top protection ring surrounds the tray;

[0011] When the second inner edge carries the wafer, the top protection ring, the edge protection ring and the wafer cooperate to cover the upper surface and the outer circumferential surface of the tray and the susceptor, so as to prevent plasma from bombarding the susceptor and the tray.

[0012] Optionally, the edge protection ring includes an inner edge disposed above the first outer edge and a lower edge extending downward along the outer edge of the inner edge; the lower edge is located radially outside the base.

[0013] Optionally, the edge protection ring and the top protection ring are of a split structure. The lower end face of the top protection ring is mounted in contact with the upper end face of the second outer edge, the lower end face of the inner edge is mounted in contact with the upper end face of the first outer edge, and there is a first reserved gap between the edge protection ring and the top protection ring.

[0014] Optionally, the edge protection ring and the top protection ring are of an integrally mounted structure. The lower end face of the top protection ring is mounted in contact with the upper end face of the second outer edge, the upper end face of the inner edge is mounted in contact with the lower end face of the top protection ring, and there is a second reserved gap between the edge protection ring and the base.

[0015] Optionally, the thickness of the inner edge is less than the height difference between the second outer edge and the first outer edge.

[0016] Optionally, the height of the first reserved gap is less than 0.5 mm.

[0017] Optionally, the height of the second reserved gap is less than 0.5 mm.

[0018] Optionally, the inner diameter of the inner edge is greater than the larger of the outer diameters of the first inner edge and the second outer edge, so as to form a third reserved gap between the inner edge and the base or the tray.

[0019] Optionally, the inner diameter of the lower edge is greater than the outer diameter of the first outer edge, so as to form a fourth reserved gap between the lower edge and the base.

[0020] Optionally, the width of the third reserved gap is greater than 1 mm.

[0021] Optionally, the width of the fourth reserved gap is greater than 1 mm.

[0022] Optionally, the inner diameter of the top protection ring is greater than the outer diameter of the second inner edge, so as to form a fifth reserved gap between the top protection ring and the second inner edge.

[0023] Optionally, the width of the fifth reserved gap is greater than 0.5 mm.

[0024] Optionally, the diameter of the wafer is greater than the inner diameter of the top protection ring;

[0025] The inner top of the top protection ring is of a stepped type with a third inner edge lower than a third outer edge; and the third inner edge is located below the wafer.

[0026] Optionally, the height difference between the third inner edge and the second outer edge is less than the height difference between the second inner edge and the second outer edge, so as to form a sixth preset gap between the third inner edge and the lower surface of the wafer.

[0027] Optionally, the height of the sixth preset gap is less than 0.5 mm.

[0028] Optionally, the third outer edge and the third inner edge are connected by an inclined surface, and the included angle between the inclined surface and the third inner edge is greater than 90°.

[0029] Optionally, the edge protection ring further includes an upper edge extending upward along the outer edge of the inner edge; a recess matching the upper edge is provided at the outer bottom of the top protection ring.

[0030] Optionally, the recess and the upper edge do not contact each other.

[0031] Optionally, a heating device and a cooling device are provided inside the base to regulate the temperature of the wafer.

[0032] Optionally, one of the base and the tray is provided with a positioning hole, and the other is provided with a positioning pin matching the positioning hole; the base and the tray are positioned by the cooperation of the positioning hole and the positioning pin.

[0033] Optionally, the base is provided with a first lifting pin hole for the lifting pin to pass through, and the tray is provided with a second lifting pin hole for the lifting pin to pass through; and the diameter of the second lifting pin hole is greater than the diameter of the first lifting pin hole.

[0034] Optionally, the upper surface and the outer circumferential surface of the base do not have a coating.

[0035] On the other hand, the present invention further provides a processing device, including: a reaction chamber; and the wafer carrying device as described above, and the wafer carrying device is arranged at the inner bottom of the reaction chamber.

[0036] The present invention has at least one of the following advantages compared with the prior art:

[0037] In the wafer carrying device and the processing device provided by the present invention, at least part of the top of the base of the carrying tray is a stepped type with the first outer edge lower than the first inner edge, at least part of the top of the tray is a stepped type with the second outer edge lower than the second inner edge, and an edge protection ring is provided above the first outer edge, and a top protection ring is provided above the second outer edge and the edge protection ring; when the second inner edge carries the wafer, the top protection ring, the edge protection ring and the wafer cooperate to cover the upper surface and the outer circumferential surface of the tray and the base, so as to prevent the plasma from bombarding the base and the tray even when the tray and the base do not have a coating, thereby ensuring the service life of the tray and the base.

[0038] When the edge protection ring and the top protection ring are of a split structure in the present invention, the lower end surface of the inner edge in the edge protection ring is attached to and installed on the upper end surface of the first outer edge, and a first reserved gap is formed between the edge protection ring and the top protection ring attached to and installed on the upper end surface of the second outer edge, so that the edge protection ring and the top protection ring do not contact each other, thereby avoiding the influence of the thermal expansion and contraction of the base and / or the edge protection ring on the flatness of the top protection ring, and further avoiding the influence on the flatness of the wafer, so as to ensure the uniformity of the wafer process treatment result.

[0039] When the edge protection ring and the top protection ring are of an integrally installed structure in the present invention, the lower end surface of the top protection ring is attached to and installed on the upper end surface of the second outer edge, the lower end surface of the inner edge in the edge protection ring is attached to and installed on the lower end surface of the top protection ring, and a second reserved gap is formed between the edge protection ring and the base, so that the edge protection ring and the base do not contact each other, thereby avoiding the influence of the thermal expansion and contraction of the base on the flatness of the edge protection ring and the top protection ring, and further avoiding the influence on the flatness of the wafer, so as to ensure the uniformity of the wafer process treatment result.

[0040] A sixth preset gap is formed between the third inner edge in the top protection ring and the lower surface of the wafer in the present invention, so that the top protection ring and the wafer do not contact each other, thereby preventing the influence of the top protection ring on the flatness of the wafer when the thermal expansion and contraction amount of the top protection ring is inconsistent with that of the wafer, and further ensuring the uniformity of the wafer process treatment result. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic structural diagram of a wafer carrier device provided in Embodiment 1 of the present invention;

[0042] Figure 2 is Figure 1 an enlarged schematic diagram of A in

[0043] Figure 3 is Figure 1 an enlarged schematic diagram of B in

[0044] Figure 4 is a schematic structural diagram of the integral installation of the edge protection ring and the top protection ring in a wafer carrier device provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The following further elaborates on a wafer carrier device and a processing apparatus proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and all use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention. In order to make the objectives, features, and advantages of the present invention more obvious and understandable, please refer to the accompanying drawings. It should be understood that the structures, scales, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the objectives that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention.

[0046] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0047] Embodiment 1

[0048] In conjunction with the attached Figures 1 to 3As shown in the figure, in this embodiment, a wafer carrier device is provided, including: a base 110, at least a part of the top of the base 110 is a stepped shape where the first outer edge 1101 is lower than the first inner edge 1102; a tray 120, disposed on the first inner edge 1102; at least a part of the top of the tray 120 is a stepped shape where the second outer edge 1201 is lower than the second inner edge 1202, and the second inner edge 1202 is used to carry the wafer 100; an edge protection ring 130, disposed above the first outer edge 1101; and the edge protection ring 130 is arranged around the base 110; and a top protection ring 140, disposed above the edge protection ring 130 and the second outer edge 1201; and the top protection ring 140 is arranged around the tray 120. When the second inner edge 1202 carries the wafer 100, the top protection ring 140, the edge protection ring 130 and the wafer 100 cooperate to cover the upper surface and the outer circumferential surface of the tray 120 and the base 110, so as to prevent plasma from bombarding the base 110 and the tray 120.

[0049] Specifically, the wafer carrier device can be disposed at the inner bottom of a reaction chamber 200, wherein the base 110 can be electrically connected to a radio frequency source (not shown in the figure), so that the base 110 serves as an electrode plate and ionizes the process gas introduced into the reaction chamber 200 into plasma, thereby performing processes such as etching and deposition on the wafer 100 carried on the second inner edge 1202 under preset conditions (such as preset temperature, preset pressure, etc.). More specifically, in this embodiment, when performing a process on the wafer 100, the edge protection ring 130 and the tray 120 carried on the first inner edge 1102 cooperate to cover the upper surface and the outer circumferential surface of the base 110; the top protection ring 140 and the wafer 100 carried on the second inner edge 1202 cooperate to cover the upper surface and a part of the outer circumferential surface of the tray, and the top protection ring 140 and the edge protection ring 130 cooperate to cover another part of the outer circumferential surface of the tray; overall, the top protection ring 140, the edge protection ring 130 and the wafer 100 cooperate to form a protective cover covering the upper surface and the outer circumferential surface of the tray 120 and the base 110, thereby preventing plasma from contacting the upper surface and the outer circumferential surface of the tray 120 and the base 110, and further preventing plasma from bombarding the tray 120 and the base 110, so as to ensure the service life of the tray 120 and the base 110.

[0050] Specifically, in one embodiment, a heating device 150 and a cooling device 160 are provided in the base 110 to regulate the temperature of the wafer 100, so that the wafer 100 can be heated to a preset temperature or cooled to a preset temperature. Optionally, the heating device 150 and the cooling device 160 can be evenly arranged in the base 110 to perform zone temperature control on the tray 120 and the wafer 100, thereby ensuring the uniformity of the temperature distribution on the wafer 100, and further ensuring the uniformity of the process treatment results of the wafer 100. Optionally, the tray 120 can be made of materials such as silicon carbide SiC, aluminum nitride AlN, aluminum oxide Al2O3 or yttrium oxide Y2O3, so that the tray 120 has both good thermal conductivity and good corrosion resistance, so that the tray 120 can quickly conduct the heat of the base 110 to the wafer 100 while having a certain resistance to plasma bombardment, but the present invention is not limited thereto.

[0051] Specifically, in one embodiment, when the top protection ring 140, the edge protection ring 130 and the wafer 100 cooperate with each other, the upper surface and the outer circumferential surface of the base 110 can be the surfaces of bare metal, that is, without a coating. This can not only avoid the problem of coating cracking under high-temperature working conditions, but also reduce the manufacturing cost of the base 110. Optionally, the material of the base 110 is aluminum alloy or stainless steel, etc., but the present invention is not limited thereto.

[0052] Please refer to Figure 1 and Figure 2 , the edge protection ring 130 includes an inner edge 1301 disposed above the first outer edge 1101 and a lower edge 1302 extending downward along the outer edge of the inner edge 1301; the lower edge 1302 is located radially outside the base 110.

[0053] Specifically, in one embodiment, the inner edge 1301 and the tray 120 cooperate to cover the upper surface of the base 110, and the lower edge 1302 can cover the outer circumferential surface of the base 110. More specifically, the inner diameter of the inner edge 1301 is greater than the larger of the outer diameters of the first inner edge 1102 and the second outer edge 1201, so as to form a third reserved gap 133 between the inner edge 1301 and the first inner edge 1102 of the base 110 or the second outer edge 1201 of the tray 120; the inner diameter of the lower edge 1302 is greater than the outer diameter of the first outer edge 1101, so as to form a fourth reserved gap 134 between the lower edge 1302 and the base 110; wherein, the third reserved gap 133 and the fourth reserved gap 134 are thermal expansion gaps and installation gaps reserved between the edge protection ring 130 and the base 110 and the tray 120, to prevent the base 110 and the tray 120 from squeezing the edge protection ring 130 after thermal expansion, thereby ensuring the reliability and service life of the edge protection ring 130. Optionally, the outer diameters of the first inner edge 1102 and the second outer edge 1201 are the same; the widths of the third reserved gap 133 and the fourth reserved gap 134 are both greater than 1 mm; preferably, the widths of the third reserved gap 133 and the fourth reserved gap 134 are both 2 mm, but the present invention is not limited thereto.

[0054] Please continue to refer to Figure 2 , the edge protection ring 130 and the top protection ring 140 are of a split structure. The lower end surface of the top protection ring 140 is fitted and installed on the upper end surface of the second outer edge 1201, the lower end surface of the inner edge 1301 is fitted and installed on the upper end surface of the first outer edge 1101, and there is a first reserved gap 131 between the edge protection ring 130 and the top protection ring 140.

[0055] Specifically, the lower end surface of the top protection ring 140 is attached to and installed on the upper end surface of the second outer edge 1201, so that the top protection ring 140 always takes the tray 120 as the installation reference, thereby ensuring that the flatness of the top protection ring 140 is always consistent with the flatness of the wafer 100 carried on the tray 120. More specifically, the setting of the first reserved gap 131 can prevent the edge protection ring 130 from contacting the top protection ring 140, thereby avoiding the influence of the thermal expansion and contraction of the base 110 and / or the edge protection ring 130 on the flatness of the top protection ring 140, and further avoiding the influence on the flatness of the wafer 100, so as to ensure the uniformity of the process treatment result of the wafer 100. Optionally, the thickness of the inner edge 1301 is less than the height difference between the second outer edge 1201 and the first outer edge 1101, that is, the thickness of the inner edge 1301 is less than the vertical distance between the upper end surface of the second outer edge 1201 and the upper end surface of the first outer edge 1101, so that the first reserved gap 131 can be formed between the edge protection ring 130 and the top protection ring 140.

[0056] Specifically, since the top protection ring 140 is located above the edge protection ring 130 and the third gap 133, the first reserved gap 131 communicates with the third reserved gap 133; optionally, the height of the first reserved gap 131 is less than 0.5 mm to prevent plasma from entering the third reserved gap 133 along the first reserved gap 131, thereby avoiding plasma bombardment on the outer circumferential surfaces of the base 110 and the tray 120. Preferably, the height of the first reserved gap 131 is 0.3 mm, but the present invention is not limited thereto.

[0057] In one embodiment, the edge protection ring 130 and the top protection ring 140 can be made of non-metallic materials to ensure that the edge protection ring 130 and the top protection ring 140 will not become part of the radio frequency path, thereby further preventing plasma from entering the third reserved gap 133 along the first reserved gap 131. Optionally, the edge protection ring 130 and the top protection ring 140 can both be made of materials such as ceramics, single crystal silicon or SiC, so that the edge protection ring 130 and the top protection ring 140 have good corrosion resistance, weak conductivity, and a small thermal conductivity coefficient, so as to reduce the heat loss of the base 110 and the tray 120, thereby ensuring the heating efficiency of the wafer 100 and the uniformity of the temperature distribution, but the present invention is not limited thereto.

[0058] Please continue to refer to Figure 2The inner diameter of the top protection ring 140 is greater than the outer diameter of the second inner edge 1202, so as to form a fifth reserved gap 141 between the top protection ring 140 and the second inner edge 1202.

[0059] Specifically, the fifth reserved gap 141 is a thermal expansion gap and an installation gap reserved between the top protection ring 140 and the tray 120, to prevent the tray 120 from squeezing the top protection ring 140 after thermal expansion, so as to avoid damage to the top protection ring 140 or the top protection ring 140 being stuck by the tray 120 and the edge protection ring 130 and unable to be disassembled, thereby ensuring the reliability and service life of the top protection ring 140. Optionally, the width of the fifth reserved gap 141 is greater than 0.5 mm; preferably, the width of the fifth reserved gap 141 is 1 mm, but the present invention is not limited thereto.

[0060] Please continue to refer to Figure 2 The diameter of the wafer 100 is greater than the inner diameter of the top protection ring 140; the inner top of the top protection ring 140 is a stepped shape where the third inner edge 1401 is lower than the third outer edge 1402; and the third inner edge 1401 is located below the wafer 100.

[0061] Specifically, in one embodiment, the third outer edge 1402 and the third inner edge 1401 are connected by an inclined surface 1403, and the included angle between the inclined surface 1403 and the third inner edge 1401 is greater than 90°, to prevent plasma from accumulating at this included angle; at this time, the third inner edge 1401 has an inner diameter and an outer diameter, and the inner diameter of the third inner edge 1401 is the inner diameter of the top protection ring 140; optionally, the inner diameter of the third inner edge 1401 can be 0.5 mm to 3 mm smaller than the diameter of the wafer 100, and the outer diameter of the third inner edge 1401 can be 0.5 mm to 2 mm larger than the diameter of the wafer 100, but the present invention is not limited thereto.

[0062] Specifically, in one embodiment, the height difference between the third inner edge 1401 and the second outer edge 1201 is less than the height difference between the second inner edge 1202 and the second outer edge 1201, that is, the vertical distance between the upper end surfaces of the third inner edge 1401 and the second outer edge 1201 is less than the vertical distance between the upper end surfaces of the second inner edge 1202 and the second outer edge 1201, so as to form a sixth preset gap 142 between the third inner edge 1401 and the lower surface of the wafer 100; and the setting of the sixth preset gap 142 can prevent the top protection ring 140 from contacting the wafer 100, thereby preventing the flatness of the wafer 100 from being affected when the thermal expansion and contraction amount of the top protection ring 140 is inconsistent with that of the wafer 100, and further ensuring the uniformity of the process treatment result of the wafer 100. More specifically, the sixth reserved gap 142 communicates with the fifth reserved gap 141, and the height of the sixth reserved gap 142 is less than 0.5 mm to prevent plasma from entering the fifth reserved gap 141 along the sixth reserved gap 142, thereby preventing the plasma from bombarding the outer circumferential surface of the tray 120. Optionally, the height of the sixth reserved gap 142 is 0.3 mm, but the present invention is not limited thereto.

[0063] Specifically, in one embodiment, the edge protection ring 130 further includes an upper edge 1303 extending upward along the outer edge of the inner edge 1301. A recess matching the upper edge 1303 is provided at the outer bottom of the top protection ring, and the recess does not contact the upper edge 1303. At this time, the cross-section of the first reserved gap 131 between the top protection ring 140 and the edge protection ring 130 is zigzag, making it more difficult for plasma to enter the third reserved gap 133 along the first reserved gap 131, further preventing the plasma from bombarding the outer circumferential surfaces of the base 110 and the tray 120, but the present invention is not limited thereto.

[0064] Please refer to Figure 1, one of the base 110 and the tray 120 is provided with a positioning hole, and the other is provided with a positioning pin 171 that matches the positioning hole; and the base 110 and the tray 120 are positioned by the cooperation of the positioning hole and the positioning pin 171. In this way, the tray 120 can be stably installed on the base 110, and the centering accuracy between the tray 120 and the base 110 can be ensured, thereby improving the uniformity of the process treatment result of the wafer 100. Optionally, the positioning hole can be a radial waist-shaped hole to reserve a thermal expansion displacement margin for the positioning pin 171, so that the positioning pin 171 can still achieve a clearance fit with the positioning hole after thermal expansion, and thus the positioning pin 171 and the positioning hole are not damaged. However, the present invention is not limited thereto.

[0065] Please also refer to Figure 1 and Figure 3 , a lifting pin (not shown in the figure) passes through the first lifting pin hole 111 on the base 110, and a second lifting pin hole 121 for the lifting pin to pass through is provided on the tray 120. And the lifting pin can sequentially pass through the first lifting pin hole 111 and the second lifting pin hole 121 to lift the wafer 100 or lower the wafer 100 back into the tray 120 according to process requirements. More specifically, the diameter of the second lifting pin hole 121 is larger than the diameter of the first lifting pin hole 111, so that when the base 110 and the lifting pin are thermally expanded and the expansion value is greater than the expansion value of the tray 120, the lifting pin can still smoothly pass through the second lifting pin hole 121, thereby not damaging the lifting pin and the tray 120. However, the present invention is not limited thereto.

[0066] Embodiment 2

[0067] Combined with the attached Figure 4 As shown, the difference between this embodiment and Embodiment 1 is that the edge protection ring 130 and the top protection ring 140 are integrally installed structures. The lower end surface of the top protection ring 140 is attached to the upper end surface of the second outer edge 1201 for installation, the upper end surface of the inner edge 1301 is attached to the lower end surface of the top protection ring 140 for installation, and there is a second reserved gap 132 between the edge protection ring 130 and the base 110.

[0068] Specifically, in this embodiment, the top protection ring 140 also takes the tray 120 as the installation reference, and the setting of the second reserved gap 132 can prevent the edge protection ring 130 from contacting the base 110, so as to avoid the influence of the thermal expansion and contraction of the base 110 on the flatness of the edge protection ring 130 and the top protection ring 140, thereby avoiding the influence on the flatness of the wafer 100, and further ensuring the uniformity of the process treatment result of the wafer 100. Optionally, the thickness of the inner edge 1301 is less than the height difference between the second outer edge 1201 and the first outer edge 1101, that is, the thickness of the inner edge 1301 is less than the vertical distance between the upper end surfaces of the second outer edge 1201 and the first outer edge 1101, so that the second reserved gap 132 can be formed between the edge protection ring 130 and the base 110; preferably, the height of the second reserved gap 132 is less than 0.5 mm.

[0069] Specifically, in this embodiment, the second reserved gap 132 communicates with the fourth reserved gap 134 and the third reserved gap 133. Since the opening of the fourth reserved gap 134 faces the bottom of the reaction chamber, it is difficult for the plasma to enter the second reserved gap 132 and the third reserved gap 133 along the fourth reserved gap 134. At this time, there is no limitation on whether the edge protection ring 130 is a part of the radio frequency path, and the edge protection ring 130 can also be made of materials such as pure nickel, hard anodized aluminum, and Hastelloy. In addition, the upper edge 1303 in the edge protection ring 130 and the recess in the top protection ring 140 may or may not be in contact, but the present invention is not limited thereto.

[0070] On the other hand, in combination with the attached Figure 1 As shown, the present invention also provides a processing device, including: a reaction chamber 200; and the wafer carrier device as described above, and the wafer carrier device is arranged at the inner bottom of the reaction chamber 200.

[0071] Specifically, a shower head 210 is further provided at the inner top of the reaction chamber 200 for introducing the process gas into the reaction chamber 200; and the shower head 210 is disposed opposite to the base 110, but the present invention is not limited thereto.

[0072] In summary, in a wafer carrier device and a processing equipment provided by the present invention, at least part of the top of the base of the carrier tray is a stepped shape with a first outer edge lower than a first inner edge, at least part of the top of the tray is a stepped shape with a second outer edge lower than a second inner edge, an edge protection ring is provided above the first outer edge, and a top protection ring is provided above the second outer edge and the edge protection ring; when the second inner edge carries the wafer, the top protection ring, the edge protection ring and the wafer cooperate to cover the upper surface and the outer circumferential surface of the tray and the base, so as to prevent the plasma from bombarding the base and the tray even when the tray and the base have no plating layer, thereby ensuring the service life of the tray and the base. When the edge protection ring and the top protection ring are of a split structure in the present invention, the lower end surface of the inner edge of the edge protection ring is attached to and installed on the upper end surface of the first outer edge, and a first reserved gap is formed between the edge protection ring and the top protection ring attached to and installed on the upper end surface of the second outer edge, so that the edge protection ring and the top protection ring do not contact each other, thereby avoiding the influence of the thermal expansion and contraction of the base and / or the edge protection ring on the flatness of the top protection ring, and further avoiding the influence on the flatness of the wafer, so as to ensure the uniformity of the wafer process treatment result. When the edge protection ring and the top protection ring are of an integral installation structure, the lower end surface of the top protection ring is attached to and installed on the upper end surface of the second outer edge, the lower end surface of the inner edge of the edge protection ring is attached to and installed on the lower end surface of the top protection ring, and a second reserved gap is formed between the edge protection ring and the base, so that the edge protection ring and the base do not contact each other, thereby avoiding the influence of the thermal expansion and contraction of the base on the flatness of the edge protection ring and the top protection ring, and further avoiding the influence on the flatness of the wafer, so as to ensure the uniformity of the wafer process treatment result. In addition, a sixth preset gap is formed between the third inner edge of the top protection ring and the lower surface of the wafer, so that the top protection ring and the wafer do not contact each other, thereby preventing the influence of the top protection ring on the flatness of the wafer when the thermal expansion and contraction amount of the top protection ring is inconsistent with that of the wafer, and further ensuring the uniformity of the wafer process treatment result.

[0073] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description should not be construed as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and substitutions to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A wafer carrier device, characterized in that, comprising: a base, at least part of the top of the base being a stepped shape with a first outer edge lower than a first inner edge; a tray, disposed on the first inner edge; at least part of the top of the tray being a stepped shape with a second outer edge lower than a second inner edge; an edge protection ring, disposed above the first outer edge; and the edge protection ring surrounding the base; and a top protection ring, disposed above the second outer edge and the edge protection ring; and the top protection ring surrounding the tray; when the second inner edge carries the wafer, the top protection ring, the edge protection ring and the wafer cooperate to cover the upper surface and the outer circumferential surface of the tray and the base, so as to prevent plasma from bombarding the base and the tray.

2. The wafer carrier device according to claim 1, characterized in that, the edge protection ring includes an inner edge disposed above the first outer edge and a lower edge extending downward along the outer edge of the inner edge; the lower edge is located radially outside the base.

3. The wafer carrier device according to claim 2, characterized in that, the edge protection ring and the top protection ring are of a split structure, the lower end surface of the top protection ring is installed in contact with the upper end surface of the second outer edge, the lower end surface of the inner edge is installed in contact with the upper end surface of the first outer edge, and there is a first reserved gap between the edge protection ring and the top protection ring.

4. The wafer carrier device according to claim 2, characterized in that, the edge protection ring and the top protection ring are of an integral installation structure, the lower end surface of the top protection ring is installed in contact with the upper end surface of the second outer edge, the upper end surface of the inner edge is installed in contact with the lower end surface of the top protection ring, and there is a second reserved gap between the edge protection ring and the base.

5. The wafer carrier device according to claim 3 or 4, characterized in that, the thickness of the inner edge is less than the height difference between the second outer edge and the first outer edge.

6. The wafer carrier device according to claim 3, characterized in that, the height of the first reserved gap is less than 0.5 mm.

7. The wafer carrier device according to claim 4, characterized in that, the height of the second reserved gap is less than 0.5 mm.

8. The wafer carrier device according to claim 3 or 4, characterized in that, the inner diameter of the inner edge is greater than the larger of the outer diameters of the first inner edge and the second outer edge, so as to form a third reserved gap between the inner edge and the base or the tray.

9. The wafer carrier device according to claim 3 or 4, characterized in that, the inner diameter of the lower edge is greater than the outer diameter of the first outer edge, so as to form a fourth reserved gap between the lower edge and the base.

10. The wafer carrier device according to claim 8, characterized in that, the width of the third reserved gap is greater than 1 mm.

11. The wafer carrier device according to claim 9, characterized in that, the width of the fourth reserved gap is greater than 1 mm.

12. The wafer carrier device according to claim 3 or 4, characterized in that, The inner diameter of the top protection ring is greater than the outer diameter of the second inner edge, so as to form a fifth reserved gap between the top protection ring and the second inner edge.

13. The wafer carrier device according to claim 12, wherein, the width of the fifth reserved gap is greater than 0.5 mm.

14. The wafer carrier device according to claim 12, wherein, the diameter of the wafer is greater than the inner diameter of the top protection ring; the inner top of the top protection ring is a stepped shape where the third inner edge is lower than the third outer edge; and the third inner edge is located below the wafer.

15. The wafer carrier device according to claim 14, wherein, the height difference between the third inner edge and the second outer edge is less than the height difference between the second inner edge and the second outer edge, so as to form a sixth preset gap between the third inner edge and the lower surface of the wafer.

16. The wafer carrier device according to claim 15, wherein, the height of the sixth preset gap is less than 0.5 mm.

17. The wafer carrier device according to claim 14, wherein, the third outer edge and the third inner edge are connected by an inclined surface, and the included angle between the inclined surface and the third inner edge is greater than 90°.

18. The wafer carrier device according to claim 3 or 4, wherein, the edge protection ring further includes an upper edge extending upward along the outer edge of the inner edge; a recess matching the upper edge is provided at the outer bottom of the top protection ring.

19. The wafer carrier device according to claim 18, wherein, the recess and the upper edge do not contact.

20. The wafer carrier device according to claim 1, wherein, a heating device and a cooling device are provided inside the base to regulate the temperature of the wafer.

21. The wafer carrier device according to claim 1, wherein, one of the base and the tray is provided with a positioning hole, and the other is provided with a positioning pin matching the positioning hole; and the base and the tray are positioned by the cooperation of the positioning hole and the positioning pin.

22. The wafer carrier device according to claim 1, wherein, the base is provided with a first lifting pin hole for the lifting pin to pass through, and the tray is provided with a second lifting pin hole for the lifting pin to pass through; and the diameter of the second lifting pin hole is greater than the diameter of the first lifting pin hole.

23. The wafer carrier device according to claim 1, wherein, the upper surface and the outer circumferential surface of the base have no coating.

24. A processing device, wherein, comprises: a reaction chamber; and the wafer carrier device according to any one of claims 1 to 23, and the wafer carrier device is arranged at the inner bottom of the reaction chamber.

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