Pixel doping diffusion test structure, test method and calibration method

Abstract

The invention discloses a pixel doping diffusion test structure, a test method and a calibration method, the test method is suitable for a CMOS image sensor, and the test method comprises the following steps: providing a test wafer; forming a test modulation structure on the front surface of the test wafer so as to modulate doping of the test wafer; performing doping treatment on the test wafer from the front surface of the test wafer, and forming a doped region in the test wafer; and performing a doping diffusion test on the test wafer from the front surface of the test wafer to obtain the doping distribution condition of the doped region. The test modulation structure is arranged on the front surface of the test wafer to modulate doping of the test wafer, and then the test wafer provided with the test modulation structure is subjected to a doping diffusion test, so that the influence of the test modulation structure on doping distribution of a doping region in the test wafer can be tested; and the test result is closer to the actual doping effect, so that the doping can be calibrated better.

Description

Technical Field

[0001] The present invention relates to the technical field of pixel doping diffusion testing, and particularly to a testing structure for pixel doping diffusion, a testing method, and a calibration method. Background Art

[0002] An image sensor refers to a device that converts optical signals into electrical signals. Generally, large-scale commercially available image sensor chips include two major categories: charge-coupled device (CCD) and complementary metal oxide semiconductor (CMOS) image sensor chips.

[0003] Compared with traditional CCD sensors, CMOS image sensors have the characteristics of low power consumption, low cost, and compatibility with CMOS processes, so they are increasingly widely used. Now, CMOS image sensors are not only used in the field of consumer electronics, such as miniature digital cameras (DSCs), mobile phone cameras, video cameras, and digital single-lens reflex (DSLR) cameras, but also widely used in the fields of automotive electronics, monitoring, biotechnology, and medicine.

[0004] According to the different paths of incident light entering the photodiode, CMOS image sensors can be divided into two types: front-illuminated and back-illuminated image sensors. Front-illuminated means that the incident light enters the photodiode from the side close to the circuit connection layer, while back-illuminated means that the incident light enters the photodiode from the side far from the circuit connection layer. Among them, the photodiode is mainly formed by N-type doping of a P-type doped silicon substrate to form a PN junction. In addition, the preparation of transistors in the pixel unit, the preparation of isolation between pixel units, and the preparation of isolation between transistors in the pixel unit are mostly based on N-type doping and P-type doping. The concentrations of N-type doping and P-type doping need to be accurately controlled to ensure that the CMOS image sensor has good performance.

[0005] In order to accurately control the concentrations of N-type doping and P-type doping, it is usually necessary to test the distribution of N-type doping and P-type doping diffusion in advance. For large pixel doping calibration, doping is generally done on a light sheet, that is, N-type doping or P-type doping is performed on a clean wafer using IMP (ion implantation), and then SIMS (secondary ion mass spectrometry) testing is used to calibrate the longitudinal distribution of doping diffusion. In simulation, doping diffusion is usually set to be isotropic. However, now the pixel size is gradually decreasing, the challenges for pixel doping simulation are gradually increasing, the doping concentration is increasing, and even the diffusion temperature is relatively high. Using the calibration parameters of large pixels for simulation can no longer meet the requirements. Moreover, in the actual production of CMOS image sensors, there are also other structures that affect the doping concentration. Conducting doping tests on a clean wafer, the test results and calibration results are inaccurate and deviate from the actual doping effect. Summary of the Invention

[0006] In order to overcome the disadvantages and deficiencies existing in the prior art, the purpose of the present invention is to provide a test structure for pixel doping diffusion, a test method, and a calibration method, so as to solve the problem of inaccurate doping diffusion test of pixels in the prior art.

[0007] The purpose of the present invention is achieved by the following technical solutions:

[0008] The present invention provides a test method for pixel doping diffusion, which is applicable to a CMOS image sensor. The test method includes:

[0009] Providing a test wafer;

[0010] Forming a test modulation structure on the front surface of the test wafer to modulate the doping of the test wafer;

[0011] Performing a doping process on the test wafer from the front surface of the test wafer, and forming a doped region in the test wafer;

[0012] Performing a doping diffusion test on the test wafer from the front surface of the test wafer to obtain the doping distribution of the doped region.

[0013] In one embodiment, the test modulation structure includes at least one of a trench isolation structure and a light blocking structure.

[0014] In one embodiment, the trench isolation structure extends into the test wafer to modulate the doping process based on the trench isolation structure located inside the test wafer; and / or, the light blocking structure is located on the test wafer to modulate the doping process based on the light blocking structure located on the test wafer.

[0015] In one embodiment, the arrangement between the trench isolation structure and the doped region and the arrangement between the light blocking structure and the doped region include at least one of the following methods: the projection of the trench isolation structure and the doped region on the surface of the test wafer at least partially overlap; and, the projection of the doped region on the surface of the test wafer covers the projection of the opening between adjacent trench isolation structures on the surface of the test wafer; and, the projection of the light blocking structure and the doped region on the surface of the test wafer are staggered from each other.

[0016] In one embodiment, the projection of the trench isolation structure and the doped region on the surface of the test wafer partially overlap, the projection of the doped region on the surface of the test wafer covers the projection of the opening between adjacent trench isolation structures on the surface of the test wafer, and the projection of the light blocking structure on the surface of the test wafer is located outside the doped region.

[0017] In one embodiment, the trench isolation structure adopts a shallow trench isolation structure; and / or, the light blocking structure adopts a photoresist.

[0018] In one embodiment, the trench isolation structure includes at least one of a first trench isolation structure that is completely staggered from the light blocking structure, a second trench isolation structure that partially overlaps with the light blocking structure, and a third trench isolation structure that completely overlaps with the light blocking structure.

[0019] In one embodiment, the light blocking structure includes at least one of a first light blocking structure that is completely staggered from the trench isolation structure, a second light blocking structure that partially overlaps with the trench isolation structure, and a third light blocking structure that completely overlaps with the trench isolation structure.

[0020] In one embodiment, the image sensor includes a plurality of pixel units arranged in an array and having a size less than 3μm×3μm.

[0021] In one embodiment, the test structure prepared from the test wafer includes a plurality of test units corresponding to the pixel units of the image sensor.

[0022] In one embodiment, the arrangement mode of the test modulation structure includes that the proportion of the test modulation structure in the test unit increases as the size of the test unit decreases.

[0023] In one embodiment, the doping region includes at least one of an N-type doping layer and a P-type doping layer, and the doping distribution includes at least one of an N-type doping distribution corresponding to the doping region and a P-type doping distribution.

[0024] In one embodiment, the doping region includes one N-type doping layer and two P-type doping layers, and one N-type doping layer is located between the two P-type doping layers.

[0025] In one embodiment, the doping region includes one N-type doping layer and one P-type doping layer, and the N-type doping layer is located below the P-type doping layer.

[0026] In one embodiment, the doping region includes a first doping layer doped with a first relative atomic mass and a second doping layer doped with a second relative atomic mass less than the first relative atomic mass, and the second doping layer is located above the first doping layer.

[0027] This application also provides a calibration method for pixel doping diffusion, and the calibration method includes:

[0028] Calibrate the doping distribution of the doped region obtained by the test method of pixel doping diffusion as described above.

[0029] In one embodiment, calibrating using the doping distribution of the doped region includes: obtaining a test surface corresponding to the test wafer based on the test modulation structure, so as to perform lateral calibration based on the doping distribution of the test surface.

[0030] This application also provides a test structure for pixel doping diffusion, suitable for the test method of pixel doping diffusion as described above. The test structure includes:

[0031] A test wafer, in which a doped region is provided;

[0032] A test modulation structure is provided on the front surface of the test wafer to modulate the doping of the test wafer.

[0033] In one embodiment, the test modulation structure includes at least one of a trench isolation structure and a light blocking structure;

[0034] The trench isolation structure extends into the test wafer to modulate the doping process based on the trench isolation structure located inside the test wafer;

[0035] The light blocking structure is at least located on the test wafer to modulate the doping process based on the light blocking structure located on the test wafer.

[0036] In one embodiment, the arrangement between the trench isolation structure and the doped region and between the light blocking structure and the doped region includes at least one of the following: the projection of the trench isolation structure and the doped region on the surface of the test wafer at least partially overlap; and, the projection of the doped region on the surface of the test wafer covers the projection of the opening between adjacent trench isolation structures on the surface of the test wafer; and, the projection of the light blocking structure and the doped region on the surface of the test wafer are staggered from each other.

[0037] In one embodiment, the projection of the trench isolation structure and the doped region on the surface of the test wafer partially overlap, the projection of the doped region on the surface of the test wafer covers the projection of the opening between adjacent trench isolation structures on the surface of the test wafer, and the projection of the light blocking structure on the surface of the test wafer is located outside the doped region.

[0038] In one embodiment, the trench isolation structure includes at least one of a first trench isolation structure that is completely staggered from the light blocking structure, a second trench isolation structure that partially overlaps with the light blocking structure, and a third trench isolation structure that completely overlaps with the light blocking structure;

[0039] The light-blocking structure includes at least one of a first light-blocking structure that is completely staggered from the trench isolation structure, a second light-blocking structure that partially overlaps the trench isolation structure, and a third light-blocking structure that completely overlaps the trench isolation structure.

[0040] In one embodiment, the doped region includes at least one of an N-type doped layer and a P-type doped layer.

[0041] In one embodiment, the doped region includes one N-type doped layer and two P-type doped layers, and one N-type doped layer is located between the two P-type doped layers.

[0042] The beneficial effect of the present invention is that by providing a test modulation structure on the front surface of the test wafer to modulate the doping of the test wafer, and then performing a doping diffusion test on the test wafer provided with the test modulation structure, the influence of the test modulation structure on the doping distribution in the doped region of the test wafer can be tested, making the test result closer to the actual doping effect, so as to better calibrate the doping. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic structural diagram of a test wafer in Embodiment 1 of the present invention;

[0044] Figures 2a - 2c is a schematic flow structural diagram of the test method in Embodiment 1 of the present invention;

[0045] Figure 3 is the doping distribution obtained by the test method in Embodiment 1 of the present invention;

[0046] Figure 4 is a schematic structural diagram of a test wafer in Embodiment 2 of the present invention;

[0047] Figures 5a - 5c is a schematic flow structural diagram of the test method in Embodiment 2 of the present invention;

[0048] Figure 6 is the doping distribution obtained by the test method in Embodiment 2 of the present invention;

[0049] Figure 7 is one of the schematic structural diagrams of a test wafer in Embodiment 3 of the present invention;

[0050] Figure 8 is another schematic structural diagram of a test wafer in Embodiment 3 of the present invention;

[0051] Figure 9 is yet another schematic structural diagram of a test wafer in Embodiment 3 of the present invention;

[0052] Figure 10 It is the fourth structural schematic diagram of the test wafer in the third embodiment of the present invention;

[0053] Figure 11 It is the fifth structural schematic diagram of the test wafer in the third embodiment of the present invention;

[0054] Figure 12 It is the sixth structural schematic diagram of the test wafer in the third embodiment of the present invention;

[0055] Figure 13 It is the seventh structural schematic diagram of the test wafer in the third embodiment of the present invention;

[0056] Figures 14a - 14d It corresponds to the third embodiment of the present invention Figure 10 The flow structural schematic diagram of the test method for the test wafer in;

[0057] Figure 15 It is the structural schematic diagram of the test wafer in the fourth embodiment of the present invention;

[0058] Figures 16a - 16d It is the flow structural schematic diagram of the test method in the fourth embodiment of the present invention;

[0059] Figure 17 It is the structural schematic diagram of the test wafer in the fifth embodiment of the present invention;

[0060] Figures 18a - 18d It is the flow structural schematic diagram of the test method in the fifth embodiment of the present invention.

[0061] Figure 19 It is the structural schematic diagram of another test wafer in the fifth embodiment of the present invention. Detailed implementation manners

[0062] To further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following combines the drawings and preferred embodiments to detail the specific implementation manners, structures, features, and effects of the test structure, test method, and calibration method for pixel doping diffusion proposed according to the present invention as follows:

[0063] [Embodiment 1]

[0064] Figure 1 It is the structural schematic diagram of the test structure in the first embodiment of the present invention. As Figure 1As shown in the figure, a test structure for pixel doping diffusion provided by Embodiment 1 of the present invention includes: a test wafer 10, in which a doping region 11 is provided. A test modulation structure is provided on the front surface of the test wafer 10 to modulate the doping of the test wafer 10. Since in the actual fabrication of a CMOS image sensor, the structure on the wafer has an impact on the doping concentration, by using a test modulation structure in the test stage to simulate this structure in reality, the doping effect in the wafer test stage is made closer to the actual doping effect, reducing the deviation between the test stage and the actual doping effect, so as to better calibrate the doping in reality.

[0065] The test modulation structure includes at least one of a trench isolation structure 12 and a light blocking structure 13, so that the doping effect in the wafer test stage is closer to the actual doping effect. In this embodiment, the test modulation structure is the trench isolation structure 12, so that the influence of the trench isolation structure 12 on the doping effect can be tested. It should be noted that other conditions of the test structure can adopt the existing design in the doping simulation during the preparation of a CMOS image sensor using the SIMS-based test method. For example, the implantation energy, implantation dose, etc. when the doping region is formed can correspond to the actual device.

[0066] Further, the trench isolation structure 12 extends into the test wafer 10 to modulate the doping process based on the trench isolation structure 12 located inside the test wafer 10. That is, in the subsequent step of forming the doping region 11, the doping process is carried out in the presence of the trench isolation structure 12, which can modulate the distribution of doping ions during the ion implantation process of forming the doping region 11, and can improve the test accuracy in the subsequent test process. In this embodiment, the trench isolation structure 12 adopts a shallow trench isolation structure.

[0067] In one example, the projection of the doping region 11 on the surface of the test wafer 10 covers the opening between adjacent trench isolation structures 12 projected on the surface of the test wafer 10; in a further example, there is a partial overlap between the projection of the trench isolation structure 12 and the doping region 11 on the surface of the test wafer 10; in yet another further example, there is a complete overlap between the projection of the trench isolation structure 12 and the doping region 11 on the surface of the test wafer 10.

[0068] The doping region 11 includes at least one of an N-type doping layer 11n and a P-type doping layer 11p, and the doping distribution includes at least one of an N-type doping distribution corresponding to the doping region 11 and a P-type doping distribution. In this embodiment, the doping region 11 is a P-type doping layer 11p. Of course, in other embodiments, the doping region 11 can also be an N-type doping layer 11n, or the doping region 11 can be a composite doping structure of an N-type doping layer 11n and a P-type doping layer 11p.

[0069] In one example, the doped region 11 includes an N-type doped layer and a P-type doped layer, and the N-type doped layer is located below the P-type doped layer. In one example, the doped region 11 includes a first doped layer doped with a first relative atomic mass and a second doped layer doped with a second relative atomic mass less than the first relative atomic mass, and the second doped layer is located above the first doped layer. For example, in some embodiments, an N-doped layer may be formed first. For example, it is achieved by As doping. Since the As molecule has a large molecular weight, there is a greater possibility of amorphization of the silicon surface, which may affect subsequent doping. Then a P-doped layer is formed. For example, it is achieved by B doping. As may cause an influence on the doping distribution of B, resulting in calibration deviation. The above design of this example can effectively improve the test accuracy of the above stacked structure device.

[0070] The CMOS image sensor includes a light sensing element (e.g., a photodiode) and a pixel support circuit. The photodiode can be a buried photodiode applied in current image sensors. In one application example, the pixel support circuit includes a reset transistor (RST), a source follower transistor (SF), a pixel selection transistor (RS), and a transfer transistor (TX) connected to the photodiode. During operation, the photo-charge generated by the light sensing element responds to the incident light during the exposure process. The transfer transistor is connected to a transfer signal that controls the transfer transistor to transfer the charge accumulated in the photodiode to the floating diffusion region (FD). The reset transistor is connected between VDD and the floating diffusion region and responds to the reset signal to reset the sensor pixel circuit (e.g., discharge or charge the floating diffusion region and the photodiode to the current voltage). The gate of the source follower transistor is connected to the floating diffusion region. The source follower transistor is connected between VDD and the pixel selection transistor to respond to the potential of the floating diffusion region. The pixel selection transistor outputs the pixel circuit from the source follower transistor to the bit line in response to the pixel selection control signal. In the above pixel circuit, the photodiode and the floating diffusion region are reset by a temporarily effective reset signal and a transfer control signal. When the transfer control signal is removed, the accumulated window (e.g., the exposure stage) starts to operate, and the incident light causes charges to be generated in the photodiode. The photo-generated electrons in the photodiode gradually accumulate, and the charge of the photodiode represents the light intensity incident on the photodiode during the exposure.

[0071] In one example, a CMOS image sensor includes a plurality of pixel units arranged in an array and having a size smaller than 3 μm × 3 μm. The fact that the CMOS image sensor includes a plurality of pixel units arranged in an array and having a size smaller than 3 μm × 3 μm means that the pixel units, as the smallest repeating units in the pixel array, are arranged in rows and columns, the maximum size of the pixel units in the row direction is smaller than 3 μm, and the maximum size of the pixel units in the column direction is smaller than 3 μm. For example, the pixel units are square, and the square size is 2 μm × 2 μm. For the CMOS image sensor of this example, by using the test structure of the present invention, a more accurate effect can be obtained.

[0072] In one example, the arrangement mode of the test modulation structure includes that the proportion of the test modulation structure in the test unit increases as the size of the test unit decreases. Wherein, the test unit is several test units included in the test structure prepared from a test wafer. In some embodiments, the test unit corresponds to the pixel unit included in the pixel array of the image sensor. For example, an actual image sensor includes a pixel array composed of M rows and N columns of pixel units, and the test structure prepared from the test wafer includes an array composed of M rows and N columns of test units, and each test unit includes a test modulation structure. Of course, in other embodiments, it may also be a proportional change with respect to the pixel array. In addition, the size of the test unit may be the same as the size of the pixel unit. For example, the two have equal size areas or are proportionally enlarged or reduced. In this example, the proportion of the test modulation structure in the test unit increases as the size of the test unit decreases, which can be achieved by the fact that when the size of the test unit decreases, the degree of decrease in the size of the test modulation structure is smaller than the degree of decrease in the size of the test unit, and the size can be the corresponding projected area. For example, when the projected area of the test unit decreases from S1 to S2, the projected area of the test modulation structure decreases from S3 to S4, and S4 / S2 is greater than S3 / S1. This is beneficial to improving the test accuracy of small-sized devices based on the test modulation structure.

[0073] Figures 2a - 2c It is a schematic flowchart of the test method in Embodiment 1 of the present invention. As Figures 2a - 2c shown, Embodiment 1 further provides a test method for pixel doping diffusion, which is applicable to a CMOS image sensor. The test method includes:

[0074] As Figure 2aAs shown, a test wafer 10 is provided. The test wafer 10 is made of semiconductor, such as silicon (Si). In one example, a silicon wafer is used, and it can also be other wafers for SMIS testing. In this embodiment, a silicon wafer with P-type doping is used as the test wafer 10. Optionally, the P-type doping concentration of the test wafer 10 can be the same as that of the P-type epitaxial layer of an actual CMOS image sensor. Among them, the P-type doping can be obtained by performing P-type ion doping on a single-crystalline silicon wafer.

[0075] A test modulation structure is formed on the front surface of the test wafer 10 to modulate the doping of the test wafer 10. In this embodiment, the test modulation structure adopts a trench isolation structure 12. The trench isolation structure 12 extends into the test wafer 10 to modulate the doping process based on the trench isolation structure 12 located inside the test wafer 10. The trench isolation structure 12 adopts a shallow trench isolation structure STI. Specifically, a photoresist layer is covered on the front surface of the test wafer 10, and the photoresist layer is exposed and developed using a mask plate, so that the photoresist layer forms a patterned structure; the patterned photoresist layer is used as a mask to etch the test wafer 10, so that trenches are formed on the front surface of the test wafer 10; a trench isolation structure 12 is filled in the trenches.

[0076] As Figure 2b shown, doping treatment is performed on the test wafer 10 from the front surface of the test wafer 10 by IMP (ion implantation) to form a doping region 11 in the test wafer 10. In this embodiment, the projection of the doping region 11 on the surface of the test wafer 10 covers the projection of the opening between adjacent trench isolation structures 12 on the surface of the test wafer 10. At the same time, there is at least one trench isolation structure 12 that completely overlaps with the projection of the doping region 11 on the surface of the test wafer 10. Two are designed in this embodiment. Among them, the doping region 11 is a P-type doping layer 11p.

[0077] As Figure 2c shown, doping diffusion testing is performed on the test wafer 10 from the front surface of the test wafer 10 by SIMS (secondary ion mass spectrometry) to obtain the doping distribution of the doping region 11. Thus, in the case of the test wafer 10 with a trench isolation structure 12, a more accurate doping distribution of the doping region 11 suitable for a CMOS image sensor can be obtained, such as a more accurate P-type doping diffusion situation.

[0078] Figure 3 is the doping distribution obtained by the testing method in the first embodiment of the present invention. Figure 3 In the figure, the dashed curve is the doping distribution test curve A2 without the trench isolation structure 12, and the solid curve is the doping distribution test curve A1 with the trench isolation structure 12 in this embodiment. The abscissa is the depth (nm) of the test structure, and the ordinate is the concentration of P-type ions after doping. FromFigure 3 It can be seen that there are obvious differences in the longitudinal distribution of the trench isolation structure 12. For large pixels, the doping concentration of the trench isolation structure 12 is relatively light, the doping CD is large, and the influence caused by errors has little impact; but for small pixels, the influence is very obvious. Whether there is a trench isolation structure 12 will directly affect the accuracy of the doping distribution of P-type doping and thus the isolation performance, and whether there is a trench isolation structure 12 will directly affect the lateral diffusion of the PD (photodiode) and the PD morphology profile for the doping distribution of N-type doping.

[0079] [Embodiment 2]

[0080] Figure 4 It is a schematic structural diagram of the test structure in Embodiment 2 of the present invention. As Figure 4 shown, Embodiment 2 of the present invention provides a test structure for pixel doping diffusion, including: a test wafer 10, and a doping region 11 is provided in the test wafer 10. A test modulation structure is provided on the front surface of the test wafer 10 to modulate the doping of the test wafer 10. Since in the actual fabrication of a CMOS image sensor, the objects on the wafer have an impact on the doping concentration, by using a test modulation structure in the test stage to simulate the actual objects, the doping effect in the wafer test stage is made closer to the actual doping effect, reducing the deviation between the test stage and the actual doping effect, so as to better calibrate the doping in practice. The main differences between this embodiment and Embodiment 1 will be introduced in detail below, and similar designs will not be elaborated.

[0081] The test modulation structure includes at least one of a trench isolation structure 12 and a light blocking structure 13, so that the doping effect in the wafer test stage is closer to the actual doping effect. In this embodiment, the test modulation structure is a light blocking structure 13, so as to test the influence of the light blocking structure 13 on the doping effect.

[0082] Furthermore, the light blocking structure 13 is at least located on the test wafer 10 to modulate the doping process based on the light blocking structure 13 located on the test wafer 10. That is, in the subsequent step of forming the doping region 11, doping is performed in the presence of the light blocking structure 13, which can improve the test accuracy in the subsequent test process. In this embodiment, the projection of the light blocking structure 13 and the doping region 11 on the surface of the test wafer 10 are staggered from each other, and the light blocking structure 13 uses photoresist.

[0083] The doped region 11 includes at least one of an N-type doped layer 11n and a P-type doped layer 11p, and the doping distribution includes at least one of an N-type doping distribution corresponding to the doped region 11 and a P-type doping distribution. In this embodiment, the doped region 11 is the P-type doped layer 11p. Of course, in other embodiments, the doped region 11 may also be the N-type doped layer 11n, or the doped region 11 may be a composite doping structure of the N-type doped layer 11n and the P-type doped layer 11p.

[0084] Figures 5a - 5c is a schematic flow structure diagram of the testing method in Embodiment 1 of the present invention. As Figures 5a - 5c shown, Embodiment 2 of the present invention also provides a testing method for pixel doping diffusion, which is applicable to a CMOS image sensor. The same parts as those in Embodiment 1 will not be described in detail. The testing method includes:

[0085] As Figure 5a shown, a test wafer 10 is provided. The test wafer 10 is made of a semiconductor, such as silicon (Si). In this embodiment, a silicon wafer with P-type doping is used as the test wafer 10.

[0086] A test modulation structure is formed on the front surface of the test wafer 10 to modulate the doping of the test wafer 10. In this embodiment, the test modulation structure uses a light blocking structure 13. The light blocking structure 13 is at least located on the test wafer 10 to modulate the doping process based on the light blocking structure 13 located on the test wafer 10. The light blocking structure 13 uses photoresist PR. Specifically, a photoresist layer is covered on the front surface of the test wafer 10, and the photoresist layer is subjected to exposure and development processing using a mask plate, so that the photoresist layer forms a patterned structure.

[0087] As Figure 5b shown, the test wafer 10 is doped by IMP (ion implantation) from the front surface of the test wafer 10 to form a doped region 11 in the test wafer 10. The projection of the light blocking structure 13 and the doped region 11 on the surface of the test wafer 10 are staggered from each other. Among them, the doped region 11 is the P-type doped layer 11p.

[0088] As Figure 5c shown, the test wafer 10 is subjected to SIMS (secondary ion mass spectrometry) doping diffusion testing from the front surface of the test wafer 10 to obtain the doping distribution of the doped region 11. Thus, in the case of the test wafer 10 with the light blocking structure 13, a more accurate doping distribution of the doped region 11 suitable for the CMOS image sensor can be obtained, such as a more accurate P-type doping diffusion situation.

[0089] Figure 6 is the doping distribution tested by the testing method in Embodiment 2 of the present invention. Figure 6The middle dashed curve is the doping distribution test curve B2 without the light blocking structure 13 being set, and the solid curve is the doping distribution test curve B1 with the light blocking structure 13 being set in this embodiment. The abscissa is the depth (nm) of the test structure, and the ordinate is the concentration of P-type ions after doping. From Figure 6 it can be seen that there is more doping on the surface of the test wafer 10 with the light blocking structure 13 being set. That is, there is more doping distribution in the region between the doping region 11 and the front of the test structure. This is also the influence caused by the smaller distance of the light blocking structure 13 in the small pixel.

[0090] [Embodiment Three]

[0091] Figure 7 is one of the schematic structural diagrams of the test wafer in Embodiment Three of the present invention. Figure 8 is another schematic structural diagram of the test wafer in Embodiment Three of the present invention. Figure 9 is the third schematic structural diagram of the test wafer in Embodiment Three of the present invention. Figure 10 is the fourth schematic structural diagram of the test wafer in Embodiment Three of the present invention. Figure 11 is the fifth schematic structural diagram of the test wafer in Embodiment Three of the present invention. Figure 12 is the sixth schematic structural diagram of the test wafer in Embodiment Three of the present invention. Figure 13 is the seventh schematic structural diagram of the test wafer in Embodiment Three of the present invention. The main differences between this embodiment and Embodiment One and Two will be introduced in detail below, and similar designs will not be elaborated.

[0092] As Figures 7 to 13 shown, a test structure for pixel doping diffusion provided in Embodiment Three of the present invention includes: a test wafer 10, and a doping region 11 is provided in the test wafer 10. A test modulation structure is provided on the front of the test wafer 10 to modulate the doping of the test wafer 10. Since in the actual fabrication of a CMOS image sensor, the structure on the wafer has an impact on the doping concentration, by adopting a test modulation structure in the test stage to simulate the structure in the actual CMOS image sensor, the doping effect in the wafer test stage is made closer to the actual doping effect, reducing the deviation between the test stage and the actual doping effect, so as to better calibrate the doping in practice.

[0093] The test modulation structure includes at least one of a trench isolation structure 12 and a light blocking structure 13, so that the doping effect during the wafer test stage is closer to the actual doping effect. In this embodiment, the test modulation structure includes a trench isolation structure 12 and a light blocking structure 13, so that a more accurate doping distribution can be obtained based on the influence of the trench isolation structure 12 and the light blocking structure 13 on the doping effect. The trench isolation structure 12 extends into the test wafer 10 to modulate the doping process based on the trench isolation structure 12 located inside the test wafer 10. The light blocking structure 13 is located on the test wafer 10 to modulate the doping process based on the light blocking structure 13 located on the test wafer 10. Further, in this embodiment, the trench isolation structure 12 adopts a shallow trench isolation structure, and the light blocking structure 13 adopts a photoresist.

[0094] Furthermore, the trench isolation structure 12 and the doping region 11 overlap at least partially on the surface of the test wafer 10. The projection of the light blocking structure 13 and the doping region 11 on the surface of the test wafer 10 are staggered from each other.

[0095] The trench isolation structure 12 includes at least one of a first trench isolation structure 12a that is completely staggered from the light blocking structure 13, a second trench isolation structure 12b that partially overlaps with the light blocking structure 13, and a third trench isolation structure 12c that completely overlaps with the light blocking structure 13.

[0096] The light blocking structure 13 includes at least one of a first light blocking structure 13a that is completely staggered from the trench isolation structure 12, a second light blocking structure 13b that partially overlaps with the trench isolation structure 12, and a third light blocking structure 13c that completely overlaps with the trench isolation structure 12.

[0097] In one embodiment, as Figure 7 shown, the trench isolation structure 12 and the doping region 11 completely overlap on the surface of the test wafer 10. The trench isolation structure 12 adopts the first trench isolation structure 12a that is completely staggered from the light blocking structure 13, and the light blocking structure 13 adopts the first light blocking structure 13a that is completely staggered from the trench isolation structure 12.

[0098] In one embodiment, as Figure 8 shown, the trench isolation structure 12 and the doping region 11 partially overlap on the surface of the test wafer 10. The trench isolation structure 12 adopts the second trench isolation structure 12b that partially overlaps with the light blocking structure 13, and the light blocking structure 13 adopts the second light blocking structure 13b that partially overlaps with the trench isolation structure 12.

[0099] In one embodiment, as Figure 9As shown, the trench isolation structure 12 adopts a third trench isolation structure 12c that completely overlaps with the light blocking structure 13. The light blocking structure 13 adopts a third light blocking structure 13c that completely overlaps with the trench isolation structure 12. The projection of the third trench isolation structure 12c on the surface of the test wafer 10 is staggered from the doped region 11.

[0100] In one embodiment, as Figure 10 shown, the trench isolation structure 12 partially overlaps with the doped region 11 on the surface of the test wafer 10. The trench isolation structure 12 adopts a second trench isolation structure 12b that partially overlaps with the light blocking structure 13. The light blocking structure 13 includes a first light blocking structure 13a that is completely staggered from the trench isolation structure 12 and a second light blocking structure 13b that partially overlaps with the trench isolation structure 12.

[0101] In one embodiment, as Figure 11 shown, the trench isolation structure 12 includes a first trench isolation structure 12a that is completely staggered from the light blocking structure 13 and a third trench isolation structure 12c that completely overlaps with the light blocking structure 13. The light blocking structure 13 includes a first light blocking structure 13a that is completely staggered from the trench isolation structure 12 and a third light blocking structure 13c that completely overlaps with the trench isolation structure 12. The projection of the doped region 11 on the surface of the test wafer 10 covers the projection of the opening between adjacent trench isolation structures 12 on the surface of the test wafer 10.

[0102] In one embodiment, as Figure 12 shown, the trench isolation structure 12 includes a first trench isolation structure 12a that is completely staggered from the light blocking structure 13 and a second trench isolation structure 12b that partially overlaps with the light blocking structure 13. The light blocking structure 13 includes a first light blocking structure 13a that is completely staggered from the trench isolation structure 12 and a second light blocking structure 13b that partially overlaps with the trench isolation structure 12. The projection of the doped region 11 on the surface of the test wafer 10 covers the projection of the opening between adjacent trench isolation structures 12 on the surface of the test wafer 10. In this example, the opening between adjacent trench isolation structures 12 refers to the opening formed between the first trench isolation structure 12a that is completely staggered from the light blocking structure 13 and the second trench isolation structure 12b that partially overlaps with the light blocking structure 13.

[0103] In one embodiment, as Figure 13As shown, the trench isolation structure 12 includes a first trench isolation structure 12a that is completely staggered from the light blocking structure 13, a second trench isolation structure 12b that partially overlaps with the light blocking structure 13, and a third trench isolation structure 12c that completely overlaps with the light blocking structure 13. The light blocking structure 13 includes a first light blocking structure 13a that is completely staggered from the trench isolation structure 12, a second light blocking structure 13b that partially overlaps with the trench isolation structure 12, and a third light blocking structure 13c that completely overlaps with the trench isolation structure 12. The projection of the doped region 11 on the surface of the test wafer 10 covers the projection of the opening between adjacent trench isolation structures 12 on the surface of the test wafer 10.

[0104] Among them, the specific patterns of the trench isolation structure 12 and the light blocking structure 13 can be set according to actual test needs. In the present invention, the existing test modulation structure can make the test structure closer to the actual structure of the CMOS image sensor, thereby improving the accuracy of the doping diffusion test.

[0105] The doped region 11 includes at least one of an N-type doped layer 11n and a P-type doped layer 11p, and the doping distribution includes at least one of an N-type doping distribution corresponding to the doped region 11 and a P-type doping distribution. In this embodiment, the doped region 11 is an N-type doped layer 11n.

[0106] Figures 14a - 14d It corresponds to Embodiment 3 of the present invention Figure 10 It is a schematic flow structure diagram of the test method of the test wafer in Figures 14a - 14c As shown, Embodiment 3 also provides a test method for pixel doping diffusion, which is applicable to a CMOS image sensor. The test method includes:

[0107] As Figure 14a shown, a test wafer 10 is provided. The test wafer 10 is made of a semiconductor, such as silicon (Si). In this embodiment, a silicon wafer with P-type doping is used as the test wafer 10.

[0108] A test modulation structure is formed on the front surface of the test wafer 10 to modulate the doping of the test wafer 10. In this embodiment, the test modulation structure includes a trench isolation structure 12 and a light blocking structure 13. The trench isolation structure 12 extends into the test wafer 10 to modulate the doping process based on the trench isolation structure 12 located inside the test wafer 10. The light blocking structure 13 is at least located on the test wafer 10 to modulate the doping process based on the light blocking structure 13 located on the test wafer 10.

[0109] The trench isolation structure 12 adopts a shallow trench isolation (STI) structure. Specifically, a first photoresist layer is covered on the front side of the test wafer 10, and the first photoresist layer is exposed and developed using a mask plate, so that the first photoresist layer forms a patterned structure; the test wafer 10 is etched using the patterned first photoresist layer as a mask, so that trenches are formed on the front side of the test wafer 10; a trench isolation structure 12 is filled in the trenches, and the filling material is selected as silicon oxide in this embodiment.

[0110] As Figure 14b shown, the light blocking structure 13 adopts a photoresist PR. Specifically, a second photoresist layer is covered on the front side of the test wafer 10, and the second photoresist layer is exposed and developed using a mask plate, so that the second photoresist layer forms a patterned structure to form the light blocking structure 13.

[0111] As Figure 14c shown, the test wafer 10 is doped by IMP (ion implantation) from the front side of the test wafer 10 to form a doped region 11 in the test wafer 10. Among them, in this embodiment, the doped region 11 is an N-type doped layer 11n. The trench isolation structure 12 and the doped region 11 partially overlap on the surface of the test wafer 10. The trench isolation structure 12 adopts a second trench isolation structure 12b that partially overlaps with the light blocking structure 13. The light blocking structure 13 includes a first light blocking structure 13a that is completely staggered from the trench isolation structure 12 and a second light blocking structure 13b that partially overlaps with the trench isolation structure 12.

[0112] As Figure 14d shown, the test wafer 10 is subjected to a doping diffusion test by SIMS (secondary ion mass spectrometry) from the front side of the test wafer 10 to obtain the doping distribution of the doped region 11. Thus, in the case of the test wafer 10 having both the trench isolation structure 12 and the light blocking structure 13, a more accurate doping distribution of the doped region 11 suitable for a CMOS image sensor can be obtained, such as a more accurate N-type doping diffusion situation.

[0113] [Embodiment 4]

[0114] Figure 15 is a schematic structural diagram of the test wafer of Embodiment 4 of the present invention. As Figure 15 shown, the test structure and test method for pixel doping diffusion provided in Embodiment 4 of the present invention are the same as those in Embodiment 3 ( Figures 7 to 13) The test structures and test methods for pixel doping diffusion are basically the same. The difference is that in this embodiment: the doping region 11 is a P-type doping layer 11p, so that in the case of a test wafer 10 having both a trench isolation structure 12 and a light blocking structure 13, a more accurate doping distribution of the doping region 11 suitable for a CMOS image sensor can be obtained, such as a more accurate P-type doping diffusion situation.

[0115] Figures 16a - 16d This corresponds to Embodiment 4 of the present invention Figure 10 in the flow structure schematic diagram of the test method of the test wafer. As Figures 16a - 16d shown, Embodiment 4 also provides a test method for pixel doping diffusion, which is applicable to a CMOS image sensor. The test method includes:

[0116] As Figure 16a shown, a test wafer 10 is provided. The test wafer 10 is made of a semiconductor, such as silicon (Si). In this embodiment, a silicon wafer with P-type doping is used as the test wafer 10.

[0117] A test modulation structure is formed on the front surface of the test wafer 10 to modulate the doping of the test wafer 10. In this embodiment, the test modulation structure includes a trench isolation structure 12 and a light blocking structure 13. The trench isolation structure 12 extends into the test wafer 10 to modulate the doping process based on the trench isolation structure 12 located inside the test wafer 10. The light blocking structure 13 is at least located on the test wafer 10 to modulate the doping process based on the light blocking structure 13 located on the test wafer 10.

[0118] The trench isolation structure 12 adopts a shallow trench isolation structure STI. Specifically, a first photoresist layer is covered on the front surface of the test wafer 10, and the first photoresist layer is exposed and developed using a mask plate, so that the first photoresist layer forms a patterned structure; the test wafer 10 is etched using the patterned first photoresist layer as a mask, so that trenches are formed on the front surface of the test wafer 10; a trench isolation structure 12 is filled in the trenches, and the filling material is selected as silicon oxide in this embodiment.

[0119] As Figure 16b shown, the light blocking structure 13 adopts a photoresist PR. Specifically, a second photoresist layer is covered on the front surface of the test wafer 10, and the second photoresist layer is exposed and developed using a mask plate, so that the second photoresist layer forms a patterned structure to form the light blocking structure 13.

[0120] As Figure 16cAs shown in the figure, doping treatment is performed on the test wafer 10 by IMP (ion implantation) from the front side of the test wafer 10 to form a doped region 11 within the test wafer 10. Among them, in this embodiment, the doped region 11 is a P-type doped layer 11p. The trench isolation structure 12 partially overlaps with the portion of the doped region 11 on the surface of the test wafer 10. The trench isolation structure 12 adopts a second trench isolation structure 12b that partially overlaps with the light blocking structure 13. The light blocking structure 13 includes a first light blocking structure 13a that is completely staggered from the trench isolation structure 12 and a second light blocking structure 13b that partially overlaps with the trench isolation structure 12.

[0121] As Figure 16d shown, doping diffusion testing is performed on the test wafer 10 by SIMS (secondary ion mass spectrometry) from the front side of the test wafer 10 to obtain the doping distribution of the doped region 11. Thus, in the case of the test wafer 10 having both the trench isolation structure 12 and the light blocking structure 13, a more accurate doping distribution of the doped region 11 suitable for a CMOS image sensor can be obtained, such as a more accurate P-type doping diffusion situation.

[0122] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment III and will not be elaborated here.

[0123] [Embodiment V]

[0124] Figure 17 is a schematic structural diagram of the test wafer according to Embodiment V of the present invention. As Figure 17 shown, the test wafer provided in Embodiment V of the present invention is basically the same as the test wafer in Embodiment III ( Figures 7 to 14d ), with the difference that, in this embodiment: the doped region 11 includes one layer of N-type doped layer 11n and two layers of P-type doped layers 11p, and one layer of N-type doped layer 11n is located between the two layers of P-type doped layers 11p, so as to test the influence of the trench isolation structure 12 and the light blocking structure 13 on the combined doping diffusion of P-type doping and N-type doping of the test wafer 10. Of course, in other embodiments, it may also be that the doped region 11 includes one layer of N-type doped layer 11n and one layer of P-type doped layer 11p, and the N-type doped layer 11n is located below the P-type doped layer 11p. As Figure 19 shown, the main differences between this embodiment and the foregoing embodiments will be introduced in detail below, and similar designs will not be elaborated.

[0125] Figures 18a - 18d is a schematic flow structure diagram of the test method in Embodiment V of the present invention. As Figures 18a - 18d shown, Embodiment V also provides a method for testing pixel doping diffusion, which is applicable to a CMOS image sensor. The test method includes:

[0126] AsFigure 18a As shown, a test wafer 10 is provided. The test wafer 10 is made of semiconductor, such as silicon (Si). In this embodiment, a silicon wafer with P-type doping is used as the test wafer 10.

[0127] A test modulation structure is formed on the front surface of the test wafer 10 to modulate the doping of the test wafer 10. In this embodiment, the test modulation structure includes a trench isolation structure 12 and a light blocking structure 13. The trench isolation structure 12 extends into the test wafer 10 to modulate the doping process based on the trench isolation structure 12 located inside the test wafer 10. The light blocking structure 13 is at least located on the test wafer 10 to modulate the doping process based on the light blocking structure 13 located on the test wafer 10.

[0128] The trench isolation structure 12 adopts a shallow trench isolation structure STI. Specifically, a first photoresist layer is covered on the front surface of the test wafer 10, and the first photoresist layer is exposed and developed using a mask plate, so that the first photoresist layer forms a patterned structure; the test wafer 10 is etched using the patterned first photoresist layer as a mask, so that trenches are formed on the front surface of the test wafer 10; a trench isolation structure 12 is filled in the trenches, and the filling material is selected as silicon oxide in this embodiment.

[0129] As Figure 18b shown, the light blocking structure 13 adopts a photoresist PR. Specifically, a second photoresist layer is covered on the front surface of the test wafer 10, and the second photoresist layer is exposed and developed using a mask plate, so that the second photoresist layer forms a patterned structure to form the light blocking structure 13.

[0130] As Figure 18c shown, the test wafer 10 is doped by IMP (ion implantation) from the front surface of the test wafer 10, and a doped region 11 is formed in the test wafer 10. Among them, in this embodiment, the doped region 11 includes a layer of N-type doped layer 11n and two layers of P-type doped layers 11p, and a layer of N-type doped layer 11n is located between the two layers of P-type doped layers 11p. The trench isolation structure 12 partially overlaps with the portion of the doped region 11 on the surface of the test wafer 10. The trench isolation structure 12 adopts a second trench isolation structure 12b that partially overlaps with the light blocking structure 13. The light blocking structure 13 includes a first light blocking structure 13a that is completely staggered from the trench isolation structure 12 and a second light blocking structure 13b that partially overlaps with the trench isolation structure 12.

[0131] As Figure 18dAs shown in the figure, SIMS (Secondary Ion Mass Spectrometry) is used to perform doping diffusion testing on the test wafer 10 from the front side of the test wafer 10 to obtain the doping distribution of the doped region 11, so as to test the influence of the trench isolation structure 12 and the light blocking structure 13 on the combined doping diffusion of P-type doping and N-type doping in the test wafer 10.

[0132] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 3 and will not be elaborated here.

[0133] [Embodiment Six]

[0134] This application also provides a calibration method for pixel doping diffusion. The calibration method includes: calibrating based on the doping distribution of the doped region 11 obtained by using the above-mentioned test method for pixel doping diffusion. Since the doping distribution of the doped region 11 obtained by the test method is closer to the actual doping effect, the deviation between the test stage and the actual doping effect is reduced, so as to better calibrate the doping in practice and can be applied to the lateral and longitudinal calibration of image sensor doping.

[0135] In one implementation, calibrating based on the doping distribution of the doped region includes: obtaining the test surface corresponding to the test wafer based on the test modulation structure to perform lateral calibration based on the doping distribution of the test surface. The design of the test modulation structure can affect the doping distribution of the test surface (for example, the horizontal plane of the test structure corresponding to a certain depth position). For example, when the test modulation structure is a shallow trench isolation structure, its structure in the test wafer may affect the reflection of doping ions and the injection distribution in depth due to different materials from the test wafer. When the test modulation structure is a photoresist, it can block the injected ions and affect the ion distribution on the test surface. Of course, it can also affect ion implantation based on the reflection or refraction of the part located on the surface of the test wafer. In this embodiment, based on the influence of the test modulation structure, it is beneficial to improve the accuracy of lateral diffusion and is beneficial to the calibration of small-size devices.

[0136] In this article, the orientation terms such as up, down, left, right, front, and back are defined based on the positions of the structures in the drawings and the positions relative to each other, only for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of the orientation terms should not limit the scope of protection requested by this application. It should also be understood that the terms "first" and "second" used in this article are only for distinction in name and do not limit the quantity and order.

[0137] The above are only the preferred embodiments of the present invention, and do not impose any formal limitations on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications using the above-disclosed technical content within the scope of the technical solution of the present invention, which are equivalent embodiments of equivalent changes. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A test method for pixel doping diffusion, applicable to a CMOS image sensor, characterized in that, the test method includes: providing a test wafer; forming a test modulation structure on the front surface of the test wafer to modulate the doping of the test wafer; performing a doping process on the test wafer from the front surface of the test wafer, and forming a doping region in the test wafer; performing a doping diffusion test on the test wafer from the front surface of the test wafer to obtain the doping distribution of the doping region.

2. The test method for pixel doping diffusion according to claim 1, characterized in that, the test modulation structure includes at least one of a trench isolation structure and a light blocking structure.

3. The test method for pixel doping diffusion according to claim 2, characterized in that, the trench isolation structure extends into the test wafer to modulate the doping process based on the trench isolation structure located inside the test wafer; and / or, the light blocking structure is located on the test wafer to modulate the doping process based on the light blocking structure located on the test wafer.

4. The test method for pixel doping diffusion according to claim 3, characterized in that, the arrangement between the trench isolation structure and the doping region and between the light blocking structure and the doping region includes at least one of the following methods: the projection of the trench isolation structure and the doping region on the surface of the test wafer at least partially overlap; and, the projection of the doping region on the surface of the test wafer covers the projection of the opening between adjacent trench isolation structures on the surface of the test wafer; and, the projection of the light blocking structure and the doping region on the surface of the test wafer are staggered from each other.

5. The test method for pixel doping diffusion according to claim 4, characterized in that, the projection of the trench isolation structure and the doping region on the surface of the test wafer partially overlap, the projection of the doping region on the surface of the test wafer covers the projection of the opening between adjacent trench isolation structures on the surface of the test wafer, and the projection of the light blocking structure on the surface of the test wafer is located outside the doping region.

6. The test method for pixel doping diffusion according to claim 2, characterized in that, the trench isolation structure includes at least one of a first trench isolation structure completely staggered from the light blocking structure, a second trench isolation structure partially overlapping with the light blocking structure, and a third trench isolation structure completely overlapping with the light blocking structure; and / or, the light blocking structure includes at least one of a first light blocking structure completely staggered from the trench isolation structure, a second light blocking structure partially overlapping with the trench isolation structure, and a third light blocking structure completely overlapping with the trench isolation structure and / or, the trench isolation structure adopts a shallow trench isolation structure, and the light blocking structure adopts a photoresist.

7. The test method for pixel doping diffusion according to claim 1, characterized in that, The image sensor includes a plurality of pixel units arranged in an array with a size less than 3μm×3μm; and / or, the test structure prepared from the test wafer includes a plurality of test units corresponding to the pixel units of the image sensor; and / or, the arrangement mode of the test modulation structure includes that the proportion of the test modulation structure in the test unit increases as the size of the test unit decreases.

8. The method for testing pixel doping diffusion according to any one of claims 1-7, wherein, the doped region includes at least one of an N-type doped layer and a P-type doped layer, and the doping distribution includes at least one of an N-type doping distribution corresponding to the doped region and a P-type doping distribution.

9. The method for testing pixel doping diffusion according to claim 8, wherein, the doped region includes one N-type doped layer and two P-type doped layers, and one N-type doped layer is located between the two P-type doped layers; and / or, the doped region includes one N-type doped layer and one P-type doped layer, and the N-type doped layer is located below the P-type doped layer; and / or, the doped region includes a first doped layer doped with a first relative atomic mass and a second doped layer doped with a second relative atomic mass less than the first relative atomic mass, and the second doped layer is located above the first doped layer.

10. A calibration method for pixel doping diffusion, wherein, the calibration method includes: calibrating according to the doping distribution of the doped region obtained by using the method for testing pixel doping diffusion according to any one of claims 1-9.

11. The calibration method for pixel doping diffusion according to claim 10, wherein, calibrating according to the doping distribution of the doped region includes: obtaining the test surface corresponding to the test wafer based on the test modulation structure to perform lateral calibration based on the doping distribution of the test surface.

12. A test structure for pixel doping diffusion, wherein, the test structure includes: a test wafer, and a doped region is provided in the test wafer; a test modulation structure is provided on the front surface of the test wafer to modulate the doping of the test wafer.

13. The test structure for pixel doping diffusion according to claim 12, wherein, the test modulation structure includes at least one of a trench isolation structure and a light blocking structure; the trench isolation structure extends into the test wafer to modulate the doping process based on the trench isolation structure located inside the test wafer; the light blocking structure is at least located on the test wafer to modulate the doping process based on the light blocking structure located on the test wafer.

14. The test structure for pixel doping diffusion according to claim 13, wherein, the arrangement mode between the trench isolation structure and the doped region and between the light blocking structure and the doped region includes at least one of the following modes: The trench isolation structure and the projection of the doped region on the surface of the test wafer overlap at least partially; and, the projection of the doped region on the surface of the test wafer covers the projection of the opening between adjacent trench isolation structures on the surface of the test wafer; and, the light blocking structure and the projection of the doped region on the surface of the test wafer are staggered from each other.

15. The test structure for pixel doping diffusion according to claim 14, wherein, the trench isolation structure and the projection of the doped region on the surface of the test wafer overlap partially, the projection of the doped region on the surface of the test wafer covers the projection of the opening between adjacent trench isolation structures on the surface of the test wafer, and the projection of the light blocking structure on the surface of the test wafer is located outside the doped region.

16. The test structure for pixel doping diffusion according to any one of claims 12 - 15, wherein, the doped region includes at least one of an N-type doped layer and a P-type doped layer.

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