Three-phase inverter and related equipment

Abstract

The invention provides a three-phase inverter and related equipment, and the three-phase inverter comprises a first-phase bridge arm, a second-phase bridge arm, a third-phase bridge arm and a drive circuit, the first-phase bridge arm, the second-phase bridge arm and the third-phase bridge arm are connected in parallel and then are connected with the input end of the three-phase inverter, and the drive circuit is connected with the input end of the three-phase inverter. The midpoint of the first-phase bridge arm, the midpoint of the second-phase bridge arm and the midpoint of the third-phase bridge arm are connected with the three-phase output end of the three-phase inverter. Under the condition that an upper bridge arm switch and a lower bridge arm switch in each phase of bridge arm are both hybrid devices, a driving circuit (namely an analog circuit) is used for outputting a driving signal corresponding to each phase of bridge arm according to voltage signals at the two ends of the first phase of bridge arm, and the driving signal is output without depending on an external digital driver. Therefore, the cost and the size of the driving circuit are greatly reduced, and the applicability is high.

Description

Technical Field

[0001] This application relates to the technical field of new energy vehicles, and particularly to a three-phase inverter and related equipment. Background Art

[0002] Existing silicon (Si) insulated gate bipolar transistors (IGBTs) have advantages such as large current-carrying capacity and low chip cost. Therefore, Si IGBTs are often used in medium- and high-power application fields. However, there is a tail current during the turn-off process of Si IGBTs, resulting in excessive switching losses of Si IGBTs. Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have advantages such as lower on-state voltage drop and faster switching speed. Therefore, when Si IGBTs are used in medium- and high-power application fields, a SiC MOSFET is usually connected in parallel at both ends of the Si IGBT to form a Si / SiC hybrid device (hybrid switch), so that the Si / SiC hybrid device simultaneously has the advantages of low on-state voltage drop, high current-carrying capacity, and low switching losses, thereby improving the comprehensive performance of the system.

[0003] Currently, when a Si / SiC hybrid device is applied to an inverter, due to the different working timings of the SiC MOSFET and the Si IGBT, the inverter outputs independent pulse width modulation (PWM) drive signals to the SiC MOSFET and the Si IGBT respectively for different circuit conditions (such as light load, heavy load, open circuit, and short circuit conditions), so that the inverter can supply power to the load normally. Among them, the drive circuit in the inverter needs to rely on an external digital signal processor (DSP) to output independent PWM drive signals, resulting in a larger volume and higher cost of the overall drive circuit. Summary of the Invention

[0004] This application provides a three-phase inverter and related equipment, which can greatly reduce the cost and volume of the drive circuit.

[0005] In a first aspect, an embodiment of the present application provides a three-phase inverter. The input end of the three-phase inverter is used to connect to a DC source, and the three-phase output ends of the three-phase inverter are used to connect to an AC load. The three-phase inverter includes a first-phase bridge arm, a second-phase bridge arm, a third-phase bridge arm, and a driving circuit. The first-phase bridge arm, the second-phase bridge arm, and the third-phase bridge arm form a three-phase inverter circuit. Among them, the first-phase bridge arm, the second-phase bridge arm, and the third-phase bridge arm are connected in parallel and then connected to the input end of the three-phase inverter. The midpoints of the first-phase bridge arm, the second-phase bridge arm, and the third-phase bridge arm are connected to the three-phase output ends of the three-phase inverter. Each phase bridge arm of the first-phase bridge arm, the second-phase bridge arm, and the third-phase bridge arm includes a series-connected upper-bridge-arm switch and a lower-bridge-arm switch. The driving circuit includes a driving signal output circuit, a first phase delay circuit, and a second phase delay circuit. Among them, the first input end and the second input end of the driving signal output circuit are both used to receive the voltage signal across the first-phase bridge arm. The first output end of the driving signal output circuit is connected to the upper-bridge-arm switch in the first-phase bridge arm, and the second output end of the driving signal output circuit is connected to the lower-bridge-arm switch in the first-phase bridge arm. The first output end of the driving signal output circuit is connected to the input end of the first phase delay circuit. The first output end of the first phase delay circuit is connected to the upper-bridge-arm switch in the second-phase bridge arm, and the second output end of the first phase delay circuit is connected to the lower-bridge-arm switch in the second-phase bridge arm. The first output end of the driving signal output circuit or the first output end of the first phase delay circuit is connected to the input end of the second phase delay circuit. The first output end of the second phase delay circuit is connected to the upper-bridge-arm switch in the third-phase bridge arm, and the second output end of the second phase delay circuit is connected to the lower-bridge-arm switch in the third-phase bridge arm. By implementing the embodiment of the present application, when the upper and lower bridge arm switches in each phase bridge arm are all hybrid devices, the driving circuit (i.e., the analog circuit) can also output the corresponding driving signal for each phase bridge arm according to the voltage signal across the first-phase bridge arm, without relying on an external digital driver to output the driving signal, thereby greatly reducing the cost and volume of the driving circuit and having strong applicability.

[0006] Combined with the first aspect, in a possible implementation manner, each of the upper-bridge-arm switch and the lower-bridge-arm switch is composed of a first switch and a second switch connected in parallel, that is, both the upper-bridge-arm switch and the lower-bridge-arm switch are hybrid devices. The above-mentioned drive signal output circuit includes analog circuits such as a first modulation wave output circuit, a second modulation wave output circuit, and a drive signal generation circuit. Among them, the input end of the first modulation wave output circuit serves as the first input end of the drive signal output circuit and is used to receive the voltage signal across the two ends of the first-phase bridge arm. The input end of the second modulation wave output circuit serves as the second input end of the drive signal output circuit and is used to receive the voltage signal across the two ends of the first-phase bridge arm. The output end of the first modulation wave output circuit is connected to the first input end of the drive signal generation circuit, the output end of the second modulation wave output circuit is connected to the second input end of the drive signal generation circuit, and the third input end of the drive signal generation circuit is used to receive the carrier wave. The first output end of the drive signal generation circuit is connected to the first switch in the upper-bridge-arm switch of the first-phase bridge arm, and the second output end of the drive signal generation circuit is connected to the second switch in the upper-bridge-arm switch of the first-phase bridge arm. Among them, the first output end and the second output end of the drive signal generation circuit can form the first output end of the drive signal output circuit. The first output end of the drive signal generation circuit is connected to the second switch in the lower-bridge-arm switch of the first-phase bridge arm through a first inverter, and the second output end of the drive signal generation circuit is connected to the first switch in the lower-bridge-arm switch of the first-phase bridge arm through a second inverter. Among them, one end of the first inverter far from the first output end of the drive signal generation circuit and one end of the second inverter far from the second output end of the drive signal generation circuit form the second output end of the drive signal output circuit. The first inverter and the second inverter in the embodiments of the present application can be arranged inside the drive signal output circuit. Optionally, they can also be arranged outside the drive signal output circuit, which is not limited herein.

[0007] Implementing the embodiments of the present application, using analog circuits such as the first modulation wave output circuit, the second modulation wave output circuit, and the drive signal generation circuit to control the drive signals of hybrid devices such as the upper-bridge-arm switch and the lower-bridge-arm switch can give full play to the advantages of low conduction voltage drop, high current-carrying capacity, and low switching loss of the hybrid devices, and there is no need to rely on an external digital driver to output drive signals, thereby greatly reducing the cost and volume of the drive circuit, while reducing the usage threshold of the hybrid devices and having strong applicability.

[0008] In combination with the first aspect, in a possible implementation manner, the above-mentioned first modulation wave output circuit is configured to output a first modulation wave with a first voltage amplitude to the drive signal generation circuit based on the voltage signal across the first phase bridge arm. The second modulation wave output circuit is configured to output a second modulation wave with a second voltage amplitude to the drive signal generation circuit based on the voltage signal across the first phase bridge arm. Wherein, the first voltage amplitude and the second voltage amplitude are different voltage amplitudes, and both the first voltage amplitude and the second voltage amplitude are the instantaneous voltage amplitudes of the modulation wave at any moment. That is to say, as time changes, the specific values of the first voltage amplitude and the second voltage amplitude will also change. Further, the drive signal generation circuit is configured to compare the first modulation wave with the carrier wave, output a first drive signal to the first switch in the upper bridge arm switch of the first phase bridge arm, and output a first inverted drive signal to the second switch in the lower bridge arm switch of the first phase bridge arm through a first inverter. The drive signal generation circuit is further configured to compare the second modulation wave with the carrier wave, output a second drive signal to the second switch in the upper bridge arm switch of the first phase bridge arm, and output a second inverted drive signal to the first switch in the lower bridge arm switch of the first phase bridge arm through a second inverter. Implementing the embodiments of the present application can output different drive signals to hybrid devices such as the upper bridge arm switch and the lower bridge arm switch based on the voltage signal across the first phase bridge arm collected in real time, so that the three-phase inverter can adapt to different working conditions such as full load condition, light load condition, and no-load condition, thereby improving the control flexibility of the drive signal, and the applicable application scenarios of the three-phase inverter are more diverse.

[0009] In combination with the first aspect, in a possible implementation manner, the above-mentioned first phase delay circuit includes a first phase shifter and a second phase shifter. The input end of the first phase shifter is connected to the first output end of the drive signal generation circuit, and the output end of the first phase shifter is connected to the first switch in the upper bridge arm switch of the second phase bridge arm. The input end of the second phase shifter is connected to the second output end of the drive signal generation circuit, and the output end of the second phase shifter is connected to the second switch in the upper bridge arm switch of the second phase bridge arm. Wherein, the input end of the first phase shifter and the input end of the second phase shifter can form the input end of the first phase delay circuit, and the output end of the first phase shifter and the output end of the second phase shifter can form the first output end of the first phase delay circuit. The output end of the first phase shifter is connected to the second switch in the lower bridge arm switch of the second phase bridge arm through a third inverter, and the output end of the second phase shifter is connected to the first switch in the lower bridge arm switch of the second phase bridge arm through a fourth inverter. Wherein, one end of the third inverter far from the output end of the first phase shifter and one end of the fourth inverter far from the output end of the second phase shifter form the second output end of the first phase delay circuit. The third inverter and the fourth inverter in the embodiments of the present application can be arranged inside the first phase delay circuit, and optionally, they can also be arranged outside the first phase delay circuit, which is not limited herein.

[0010] When the first phase delay circuit is operating, the first phase shifter is configured to delay the phase of the first driving signal by a first angle and output a third driving signal to a first switch in the upper arm switch of the second phase leg, and output a third inverted driving signal to a second switch in the lower arm switch of the second phase leg through a third inverter. The second phase shifter is configured to delay the phase of the second driving signal by the first angle and output a fourth driving signal to a second switch in the upper arm switch of the second phase leg, and output a fourth inverted driving signal to a first switch in the lower arm switch of the second phase leg through a fourth inverter. At this time, the phase angle of the second phase leg lags behind that of the first phase leg by the first angle, that is, the second phase leg conducts with a lag of the first angle behind the first phase leg.

[0011] Implementing the embodiments of the present application, the third driving signal and the fourth driving signal are respectively the driving signals after the phase delay of the first driving signal and the second driving signal, and the third inverted driving signal and the fourth inverted driving signal are respectively the driving signals after the inversion of the third driving signal and the fourth driving signal. That is to say, when the first driving signal and the second driving signal are different, the third driving signal, the fourth driving signal, the third inverted driving signal and the fourth inverted driving signal will also change accordingly, thereby improving the control flexibility of the driving signal. In addition, the first phase shifter, the second phase shifter, the third inverter and the fourth inverter are all analog circuits with smaller volume, which can reduce the volume and cost of the entire driving circuit.

[0012] Combined with the first aspect, in a possible implementation manner, the above-mentioned second phase delay circuit includes a third phase shifter and a fourth phase shifter. When the output end of the first phase delay circuit is connected to the input end of the second phase delay circuit, the input end of the third phase shifter is connected to the output end of the first phase shifter, and the output end of the third phase shifter is connected to a first switch in the upper arm switch of the third phase leg. The input end of the fourth phase shifter is connected to the output end of the second phase shifter, and the output end of the fourth phase shifter is connected to a second switch in the upper arm switch of the third phase leg. Among them, the input ends of the third phase shifter and the fourth phase shifter can form the input end of the second phase delay circuit, and the output ends of the third phase shifter and the fourth phase shifter can form the first output end of the second phase delay circuit. The output end of the third phase shifter is connected to a second switch in the lower arm switch of the third phase leg through a fifth inverter, and the output end of the fourth phase shifter is connected to a first switch in the lower arm switch of the third phase leg through a sixth inverter. Among them, one end of the fifth inverter far from the output end of the third phase shifter and one end of the sixth inverter far from the output end of the fourth phase shifter form the second output end of the second phase delay circuit. The fifth inverter and the sixth inverter in the embodiments of the present application can be arranged inside the second phase delay circuit, and optionally, they can also be arranged outside the second phase delay circuit, which is not limited here.

[0013] When the second phase delay circuit is operating, the third phase shifter is used to delay the phase of the third driving signal by a first angle and output a fifth driving signal to the first switch in the upper bridge arm switch of the third phase bridge arm, and output a fifth inverted driving signal to the second switch in the lower bridge arm switch of the third phase bridge arm through a fifth inverter. The fourth phase shifter is used to delay the phase of the fourth driving signal by the first angle and output a sixth driving signal to the second switch in the upper bridge arm switch of the third phase bridge arm, and output a sixth inverted driving signal to the first switch in the lower bridge arm switch of the third phase bridge arm through a sixth inverter, so that the current output power of the three-phase inverter is less than or equal to the rated output power. At this time, the phase angle of the third phase bridge arm lags behind that of the second phase bridge arm by the first angle, that is, the third phase bridge arm conducts with a lag of the first angle behind the second phase bridge arm. Exemplarily, the first angle is 120°. When the current output power of the three-phase inverter is equal to the rated output power, the three-phase inverter is in a full-load condition. When the current output power of the three-phase inverter is less than the rated output power, the three-phase inverter is in a light-load condition or a no-load condition.

[0014] Implementing the embodiments of the present application, the fifth driving signal and the sixth driving signal are respectively the driving signals after the phase delay of the third driving signal and the fourth driving signal, and the fifth inverted driving signal and the sixth inverted driving signal are respectively the driving signals after the inversion of the fifth driving signal and the sixth driving signal. That is to say, when the third driving signal and the fourth driving signal are different, the fifth driving signal, the sixth driving signal, the fifth inverted driving signal and the sixth inverted driving signal will also change accordingly, so that the three-phase inverter is in different conditions such as full-load condition, light-load condition and no-load condition, thereby improving the control flexibility of the driving signal, and the applicable application scenarios of the three-phase inverter are more diverse. In addition, the third phase shifter, the fourth phase shifter, the fifth inverter and the sixth inverter are all analog circuits with smaller volume, which can reduce the volume and cost of the entire driving circuit.

[0015] In combination with the first aspect, in a possible implementation manner, the above-mentioned second phase delay circuit includes a third phase shifter and a fourth phase shifter. When the output end of the drive signal output circuit is connected to the input end of the second phase delay circuit, the input end of the third phase shifter is connected to the first output end of the drive signal generation circuit, and the output end of the third phase shifter is connected to the first switch in the upper arm switch of the third phase bridge arm. The input end of the fourth phase shifter is connected to the second output end of the drive signal generation circuit, and the output end of the fourth phase shifter is connected to the second switch in the upper arm switch of the third phase bridge arm. The output end of the third phase shifter is connected to the second switch in the lower arm switch of the third phase bridge arm through a fifth inverter, and the output end of the fourth phase shifter is connected to the first switch in the lower arm switch of the third phase bridge arm through a sixth inverter. When the second phase delay circuit is working, the third phase shifter is used to delay the phase of the first drive signal by a second angle and output a fifth drive signal to the first switch in the upper arm switch of the third phase bridge arm, and output a fifth inverted drive signal to the second switch in the lower arm switch of the third phase bridge arm through the fifth inverter. The fourth phase shifter is used to delay the phase of the second drive signal by a second angle and output a sixth drive signal to the second switch in the upper arm switch of the third phase bridge arm, and output a sixth inverted drive signal to the first switch in the lower arm switch of the third phase bridge arm through the sixth inverter, so that the current output power of the three-phase inverter is less than or equal to the rated output power. Wherein, the first angle and the second angle are opposite to each other. At this time, the phase angle of the third phase bridge arm lagging behind the first phase bridge arm is the second angle, that is, the third phase bridge arm lags behind the first phase bridge arm by the second angle to conduct.

[0016] Implementing the embodiments of the present application, the fifth drive signal and the sixth drive signal are respectively the drive signals after the phase delay of the first drive signal and the second drive signal, and the fifth inverted drive signal and the sixth inverted drive signal are respectively the drive signals after the inversion of the fifth drive signal and the sixth drive signal. That is to say, when the first drive signal and the second drive signal are different, the fifth drive signal, the sixth drive signal, the fifth inverted drive signal and the sixth inverted drive signal will also change accordingly, so that the three-phase inverter is in different working conditions such as full load condition, light load condition and no-load condition, thereby improving the control flexibility of the drive signal, and the applicable application scenarios of the three-phase inverter are more diverse. In addition, the third phase shifter, the fourth phase shifter, the fifth inverter and the sixth inverter are all analog circuits with smaller volume, which can reduce the volume and cost of the entire drive circuit.

[0017] In combination with the first aspect, in a possible implementation manner, each of the first modulation wave output circuit and the second modulation wave output circuit includes an amplitude adjustment circuit and a modulation wave generation circuit. Among them, the input end of the amplitude adjustment circuit is connected to the input end of each modulation wave output circuit, the output end of the amplitude adjustment circuit is connected to the input end of the modulation wave generation circuit, and the output end of the modulation wave generation circuit is connected to the output end of each modulation wave output circuit. When each modulation wave output circuit is working, the amplitude adjustment circuit is used to adjust the voltage amplitude of the voltage signal across the first phase bridge arm and output a target voltage signal to the modulation wave generation circuit. Further, the modulation wave generation circuit is used to generate a modulation wave based on the target voltage signal. Among them, when the voltage amplitude of the target voltage signal is the first voltage amplitude, the modulation wave is the first modulation wave. When the voltage amplitude of the target voltage signal is the second voltage amplitude, the modulation wave is the second modulation wave. Implementing the embodiments of the present application, since the voltage amplitude of the carrier remains unchanged, it can be obtained that the magnitude of the voltage amplitude of the modulation wave determines the pulse width (i.e., the high-level signal width) of the driving signal of the first phase bridge arm. Therefore, based on the voltage signal across the first phase bridge arm collected in real time to dynamically adjust the voltage amplitude of the modulation wave, the pulse width of the driving signal of the first phase bridge arm can be further adjusted, thereby improving the control flexibility of the driving signal of the first phase bridge arm.

[0018] In combination with the first aspect, in a possible implementation manner, the modulation wave generation circuit includes a first signal generator, a second signal generator, a second adder, and an absolute value circuit. Among them, the input end of the first signal generator is connected to the input end of the modulation wave generation circuit, the output end of the first signal generator is connected to the first input end of the second adder, the output end of the second signal generator is connected to the second input end of the second adder, the output end of the second adder is connected to the input end of the absolute value circuit, and the output end of the absolute value circuit is connected to the output end of the modulation wave generation circuit. When the modulation wave generation circuit is working, the first signal generator is used to output a first waveform signal to the second adder based on the target voltage signal. The second signal generator is used to output a second waveform signal to the second adder based on the target voltage signal, where the frequency of the second waveform signal is three times that of the first waveform signal. Further, the second adder is used to superimpose the second waveform signal on the first waveform signal and output a superimposed waveform signal to the absolute value circuit. Exemplarily, the superimposed waveform signal can be a saddle wave. Further, the absolute value circuit is used to generate a modulation wave based on the superimposed waveform signal. Exemplarily, the saddle wave of the negative voltage in the superimposed waveform signal is flipped to the positive voltage range to generate the first modulation wave. Implementing the embodiments of the present application, the first modulation wave with a positive voltage can be generated through the first signal generator, the second signal generator, the second adder, and the absolute value circuit, which is more convenient for comparison with the carrier and the driving method is simpler.

[0019] In combination with the first aspect, in a possible implementation manner, the amplitude adjustment circuit includes a voltage amplifier. The input end of the voltage amplifier is connected to the input end of the amplitude adjustment circuit, and the output end of the voltage amplifier is connected to the output end of the amplitude adjustment circuit. The above-mentioned voltage amplifier is used to amplify the voltage amplitude of the voltage signal across the first phase leg and output a target voltage signal to the modulation wave generation circuit. The voltage amplitude of the target voltage signal is the amplified voltage amplitude, and the voltage amplitude of the target voltage signal is specifically determined by the component parameters inside the voltage amplifier, which is not limited here. Implementing the embodiments of the present application, the voltage amplitude of the voltage signal across the first phase leg can be dynamically adjusted by adjusting the component parameters inside the voltage amplifier, and the adjustment method is more flexible.

[0020] In combination with the first aspect, in a possible implementation manner, the amplitude adjustment circuit further includes an adder, where the adder is arranged between the input end of the voltage amplifier and the input end of the amplitude adjustment circuit. The above-mentioned adder is used to adjust the voltage amplitude of the voltage signal across the first phase leg and output the adjusted voltage signal to the voltage amplifier. Further, the voltage amplifier is used to amplify the voltage amplitude of the adjusted voltage signal and output a target voltage signal to the modulation wave generation circuit. The voltage amplitude of the target voltage signal is specifically determined by the component parameters inside the adder and the voltage amplifier, which is not limited here. Implementing the embodiments of the present application, the voltage amplitude of the voltage signal across the first phase leg can be dynamically adjusted by adjusting the component parameters inside the adder and the voltage amplifier, and the adjustment range of the voltage amplitude is larger.

[0021] In combination with the first aspect, in a possible implementation manner, the drive signal generation circuit includes a first comparator. The first input end of the first comparator is connected to the first input end of the drive signal generation circuit to receive the first modulation wave, the second input end of the first comparator is connected to the third input end of the drive signal generation circuit to receive the carrier wave, and the output end of the first comparator is connected to the first output end of the drive signal generation circuit. The above-mentioned first comparator is used to output the first drive signal as the first level when the first voltage amplitude of the first modulation wave is greater than the voltage amplitude of the carrier wave, and output the first drive signal as the second level when the first voltage amplitude of the first modulation wave is less than the voltage amplitude of the carrier wave. Among them, when the first level is low, the second level is high, or when the first level is high, the second level is low. Taking the case where the first level is high and the second level is low as an example for illustration, the first switch is used to conduct when the first drive signal is high and turn off when the first drive signal is low. Implementing the embodiments of the present application, different pulse-width first drive signals are output in real time according to the voltage amplitude of the carrier wave and the dynamically adjusted first voltage amplitude, thereby improving the control flexibility of the first switch and adapting to different working conditions of the three-phase inverter.

[0022] In combination with the first aspect, in a possible implementation manner, the drive signal generation circuit further includes a second comparator. The first input terminal of the second comparator is connected to the second input terminal of the drive signal generation circuit to receive a second modulation wave. The second input terminal of the second comparator is connected to the third input terminal of the drive signal generation circuit to receive a carrier wave. The output terminal of the second comparator is connected to the second output terminal of the drive signal generation circuit. The second comparator is configured to output the second drive signal as a first level when the second voltage amplitude of the second modulation wave is greater than the voltage amplitude of the carrier wave, and output the second drive signal as a second level when the second voltage amplitude of the second modulation wave is less than the voltage amplitude of the carrier wave. Taking the case where the first level is a high level and the second level is a low level as an example, the second switch is configured to conduct when the second drive signal is a high level and turn off when the second drive signal is a low level. Implementing the embodiments of the present application can output the second drive signal with different pulse widths in real time according to the voltage amplitude of the carrier wave and the dynamically adjusted second voltage amplitude, thereby improving the control flexibility of the second switch and adapting to different working conditions of the three-phase inverter.

[0023] In combination with the first aspect, in a possible implementation manner, the drive circuit further includes a carrier wave output circuit. The carrier wave output circuit includes a third signal generator and a level shift circuit. The output terminal of the third signal generator is connected to the input terminal of the level shift circuit, and the output terminal of the level shift circuit is connected to the third input terminal of the drive signal generation circuit. When the carrier wave output circuit is operating, the third signal generator is configured to output a third waveform signal to the level shift circuit. Further, the level shift circuit is configured to output a carrier wave to the drive signal generation circuit based on the third waveform signal. Exemplarily, the triangular wave with a negative voltage in the second waveform signal is shifted to the positive voltage range to output a carrier wave with a positive voltage to the drive signal output circuit. The voltage amplitude of the carrier wave remains unchanged. Implementing the embodiments of the present application can generate a carrier wave with a positive voltage through the third signal generator and the level shift circuit, which is more convenient for comparison with the modulation wave and the drive method is simpler.

[0024] In combination with the first aspect, in a possible implementation manner, the drive circuit further includes a current sensor. When the three-phase inverter is in any one of the full-load condition, light-load condition, and no-load condition, the input end of the current sensor is connected to the input end of the three-phase inverter, and the output end of the current sensor is connected to the input ends of the first modulation wave output circuit and the second modulation wave output circuit. The above-mentioned current sensor is used to collect the input current of the three-phase inverter, and based on the input current of the three-phase inverter, output the voltage signal across the first phase leg to the first modulation wave output circuit and the second modulation wave output circuit respectively. Among them, the magnitude of the input current of the three-phase inverter is used to judge the actual condition of the three-phase inverter. Implementing the embodiments of the present application can output voltage signals under different conditions according to the input current of the three-phase inverter, so as to control the drive signals of the first phase leg required under different conditions.

[0025] In combination with the first aspect, in a possible implementation manner, the drive circuit further includes a current sensor. When the three-phase inverter is in the full-load condition, the current passing through the first phase leg is relatively large. At this time, the input end of the current sensor can also be connected to the end of the upper-bridge-arm switch of the first phase leg far from the lower-bridge-arm switch, and the output end of the current sensor is connected to the input ends of the first modulation wave output circuit and the second modulation wave output circuit. The above-mentioned current sensor is used to collect the current passing through the first phase leg, and based on the current passing through the first phase leg, output the voltage signal across the first phase leg to the first modulation wave output circuit and the second modulation wave output circuit respectively. Among them, the magnitude of the current passing through the first phase leg is used to judge the actual condition of the three-phase inverter. Implementing the embodiments of the present application can output voltage signals under different conditions according to the current passing through the first phase leg, so as to control the drive signals of the first phase leg required under different conditions.

[0026] In the second aspect, an embodiment of the present application provides a motor control unit (MCU). The MCU includes an input port, a three-phase output port, and a three-phase inverter provided in any one of the possible implementation manners of the first aspect and its combinations. The input port is used to connect to a power battery, and the three-phase output port is used to connect to a motor. Among them, the input end of the three-phase inverter is connected to the input port, and the three-phase output ends of the three-phase inverter are connected to the three-phase output port. The three-phase inverter is used to invert the direct current output by the power battery into three-phase alternating current and drive the motor. Implementing the embodiments of the present application can improve the integration of the MCU and reduce the cost and volume of the MCU because the three-phase inverter is smaller in volume and lower in cost.

[0027] In the third aspect, an embodiment of the present application provides a powertrain. The powertrain includes a motor and the MCU provided in the second aspect. Among them, the MCU is used to invert the direct current output by the power battery into three-phase alternating current and drive the motor.

[0028] Fourthly, an embodiment of the present application provides an electric vehicle, which includes a power battery and a powertrain as provided in the third aspect. Among them, the power battery is used to output direct current to the powertrain.

[0029] It should be understood that the implementation and beneficial effects of the above-mentioned multiple aspects of the present application can be referred to each other. Description of the Drawings

[0030] Figure 1 is a schematic structural diagram of the electric vehicle provided by the embodiment of the present application;

[0031] Figure 2 is a schematic structural diagram of a three-phase inverter provided by the embodiment of the present application;

[0032] Figure 3 is a schematic circuit diagram of a three-phase inverter provided by the embodiment of the present application;

[0033] Figure 4 is a schematic structural diagram of a drive signal output circuit provided by the embodiment of the present application;

[0034] Figure 5 is another schematic structural diagram of a drive signal output circuit provided by the embodiment of the present application;

[0035] Figure 6A is a schematic circuit diagram of an amplitude adjustment circuit provided by the embodiment of the present application;

[0036] Figure 6B is another schematic circuit diagram of an amplitude adjustment circuit provided by the embodiment of the present application;

[0037] Figure 7 is a circuit diagram of a modulation wave generation circuit provided by the embodiment of the present application;

[0038] Figure 8 is a circuit diagram of a carrier output circuit provided by the embodiment of the present application;

[0039] Figure 9 is a circuit diagram of a drive signal generation circuit provided by the embodiment of the present application;

[0040] Figure 10 is a waveform diagram of the drive signal of the first phase leg provided by the embodiment of the present application;

[0041] Figure 11A is a waveform diagram of the voltages of the first switch and the second switch in the upper bridge arm switches of the three-phase inverter under full load conditions provided by the embodiment of the present application;

[0042] Figure 11BIt is a schematic diagram of the voltage waveforms of the first switch and the second switch in the upper bridge arm of the three-phase inverter provided by the embodiment of the present application when it is in a light load condition;

[0043] Figure 12 It is a schematic connection diagram between the drive signal output circuit, the first phase delay circuit, and the second phase bridge arm provided by the embodiment of the present application;

[0044] Figure 13 It is a schematic circuit diagram of the first phase shifter provided by the embodiment of the present application;

[0045] Figure 14A It is a schematic connection diagram between the first phase delay circuit, the second phase delay circuit, and the third phase bridge arm provided by the embodiment of the present application;

[0046] Figure 14B It is a schematic connection diagram between the drive signal output circuit, the second phase delay circuit, and the third phase bridge arm provided by the embodiment of the present application;

[0047] Figure 15 It is another schematic circuit diagram of the three-phase inverter provided by the embodiment of the present application;

[0048] Figure 16 It is a schematic structural diagram of the motor controller MCU provided by the embodiment of the present application. Detailed implementation manners

[0049] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0050] Next, the implementation of the technical solutions of the present application will be further described in detail with reference to the accompanying drawings.

[0051] See Figure 1 , Figure 1 It is a schematic structural diagram of an electric vehicle provided by the embodiment of the present application. As Figure 1 shown, the electric vehicle 1 includes a power battery 10 and a powertrain 11, and the power battery 10 is used to output direct current to the powertrain 11.

[0052] The powertrain 11 includes a motor 111 and a motor control unit (MCU) 112. The MCU 112 is used to invert the direct current output by the power battery 10 into three-phase alternating current and drive the motor 111. In a specific implementation, the MCU 112 includes a first-phase bridge arm, a second-phase bridge arm, a third-phase bridge arm, and a drive circuit. The first-phase bridge arm, the second-phase bridge arm, and the third-phase bridge arm are connected in parallel and then connected to the power battery 10. The midpoint of the first-phase bridge arm, the midpoint of the second-phase bridge arm, and the midpoint of the third-phase bridge arm are connected to the motor 111. Among them, the drive circuit is used to output a first bridge arm drive signal to the first-phase bridge arm based on the voltage signal at both ends of the first-phase bridge arm, delay the phase of the first bridge arm drive signal by a first angle and output a second bridge arm drive signal to the second-phase bridge arm, and delay the phase of the second bridge arm drive signal by the first angle to output a third bridge arm drive signal to the third-phase bridge arm, so that the MCU 112 inverts the direct current output by the power battery 10 into three-phase alternating current and drives the motor 111.

[0053] Implementing the embodiments of the present application, independent bridge arm drive signals can be respectively output to the three-phase bridge arms through the drive circuit, without relying on an external digital signal processor (DSP) to output bridge arm drive signals, thereby greatly reducing the cost and volume of the drive circuit, and further reducing the cost and volume of the MCU 112 and the powertrain 11, with strong applicability.

[0054] Next, Figures 2 to 16 an example will be given to illustrate the three-phase inverter, the motor control unit MCU, and its working principle provided by the present application.

[0055] Figure 2 is a schematic structural diagram of a three-phase inverter provided by an embodiment of the present application. As Figure 2 shown, the input end of the three-phase inverter 2 is used to connect to a DC source U DC , and the three-phase output ends of the three-phase inverter 2 are used to connect to an AC load 3. Among them, the input end of the three-phase inverter 2 includes an input terminal in 11 and an input terminal in 12 , the input terminal in 11 and the input terminal in 12 of the three-phase inverter 2 are connected to both ends of the DC source U DC . The three-phase output ends of the three-phase inverter 2 include a first-phase output terminal out 11 , a second-phase output terminal out 12 , and a third-phase output terminal out 13 , the first-phase output terminal out 11 , the second-phase output terminal out 12 , and the third-phase output terminal out 13Connect to the three-phase input terminal of the AC load 3. When powering the AC load 3, the three-phase inverter 2 is used to invert the direct current output by the DC source U DC into three-phase alternating current and supply power to the AC load 3.

[0056] The above three-phase inverter 2 includes a first-phase bridge arm 20, a second-phase bridge arm 21, a third-phase bridge arm 22, and a drive circuit 23. The first-phase bridge arm 20, the second-phase bridge arm 21, and the third-phase bridge arm 22 constitute a three-phase inverter circuit. Among them, the first-phase bridge arm 20, the second-phase bridge arm 21, and the third-phase bridge arm 22 are connected in parallel and then connected to the input terminal of the three-phase inverter 2. The midpoints of the first-phase bridge arm 20, the second-phase bridge arm 21, and the third-phase bridge arm 22 are connected to the three-phase output terminals of the three-phase inverter 2. Exemplarily, the first parallel connection ends of the first-phase bridge arm 20, the second-phase bridge arm 21, and the third-phase bridge arm 22 are connected to the input terminal in of the three-phase inverter 2 11 , and the second parallel connection ends of the first-phase bridge arm 20, the second-phase bridge arm 21, and the third-phase bridge arm 22 are connected to the input terminal in of the three-phase inverter 2 12 . The midpoint of the first-phase bridge arm 20 is connected to the first-phase output terminal out of the three-phase inverter 2 11 , the midpoint of the second-phase bridge arm 21 is connected to the second-phase output terminal out of the three-phase inverter 2 12 , and the midpoint of the third-phase bridge arm 22 is connected to the third-phase output terminal out of the three-phase inverter 2 13 . Each phase bridge arm of the above first-phase bridge arm 20, second-phase bridge arm 21, and third-phase bridge arm 22 includes a series-connected upper bridge arm switch and a lower bridge arm switch, and the series connection point of the upper bridge arm switch and the lower bridge arm switch is the midpoint of each phase bridge arm. Exemplarily, the above first-phase bridge arm 20 (such as the U-phase bridge arm) includes a series-connected upper bridge arm switch H1 and a lower bridge arm switch H2, and the series connection point of the upper bridge arm switch H1 and the lower bridge arm switch H2 is the midpoint of the first-phase bridge arm 20. The second-phase bridge arm 21 (such as the V-phase bridge arm) includes a series-connected upper bridge arm switch H3 and a lower bridge arm switch H4, and the series connection point of the upper bridge arm switch H3 and the lower bridge arm switch H4 is the midpoint of the second-phase bridge arm 21. The third-phase bridge arm 22 (such as the W-phase bridge arm) includes a series-connected upper bridge arm switch H5 and a lower bridge arm switch H6, and the series connection point of the upper bridge arm switch H5 and the lower bridge arm switch H6 is the midpoint of the third-phase bridge arm 22.

[0057] The above drive circuit 23 includes a drive signal output circuit 230, a first phase delay circuit 231, and a second phase delay circuit 232. Both the first phase delay circuit 231 and the second phase delay circuit 232 are circuits that delay the phase of the input signal by a certain angle, and the present application does not limit the delay angle. Among them, the first input terminal in of the drive signal output circuit 230 21 and the second input terminal in 22are all used to receive the voltage signal U across the two ends of the first-phase bridge arm 20 i , the first output terminal out of the drive signal output circuit 230 21 is connected to the upper-bridge-arm switch H1, and the second output terminal out of the drive signal output circuit 230 22 is connected to the lower-bridge-arm switch H2. The first output terminal out of the drive signal output circuit 230 21 is connected to the input terminal in of the first phase delay circuit 231 3 , and the first output terminal out of the first phase delay circuit 231 31 is connected to the upper-bridge-arm switch H3, and the second output terminal out of the first phase delay circuit 231 32 is connected to the lower-bridge-arm switch H4. The first output terminal out of the first phase delay circuit 231 31 is connected to the input terminal in of the second phase delay circuit 232 4 , optionally, the first output terminal out of the drive signal output circuit 230 21 is connected to the input terminal in of the second phase delay circuit 232 4 , specifically as Figure 2 the first output terminal out 21 and the input terminal in 4 as shown by the dashed line therebetween. The first output terminal out of the second phase delay circuit 232 41 is connected to the upper-bridge-arm switch H5, and the second output terminal out of the second phase delay circuit 232 42 is connected to the lower-bridge-arm switch H6.

[0058] Implementing the embodiments of the present application, when the upper and lower bridge-arm switches in each phase bridge arm are all hybrid devices, the drive circuit 23 (i.e., the analog circuit) can also output the drive signal corresponding to each phase bridge arm according to the voltage signal U across the two ends of the first phase bridge arm 20 i , without relying on an external digital driver to output the drive signal, thereby greatly reducing the cost and volume of the drive circuit 23 and having strong applicability. Exemplarily, the digital driver can be one of a DSP, a field-programmable gate array (FPGA), and a complex programmable logic device (CPLD).

[0059] In some feasible implementation manners, when the three-phase inverter 2 is applied to an electric vehicle scenario, the DC source U DC is a power battery and the AC load 3 is a motor. When the three-phase inverter 2 is applied to a photovoltaic power supply scenario, the DC source U DCThe PV array, and the AC load 3 is an AC power grid or other electrical equipment. When the three-phase inverter 2 is applied to an energy storage power supply scenario, the DC source U DC is an energy storage battery pack, and the AC load 3 is an AC power grid or other electrical equipment.

[0060] In some feasible embodiments, the AC load 3 is a three-phase load. Optionally, the AC load 3 is composed of three single-phase loads. The present application does not limit the specific type of the AC load 3.

[0061] In some feasible embodiments, each of the upper-bridge switches and lower-bridge switches of each phase leg is composed of a first switch and a second switch connected in parallel. Exemplarily, when the first switch is an IGBT, the second switch is a MOSFET; or when the first switch is a MOSFET, the second switch is an IGBT. As Figure 3 shown, the upper-bridge switch H1 shown above Figure 2 is composed of a first switch Q1 and a second switch Q2 connected in parallel, and the lower-bridge switch H2 is composed of a first switch Q3 and a second switch Q4 connected in parallel. The upper-bridge switch H3 is composed of a first switch Q5 and a second switch Q6 connected in parallel, and the lower-bridge switch H4 is composed of a first switch Q7 and a second switch Q8 connected in parallel. The upper-bridge switch H5 is composed of a first switch Q9 and a second switch Q10 connected in parallel, and the lower-bridge switch H6 is composed of a first switch Q11 and a second switch Q12 connected in parallel. Among them, the first switch in each phase leg is a Si IGBT, and the second switch in each phase leg is a SiC MOSFET, that is, the upper-bridge switches and lower-bridge switches in each phase leg are all Si IGBT&SiC MOS hybrid devices. Implementing the embodiments of the present application, since the upper and lower-bridge switches adopted in the circuit topology of the three-phase inverter 2 are all Si IGBT&SiC MOS hybrid devices, this circuit topology can take into account the advantages of low conduction voltage drop and high current-carrying capacity of Si IGBT, as well as the advantage of low switching loss of SiC MOS, and has stronger applicability.

[0062] In some feasible embodiments, as Figure 3 shown, the driving circuit 23 shown above Figure 2 further includes a current sensor 233. When the three-phase inverter 2 is in any one of the full-load condition, light-load condition, and no-load condition, the input end in 5 of the current sensor 233 is connected to the input end in 11 of the three-phase inverter 2, and the output end out 5 of the current sensor 233 is connected to the first input end in 21 and the second input end in 22 of the driving signal output circuit 230. Among them, the current sensor 233 is used to collect the input current I 0, and based on the input current I of the three-phase inverter 2 0 respectively output the voltage signal U across the first phase leg 20 to the first input terminal in of the drive signal output circuit 230 21 and the second input terminal in 22 of the drive signal output circuit 230. Optionally, when the three-phase inverter 2 is in the full-load operating condition, the current I passing through the first phase leg 20 i is relatively large. At this time, the input terminal in of the current sensor 233 1 can also be connected to the end of the upper-bridge-arm switch H1 of the first phase leg 20 that is far from the lower-bridge-arm switch H2, specifically as shown by the dotted line between the input terminal in of the current sensor 233 5 in Figure 3 and the end of the upper-bridge-arm switch H1 that is far from the lower-bridge-arm switch H2. The above-mentioned current sensor 233 is used to collect the current I passing through the first phase leg 20 5 , and based on the current I passing through the first phase leg 20 1 , respectively output the voltage signal U across the first phase leg 20 to the first input terminal in 1 and the second input terminal in 21 of the drive signal output circuit 230 22 . Among them, the current I passing through the first phase leg 20 i can also be referred to as the loop leg current. Implementing the embodiments of the present application, different operating-condition voltage signals U 1 can be output according to the input current I of the three-phase inverter 2 0 or the current I passing through the first phase leg 20 1 , and the driving flexibility is stronger. i

[0063] See Figure 4 , Figure 4 which is a schematic structural diagram of the drive signal output circuit provided by the embodiments of the present application. As shown in Figure 4 , the drive signal output circuit 230 includes a first modulation wave output circuit 2300, a second modulation wave output circuit 2301, and a drive signal generation circuit 2302. It should be understood that the first modulation wave output circuit 2300 is a circuit for outputting the modulation wave M 1 corresponding to the first switch Q1, and the second modulation wave output circuit 2301 is a circuit for outputting the modulation wave M 2 corresponding to the second switch Q2. The drive signal generation circuit 2302 is a circuit for generating the drive signal of the first phase leg 20.

[0064] Among them, the input terminal in of the first modulation wave output circuit 2300 6 serves as the first input terminal in of the drive signal output circuit 230 21, and is used to receive the voltage signal U across the two ends of the first-phase bridge arm 20 i . The input end in of the second modulation wave output circuit 2301 7 serves as the second input end in of the drive signal output circuit 230 22 , and is used to receive the voltage signal U across the two ends of the first-phase bridge arm 20 i . The output end out of the first modulation wave output circuit 2300 6 is connected to the first input end in of the drive signal generation circuit 2302 81 . The output end out of the second modulation wave output circuit 2301 7 is connected to the second input end in of the drive signal generation circuit 2302 82 . The third input end in of the drive signal generation circuit 2302 83 is used to receive the carrier wave Z.

[0065] The first output end out of the above-mentioned drive signal generation circuit 2302 81 serves as the output end out of the drive signal output circuit 230 211 , and is connected to the first switch Q1. The second output end out of the drive signal generation circuit 2302 82 serves as the output end out of the drive signal output circuit 230 212 , and is connected to the second switch Q2. Among them, the output end out and the output end out 211 of the above-mentioned drive signal output circuit 230 212 can form the first output end of the drive signal output circuit 230. The first output end out of the drive signal generation circuit 2302 81 is connected to the second switch Q4 through the first inverter N1, that is, one end of the first inverter N1 far from the first output end out of the drive signal generation circuit 2302 31 serves as the output end out of the drive signal output circuit 230 221 , and is connected to the second switch Q4. The second output end out of the drive signal generation circuit 2302 82 is connected to the first switch Q3 through the second inverter N2, that is, one end of the second inverter N2 far from the second output end out of the drive signal generation circuit 2302 82 serves as the output end out of the drive signal output circuit 230 222 , and is connected to the first switch Q3. Among them, the output end out and the output end out 221 of the above-mentioned drive signal output circuit 230 222 can form the second output end of the drive signal output circuit 230. The first inverter N1 and the second inverter N2 are devices that reverse the phase of the input signal by 180 degrees Figure 4The first inverter N1 and the second inverter N2 shown are only examples, and the present application does not limit their specific circuit topologies.

[0066] Implementing the embodiments of the present application, using analog circuits such as the first modulation wave output circuit 2300, the second modulation wave output circuit 2301, and the drive signal generation circuit 2302 to control the drive signals of Si IGBT&SiCMOS hybrid devices such as the upper bridge arm switch H1 and the lower bridge arm switch H2 can give full play to the advantages of low on-state voltage drop, high current-carrying capacity, and low switching loss of Si IGBT&SiC MOS hybrid devices, and there is no need to rely on an external digital driver to output drive signals, thereby greatly reducing the cost and volume of the drive circuit 23, and at the same time reducing the usage threshold of Si IGBT&SiC MOS hybrid devices, with strong applicability.

[0067] In some feasible implementation manners, the first inverter N1 and the second inverter N2 may be disposed inside the drive signal output circuit 230, and optionally, may also be disposed outside the drive signal output circuit 230, which is not limited herein.

[0068] In some feasible implementation manners, the component parameters inside the above-mentioned drive signal output circuit 230, the first phase delay circuit 231, and the second phase delay circuit 232 are determined by the preset pulse width of the first switch Q1, the preset pulse width of the second switch Q2, and the preset switch delay time between the first switch Q1 and the second switch Q2. Among them, the preset pulse widths and the preset switch delay time of the first switch Q1 and the second switch Q2 may be pre-set values, or may be values determined according to the voltage waveforms simulated under the specific working conditions of the three-phase inverter 2. Exemplarily, the specific working conditions of the three-phase inverter 2 include light load conditions, no-load conditions, and full load conditions. Implementing the embodiments of the present application, the component parameters inside analog circuits such as the drive signal output circuit 230, the first phase delay circuit 231, and the second phase delay circuit 232 can be adjusted to control the drive signals of each phase bridge arm so that the three-phase inverter 2 is in different working conditions, with stronger adaptability.

[0069] In some feasible implementation manners, as Figure 4 shown, the input end in of the current sensor 233 5 is connected to the input end in of the three-phase inverter 2 11 , and the output end out of the current sensor 233 5 is connected to the input end in of the first modulation wave output circuit 2300 6 and the input end in of the second modulation wave output circuit 2301 7 . The above-mentioned current sensor 233 is used to collect the input current I of the three-phase inverter 2 0 , and based on the input current I of the three-phase inverter 20 Output the voltage signal U across both ends of the first phase leg 20 to the first modulation wave output circuit 2300 and the second modulation wave output circuit 2301 respectively i .

[0070] It should be understood that the magnitude of the current I 0 is used to judge the actual working condition of the three-phase inverter 2. In a specific implementation, when the current I 0 is greater than the first current threshold, the voltage value corresponding to the voltage signal U i is greater than the first voltage threshold. At this time, the three-phase inverter 2 is in a full-load working condition, where the first voltage threshold is the voltage value corresponding to the first current threshold. When the current I 0 is less than the first current threshold, the voltage value corresponding to the voltage signal U i is less than the first voltage threshold. At this time, the three-phase inverter 2 is in a light-load working condition. Optionally, when the current I 0 is greater than the second current threshold, the voltage value corresponding to the voltage signal U i is greater than the second voltage threshold. At this time, the three-phase inverter 2 is in a full-load working condition, where the second voltage threshold is the voltage value corresponding to the second current threshold. When the current I 0 is greater than the third current threshold and less than the second current threshold, the voltage value corresponding to the voltage signal U i is greater than the third voltage threshold and less than the second voltage threshold. At this time, the three-phase inverter 2 is in a light-load working condition, where the third voltage threshold is the voltage value corresponding to the third current threshold. When the current I 0 is less than the third current threshold, the voltage value corresponding to the voltage signal U i is greater than the third voltage threshold. At this time, the three-phase inverter 2 is in an idle-load working condition, where the third voltage threshold is the voltage value corresponding to the third current threshold. Among them, the first current threshold, the second current threshold, the third current threshold, the first voltage threshold, the second voltage threshold, and the third voltage threshold can be preset values, or values determined according to the components used in the three-phase inverter 2, and are not specifically limited here.

[0071] Implementing the embodiments of the present application, different working condition voltage signals U 0 can be output according to the input current I i of the three-phase inverter 2, so as to control the drive signal of the first phase leg 20 required for different working conditions.

[0072] Optionally, in some feasible implementation manners, the input end in 5 of the current sensor 233 is connected to one end of the upper bridge arm switch H1 of the first phase leg 20 far from the lower bridge arm switch H2, and the output end out 5 of the current sensor 233 is connected to the input end in 6and the input terminal in of the second modulation wave output circuit 2301 7 The current sensor 233 is used to collect the current I passing through the first phase leg 20 1 and based on the current I passing through the first phase leg 20 1 respectively output the voltage signal U across the first phase leg 20 to the first modulation wave output circuit 2300 and the second modulation wave output circuit 2301 i Among them, the magnitude of the current I 1 is used to judge the actual working condition of the three-phase inverter 2. Specifically, reference can be made to the above description about the magnitude of the current I 0 The magnitude of which is used to judge the actual working condition of the three-phase inverter 2, and details are not described herein again. It should be noted that the first current threshold, the second current threshold, and the third current threshold corresponding to the current I 1 are different from the first current threshold, the second current threshold, and the third current threshold corresponding to the current I 0 Implementing the embodiments of the present application, different voltage signals U can be output according to the current I passing through the first phase leg 20 1 so as to control the drive signal of the first phase leg 20 required for different working conditions. i

[0073] In some feasible embodiments, in the case where the current sensor 233 is not provided in the drive circuit 23, the voltage signal U across the first phase leg 20 i can also be directly collected by the voltage detection circuit inside the drive circuit 23, and no specific limitation is made here.

[0074] In some feasible embodiments, the first modulation wave output circuit 2300 is used to output the first modulation wave M with the first voltage amplitude to the drive signal generation circuit 2302 based on the voltage signal U across the first phase leg 20 i The second modulation wave output circuit 2301 is used to output the second modulation wave M with the second voltage amplitude to the drive signal generation circuit 2302 based on the voltage signal U across the first phase leg 20 1 The second modulation wave output circuit 2301 is used to output the second modulation wave M with the second voltage amplitude to the drive signal generation circuit 2302 based on the voltage signal U across the first phase leg 20 i to the drive signal generation circuit 2302. Among them, the first voltage amplitude and the second voltage amplitude are different voltage amplitudes, and moreover, the first voltage amplitude and the second voltage amplitude are the instantaneous voltage amplitudes of the modulation wave at any moment. That is to say, as time changes, the specific values of the first voltage amplitude and the second voltage amplitude will also change. 2 Among them, the first voltage amplitude and the second voltage amplitude are different voltage amplitudes, and moreover, the first voltage amplitude and the second voltage amplitude are the instantaneous voltage amplitudes of the modulation wave at any moment. That is to say, as time changes, the specific values of the first voltage amplitude and the second voltage amplitude will also change.

[0075] Furthermore, the drive signal generation circuit 2302 is used to process the first modulation wave M 1 ​Compare with the carrier wave Z, output a first driving signal to the first switch Q1, and output a first inverted driving signal to the second switch Q4 through the first inverter N1. The driving signal generation circuit 2302 is further configured to compare the second modulation wave M 2 Compare with the carrier wave Z, output a second driving signal to the second switch Q2, and output a second inverted driving signal to the first switch Q3 through the second inverter N2. At this time, the first switch Q1 is configured to conduct or turn off according to the first driving signal, the second switch Q4 is configured to conduct or turn off according to the first inverted driving signal, the second switch Q2 is configured to conduct or turn off according to the second driving signal, and the first switch Q3 is configured to conduct or turn off according to the second inverted driving signal, so that the current output power of the three-phase inverter 2 is less than or equal to the rated output power. Wherein, when the first driving signal or the second driving signal is at a high level, the first inverted driving signal or the second inverted driving signal is at a low level, or when the first driving signal or the second driving signal is at a low level, the first inverted driving signal or the second inverted driving signal is at a high level. And, the first driving signal, the first inverted driving signal, the second driving signal, and the second inverted driving signal can form the driving signal of the first phase bridge arm 20.

[0076] It should be understood that when the voltage signal U i The corresponding voltage value is greater than the first voltage threshold, the current output power of the three-phase inverter 2 is equal to the rated output power, and the three-phase inverter 2 is in the full-load condition. When the voltage signal U i The corresponding voltage value is less than the first voltage threshold, the current output power of the three-phase inverter 2 is less than the rated output power, and the three-phase inverter 2 is in the light-load condition. Optionally, when the voltage signal U i The corresponding voltage value is greater than the second voltage threshold, the current output power of the three-phase inverter 2 is equal to the rated output power, and the three-phase inverter 2 is in the full-load condition. When the voltage signal U i The corresponding voltage value is greater than the third voltage threshold and less than the second voltage threshold, the current output power of the three-phase inverter 2 is less than the rated output power, and the three-phase inverter 2 is in the light-load condition. When the voltage signal U i The corresponding voltage value is less than the third voltage threshold, the current output power of the three-phase inverter 2 is less than the rated output power, and the three-phase inverter 2 is in the no-load condition.

[0077] Implementing the embodiments of the present application can output different driving signals to the upper-bridge-arm switch H1 and the lower-bridge-arm switch H2, such as Si IGBT&SiC MOS hybrid devices, based on the voltage signal U i at both ends of the first phase bridge arm 20 collected in real time, so that the three-phase inverter 2 can adapt to different conditions such as full-load condition, light-load condition, and no-load condition, thereby improving the control flexibility of the driving signal, and the application scenarios applicable to the three-phase inverter 2 are more diverse.

[0078] See Figure 5 , Figure 5 which is another schematic structural diagram of the drive signal output circuit provided by the embodiment of the present application. As Figure 4 shown, each modulation wave output circuit in the above Figure 3 shown first modulation wave output circuit 2300 and second modulation wave output circuit 2301 includes an amplitude adjustment circuit and a modulation wave generation circuit. Among them, the input end of the amplitude adjustment circuit is connected to the input end of each modulation wave output circuit, the output end of the amplitude adjustment circuit is connected to the input end of the modulation wave generation circuit, and the output end of the modulation wave generation circuit is connected to the output end of each modulation wave output circuit. It should be understood that the amplitude adjustment circuit is a circuit for adjusting the voltage amplitude of the voltage signal U i across the two ends of the first phase bridge arm 20, that is, a circuit for adjusting the voltage amplitude of the modulation wave.

[0079] When each modulation wave output circuit is working, the amplitude adjustment circuit is used to adjust the voltage amplitude of the voltage signal U i across the two ends of the first phase bridge arm 20 and output a target voltage signal to the modulation wave generation circuit. Further, the modulation wave generation circuit is used to generate a modulation wave based on the target voltage signal. Among them, when the voltage amplitude of the target voltage signal is the first voltage amplitude, the modulation wave is the first modulation wave. When the voltage amplitude of the target voltage signal is the second voltage amplitude, the modulation wave is the second modulation wave.

[0080] Implementing the embodiment of the present application, since the voltage amplitude of the carrier Z remains unchanged, it can be obtained that the size of the voltage amplitude of the modulation wave determines the pulse width (i.e., the high-level signal width) of the drive signal of the first phase bridge arm 20. Therefore, based on the voltage signal U i across the two ends of the first phase bridge arm 20 collected in real time to dynamically adjust the voltage amplitude of the modulation wave, the pulse width of the drive signal of the first phase bridge arm 20 can be further adjusted, thereby improving the control flexibility of the drive signal of the first phase bridge arm 20.

[0081] In some feasible implementation manners, the first modulation wave output circuit 2300 includes an amplitude adjustment circuit 23001 and a modulation wave generation circuit 23002. Among them, the input end in 61 of the amplitude adjustment circuit 23001 is connected to the input end in 6 of the first modulation wave output circuit 2300, the output end out 61 of the amplitude adjustment circuit 23001 is connected to the input end in 62 of the modulation wave generation circuit 23002, and the output end out 62 of the modulation wave generation circuit 23002 is connected to the output end out 6。The amplitude adjustment circuit 23001 is used to adjust the voltage amplitude of the voltage signal U across the first phase leg 20 and output a target voltage signal U to the modulation wave generation circuit 23002 i 。 o1 。The modulation wave generation circuit 23002 is used to generate a first modulation wave M based on the target voltage signal U o1 。 1 。At this time, the first modulation wave output circuit 2300 is in an operating state and outputs the first modulation wave M with the first voltage amplitude to the drive signal generation circuit 2302 1 。

[0082] In some feasible embodiments, the second modulation wave output circuit 2301 includes an amplitude adjustment circuit 23011 and a modulation wave generation circuit 23012. Among them, the input end in of the amplitude adjustment circuit 23011 71 is connected to the input end in of the second modulation wave output circuit 2301 7 , and the output end out of the amplitude adjustment circuit 23011 71 is connected to the input end in of the modulation wave generation circuit 23012 72 , and the output end out of the modulation wave generation circuit 23012 72 is connected to the output end out of the second modulation wave output circuit 2301 7 。The amplitude adjustment circuit 23011 is used to adjust the voltage amplitude of the voltage signal U across the first phase leg 20 and output a target voltage signal U to the modulation wave generation circuit 23002 i 。 o2 。The modulation wave generation circuit 23012 is used to generate a first modulation wave M based on the target voltage signal U o2 。 2 。At this time, the second modulation wave output circuit 2301 is in an operating state and outputs the first modulation wave M with the first voltage amplitude to the drive signal generation circuit 2302 2 。

[0083] Refer to Figure 6A , Figure 6A is a circuit schematic diagram of the amplitude adjustment circuit provided by the embodiment of the present application. As Figure 6A shown, the above-mentioned Figure 5 shown amplitude adjustment circuit 23001 includes a voltage amplifier 230011. Among them, the input end of the voltage amplifier 230011 is connected to the input end in of the amplitude adjustment circuit 23001 61 , and the output end of the voltage amplifier 230011 is connected to the output end out of the amplitude adjustment circuit 23001 61 。The voltage amplifier 230011 is used to amplify the voltage signal U across the first phase leg 20 iamplify the voltage amplitude and output a target voltage signal U to the modulation wave generation circuit 23002 o1 , where the target voltage signal U o1 has an amplified voltage amplitude, and the voltage amplitude of the target voltage signal U o1 is specifically determined by the component parameters inside the voltage amplifier 230011, which is not limited here. Implementing the embodiments of the present application, the voltage signal U at both ends of the first phase bridge arm 20 can be dynamically adjusted by adjusting the component parameters inside the voltage amplifier 230011 i , and the adjustment method is more flexible.

[0084] Exemplarily, the voltage amplifier 230011 is composed of a resistor R a resistor R b , resistor R set1 , and an operational amplifier CF1. Among them, one end of the resistor R a is used as the input end of the voltage amplifier 230011, the other end of the resistor R a is connected to one end of the resistor R set1 and the inverting input end of the operational amplifier CF1. The non-inverting input end of the operational amplifier CF1 is grounded through the resistor R b , and the other end of the resistor R set1 is connected to the output end of the operational amplifier CF1 and used as the output end of the voltage amplifier 230011. The voltage amplitude of the above-mentioned target voltage signal U o1 is determined according to the following formula (1).

[0085]

[0086] wherein, the specific resistance values of R a and R set1 are the component parameters inside the voltage amplifier 230011, and are values determined according to the preset pulse widths and preset switch delay times of the first switch Q1 and the second switch Q2.

[0087] See Figure 6B , Figure 6B is another circuit schematic diagram of the amplitude adjustment circuit provided by the embodiments of the present application. As Figure 6B shown, the above-mentioned Figure 5 shown amplitude adjustment circuit 23001 includes a first adder 230012 and a voltage amplifier 230013. Among them, the first adder 230012 is arranged between the input end of the voltage amplifier 230013 and the input end in 61 of the amplitude adjustment circuit 23001. The first adder 230012 is used to adjust the voltage signal U at both ends of the first phase bridge arm 20 iThe voltage amplitude is output to the voltage amplifier 230013 as an adjusted voltage signal. Further, the voltage amplifier 230013 is configured to amplify the voltage amplitude of the adjusted voltage signal and output a target voltage signal U to the modulation wave generation circuit 23002 o1 . Among them, the voltage amplitude of the target voltage signal U o1 is specifically determined by the component parameters inside the first adder 230012 and the voltage amplifier 230013, which is not limited here. Implementing the embodiments of the present application, the voltage amplitude of the voltage signal U at both ends of the first phase bridge arm 20 can be dynamically adjusted by adjusting the component parameters inside the first adder 230012 and the voltage amplifier 230013 i , and the adjustment range of the voltage amplitude is larger.

[0088] Exemplarily, the first adder 230012 consists of a pull-up resistor R c and resistors R d to resistor R f . Among them, one ends of the resistors R d to resistor R f are connected in parallel and then connected to the input end in of the amplitude adjustment circuit 23001 11 , and the other ends of the resistors R d to resistor R f are connected to the input end of the voltage amplifier 230013 with one end of the pull-up resistor R c , and the other end of the pull-up resistor R c is used to connect to the power supply VCC1. The voltage amplifier 230013 consists of a resistor R g , a resistor R set2 and an operational amplifier CF2. Among them, one end of the resistor R set2 is connected to the inverting input end of the operational amplifier CF2 and used as the input end of the voltage amplifier 230013. The non-inverting input end of the operational amplifier CF2 is grounded through a resistor R g , and the other end of the resistor R set2 is connected to the output end of the operational amplifier CF2 and used as the output end of the voltage amplifier 230013. The voltage amplitude of the above target voltage signal U o1 is determined according to the following formula (2).

[0089]

[0090] Among them, is used to represent the voltage amplitude of the adjusted voltage signal. R c , R d to R f are the component parameters inside the amplitude adjustment circuit 23001, and R c , R d to Rf The specific resistance value is a value determined according to the preset pulse widths of the first switch Q1 and the second switch Q2 and the preset switch delay time.

[0091] See Figure 7 , Figure 7 which is a schematic circuit diagram of the modulation wave generation circuit provided by an embodiment of the present application. As Figure 7 shown, the modulation wave generation circuit 23002 shown above Figure 5 includes a first signal generator 230021, a second signal generator 230022, a second adder 230023, and an absolute value circuit 230024. Among them, the input end of the first signal generator 230021 is connected to the input end in of the modulation wave generation circuit 23002 62 , the output end of the first signal generator 230021 is connected to the first input end of the second adder 230023, the output end of the second signal generator 230022 is connected to the second input end of the second adder 230023, the output end of the second adder 230023 is connected to the input end of the absolute value circuit 230024, and the output end of the absolute value circuit 230024 is connected to the output end out of the modulation wave generation circuit 23002 62 .

[0092] When the modulation wave generation circuit 23002 is operating, the first signal generator 230021 is used to output a first waveform signal to the second adder 230023 based on the target voltage signal U o1 . The second signal generator 230022 is used to output a second waveform signal to the second adder 230023 based on the target voltage signal U o1 , where the third harmonic frequency f 3 of the second waveform signal is three times the fundamental frequency f 1 of the first waveform signal, that is, f 3 = 3f 1 . The present application does not limit the specific waveforms of the first waveform signal and the second waveform signal. Exemplarily, the first waveform signal and the second waveform signal can be sine wave signals. Among them, the maximum voltage amplitude (which can be expressed as U o1 ) of the first waveform signal and the maximum voltage amplitude (which can be expressed as U s1 ) of the second waveform signal satisfy a certain relationship. Exemplarily, when U s1 = U o1 *2 / π, the DC voltage utilization rate of the modulation wave generation circuit 23002 is the highest. The above is only an example for illustration, and the embodiments of the present application do not specifically limit the certain relationship satisfied by the maximum voltage amplitude U o1 of the first waveform signal and the maximum voltage amplitude U s1 of the second waveform signal.

[0093] Further, the second adder 230023 is configured to superimpose a second waveform signal on the first waveform signal and output a superimposed waveform signal U1 to the absolute value circuit 230024. The specific waveform of the superimposed waveform signal U1 is not limited in this application. Exemplarily, the superimposed waveform signal U1 may be the saddle wave in Figure 7 , and this saddle wave is a saddle-shaped wave formed by superimposing a second waveform signal with a triple fundamental wave frequency f 1 (i.e., the third harmonic frequency f 3 ) on the first waveform signal. When the maximum voltage amplitude U o1 of the first waveform signal is closer to the maximum voltage amplitude U s1 of the second waveform signal, the depression degree of the saddle wave is greater. When the difference between the maximum voltage amplitude U o1 of the first waveform signal and the maximum voltage amplitude U s1 of the second waveform signal is greater, the depression degree of the saddle wave is smaller. Among them, the maximum voltage amplitude of the superimposed waveform signal U1 in the positive half cycle is U s , and the minimum voltage amplitude of the superimposed waveform signal U1 in the negative half cycle is -U s . Exemplarily, when U s1 = U o1 * 2 / π, the maximum voltage amplitude U s of the superimposed waveform signal U1 in the positive half cycle is the same as the maximum voltage amplitude U o1 of the first waveform signal.

[0094] Further, the absolute value circuit 230024 is configured to generate a first modulation wave M 1 based on the superimposed waveform signal U1. Exemplarily, the saddle wave of the negative voltage in the superimposed waveform signal U1 is flipped to the positive voltage range to generate the first modulation wave M Figure 7 in 1 . It should be understood that since the first modulation wave M 1 is a saddle-shaped modulation wave, when the maximum voltage amplitude of the first modulation wave M 1 is less than the maximum voltage amplitude of the carrier Z, that is, when the first modulation wave M 1 is not over-modulated, the fundamental wave amplitude of the output voltage of the three-phase inverter 2 can be effectively increased, and the first modulation wave M 1 is more suitable for the three-phase inverter 2 with the cancellation of the third harmonics.

[0095] Implementing the embodiments of this application can generate a first modulation wave M 1 with a positive voltage through the first signal generator 230021, the second signal generator 230022, the second adder 230023, and the absolute value circuit 230024, which is more convenient for comparison with the carrier Z and the driving method is simpler.

[0096] Exemplarily, when the first signal generator 230021 is a sine wave generator, the first signal generator 230021 includes resistors R1 to R4, capacitors C1 and C2, and operational amplifier CF3. One end of resistor R1, one end of resistor R2, and one end of capacitor C1 are grounded. The other end of resistor R1 and one end of resistor R3 are connected to the inverting input terminal of operational amplifier CF3. The other end of resistor R2, the other end of capacitor C1, and one end of capacitor C2 are connected to the non-inverting input terminal of operational amplifier CF3. The positive power supply terminal of operational amplifier CF3 serves as the input terminal of the first signal generator 230021 to access the target voltage signal U o1 , and the positive power supply terminal of operational amplifier CF3 serves as the input terminal of the first signal generator 230021 to access the voltage signal -U o1 . One end of capacitor C2 is connected to the output terminal of operational amplifier CF3 through resistor R4. One end of resistor R3 and the output terminal of operational amplifier CF3 are connected and serve as the output terminal of the first signal generator 230021 to output the first waveform signal. Among them, the fundamental frequency f 1 of the first waveform signal = 1 / 2ΠRC, where R is the resistance value of resistor R2 and resistor R4, and C is the capacitance value of capacitor C1 and capacitor C2. In addition, R and C are the internal component parameters of the first signal generator 230021, and the specific values of R and C can be values adjusted according to the preset pulse width and preset switch delay time of the first switch Q1 and the second switch Q2. When the second signal generator 230022 is a sine wave generator, the second signal generator 230022 includes resistors R5 to R8, capacitors C3 and C4, and operational amplifier CF4. The specific connection relationship between the components can be specifically referred to the description of the connection relationship between the internal components of the first signal generator 230021 above, and will not be elaborated here. Among them, the third harmonic frequency f 3 of the second waveform signal output by operational amplifier CF4 = 1 / 2ΠR s1 C s1 , where R s1 is the resistance value of resistor R6 and resistor R8, and C s1 is the capacitance value of capacitor C3 and capacitor C4. In addition, R s1 and C s1 are the internal component parameters of the first signal generator 230021, and the specific values of R s1 and C s1 can be values adjusted according to the preset pulse width and preset switch delay time of the first switch Q1 and the second switch Q2.

[0097] Exemplarily, the second adder 230023 includes a resistor R9, a resistor R10, a resistor R11, and an operational amplifier CF5. One end of the resistor R9 serves as the first input terminal of the second adder 230023 to receive the first waveform signal, and one end of the resistor R10 serves as the second input terminal of the second adder 230023 to receive the second waveform signal. The other ends of the resistor R9 and the resistor R10 are connected to the non-inverting input terminal of the operational amplifier CF5, one end of the resistor R11 is connected to the inverting input terminal of the operational amplifier CF5, and the other end of the resistor R11 and the output terminal of the operational amplifier CF5 are connected and then serve as the output terminal of the second adder 230023 to output the saddle wave U1.

[0098] Exemplarily, the absolute value circuit 230024 includes operational amplifiers CF6 and CF7, resistors R12 to R15, and diodes D1 and D2. The non-inverting input terminal of the operational amplifier CF6 serves as the input terminal of the absolute value circuit 230024 to receive the saddle wave signal U1. The inverting input terminal of the operational amplifier CF6 is connected to one end of the resistor R12, one end of the resistor R13, and the positive electrode of the diode D1. The other end of the resistor R13 is connected to one end of the resistor R14 and the positive electrode of the diode D2. The negative electrodes of the diode D1 and the diode D2 are connected to the output terminal of the operational amplifier CF6. The non-inverting input terminal of the operational amplifier CF7 is connected to the non-inverting input terminal of the operational amplifier CF6. The inverting input terminal of the operational amplifier CF7 is connected to the other end of the resistor R14 and one end of the resistor R15. The other end of the resistor R15 is connected to the output terminal of the operational amplifier CF7 and then serves as the output terminal of the absolute value circuit 230024 to output the first modulation wave M to the drive signal generation circuit 2302. 1 。

[0099] It should be understood that for the circuit structures of the amplitude adjustment circuit 23011 and the modulation wave generation circuit 23012 and the working principle of generating the second modulation wave M 2 reference can be made to Figures 6A to 7 and its corresponding embodiments, which will not be elaborated here. It should be noted that Figures 6A to 7 the circuit structures shown are only for illustrative purposes, and the present application does not limit the circuit structures of the amplitude adjustment circuit 23001 and the modulation wave generation circuit 23002.

[0100] In some feasible embodiments, as Figure 5 shown, the above-mentioned Figure 4 shown drive signal output circuit 230 further includes a carrier output circuit 2303. The output terminal out 83 of this carrier output circuit 2303 is connected to the third input terminal in 83Among them, the carrier output circuit 2303 is used to output the carrier Z to the drive signal generation circuit 2302. Implementing the embodiments of the present application, the carrier output circuit 2303 (i.e., the analog circuit) can be used to output the carrier Z for comparison with the modulation wave, without relying on an external digital driver to output the carrier Z, thereby reducing the volume and cost of the drive circuit 23.

[0101] In some feasible implementation manners, the circuit structure of the carrier output circuit 2303 is as Figure 8 shown. The carrier output circuit 2303 includes a third signal generator 23031 and a level shift circuit 23032. Among them, the output end of the third signal generator 23031 is connected to the input end of the level shift circuit 23032, and the output end of the level shift circuit 23032 is connected to the output end out of the carrier output circuit 2303. 83 The above-mentioned third signal generator 23031 is used to output a third waveform signal U2 to the level shift circuit 23032. The present application does not limit the specific waveform of the third waveform signal U2. Exemplarily, the third waveform signal U2 is a sawtooth wave signal or a triangular wave signal as Figure 8 shown. Further, the level shift circuit 23032 is used to generate the carrier Z based on the third waveform signal U2. Exemplarily, the triangular wave of the negative voltage in the third waveform signal U2 is shifted to the positive voltage range to output the carrier Z with a positive voltage to the drive signal generation circuit 2302. Among them, the voltage amplitude of the carrier Z remains unchanged.

[0102] Implementing the embodiments of the present application, the carrier Z with a positive voltage can be generated by the third signal generator 23031 and the level shift circuit 23032, which is more convenient for comparison with the modulation wave and the driving method is simpler.

[0103] Exemplarily, the third signal generator 23031 includes operational amplifiers CF8 and CF9, resistors R16 to R20, a bidirectional voltage regulator D3, and a capacitor C5. Among them, the inverting input terminal of the operational amplifier CF8 is grounded, the non-inverting input terminal of the operational amplifier CF8 is connected to the output terminal of the operational amplifier CF9 through the resistor R16, the non-inverting input terminal of the operational amplifier CF8 is connected to one end of the bidirectional voltage regulator D3 through the resistor R17, the other end of the bidirectional voltage regulator D3 is grounded, the output terminal of the operational amplifier CF8 is connected to one end of the capacitor C5 and the inverting input terminal of the operational amplifier CF9 through the series-connected resistors R18 and R19, and the series connection point of the resistors R18 and R19 is connected to one end of the bidirectional voltage regulator D3. The non-inverting input terminal of the operational amplifier CF9 is grounded through the resistor R20, and the output terminal of the operational amplifier CF9 and the other end of the capacitor C5 are connected and used as the output terminal of the third signal generator 23031 to output the triangular wave signal U2.

[0104] Exemplarily, the level shift circuit 23032 includes resistors R21 to R24, a zener diode D4, and an operational amplifier CF10. Among them, the inverting input terminal of the operational amplifier CF10 is grounded through the resistor R21. One end of the resistor R22 serves as the input terminal of the level shift circuit 23032. The other end of the resistor R22 and one end of the resistor R23 are connected to the non-inverting input terminal of the operational amplifier CF10. The other end of the resistor R23 is grounded through the zener diode D4. One end of the resistor R24 is connected to the inverting input terminal of the operational amplifier CF10. The other end of the resistor R24 is connected to the output terminal of the operational amplifier CF10 and serves as the output terminal of the level shift circuit 23032 to output the carrier wave Z. It should be understood that in Figure 8 one end of the bidirectional zener diode D3 is connected to +Uz, and the other end of the bidirectional zener diode D3 is connected to -Uz, so that the maximum voltage amplitude of the triangular wave signal U2 output by the third signal generator 23031 is +Uz in the positive half cycle, and the maximum voltage amplitude of the triangular wave signal U2 in the positive half cycle is -Uz. The zener diode D4 is connected to +Uz, so that the maximum voltage amplitude of the carrier wave Z output by the level shift circuit 23032 is 2Uz. The frequency f of the carrier wave Z c = 1 / 4R c C c , where R c is the resistance value of the resistor R12, and C c is the capacitance value of the capacitor C3. Among them, Uz, R c and C c are the component parameters inside the carrier output circuit 2303, and the specific value of Uz is a value determined according to the preset pulse width and preset switch delay time of the first switch Q1 and the second switch Q2.

[0105] It should be noted that Figure 8 the circuit structure shown is only for illustrative purposes, and the present application does not limit the circuit structures of the third signal generator 23031 and the level shift circuit 23032.

[0106] Refer to Figure 9 , Figure 9 which is the circuit schematic diagram of the drive signal generation circuit provided by the embodiment of the present application. As Figure 9 shown, the drive signal generation circuit 2302 shown above Figure 5 includes a first comparator 23021. Among them, the first input terminal of the first comparator 23021 is connected to the first input terminal in of the drive signal generation circuit 2302 81 to receive the first modulation wave M 1 , and the second input terminal of the first comparator 23021 is connected to the third input terminal in of the drive signal generation circuit 2302 83With the received carrier Z, the output terminal of the first comparator 23021 is connected to the first output terminal out of the drive signal generation circuit 2302 81 . The above-mentioned first comparator 23021 is used to output the first drive signal as the first level when the first voltage amplitude of the first modulation wave M 1 is greater than the voltage amplitude of the carrier Z, and output the first drive signal as the second level when the first voltage amplitude of the first modulation wave M 1 is less than the voltage amplitude of the carrier Z. Among them, when the first level is low level, the second level is high level, or when the first level is high level, the second level is low level. Taking the case where the first level is high level and the second level is low level as an example, the first switch Q1 is used to conduct when the first drive signal is high level and turn off when the first drive signal is low level. Implementing the embodiments of the present application, different pulse widths of the first drive signal are output in real time according to the voltage amplitude of the carrier Z and the dynamically adjusted first voltage amplitude, thereby improving the control flexibility of the first switch Q1 and adapting to different working conditions of the three-phase inverter 2

[0107] Exemplarily, the first comparator 23021 includes a resistor R25 to a resistor R27 and an operational amplifier CF11. Among them, one end of the resistor R26 serves as the first input terminal of the first comparator 23021 to receive the first modulation wave M 1 , the other end of the resistor R26 is connected to the non-inverting input terminal of the operational amplifier CF11, one end of the resistor R25 serves as the second input terminal of the first comparator 23021 to receive the carrier Z, and the other end of the resistor R25 is connected to the inverting input terminal of the operational amplifier CF11. The positive power supply terminal of the operational amplifier CF11 and one end of the resistor R27 are connected to the power supply VCC2, and the negative power supply terminal of the operational amplifier CF11 is grounded. The other end of the resistor R27 and the output terminal of the operational amplifier CF11 are connected and used as the output terminal of the first comparator 23021 to output the first drive signal

[0108] In some feasible implementation manners, the above-mentioned drive signal generation circuit 2302 further includes a second comparator 23022. Among them, the first input terminal of the second comparator 23022 is connected to the second input terminal in of the drive signal generation circuit 2302 82 to receive the second modulation wave M 2 , the second input terminal of the second comparator 23022 is connected to the third input terminal in of the drive signal generation circuit 2302 83 to receive the carrier Z, and the output terminal of the second comparator 23022 is connected to the second output terminal out of the drive signal generation circuit 2302 82 . The above-mentioned second comparator 23022 is used to output the second drive signal as the first level when the second modulation wave M 2When the second voltage amplitude of is greater than the voltage amplitude of carrier Z, the second driving signal is output as the first level, and in the second modulation wave M 2 When the second voltage amplitude of is less than the voltage amplitude of carrier Z, the second driving signal is output as the second level. Wherein, when the first level is low level, the second level is high level, or when the first level is high level, the second level is low level. Taking the case where the first level is high level and the second level is low level as an example for illustration, the second switch Q2 is used to conduct when the second driving signal is high level and turn off when the second driving signal is low level. Implementing the embodiments of the present application, different pulse-width second driving signals are output in real time according to the voltage amplitude of carrier Z and the dynamically adjusted second voltage amplitude, thereby improving the control flexibility of the second switch Q2 and adapting to different working conditions of the three-phase inverter 2.

[0109] Exemplarily, the second comparator 23022 includes a resistor R28, a resistor R29, a resistor R30, and an operational amplifier CF12. Among them, the circuit connection relationship between the resistor R28, the resistor R29, the resistor R30, and the operational amplifier CF12 can refer to the description of the internal circuit structure of the first comparator 23021 above, and will not be elaborated here.

[0110] In some feasible implementation manners, taking the case where the first level is high level and the second level is low level as an example for illustration, the driving signal of the first phase leg 20 can be as Figure 10 shown, the voltage amplitude of carrier Z can be expressed as u Z , the first voltage amplitude of the first modulation wave M 1 can be expressed as u M1 =U o1 *sin(wt), and the second voltage amplitude of the second modulation wave M 2 can be expressed as u M2 =U o2 *sin(wt). And, the amplitude of the first voltage amplitude u M1 at time t1 is less than the amplitude of the second voltage amplitude u M2 at time t1. When the first voltage amplitude u M1 is greater than the voltage amplitude u Z , the first driving signal PWM_11 is high level to control the first switch Q1 to conduct, and the first inverted driving signal PWM_12 is low level to control the second switch Q4 to turn off. Among them, the pulse width δIGBT of the first driving signal PWM_11 is the preset pulse width of the first switch Q1. When the first voltage amplitude u M1 is less than the voltage amplitude u Z , the first driving signal PWM_11 is low level to control the first switch Q1 to turn off, and the first inverted driving signal PWM_12 is high level to control the second switch Q4 to conduct. When the second voltage amplitude uM2 Greater than the voltage amplitude u Z When it is, the second driving signal PWM_21 is at a high level to control the conduction of the second switch Q2, and the second inverted driving signal PWM_22 is at a low level to control the turn-off of the first switch Q3. Among them, the pulse width δMOS of the second driving signal PWM_21 is the preset pulse width of the second switch Q2. When the second voltage amplitude u M2 Less than the voltage amplitude u Z When it is, the second driving signal PWM_21 is at a low level to control the turn-off of the second switch Q2, and the second inverted driving signal PWM_22 is at a high level to control the conduction of the first switch Q3.

[0111] Implementing the embodiments of the present application, when dynamically adjusting the magnitudes of the first voltage amplitude u M1 and the second voltage amplitude u M2 , driving signals of the first phase leg 20 with different pulse widths can be obtained, so as to control complementary conduction of Si IGBT&SiC MOS hybrid devices such as the upper arm switch H1 and the lower arm switch H2 to adapt to different working conditions of the three-phase inverter 2. Among them, the different working conditions can be one of a light load condition, an idle load condition, and a full load condition.

[0112] In some feasible implementation manners, when the three-phase inverter 2 is in a full load condition (i.e., driving mode 1), the voltage V GE between the gate and the emitter of the first switch Q1 and the voltage V GS between the gate and the source of the second switch Q2 are as shown in Figure 11A . The switching delay time t_delay1 between the first switch Q1 and the second switch Q2 is the preset switching delay time. When the three-phase inverter 2 is in a light load condition (i.e., driving mode 2), the voltage V GE between the gate and the emitter of the first switch Q1 and the voltage V GS between the gate and the source of the second switch Q2 are as shown in Figure 11B . The switching delay times t_delay2 and t_delay3 between the first switch Q1 and the second switch Q2 are both the preset switching delay times. Implementing the embodiments of the present application, the switching delay time between the first switch Q1 and the second switch Q2 can be adjusted according to the preset switching delay time, so as to output the driving signals of the first phase leg 20 required for different driving modes to adapt to different working conditions of the three-phase inverter 2.

[0113] See Figure 12 , Figure 12 is a connection schematic diagram between the driving signal output circuit, the first phase delay circuit, and the second phase leg provided by the embodiments of the present application. As shown in Figure 12 , the above Figure 3The first phase delay circuit 231 shown includes a first phase shifter 2311 and a second phase shifter 2312. The input terminal in of the first phase delay circuit 231 3 includes the input terminal in 31 and a second input terminal in 32 . The first output terminal out of the first phase delay circuit 231 31 includes the output terminal out 311 and the output terminal out 312 . The second output terminal out of the first phase delay circuit 231 32 includes the output terminal out 321 and the output terminal out 322 . Among them, the input terminal of the first phase shifter 2311 serves as the input terminal in of the first phase delay circuit 231 31 and is connected to the first output terminal out of the drive signal generation circuit 2302 81 (i.e., the output terminal out of the drive signal output circuit 230 211 ). The output terminal of the first phase shifter 2311 serves as the output terminal out of the first phase delay circuit 231 311 and is connected to the first switch Q5. The input terminal of the second phase shifter 2312 serves as the input terminal in of the first phase delay circuit 231 32 and is connected to the second output terminal out of the drive signal generation circuit 2302 82 (i.e., the output terminal out of the drive signal output circuit 230 212 ). The output terminal of the second phase shifter 2312 serves as the output terminal out of the first phase delay circuit 231 312 and is connected to the second switch Q6. The output terminal of the first phase shifter 2311 is connected to the second switch Q8 through the third inverter N3, that is, the end of the third inverter N3 far from the output terminal of the first phase shifter 2311 serves as the output terminal out of the first phase delay circuit 231 321 and is connected to the second switch Q8. The output terminal of the second phase shifter 2312 is connected to the first switch Q7 through the fourth inverter N4, that is, the end of the fourth inverter N4 far from the output terminal of the second phase shifter 2312 serves as the output terminal out of the first phase delay circuit 231 322 and is connected to the first switch Q7.

[0114] When the first phase delay circuit 231 is operating, the first phase shifter 2311 is configured to delay the phase of the first driving signal PWM_11 by a first angle and output a third driving signal PWM_31 to the first switch Q5, and output a third inverted driving signal PWM_33 to the second switch Q8 through the third inverter N3. The second phase shifter 2312 is configured to delay the phase of the second driving signal PWM_21 by the first angle and output a fourth driving signal PWM_32 to the second switch Q6, and output a fourth inverted driving signal PWM_34 to the first switch Q7 through the fourth inverter N4. At this time, the phase angle by which the second phase bridge arm 21 lags behind the first phase bridge arm 20 is the first angle, that is, the second phase bridge arm 21 conducts with a lag of the first angle behind the first phase bridge arm 20. Among them, the third driving signal PWM_31, the fourth driving signal PWM_32, the third inverted driving signal PWM_33, and the fourth inverted driving signal PWM_34 can form the driving signals of the second phase bridge arm 21. When any one of the driving signals is at a high level, the switch corresponding to the any one driving signal conducts, and when any one driving signal is at a low level, the switch corresponding to the any one driving signal turns off.

[0115] Implementing the embodiments of the present application, since the third driving signal PWM_31 and the fourth driving signal PWM_32 are respectively the driving signals after the phase delay of the first driving signal PWM_11 and the second driving signal PWM_21, and the third inverted driving signal PWM_33 and the fourth inverted driving signal PWM_34 are respectively the driving signals after the inversion of the third driving signal PWM_31 and the fourth driving signal PWM_32, when the first driving signal PWM_11 and the second driving signal PWM_21 are different, the third driving signal PWM_31, the fourth driving signal PWM_32, the third inverted driving signal PWM_33, and the fourth inverted driving signal PWM_34 will also change accordingly, thereby improving the control flexibility of the driving signals. In addition, the first phase shifter 2311, the second phase shifter 2312, the third inverter N3, and the fourth inverter N4 are all analog circuits with smaller volumes, which can reduce the volume and cost of the entire driving circuit 23.

[0116] In some feasible implementation manners, a circuit topology of the first phase shifter 2311 can be as Figure 13As shown in the figure, the first phase shifter 2311 includes a resistor R31, a resistor R32, a resistor R33, a capacitor C6, and an operational amplifier CF13. One end of the resistor R31 serves as the input end of the first phase shifter 2311 and is used to receive the first driving signal PWM_11. The other end of the resistor R31 is connected to the inverting input end of the operational amplifier CF13 and one end of the capacitor C6. The non-inverting input end of the operational amplifier CF13 is grounded through the resistor R32, and the other end of the capacitor C6 is connected to the output end of the operational amplifier CF13 through the resistor R33. The output end of the operational amplifier CF13 serves as the output end of the first phase shifter 2311 and is used to output the third driving signal PWM_31. It should be understood that the specific value of the first angle delayed by the first phase shifter 2311 can be adjusted by adjusting the component parameters inside the first phase shifter 2311. Exemplarily, the component parameters inside the first phase shifter 2311 include parameters such as the resistance value of the resistor R31, the resistance value of the resistor R33, and the capacitance value of the capacitor C6, and the first angle can be 120°.

[0117] It should be understood that the circuit topology of the second phase shifter 2312 can be the same as or different from the circuit topology of the first phase shifter 2311. It should be noted that Figure 13 The circuit topology of the first phase shifter 2311 shown in the figure is only an example, and the present application does not limit the specific circuit topology of the first phase shifter 2311.

[0118] In some feasible embodiments, the third inverter N3 and the fourth inverter N4 can be arranged inside the first phase delay circuit 231. Optionally, they can also be arranged outside the first phase delay circuit 231, which is not limited here.

[0119] See Figure 14A , Figure 14A is a schematic connection diagram between the first phase delay circuit, the second phase delay circuit, and the third phase bridge arm provided by the embodiment of the present application. Taking the first output end out of the first phase delay circuit 231 31 connected to the input end in of the second phase delay circuit 232 4 as an example for illustration, as Figure 14A shown, the second phase delay circuit 232 shown above Figure 3 includes a third phase shifter 2321a and a fourth phase shifter 2322a. The input end in of the second phase delay circuit 232 4 includes an input end in 41 and an input end in 42 , and the first output end out of the second phase delay circuit 232 41 includes an output end out 411 and an output end out 412, the second output terminal out of the second phase delay circuit 232 42 includes the output terminal out 421 and the output terminal out 422 . Among them, the input terminal of the third phase shifter 2321a serves as the input terminal in of the second phase delay circuit 232 41 , and is connected to the output terminal of the first phase shifter 2311. The output terminal of the third phase shifter 2321a serves as the output terminal out of the second phase delay circuit 232 411 , and is connected to the first switch Q9. The input terminal of the fourth phase shifter 2322a serves as the input terminal in of the second phase delay circuit 232 42 , and is connected to the output terminal of the second phase shifter 2312. The output terminal of the fourth phase shifter 2322a serves as the output terminal out of the second phase delay circuit 232 412 , and is connected to the second switch Q10. The output terminal of the third phase shifter 2321a is connected to the second switch Q12 through the fifth inverter N5a, that is, one end of the fifth inverter N5a far from the output terminal of the third phase shifter 2321a serves as the output terminal out of the second phase delay circuit 232 421 , and is connected to the second switch Q12. The output terminal of the fourth phase shifter 2322a is connected to the first switch Q11 through the sixth inverter N6a, that is, one end of the sixth inverter N6a far from the output terminal of the fourth phase shifter 2322a serves as the output terminal out of the second phase delay circuit 232 422 , and is connected to the first switch Q11.

[0120] When the second phase delay circuit 232 is working, the third phase shifter 2321a is used to delay the phase of the third driving signal PWM_31 by a first angle and output a fifth driving signal PWM_41 to the first switch Q9, and output a fifth inverted driving signal PWM_43 to the second switch Q12 through the fifth inverter N5a. The fourth phase shifter 2322a is used to delay the phase of the fourth driving signal PWM_32 by a first angle and output a sixth driving signal PWM_42 to the second switch Q10, and output a sixth inverted driving signal PWM_44 to the first switch Q11 through the sixth inverter N6a, so that the current output power of the three-phase inverter 2 is less than or equal to the rated output power. At this time, the phase angle by which the third phase leg 22 lags behind the second phase leg 21 is the first angle, that is, the third phase leg 22 conducts with a lag of the first angle behind the second phase leg 21. Among them, the fifth driving signal PWM_41, the sixth driving signal PWM_42, the fifth inverted driving signal PWM_43, and the sixth inverted driving signal PWM_44 can form the driving signal of the third phase leg 22. When any one of the driving signals is at a high level, the switch corresponding to the any one of the driving signals conducts, and when any one of the driving signals is at a low level, the switch corresponding to the any one of the driving signals turns off.

[0121] In the implementation of the embodiments of the present application, since the fifth driving signal PWM_41 and the sixth driving signal PWM_42 are respectively the driving signals after the phase delay of the third driving signal PWM_31 and the fourth driving signal PWM_32, and the fifth inverted driving signal PWM_43 and the sixth inverted driving signal PWM_44 are respectively the driving signals after the inversion of the fifth driving signal PWM_41 and the sixth driving signal PWM_42, when the third driving signal PWM_31 and the fourth driving signal PWM_32 are different, the fifth driving signal PWM_41, the sixth driving signal PWM_42, the fifth inverted driving signal PWM_43, and the sixth inverted driving signal PWM_44 will also change accordingly, so that the three-phase inverter 2 is in different working conditions such as full-load working condition, light-load working condition, and no-load working condition, thereby improving the control flexibility of the driving signal, and the applicable application scenarios of the three-phase inverter 2 are more diverse. In addition, the third phase shifter 2321a, the fourth phase shifter 2322a, the fifth inverter N5a, and the sixth inverter N6a are all analog circuits with smaller volumes, which can reduce the volume and cost of the entire driving circuit 23.

[0122] In some feasible implementation manners, the fifth inverter N5a and the sixth inverter N6a can be disposed inside the second phase delay circuit 232, and optionally, they can also be disposed outside the second phase delay circuit 232, which is not limited herein.

[0123] See Figure 14B , Figure 14B is a schematic connection diagram between the driving signal output circuit, the second phase delay circuit, and the third phase bridge arm provided by the embodiments of the present application. When the first output terminal out of the driving signal output circuit 230 21 is connected to the input terminal in of the second phase delay circuit 232 4 , as Figure 14B shown, the second phase delay circuit 232 shown above Figure 3 includes a third phase shifter 2321b and a fourth phase shifter 2322b. The input terminal in of the second phase delay circuit 232 4 includes an input terminal in 41 and an input terminal in 42 , the first output terminal out of the second phase delay circuit 232 41 includes an output terminal out 411 and an output terminal out 412 , the second output terminal out of the second phase delay circuit 232 42 includes an output terminal out 421 and an output terminal out 422 . Among them, the input terminal of the third phase shifter 2321b is used as the input terminal in of the second phase delay circuit 232 41and connect to the first output terminal out of the drive signal generation circuit 2302 81 (i.e., the output terminal out of the drive signal output circuit 230 211 ), the output terminal of the third phase shifter 2321b serves as the output terminal out of the second phase delay circuit 232 411 and connect to the first switch Q9. The input terminal of the fourth phase shifter 2322b serves as the input terminal in of the second phase delay circuit 232 42 and connect to the second output terminal out of the drive signal generation circuit 2302 82 (i.e., the output terminal out of the drive signal output circuit 230 212 ), the output terminal of the fourth phase shifter 2322b serves as the output terminal out of the second phase delay circuit 232 412 and connect to the second switch Q10. The output terminal of the third phase shifter 2321b is connected to the second switch Q12 through the fifth inverter N5b, that is, the end of the fifth inverter N5b far from the output terminal of the third phase shifter 2321b serves as the output terminal out of the second phase delay circuit 232 421 and connect to the second switch Q12. The output terminal of the fourth phase shifter 2322b is connected to the first switch Q11 through the sixth inverter N6b, that is, the end of the sixth inverter N6b far from the output terminal of the fourth phase shifter 2322b serves as the output terminal out of the second phase delay circuit 232 422 and connect to the first switch Q11.

[0124] When the second phase delay circuit 232 is working, the third phase shifter 2321b is used to delay the phase of the first drive signal PWM_11 by a second angle and output a fifth drive signal PWM_41 to the first switch Q9, and output a fifth inverted drive signal PWM_43 to the second switch Q12 through the fifth inverter N5b. The fourth phase shifter 2322b is used to delay the phase of the second drive signal PWM_21 by a second angle and output a sixth drive signal PWM_42 to the second switch Q10, and output a sixth inverted drive signal PWM_44 to the first switch Q11 through the sixth inverter N6b, so that the current output power of the three-phase inverter 2 is less than or equal to the rated output power. Wherein, the first angle and the second angle are opposite to each other. Exemplarily, the first angle is 120°, and the second angle is -120°. At this time, the phase angle by which the third phase leg 22 lags behind the first phase leg 20 is the second angle, that is, the third phase leg 22 conducts with a lag of the second angle behind the first phase leg 20.

[0125] Implementing the embodiments of the present application, since the fifth driving signal PWM_41 and the sixth driving signal PWM_42 are respectively the driving signals after the phase delay of the first driving signal PWM_11 and the second driving signal PWM_21, and the fifth inverted driving signal PWM_43 and the sixth inverted driving signal PWM_44 are respectively the driving signals after the inversion of the fifth driving signal PWM_41 and the sixth driving signal PWM_42, when the first driving signal PWM_11 and the second driving signal PWM_21 are different, the fifth driving signal PWM_41, the sixth driving signal PWM_42, the fifth inverted driving signal PWM_43 and the sixth inverted driving signal PWM_44 will also change accordingly, so that the three-phase inverter 2 is in different working conditions such as full-load condition, light-load condition and no-load condition, thereby improving the control flexibility of the driving signal, and the applicable application scenarios of the three-phase inverter 2 are more diverse. In addition, the third phase shifter 2321b, the fourth phase shifter 2322b, the fifth inverter N5b and the sixth inverter N6b are all analog circuits with smaller volume, which can reduce the volume and cost of the entire driving circuit 23.

[0126] In some feasible implementation manners, the circuit topology of any one of the third phase shifter 2321a, the fourth phase shifter 2322a, the third phase shifter 2321b and the fourth phase shifter 2322b may be the same as or different from the circuit topology of the first phase shifter 2311 shown above. The present application does not limit its specific circuit topology. Figure 13 The circuit topology of the first phase shifter 2311 shown above may be the same or different, and the present application does not limit its specific circuit topology.

[0127] In some feasible implementation manners, the fifth inverter N5b and the sixth inverter N6b may be disposed inside the second phase delay circuit 232. Optionally, they may also be disposed outside the second phase delay circuit 232, which is not limited herein.

[0128] It can be understood that according to the above Figures 2 to 14BAs can be obtained from the corresponding embodiments, the drive signal output circuit 230, the first phase delay circuit 231, the second phase delay circuit 232, and the current sensor 233 are all analog circuits. By adjusting the component parameters inside the analog circuit, drive signals with different pulse widths can be output to the Si IGBT&SiC MOS hybrid device in the three-phase bridge arm to adapt to different working conditions of the three-phase inverter 2, and the customization and convenience of adjusting the drive signal are ensured, with stronger applicability. In addition, the entire drive circuit 23 is an analog circuit with a smaller volume. Therefore, the drive circuit 23 can be integrated with the three-phase inverter circuit on the same circuit board, thereby realizing the integration and miniaturization of the three-phase inverter 2. It should be noted that this application does not limit the specific positions of the internal functional circuits of the drive signal output circuit 230, the first phase delay circuit 231, and the second phase delay circuit 232. Exemplarily, the carrier output circuit 2303 can also be arranged outside the drive signal output circuit 230.

[0129] In some feasible embodiments, when the three-phase inverter 2 is a three-phase full-bridge inverter, the circuit structure of the three-phase inverter 2 can be as Figure 15 shown, and the three-phase inverter 2 shown above Figure 3 also includes a capacitor C DC 、an inductor L a 、an inductor L b 、an inductor L c 、a capacitor C ab 、a capacitor C bc and a capacitor C ac . Among them, both ends of the capacitor C DC are used to connect to the DC source U DC , and filter the direct current output by the DC source U DC . The midpoint of the first-phase bridge arm 20 is connected to one end of the inductor L a , and the other end of the inductor L a , one end of the capacitor C ab and one end of the capacitor C ac are connected to the first-phase output terminal out 11 . The midpoint of the second-phase bridge arm 21 is connected to one end of the inductor L b , and the other end of the inductor L b , the other end of the capacitor C ab and one end of the capacitor C bc are connected to the second-phase output terminal out 12 . The midpoint of the third-phase bridge arm 22 is connected to one end of the inductor L c , and the other end of the inductor L c , the other end of the capacitor C bc and the other end of the capacitor C ac are connected to the third-phase output terminal out 13When the AC load 3 includes single-phase loads U ab single-phase load U bc and single-phase load U ac at this time, the first-phase output terminal out 11 and the second-phase output terminal out 12 are used to connect both ends of the single-phase load U ab The second-phase output terminal out 12 and the third-phase output terminal out 13 are used to connect both ends of the single-phase load U bc The first-phase output terminal out 11 and the third-phase output terminal out 13 are used to connect both ends of the single-phase load U ac The inductor L a inductor L b inductor L c capacitor C ab capacitor C bc and capacitor C ac constitute an output filter circuit, which is used to filter the three-phase alternating current output by the three-phase inverter circuit and supply power to the single-phase load U ab single-phase load U bc and single-phase load U ac respectively. Implementing the embodiments of the present application can meet the different working condition requirements of the AC load 3 while supplying power to the AC load 3, and has stronger applicability.

[0130] It should be noted that Figure 15 the circuit structure shown is only for illustrative purposes, and the present application does not limit the circuit structure of the three-phase inverter 2.

[0131] See Figure 16 , Figure 16 is the structural schematic diagram of the motor controller MCU provided by the embodiments of the present application. As Figure 16 shown, the MCU 4 includes an input port 40, a three-phase inverter 41, and a three-phase output port 42. At this time, the three-phase inverter 41 can also be called an in-vehicle MCU inverter. Among them, the input port 40 is used to connect the power battery 5, the input end of the three-phase inverter 41 is connected to the input port 40, the three-phase output ends of the three-phase inverter 41 are connected to the three-phase output port 42, and the three-phase output port 42 is used to connect the motor 6. Among them, the three-phase inverter 41 converts the direct current output by the power battery 5 into three-phase alternating current and drives the motor 6. Implementing the embodiments of the present application can improve the integration degree of the MCU 4 and reduce the cost and volume of the MCU 4 because the three-phase inverter 41 has a smaller volume and lower cost.

[0132] It should be noted that the above terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0133] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claimed rights.

Claims

1. A three-phase inverter, characterized in that, the input end of the three-phase inverter is used to connect to a DC source, and the three-phase output ends of the three-phase inverter are used to connect to an AC load; the three-phase inverter includes a first phase bridge arm, a second phase bridge arm, a third phase bridge arm, and a drive circuit. Among them, the first phase bridge arm, the second phase bridge arm, and the third phase bridge arm are connected in parallel and then connected to the input end of the three-phase inverter. The midpoints of the first phase bridge arm, the second phase bridge arm, and the third phase bridge arm are connected to the three-phase output ends of the three-phase inverter; each phase bridge arm includes a series-connected upper bridge arm switch and a lower bridge arm switch; the drive circuit includes a drive signal output circuit, a first phase delay circuit, and a second phase delay circuit; wherein, the first input end and the second input end of the drive signal output circuit are both used to receive the voltage signals at both ends of the first phase bridge arm. The first output end of the drive signal output circuit is connected to the upper bridge arm switch in the first phase bridge arm, and the second output end of the drive signal output circuit is connected to the lower bridge arm switch in the first phase bridge arm. The first output end of the drive signal output circuit is connected to the input end of the first phase delay circuit. The first output end of the first phase delay circuit is connected to the upper bridge arm switch in the second phase bridge arm, and the second output end of the first phase delay circuit is connected to the lower bridge arm switch in the second phase bridge arm. The first output end of the drive signal output circuit or the first output end of the first phase delay circuit is connected to the input end of the second phase delay circuit. The first output end of the second phase delay circuit is connected to the upper bridge arm switch in the third phase bridge arm, and the second output end of the second phase delay circuit is connected to the lower bridge arm switch in the third phase bridge arm.

2. The three-phase inverter according to claim 1, characterized in that, each bridge arm switch in the upper bridge arm switch and the lower bridge arm switch is composed of a first switch and a second switch connected in parallel; the drive signal output circuit includes a first modulation wave output circuit, a second modulation wave output circuit, and a drive signal generation circuit; The input ends of the first modulation wave output circuit and the second modulation wave output circuit are both used to receive the voltage signal across the first phase bridge arm. The output end of the first modulation wave output circuit is connected to the first input end of the drive signal generation circuit, and the output end of the second modulation wave output circuit is connected to the second input end of the drive signal generation circuit. The third input end of the drive signal generation circuit is used to receive the carrier wave. The first output end of the drive signal generation circuit is connected to the first switch among the upper bridge arm switches of the first phase bridge arm, and the second output end of the drive signal generation circuit is connected to the second switch among the upper bridge arm switches of the first phase bridge arm. The first output end of the drive signal generation circuit is connected to the second switch among the lower bridge arm switches of the first phase bridge arm through a first inverter, and the second output end of the drive signal generation circuit is connected to the first switch among the lower bridge arm switches of the first phase bridge arm through a second inverter.

3. The three-phase inverter according to claim 2, characterized in that the first modulation wave output circuit is configured to output a first modulation wave with a first voltage amplitude to the drive signal generation circuit based on the voltage signal across the first phase bridge arm; the second modulation wave output circuit is configured to output a second modulation wave with a second voltage amplitude to the drive signal generation circuit based on the voltage signal across the first phase bridge arm; the drive signal generation circuit is configured to compare the first modulation wave and the carrier wave, output a first drive signal to the first switch among the upper bridge arm switches of the first phase bridge arm, and output a first inverted drive signal to the second switch among the lower bridge arm switches of the first phase bridge arm through the first inverter; compare the second modulation wave and the carrier wave, output a second drive signal to the second switch among the upper bridge arm switches of the first phase bridge arm, and output a second inverted drive signal to the first switch among the lower bridge arm switches of the first phase bridge arm through the second inverter.

4. The three-phase inverter according to claim 3, characterized in that the first phase delay circuit includes a first phase shifter and a second phase shifter; wherein, the input end of the first phase shifter is connected to the first output end of the drive signal generation circuit, the output end of the first phase shifter is connected to the first switch among the upper bridge arm switches of the second phase bridge arm, the input end of the second phase shifter is connected to the second output end of the drive signal generation circuit, and the output end of the second phase shifter is connected to the second switch among the upper bridge arm switches of the second phase bridge arm; the output end of the first phase shifter is connected to the second switch among the lower bridge arm switches of the second phase bridge arm through a third inverter, and the output end of the second phase shifter is connected to the first switch among the lower bridge arm switches of the second phase bridge arm through a fourth inverter; The first phase shifter is configured to delay the phase of the first driving signal by a first angle and output a third driving signal to the first switch among the upper-bridge-arm switches of the second phase leg, and output a third inverted driving signal to the second switch among the lower-bridge-arm switches of the second phase leg through the third inverter; The second phase shifter is configured to delay the phase of the second driving signal by the first angle and output a fourth driving signal to the second switch among the upper-bridge-arm switches of the second phase leg, and output a fourth inverted driving signal to the first switch among the lower-bridge-arm switches of the second phase leg through the fourth inverter.

5. The three-phase inverter according to claim 4, wherein, the second phase delay circuit includes a third phase shifter and a fourth phase shifter; wherein, the input end of the third phase shifter is connected to the output end of the first phase shifter, the output end of the third phase shifter is connected to the first switch among the upper-bridge-arm switches of the third phase leg, the input end of the fourth phase shifter is connected to the output end of the second phase shifter, and the output end of the fourth phase shifter is connected to the second switch among the upper-bridge-arm switches of the third phase leg; the output end of the third phase shifter is connected to the second switch among the lower-bridge-arm switches of the third phase leg through a fifth inverter, and the output end of the fourth phase shifter is connected to the first switch among the lower-bridge-arm switches of the third phase leg through a sixth inverter; the third phase shifter is configured to delay the phase of the third driving signal by the first angle and output a fifth driving signal to the first switch among the upper-bridge-arm switches of the third phase leg, and output a fifth inverted driving signal to the second switch among the lower-bridge-arm switches of the third phase leg through the fifth inverter; the fourth phase shifter is configured to delay the phase of the fourth driving signal by the first angle and output a sixth driving signal to the second switch among the upper-bridge-arm switches of the third phase leg, and output a sixth inverted driving signal to the first switch among the lower-bridge-arm switches of the third phase leg, so that the current output power of the three-phase inverter is less than or equal to the rated output power.

6. The three-phase inverter according to claim 4, wherein, the second phase delay circuit includes a third phase shifter and a fourth phase shifter; wherein, the input end of the third phase shifter is connected to the first output end of the driving signal generation circuit, the output end of the third phase shifter is connected to the first switch among the upper-bridge-arm switches of the third phase leg, the input end of the fourth phase shifter is connected to the second output end of the driving signal generation circuit, and the output end of the fourth phase shifter is connected to the second switch among the upper-bridge-arm switches of the third phase leg; the output end of the third phase shifter is connected to the second switch among the lower-bridge-arm switches of the third phase leg through a fifth inverter, and the output end of the fourth phase shifter is connected to the first switch among the lower-bridge-arm switches of the third phase leg through a sixth inverter; The third phase shifter is configured to delay the phase of the first driving signal by a second angle and output a fifth driving signal to the first switch among the upper-bridge-arm switches of the third phase bridge arm, and output a fifth inverted driving signal to the second switch among the lower-bridge-arm switches of the third phase bridge arm through the fifth inverter; the fourth phase shifter is configured to delay the phase of the second driving signal by the second angle and output a sixth driving signal to the second switch among the upper-bridge-arm switches of the third phase bridge arm, and output a sixth inverted driving signal to the first switch among the lower-bridge-arm switches of the third phase bridge arm through the sixth inverter, so that the current output power of the three-phase inverter is less than or equal to the rated output power, where the second angle and the first angle are opposite to each other.

7. The three-phase inverter according to any one of claims 3-6, wherein, each of the first modulation wave output circuit and the second modulation wave output circuit includes an amplitude adjustment circuit and a modulation wave generation circuit, wherein an input end of the amplitude adjustment circuit is connected to an input end of each modulation wave output circuit, an output end of the amplitude adjustment circuit is connected to an input end of the modulation wave generation circuit, and an output end of the modulation wave generation circuit is connected to an output end of each modulation wave output circuit; the amplitude adjustment circuit is configured to adjust the voltage amplitude of the voltage signal across the first phase bridge arm and output a target voltage signal to the modulation wave generation circuit; the modulation wave generation circuit is configured to generate a modulation wave based on the target voltage signal; wherein, when the voltage amplitude of the target voltage signal is the first voltage amplitude, the modulation wave is the first modulation wave; when the voltage amplitude of the target voltage signal is the second voltage amplitude, the modulation wave is the second modulation wave.

8. The three-phase inverter according to claim 7, wherein, the modulation wave generation circuit includes a first signal generator, a second signal generator, a second adder, and an absolute value circuit, wherein an input end of the first signal generator is connected to an input end of the modulation wave generation circuit, an output end of the first signal generator is connected to a first input end of the second adder, an output end of the second signal generator is connected to a second input end of the second adder, an output end of the second adder is connected to an input end of the absolute value circuit, and an output end of the absolute value circuit is connected to an output end of the modulation wave generation circuit; the first signal generator is configured to output a first waveform signal to the second adder based on the target voltage signal; the second signal generator is configured to output a second waveform signal to the second adder based on the target voltage signal, where the frequency of the second waveform signal is three times that of the first waveform signal; the second adder is configured to superimpose the second waveform signal on the first waveform signal and output a superimposed waveform signal to the absolute value circuit; the absolute value circuit is configured to generate the modulation wave based on the superimposed waveform signal.

9. The three-phase inverter according to claim 7 or 8, characterized in that, the amplitude adjustment circuit includes a voltage amplifier, wherein the input end of the voltage amplifier is connected to the input end of the amplitude adjustment circuit, and the output end of the voltage amplifier is connected to the output end of the amplitude adjustment circuit.

10. The three-phase inverter according to claim 9, characterized in that, the amplitude adjustment circuit further includes a first adder, and the first adder is arranged between the input end of the voltage amplifier and the input end of the amplitude adjustment circuit; the first adder is used to adjust the voltage amplitude of the voltage signal at both ends of the first phase bridge arm and output the adjusted voltage signal to the voltage amplifier; the voltage amplifier is used to amplify the voltage amplitude of the adjusted voltage signal and output the target voltage signal to the modulation wave generation circuit.

11. The three-phase inverter according to any one of claims 3-10, characterized in that, the drive signal generation circuit includes a first comparator, wherein the first input end of the first comparator is connected to the first input end of the drive signal generation circuit, the second input end of the first comparator is connected to the third input end of the drive signal generation circuit, and the output end of the first comparator is connected to the first output end of the drive signal generation circuit; the first comparator is configured to output the first drive signal as a first level when the first voltage amplitude of the first modulation wave is greater than the voltage amplitude of the carrier wave, and output the first drive signal as a second level when the first voltage amplitude of the first modulation wave is less than the voltage amplitude of the carrier wave; wherein, when the first level is a low level, the second level is a high level, or when the first level is a high level, the second level is a low level.

12. The three-phase inverter according to claim 11, characterized in that, the drive signal generation circuit further includes a second comparator, wherein the first input end of the second comparator is connected to the second input end of the drive signal generation circuit, the second input end of the second comparator is connected to the third input end of the drive signal generation circuit, and the output end of the second comparator is connected to the second output end of the drive signal generation circuit; the second comparator is configured to output the second drive signal as a first level when the second voltage amplitude of the second modulation wave is greater than the voltage amplitude of the carrier wave, and output the second drive signal as a second level when the second voltage amplitude of the second modulation wave is less than the voltage amplitude of the carrier wave; wherein, when the first level is a low level, the second level is a high level, or when the first level is a high level, the second level is a low level.

13. The three-phase inverter according to any one of claims 3-12, characterized in that, The driving circuit further includes a carrier output circuit, and the carrier output circuit includes a third signal generator and a level shift circuit. Wherein, the output end of the third signal generator is connected to the input end of the level shift circuit, and the output end of the level shift circuit is connected to the third input end of the driving signal generation circuit; The third signal generator is configured to output a third waveform signal to the level shift circuit; The level shift circuit is configured to output a carrier wave to the driving signal generation circuit based on the third waveform signal.

14. The three-phase inverter according to any one of claims 2-13, characterized in that, The driving circuit further includes a current sensor. Wherein, the input end of the current sensor is connected to the input end of the three-phase inverter, and the output end of the current sensor is connected to the input ends of the first modulation wave output circuit and the second modulation wave output circuit; The current sensor is configured to collect the input current of the three-phase inverter, and output the voltage signal across the first phase leg to the first modulation wave output circuit and the second modulation wave output circuit respectively based on the input current of the three-phase inverter.

15. The three-phase inverter according to any one of claims 2-13, characterized in that, The driving circuit further includes a current sensor. Wherein, the input end of the current sensor is connected to the end of the upper bridge arm switch of the first phase leg away from the lower bridge arm switch, and the output end of the current sensor is connected to the input ends of the first modulation wave output circuit and the second modulation wave output circuit; The current sensor is configured to collect the current passing through the first phase leg, and output the voltage signal across the first phase leg to the first modulation wave output circuit and the second modulation wave output circuit respectively based on the current passing through the first phase leg.

16. A motor control unit (MCU), characterized in that, The MCU includes an input port, a three-phase output port, and the three-phase inverter according to any one of claims 1-15. The input port is configured to connect to a power battery, and the three-phase output port is configured to connect to a motor; wherein, the input end of the three-phase inverter is connected to the input port, and the three-phase output ends of the three-phase inverter are connected to the three-phase output port.

17. A powertrain, characterized in that, The powertrain includes a motor and the MCU according to claim 16. The MCU is configured to invert the direct current output by the power battery into three-phase alternating current and drive the motor.

18. An electric vehicle, characterized in that, The electric vehicle includes a power battery and the powertrain according to claim 17. The power battery is configured to output direct current to the powertrain.

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